Digital Logic Course Objective: To introduce basic principles of digital logic design, its implementation and applications. 1 Introduction (3 hours) 1. Definitions for Digital Signals Digital Waveforms Digital Logie Moving and Storing Digital Information Digital Operations Digital Computer Digital integrated Circuits 8 Dighal Ic Signa Levels 9. Clock wave form 10.Coding 1. ASCII Code 2.8¢0 3. The Excess 3 Code 4 The Gray Code 2 Digital Logie(t hour) 1. The Basic Gates: NOT, OR AND 2. Universal Logi Gates; NOR, NANO 3. AND-OR-INVERT Gates 4. Postive and Negative Logie 5. Introduction to HDL 3. Combinational Lagie Circuits(S hours) Boolean Laws and Theorems 2. Sumof- Products Method 3. Truth Table to Karnaugh Map 4. Pats, Quads, and Oetets 5. Karnaugh Simplifcations 6 Don't Care Conditions 7. Produc of Sums Method 8. Produc of Sums Simplification 9. Hazards and Hazard Covers, 1. HDL Implementation Models 4 Dat rocessing Crcuit(S hours) Mutiplexetures Demuttiplexetures Decoder 1 2 3 4 5. Seven-Segment Decoders 6 Encoder 7. Exclusve-OR Gates 8 Parity Generators and Checkers 9. Magnitude Comparator 10. Read-Only Memory 11. Programmable Array Logic 12. Programmable Logic Arrays 13. Troubleshooting with a Logi Problems 14 HDL Implementation of Data Processing Circuits 5. Arithmetic Circute(S hours) 1. Binary Adelition|2 Binary Subtraction 3. Unsigned Binary Numbers 4 Sign-Magnitude Numbers 5.2's Complement Representation 6.2'5 Complement Arithmetic 7. arithmetic Building Blocks 8. The Adder-Subtracter 9.F 10. Arithmetic Logie Unt 11. Binary Multiplication and Division 12. Arithmetic Circuits Using HDL det 6 Flip Flops(S hours) 1. RS Flip-Flops 2. Gated Flip-Flops 3. Edge-Tiiggoted RS Flip-Flops 4. Ede Tiggered D Flip-Flops 5. Egde Triggered JK Flip-Flops 6 Flip-Flop Timing 7.1K Mater Save Flip-Flops 8B Switch Contacts Bounds Circuits 9. Vaious Representation of Flip-Flops 10. Analysis of Sequencia Circuits 7 Registers(2 hours) 1. Types of Registers 2. Serial In-Serial Out 5 Serial In-Paralel Out 4. Parallel In-Seral Out 5. Paral in-Paallel Out 6. Applications of Shift Registers 8 Counters(s hours) 1. Asynchronous Counters 2. Decoding Gates 3 Synchronous Counters 4. Changing the Counter Modulus 5. Decade Counters 6 Presettable Counters 7. Counter Design 3s Synthesis Problem 8. Digial Clock 9, Sequential Machines(@ hours) 1. Symenronous Machines 1. Clock Driven Models and State Diagrams 2. Transition tables, Redundant States 3 Binary Assignment 4. Use of Flip-Flops in realizing the models 2. Asynchronous Machines 1. Hazards in Asynchronous Sy 2. Allowable Transitions 3. How tables and Merger Diagrams citation Maps and Realzation of the models snd Use of Redundant ranch 10-Digital Integrate Ciruits(4 hours) 1. Switching Circuits 2.7400 TL 3. TTL parameters 4.TTLOvervew 5. Open Colleter Gates 6.Three-sate TTL Devices 1. ternal Drive for TL Lods 8. TTL Driving External Loads 289. 74¢00 CMOS 10.€MOS characteristics 11. TTL-to-CMOS interface 12 CMOS-to-TTL Interface 11. Applications(2 hours) 1. Multiplexing Displays 2 Frequency Counters 5. Time Measurement Practical: 1. DeMorgon’s In and it's familiarization with NAND and NOR gates 2 Encoder, Decoder, and Multiplexer 3. Familarzation with Binary Adtion and Subtraction 4 Constvetion of Tue Complement Generator 5. Latches, RS, Master-Slove and Type fh flops 6.0 and i type tp flops 7. Ripple Counter, Synchronous counter 8 Familarzation with computer package fo logic circuit design 9. Design digital ccuts using hardware and sofware tools 10. Use of PLAS and PLD References: 1. Donald Peach Alber Paul Malvina and Goutam Saha, "Digital Principles and Applications, 6th edition, Tata MeGraw-Hi 2. David J Comer “Digital Logic And State Machine Design” 3rd eaition, Oxfored University Press, 2002 53 Willam L Fletcher "An Engineering Approach to Digital Design” Prinice Hall of Indi, New Delhi 1990 4 Wiliam H, Gothmann, “Digital Electronics, An Introzution to Theory and Practice’, 2nd eatin, PHI, 2009 2006 Evaluation Scheme: ‘The questions will cover al the chapters ofthe sylabus. The evaluation scheme willbe as indicated inthe table below Chapters Hours Marks distribution? 1 3 6 2 1 4 3 5 8 4 5 0 5 5 8 6 5 8 7 2 4 8 5 8 ° 8 2 10 4 8Toa! 45 80 “Note: There may be a minor deviation in the marks distribution. Sponsered Ads