ASIC

VERIFICATION
CRACK YOUR
INTERVIEW WITH
100% CONFIDENCE
Your Complete Experience-Level Guide

By Prasanthi chanda
1.How do you handle multiple virtual sequences running on different
interfaces?

Solution :

UNDERSTANDING THE PROBLEM

We need to:
Control multiple sequences running on different interfaces (e.g., AXI and
SPI).
Synchronize sequences across different sequencers.
Ensure proper coordination between transactions.

SOLUTION APPROACH
We will implement:
Virtual Sequencer: A top-level sequencer that coordinates different
sequencers.
Virtual Sequence: A sequence that controls multiple lower level
sequences.
Test Class: A test that starts the virtual sequence.

IMPLEMENTATION STEPS
Step 1: Define the Virtual Sequencer
The Virtual Sequencer contains handles to all sub-sequencers.

class my_virtual_sequencer extends uvm_sequencer;

`uvm_component_utils(my_virtual_sequencer)
// Handles to real sequencers
uvm_sequencer#(axi_transaction) axi_seqr;
uvm_sequencer#(spi_transaction) spi_seqr;
function new(string name = "my_virtual_sequencer", uvm_component
parent);
super.new(name, parent);
endfunction
endclass
Step 2: Define the Virtual Sequence
The Virtual Sequence runs different sequences in parallel.

class my_virtual_sequence extends uvm_sequence;

`uvm_object_utils(my_virtual_sequence)

// Instantiate sub-sequences
my_axi_sequence axi_seq;
my_spi_sequence spi_seq;

function new(string name = "my_virtual_sequence");

super.new(name);
endfunction

task body();
// Ensure we have a valid virtual sequencer
if (!$cast(p_sequencer, m_sequencer)) begin
`uvm_fatal("VSEQ", "Virtual Sequencer casting failed!")
end

// Run sequences on different interfaces in parallel

fork
axi_seq.start(p_sequencer.axi_seqr); // Start AXI sequence
spi_seq.start(p_sequencer.spi_seqr); // Start SPI sequence
join
endtask
endclass

Step 3: Define the AXI and SPI Sequences

These sequences run on their respective sequencers.
Step 4: Define the Environment (Connecting Virtual Sequencer)
The Environment Class connects the sequencers to the virtual sequencer.

class my_env extends uvm_env;

`uvm_component_utils(my_env)

my_virtual_sequencer vseqr;
axi_agent axi_ag;
spi_agent spi_ag;

function new(string name, uvm_component parent);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

vseqr = my_virtual_sequencer::type_id::create("vseqr", this);

axi_ag = axi_agent::type_id::create("axi_ag", this);
spi_ag = spi_agent::type_id::create("spi_ag", this);
endfunction

function void connect_phase(uvm_phase phase);

super.connect_phase(phase);

vseqr.axi_seqr = axi_ag.sequencer;
vseqr.spi_seqr = spi_ag.sequencer;
endfunction
endclass
Step 5: Define the Test Class
The Test Class starts the virtual sequence.
class my_test extends uvm_test;
`uvm_component_utils(my_test)

my_env env;
my_virtual_sequence vseq;

function new(string name, uvm_component parent);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
env = my_env::type_id::create("env", this);
endfunction

task run_phase(uvm_phase phase);

phase.raise_objection(this);
vseq = my_virtual_sequence::type_id::create("vseq");
vseq.start(env.vseqr); // Start the virtual sequence
phase.drop_objection(this);
endtask
endclass
2. How do you verify UPF (Unified Power Format) integration in an SoC
verification environment?

Solution :

Power-aware verification ensures correct behavior across power domains.

USE UVM FOR POWER-AWARE VERIFICATION
Integrate UPF files during simulation:
read_upf my_power.upf
set_power_domain PD1 -instances {inst1 inst2}

CHECK ISOLATION AND RETENTION MECHANISMS

Ensure that isolation signals behave correctly
property p_iso_check;
@(posedge clk) disable iff (!rst)
(iso_enable) |-> (sig_out == 0);
endproperty
ASSERT_ISO: assert property (p_iso_check);

POWER GATING VERIFICATION

Ensure registers retain values after power gating:

property p_retention_check;
@(posedge clk) disable iff (!rst)
(!power_on && $past(power_on)) |-> (reg_out == $past(reg_out));
endproperty
ASSERT_RETENTION: assert property (p_retention_check);

3. How do you verify the correctness of a low power sleep mode in a

Power Management Controller (PMC) ?

Solution :

Power management controllers (PMCs) must transition correctly between

states.
Check Deep Sleep Entry Timing
 property p_sleep_entry;
@(posedge clk) disable iff (!rst)
(sleep_request) |-> ##[1:10] (sleep_ack);
endproperty
ASSERT_SLEEP_ENTRY: assert property (p_sleep_entry);

Ensure Wake-Up Signal Is Processed Within Allowed Cycles

property p_wakeup_response;
@(posedge clk) disable iff (!rst)
(wakeup_request) |-> ##[1:5] (wakeup_ack);
endproperty
ASSERT_WAKEUP_RESPONSE: assert property (p_wakeup_response);

Functional Coverage for Power Transitions

covergroup power_transitions;
pwr_state: coverpoint power_mode { bins active = {0}; bins sleep
= {1}; }
endgroup

4. How do you debug an AXI interconnect issue in a full-chip verification

environment?

Solution :

Ensure Correct AXI Address Decoding

property p_axi_addr_decoding;
@(posedge clk) disable iff (!rst)
(awvalid && awready) |-> (awaddr inside {[0x1000:0x2000]});
endproperty
ASSERT_AXI_ADDR_DECODING: assert property (p_axi_addr_decoding);
 Check Write Data Integrity Across Transactions
property p_axi_data_integrity;
@(posedge clk) disable iff (!rst)
(wvalid && wready) |-> (wdata == $past(wdata));
endproperty
ASSERT_AXI_DATA_INTEGRITY: assert property (p_axi_data_integrity);

Implement UVM Scoreboard for AXI Responses

class axi_scoreboard extends uvm_scoreboard;
function void write(axi_transaction txn);
if (txn.awaddr != expected_addr)
`uvm_error("SCOREBOARD", "Address Mismatch!");
endfunction
endclass
5. How do you handle functional coverage closure when verifying a
large-scale SoC?

Solution :
For a large SoC, achieving 100% functional coverage is challenging.
Follow these strategies:
1. Identify Coverage Gaps Using UVM Reports
if (uvm_report_server::get_server().get_coverage() < 100)
`uvm_info("COVERAGE", "Coverage is incomplete! Identifying missing
bins...", UVM_MEDIUM)

2. Use Cross Coverage for Critical Scenarios

covergroup burst_cg;
addr: coverpoint awaddr;
burst_len: coverpoint awlen;
burst_type: coverpoint awburst;
cross addr, burst_len, burst_type;
endgroup
3. Constraint Randomization to Hit Coverage Holes
constraint c_coverage {
if (coverage_bin == LOW) weight = 5;
else weight = 1;
}
4. Use Directed Tests for Rare Scenarios
class directed_test extends base_test;
task run_phase();
env.sequencer.start(dir_seq);
endtask
endclass
5. Coverage-Guided Regression Runs
Prioritize tests based on missing bins to maximize coverage.

6. How do you implement a reusable scoreboard in a UVM testbench?

Solution :
A scoreboard compares expected vs. actual outputs.
1. Define a Scoreboard Class
class my_scoreboard extends uvm_scoreboard;
`uvm_component_utils(my_scoreboard)

uvm_analysis_imp#(transaction, my_scoreboard) inp, outp;

task write(transaction tr);

if (tr.exp_data !== tr.act_data)
`uvm_error("SCOREBOARD", $sformatf("Data Mismatch: Expected
%0h, Got %0h", tr.exp_data, tr.act_data))
endtask
endclass
2. Connect Scoreboard to the UVM Environment
function void connect_phase(uvm_phase phase);
monitor.analysis_port.connect(scoreboard.analysis_export);
endfunction
3. Use a Golden Model for Reference Data
Compare actual results against a precomputed golden reference.

7. How do you verify an AXI burst transaction using SystemVerilog

Assertions (SVA)?
Solution :
AXI burst transactions should increment addresses correctly.
1. Ensure Address Increments Properly
property p_axi_burst_addr;
@(posedge clk) disable iff (!rst)
(awvalid && awready && awburst == 2'b01) |-> ##1
(awaddr == $past(awaddr) + (1 << $past(awsize)));
endproperty
ASSERT_AXI_BURST_ADDR: assert property (p_axi_burst_addr);

2. Verify Data Transfer Completes Properly

property p_axi_data_transfer;
@(posedge clk) disable iff (!rst)
(wvalid && wready) |-> ##[1:$] (bvalid && bready);
endproperty
ASSERT_AXI_DATA_TRANSFER: assert property (p_axi_data_transfer);

3. Functional Coverage for Burst Verification

covergroup axi_burst_cg;
awlen_cp: coverpoint awlen;
awsize_cp: coverpoint awsize;
awburst_cp: coverpoint awburst;
cross awlen_cp, awsize_cp, awburst_cp;
endgroup
8. How do you verify low-power transitions in an SoC using UPF?
Solution :
Power-aware verification ensures correct power state transitions.
1. Check Isolation When Power Domain is OFF
property p_iso_check;
@(posedge clk) disable iff (!rst)
(iso_enable) |-> (sig_out == 0);
endproperty
ASSERT_ISO: assert property (p_iso_check);

2. Ensure Retention Logic Holds Value

property p_retention_check;
@(posedge clk) disable iff (!rst)
(!power_on && $past(power_on)) |-> (reg_out == $past(reg_out));
endproperty
ASSERT_RETENTION: assert property (p_retention_check);

3. Use UPF for Verification

read_upf my_power.upf
set_power_domain PD1 -instances {inst1 inst2}

9. How do you implement a layered testbench architecture for an SoC

verification project?
Solution :
A layered testbench separates components for better reusability and
debugging.
1. UVM Layered Testbench Components
Sequence Layer – Generates transactions.
Driver Layer – Converts transactions into signal-level operations.
Monitor Layer – Captures and forwards transactions.
Scoreboard Layer – Compares expected and actual results.
2. UVM Agent Example
class my_agent extends uvm_agent;
`uvm_component_utils(my_agent)

function new(string name, uvm_component parent);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
monitor = my_monitor::type_id::create("monitor", this);
sequencer = my_sequencer::type_id::create("sequencer", this);
driver = my_driver::type_id::create("driver", this);
endfunction
endclass

3. Use TLM for Inter-Component Communication

class my_monitor extends uvm_monitor;
uvm_analysis_port#(transaction) mon_port;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
task run_phase(uvm_phase phase);
forever begin
transaction tr = new();
// Capture signal-level data
mon_port.write(tr);
end
endtask
endclass
10. How do you debug X propagation issues in large-scale SoC
verification?
Solution :
X propagation leads to uninitialized values and unknown behaviors.
1. Enable X Propagation Debugging
property p_no_x_propagation;
@(posedge clk) disable iff (!rst)
(!isunknown(signal));
endproperty
ASSERT_NO_X: assert property (p_no_x_propagation);

2. Force Signal Initialization in RTL

initial begin
signal = 0;
end
3. Run Simulation with +warnonx Option
vcs -debug +warnonx

11. How do you optimize UVM simulation performance for a high-speed

interconnect (e.g., AXI, PCIe)?
Solution :
Simulation time can be reduced by optimizing testbench execution.
1. Reduce UVM Print Overhead
uvm_top.set_report_verbosity_level(UVM_LOW);

2. Optimize Randomization for Speed

constraint optimize {
addr dist { [0:1024] := 60, [1025:4096] := 40 };
}
3. Use Parallel Transaction Execution
fork
seq1.start(p_sequencer);
seq2.start(p_sequencer);
join_none

12. How do you handle multiple clock domains in UVM testbenches?

Solution :
SoC verification requires handling multiple asynchronous clocks (e.g., CPU,
PCIe, DDR).
1. Use Clocking Blocks for Synchronization
clocking axi_cb @(posedge axi_clk);
default input #1 output #1;
input arvalid, awvalid;
output arready, awready;
endclocking

2. Implement CDC (Clock Domain Crossing) Checks Using Assertions

property p_cdc_handshake;
@(posedge src_clk) disable iff (!rst)
(req && $rose(src_clk)) |-> ##[1:$] (ack && $rose(dest_clk));
endproperty
ASSERT_CDC_HANDSHAKE: assert property (p_cdc_handshake);

3. Verify Clock Switching in Low-Power Modes

property p_clk_switch;
@(posedge clk) disable iff (!rst)
(power_mode_change) |-> ##[1:5] (new_clk_active);
endproperty
ASSERT_CLK_SWITCH: assert property (p_clk_switch);
13. How do you verify AXI burst transactions for different data
widths and interleaving scenarios?
Solution :
AXI supports variable burst lengths, different data widths, and interleaving
of multiple transactions.
1. Check Correct Address Incrementation in Burst Mode
property p_axi_burst_addr;
@(posedge clk) disable iff (!rst)
(awvalid && awready && awburst == 2'b01) |-> ##1
(awaddr == $past(awaddr) + (1 << $past(awsize)));
endproperty
ASSERT_AXI_BURST_ADDR: assert property (p_axi_burst_addr);
2. Ensure Correct Burst Length Handling
property p_axi_burst_length;
@(posedge clk) disable iff (!rst)
(awvalid && awready) |-> (awlen <= 16);
endproperty
ASSERT_AXI_BURST_LENGTH: assert property (p_axi_burst_length);

3. Implement Functional Coverage for Different AXI Configurations

covergroup axi_burst_cg;
awlen_cp: coverpoint awlen { bins burst_4 = {4}; bins burst_8 = {8};
bins burst_16 = {16}; }
awsize_cp: coverpoint awsize;
awburst_cp: coverpoint awburst;
cross awlen_cp, awsize_cp, awburst_cp;
endgroup
14. How do you verify PCIe link training and power management
states?
Solution :
PCIe verification requires checking link training, LTSSM (Link Training and
Status State Machine), and power states (L0, L1, L2, etc.).
1. Ensure Proper LTSSM Transitions
property p_pcie_ltssm;
@(posedge clk) disable iff (!rst)
(ltssm_state == DETECT_QUIET) |-> ##[1:10] (ltssm_state ==
DETECT_ACTIVE);
endproperty
ASSERT_PCIE_LTSSM: assert property (p_pcie_ltssm);
2. Verify Power State Transitions
property p_pcie_power_state;
@(posedge clk) disable iff (!rst)
(power_state == L1) |-> ##[1:50] (power_state == L0);
endproperty
ASSERT_PCIE_POWER_STATE: assert property (p_pcie_power_state);

3. Functional Coverage for Different Link Widths

covergroup pcie_link_cg;
link_width: coverpoint pcie_link_width { bins x1 = {1}; bins x4 = {4};
bins x8 = {8}; bins x16 = {16}; }
endgroup
15. How do you achieve coverage closure for power-aware
verification in a UPF-based SoC?
Solution :
Power-aware verification requires functional coverage to track power state
transitions and isolation scenarios.
1. Cover All Power State Transitions
covergroup power_states_cg;
pwr_state: coverpoint power_domain_state { bins active = {0}; bins
sleep = {1}; bins deep_sleep = {2}; }
cross pwr_state, retention_enable;
endgroup

2. Check Isolation & Retention Signal Coverage

covergroup isolation_cg;
iso_signal: coverpoint isolation_ctrl;
retention: coverpoint retention_ctrl;
cross iso_signal, retention;
endgroup
3. Measure Power Mode Switch Timings Using Functional Coverage
covergroup power_timing_cg;
pwr_entry: coverpoint transition_start;
pwr_exit: coverpoint transition_end;
cross pwr_entry, pwr_exit;
endgroup
16. How do you implement cross-coverage for protocol
verification (AXI, PCIe)?
Solution :
Cross-coverage ensures that all protocol transactions, burst lengths, and
address patterns are exercised.
1. AXI Coverage for Different Burst Types and Sizes
covergroup axi_burst_cg;
awlen_cp: coverpoint awlen { bins burst_1 = {1}; bins burst_4 = {4};
bins burst_8 = {8}; bins burst_16 = {16}; }
awsize_cp: coverpoint awsize;
awburst_cp: coverpoint awburst;
cross awlen_cp, awsize_cp, awburst_cp;
endgroup

2. PCIe Coverage for Transaction Types

covergroup pcie_tlp_cg;
tlp_type: coverpoint pcie_tlp_hdr[31:24];
tlp_length: coverpoint pcie_tlp_hdr[9:0];
cross tlp_type, tlp_length;
endgroup
3. Ensure Coverage of Rare Transactions (e.g., Error Responses)
covergroup error_cg;
error_type: coverpoint pcie_error_code { bins completion_timeout =
{16'h0001}; bins malformed_tlp = {16'h0002}; }
endgroup
17. How do you verify the correctness of AXI outstanding
transactions using SystemVerilog Assertions?
Solution :
AXI supports multiple outstanding transactions that need to be tracked
for correctness.
1. Ensure Read Responses Are Ordered When IDs Match
property p_axi_read_order;
@(posedge clk) disable iff (!rst)
(arvalid && arready) |-> ##[1:$] (rid == $past(rid));
endproperty
ASSERT_AXI_READ_ORDER: assert property (p_axi_read_order);
2. Check That Outstanding Transactions Do Not Exceed Allowed Limit
property p_axi_outstanding_limit;
@(posedge clk) disable iff (!rst)
(num_outstanding_writes < MAX_OUTSTANDING);
endproperty
ASSERT_AXI_OUTSTANDING_LIMIT: assert property
(p_axi_outstanding_limit);

18. How do you verify reset behavior in a low-power design using

assertions?
Solution :
For power-aware verification, reset should properly restore state
retention registers.
1. Ensure Reset Clears Non-Retention Registers Only
property p_reset_behavior;
@(posedge clk) disable iff (!rst)
(reset_asserted) |-> ##1 (non_retention_reg == 0);
endproperty
ASSERT_RESET_BEHAVIOR: assert property (p_reset_behavior);
2. Ensure Power Domain Isolation During Reset
property p_iso_during_reset;
@(posedge clk) disable iff (!rst)
(reset_asserted) |-> (iso_signal == 1);
endproperty
ASSERT_ISO_DURING_RESET: assert property (p_iso_during_reset);

19. How do you ensure full handshake completion in a complex

SoC design?
Solution :
SoC designs involve multiple handshaking mechanisms, ensuring that
acknowledgment signals are always received.
1. Verify Request-Acknowledge Handshake Completes Within a Certain
Cycle Limit
property p_handshake_complete;
@(posedge clk) disable iff (!rst)
(request) |-> ##[1:5] (acknowledge);
endproperty
ASSERT_HANDSHAKE_COMPLETE: assert property (p_handshake_complete);
2. Ensure No Overlapping Handshakes
property p_no_overlap_handshake;
@(posedge clk) disable iff (!rst)
(request && !acknowledge) |-> ##1 (!new_request);
endproperty
ASSERT_NO_OVERLAP_HANDSHAKE: assert property
(p_no_overlap_handshake);
20. How do you achieve 100% functional coverage for complex
sequential operations?
Solution :
For sequential behavior verification, functional coverage must track
state transitions and timing relationships.
1. Define Coverage for Sequential Transactions
covergroup seq_cg;
state: coverpoint fsm_state { bins idle = {0}; bins active = {1}; bins
wait = {2}; }
transition: cross state, prev_state;
endgroup
2. Check Sequential Timing Relations
property p_seq_timing;
@(posedge clk) disable iff (!rst)
(state == ACTIVE) |-> ##[2:10] (state == WAIT);
endproperty
ASSERT_SEQ_TIMING: assert property (p_seq_timing);

21. How do you ensure all critical paths in an SoC are covered in
functional verification?
Solution :
Functional coverage should ensure all critical data paths are exercised.
1. Define Coverage for Data Paths
covergroup data_path_cg;
addr: coverpoint transaction.addr;
data: coverpoint transaction.data;
cross addr, data;
endgroup
2. Implement Directed Tests for Uncovered Paths
if (!$is_covered(data_path_cg))
run_directed_test();

22. How do you verify clock domain crossing (CDC) coverage in a multi-
clock SoC?
Solution :
CDC verification requires checking handshake signals and metastability
scenarios.
1. Ensure Data is Captured Correctly in Destination Domain
property p_cdc_stability;
@(posedge dest_clk) disable iff (!rst)
(src_valid) |-> ##[1:5] (dest_valid);
endproperty
ASSERT_CDC_STABILITY: assert property (p_cdc_stability);
2. Use Functional Coverage for CDC Transitions
covergroup cdc_cg;
src_clk: coverpoint source_clk_edge;
dest_clk: coverpoint dest_clk_edge;
cross src_clk, dest_clk;
endgroup

23. How do you verify protocol timing relationships using assertions?

Solution :
Timing assertions ensure that protocol constraints (e.g., setup/hold
timing, inter-packet delays) are met.
1. Ensure Setup-Hold Timing Between Signals
 property p_setup_hold;
@(posedge clk) disable iff (!rst)
(signal_a && $rose(clk)) |-> ##1 signal_b;
endproperty
ASSERT_SETUP_HOLD: assert property (p_setup_hold);

2. Verify Minimum Delay Between Transactions

property p_min_delay;
@(posedge clk) disable iff (!rst)
(transaction_valid) |-> ##[5:20] (transaction_complete);
endproperty
ASSERT_MIN_DELAY: assert property (p_min_delay);

24. How do you verify cache coherence in a multi-core processor using

assertions?
Solution :
Cache coherence requires ensuring no two processors modify the same
cache line simultaneously.
1. Ensure Atomicity of Cache Line Updates

property p_cache_coherence;
@(posedge clk) disable iff (!rst)
(cpu1_write && cpu2_write && (cpu1_addr == cpu2_addr)) |-> ##1
error_signal;
endproperty
ASSERT_CACHE_COHERENCE: assert property (p_cache_coherence);

2. Implement Functional Coverage for Cache Sharing

covergroup cache_cg;
cache_line: coverpoint cache_addr;
access_type: coverpoint access_mode;
cross cache_line, access_type;
endgroup
25. How do you verify speculative execution and branch
prediction logic using assertions?
Solution :
Branch prediction and speculative execution require correct state
transitions and rollbacks.
1. Ensure Speculative Execution Is Rolled Back on Mispredict
property p_branch_mispredict;
@(posedge clk) disable iff (!rst)
(branch_predict_taken && !branch_actual_taken) |-> rollback_occurred;
endproperty
ASSERT_BRANCH_MISPREDICT: assert property (p_branch_mispredict);
2. Ensure Prefetched Instructions Are Flushed on Pipeline Stall
property p_pipeline_flush;
@(posedge clk) disable iff (!rst)
(stall_signal) |-> ##1 (instruction_cache_flush);
endproperty
ASSERT_PIPELINE_FLUSH: assert property (p_pipeline_flush);

26. How do you ensure corner-case verification in an SoC using

functional coverage?
Solution :
Corner cases are rare but critical scenarios in SoC verification.
1. Implement Weighted Coverage for Rare Cases
covergroup corner_cases_cg;
opcode: coverpoint instr_opcode {
bins common_ops[] = {8'h00, 8'hFF};
bins rare_ops[] = {8'hA5, 8'hB7} with weight = 5;
}
endgroup
2. Use Cross Coverage to Track Complex Scenarios
covergroup multi_var_cg;
addr: coverpoint mem_addr;
data: coverpoint mem_data;
opcode: coverpoint instr_opcode;
cross addr, data, opcode;
endgroup

3. Implement Coverage-Guided Constraint Randomization

constraint adaptive_random {
if (coverage_bin == LOW) weight = 10;
else weight = 1;
}
27. How do you verify out-of-order execution in a superscalar CPU using
assertions?
Solution :
A superscalar CPU must ensure correct instruction reordering while
maintaining data integrity.
1. Ensure Instructions Complete in Correct Order

property p_reorder_check;
@(posedge clk) disable iff (!rst)
(inst_issue && !inst_dependency) |-> ##[1:$] (inst_complete);
endproperty
ASSERT_REORDER_CHECK: assert property (p_reorder_check);
2. Track Speculative Execution and Rollbacks
property p_spec_exec;
@(posedge clk) disable iff (!rst)
(branch_predict_taken && !branch_actual_taken) |-> rollback_occurred;
endproperty
ASSERT_SPEC_EXEC: assert property (p_spec_exec);
28. How do you verify write buffering and forwarding in a
pipeline using assertions?
Solution :
Write buffering allows forwarding values from earlier pipeline stages.
1. Ensure Writes Are Buffered Correctly
property p_write_buffer;
@(posedge clk) disable iff (!rst)
(write_enable && !write_commit) |-> ##[1:$] (write_commit);
endproperty
ASSERT_WRITE_BUFFER: assert property (p_write_buffer);

2. Verify Forwarding of Data from Buffer

property p_data_forward;
@(posedge clk) disable iff (!rst)
(src_reg == dest_reg && write_commit) |-> ##1 (forwarding_active);
endproperty
ASSERT_DATA_FORWARD: assert property (p_data_forward);

29. How do you verify system-level concurrency using functional coverage?

Solution :
Concurrency in SoCs arises due to parallel transactions, multi-core
interactions, and multi-threaded execution.
1. Track Overlapping Transactions Using Cross Coverage

covergroup concurrency_cg;
write_req: coverpoint axi_write;
read_req: coverpoint axi_read;
cross write_req, read_req;
endgroup
2. Measure Multi-Core Execution Overlap
covergroup multicore_cg;
core_id: coverpoint cpu_core { bins core0 = {0}; bins core1 = {1}; }
instr_exec: coverpoint instr_opcode;
cross core_id, instr_exec;
endgroup

30. How do you verify asynchronous reset deassertion coverage?

Solution :
An asynchronous reset should be deasserted cleanly and synchronized
correctly across clock domains.
1. Cover All Possible Reset Deassertion Timings
covergroup async_reset_cg;
reset_deassertion_time: coverpoint reset_deasserted_cycle { bins early =
{[1:3]}; bins late = {[4:10]}; }
endgroup
2. Cross Reset Deassertion with Clock Domains
covergroup reset_clk_cg;
reset_deassertion: coverpoint reset_deasserted;
clock_domains: coverpoint clock_id;
cross reset_deassertion, clock_domains;
endgroup

31. How do you verify deadlock scenarios in a multi-core SoC using

assertions?
Solution :
Deadlocks occur when multiple processors wait indefinitely for shared
resources.
1. Detect Resource Conflicts Leading to Deadlock
property p_deadlock_detect;
@(posedge clk) disable iff (!rst)
(cpu0_waiting && cpu1_waiting && (cpu0_resource == cpu1_resource)) |->
##[5:$] deadlock_signal;
endproperty
ASSERT_DEADLOCK: assert property (p_deadlock_detect);

2. Ensure Forward Progress in Multi-Core Processing

property p_forward_progress;
@(posedge clk) disable iff (!rst)
(cpu_instruction_valid) |-> ##[1:10] (cpu_instruction_commit);
endproperty
ASSERT_FORWARD_PROGRESS: assert property (p_forward_progress);

32. How do you verify clock gating efficiency using assertions?

Solution :
Clock gating is used to reduce power consumption but must be verified
to ensure correct operation.
1. Ensure Gated Clock Is Disabled When No Activity
property p_clock_gating;
@(posedge clk) disable iff (!rst)
(!activity_detected) |-> (clk_gated == 1);
endproperty
ASSERT_CLOCK_GATING: assert property (p_clock_gating);
2. Verify Gated Clock Is Re-enabled on Activity Detection
property p_clk_enable;
@(posedge clk) disable iff (!rst)
(activity_detected) |-> ##[1:5] (clk_gated == 0);
endproperty
ASSERT_CLK_ENABLE: assert property (p_clk_enable);
33. How do you verify security access control violations using
assertions?
Solution :
Security access control ensures that unauthorized access attempts trigger
alarms.
1. Detect Unauthorized Access Attempts
property p_security_violation;
@(posedge clk) disable iff (!rst)
(unauthorized_request && !valid_key) |-> security_alert;
endproperty
ASSERT_SECURITY_VIOLATION: assert property (p_security_violation);
2. Check Role-Based Access Control Compliance
property p_role_access;
@(posedge clk) disable iff (!rst)
(user_role inside {ADMIN, USER}) |-> access_granted;
endproperty
ASSERT_ROLE_ACCESS: assert property (p_role_access);

34. How do you verify adaptive voltage scaling (AVS) logic using
assertions?
Solution :
AVS dynamically adjusts the voltage level based on processing demand.
1. Ensure Voltage Scaling Happens Correctly

property p_avs_scaling;
@(posedge clk) disable iff (!rst)
(high_processing_load) |-> ##[1:5] (voltage_level == HIGH);
endproperty
ASSERT_AVS_SCALING: assert property (p_avs_scaling);
2. Ensure Voltage Drops During Idle States
property p_avs_idle;
@(posedge clk) disable iff (!rst)
(!processing_active) |-> ##[5:10] (voltage_level == LOW);
endproperty
ASSERT_AVS_IDLE: assert property (p_avs_idle);

35. How do you verify system-wide rollback mechanisms using

assertions?
Solution :
Rollback mechanisms are critical for error handling and speculative
execution correction.
1. Ensure Correct Rollback Execution on Error Detection
property p_rollback_on_error;
@(posedge clk) disable iff (!rst)
(error_detected) |-> ##[1:3] rollback_occurred;
endproperty
ASSERT_ROLLBACK_ON_ERROR: assert property (p_rollback_on_error);
2. Verify Checkpoint Restoration After Rollback

property p_checkpoint_restore;
@(posedge clk) disable iff (!rst)
(rollback_occurred) |-> ##1 (system_state == saved_checkpoint);
endproperty
ASSERT_CHECKPOINT_RESTORE: assert property (p_checkpoint_restore);
36. How do you verify speculative execution security
vulnerabilities (e.g., Spectre, Meltdown) using assertions?
Solution :
Speculative execution vulnerabilities allow unauthorized access to
protected memory regions.
1. Ensure Speculative Execution Does Not Access Protected Memory
property p_spec_exec_protect;
@(posedge clk) disable iff (!rst)
(spec_exec_active && (access_addr inside {[SECURE_REGION]})) |->
security_violation;
endproperty
ASSERT_SPEC_EXEC_PROTECT: assert property (p_spec_exec_protect);

2. Ensure Memory Accesses Are Committed Before Execution Continues

property p_memory_commit;
@(posedge clk) disable iff (!rst)
(memory_access) |-> ##[1:10] memory_commit;
endproperty
ASSERT_MEMORY_COMMIT: assert property (p_memory_commit);

37. How do you verify priority-based arbitration in a shared bus

architecture using assertions?
Solution :
Arbitration ensures that higher-priority transactions get access to shared
resources first.
1. Ensure Higher Priority Requests Are Granted Before Lower Priority
Requests
property p_arbitration;
@(posedge clk) disable iff (!rst)
(high_prio_req && low_prio_req) |-> ##1 (grant == high_prio_req);
endproperty
ASSERT_ARBITRATION: assert property (p_arbitration);
2. Ensure Fairness in Arbitration (No Starvation)
property p_no_starvation;
@(posedge clk) disable iff (!rst)
(low_prio_req && !$past(grant, 10)) |-> ##[1:5] grant;
endproperty
ASSERT_NO_STARVATION: assert property (p_no_starvation);

38. How do you verify hardware security against side-channel attacks

using assertions?
Solution :
Side-channel attacks analyze power, timing, and EM leakage to extract
secrets.
1. Ensure Power Variations Are Not Correlated with Key Values
property p_power_leakage;
@(posedge clk) disable iff (!rst)
(crypto_op_active) |-> ##[1:5] (!power_variation_correlated);
endproperty
ASSERT_POWER_LEAKAGE: assert property (p_power_leakage);
2. Ensure Timing Does Not Reveal Cryptographic Operations

property p_timing_leakage;
@(posedge clk) disable iff (!rst)
(crypto_op_start) |-> ##[10:20] crypto_op_end;
endproperty
ASSERT_TIMING_LEAKAGE: assert property (p_timing_leakage);
39. How do you handle complex sequence randomization in a
UVM testbench for SoC verification?
Solution :
1. Use Layered Sequences for Better Control
class complex_sequence extends uvm_sequence#(transaction);
`uvm_object_utils(complex_sequence)
function new(string name = "complex_sequence");
super.new(name);
endfunction
task body();
transaction t;
repeat(10) begin
t = transaction::type_id::create("t");
start_item(t);
assert(t.randomize() with { addr inside {[0:4096]}; data dist {8'h00
:= 20, 8'hFF := 5, [8'h01:8'hFE] := 75}; });
finish_item(t);
end
endtask
endclass

2. Use Virtual Sequences to Coordinate Multiple Interfaces

class virtual_sequence extends uvm_sequence;
`uvm_object_utils(virtual_sequence)
my_axi_seq axi_seq;
my_pcie_seq pcie_seq;
task body();
fork
axi_seq.start(p_sequencer.axi_seqr);
pcie_seq.start(p_sequencer.pcie_seqr);
join
endtask
endclass
40. How do you verify correct retention register behavior across
power domains?
Solution :
1. Implement Assertions to Ensure Retention Registers Hold Values Across
Power Cycles
property p_retention_check;
@(posedge clk) disable iff (!rst)
(!power_on && $past(power_on)) |-> (ret_reg == $past(ret_reg));
endproperty
ASSERT_RETENTION_CHECK: assert property (p_retention_check);

2. Functional Coverage for Power-Up and Retention Transitions

covergroup power_state_cg;
power_domain: coverpoint power_state { bins active = {0}; bins
low_power = {1}; bins off = {2}; }
retention_enabled: coverpoint retention_signal;
cross power_domain, retention_enabled;
endgroup

41. How do you handle dynamic reconfiguration of testbench

components in UVM?
Solution :
Dynamic reconfiguration is required when testing multiple configurations
of an SoC without recompiling.
1. Use UVM Configuration Database for Dynamic Overrides
uvm_config_db#(int)::set(this, "env.agent.sequencer",
"max_outstanding_txns", 8);
uvm_config_db#(bit)::set(this, "env.scoreboard", "enable_scoreboard", 1);
2. Implement a UVM Factory Override for Dynamic Component
Selection

uvm_factory::get().set_type_override_by_type(base_sequencer::get_type(),
optimized_sequencer::get_type());

3. Change Virtual Sequences Based on Test Mode

class dynamic_test extends uvm_test;

function void build_phase(uvm_phase phase);
if (test_mode == "low_latency")
vseq = low_latency_seq::type_id::create("vseq");
else if (test_mode == "high_throughput")
vseq = high_throughput_seq::type_id::create("vseq");
endfunction
endclass

42. How do you verify AXI interconnect fairness and starvation

prevention?
Solution :
AXI interconnect must fairly arbitrate between multiple master devices
and prevent starvation.
1. Assertion to Ensure Each Master Gets Access Within a Time Limit
property p_axi_fairness;
@(posedge clk) disable iff (!rst)
(master_request && !grant) |-> ##[1:20] (grant);
endproperty
ASSERT_AXI_FAIRNESS: assert property (p_axi_fairness);

2. Functional Coverage for Arbitration Patterns

covergroup axi_arbitration_cg;
master_id: coverpoint master_request_id;
grant_order: coverpoint grant_order;
cross master_id, grant_order;
endgroup
43. How do you implement a self-checking testbench in UVM for
an SoC?
Solution :
A self-checking testbench automatically compares expected vs. actual
results without human intervention.
1. Implement a Scoreboard with a Reference Model
class self_checking_scoreboard extends uvm_scoreboard;
`uvm_component_utils(self_checking_scoreboard)

uvm_analysis_imp#(transaction, self_checking_scoreboard)
input_analysis_imp;

function new(string name, uvm_component parent);

super.new(name, parent);
endfunction

task write(transaction tr);

transaction expected_tr;
expected_tr = reference_model(tr);
if (tr.data !== expected_tr.data)
`uvm_error("SCOREBOARD", $sformatf("Mismatch: Got %0h,
Expected %0h", tr.data, expected_tr.data));
endtask
endclass

2. Connect the Scoreboard to the UVM Testbench

function void connect_phase(uvm_phase phase);
monitor.analysis_port.connect(scoreboard.input_analysis_imp);
endfunction
44. How do you verify PCIe completion ordering for non-posted
requests?
Solution :
1. Check That Completion Packets Are Returned in the Correct Order
property p_pcie_completion_order;
@(posedge clk) disable iff (!rst)
(req_valid && comp_valid) |-> (req_id == comp_id);
endproperty
ASSERT_PCIE_COMPLETION_ORDER: assert property
(p_pcie_completion_order);

2. Use Coverage for Different PCIe Completion Scenarios

covergroup pcie_completion_cg;
req_type: coverpoint pcie_req_type;
comp_order: coverpoint completion_id;
cross req_type, comp_order;
endgroup

45. How do you handle multi-interface communication in a UVM testbench

(e.g., AXI + PCIe + UART in an SoC)?
Solution :
Handling multiple interfaces requires coordinating sequences across
different interfaces using a virtual sequence.
1. Implement a Virtual Sequence to Control Multiple Interfaces
class multi_if_virtual_seq extends uvm_sequence;
`uvm_object_utils(multi_if_virtual_seq)

axi_seq axi_sequence;
pcie_seq pcie_sequence;
uart_seq uart_sequence;

task body();
axi_sequence = axi_seq::type_id::create("axi_sequence");
pcie_sequence = pcie_seq::type_id::create("pcie_sequence");
uart_sequence = uart_seq::type_id::create("uart_sequence");

fork
axi_sequence.start(p_sequencer.axi_sequencer);
pcie_sequence.start(p_sequencer.pcie_sequencer);
uart_sequence.start(p_sequencer.uart_sequencer);
join
endtask
endclass

2. Use UVM Configuration Database to Pass Interface Handles

uvm_config_db#(virtual axi_if)::set(this, "uvm_test_top.env.agent",
"axi_vif", axi_vif);
uvm_config_db#(virtual pcie_if)::set(this, "uvm_test_top.env.agent",
"pcie_vif", pcie_vif);
uvm_config_db#(virtual uart_if)::set(this, "uvm_test_top.env.agent",
"uart_vif", uart_vif);
46. How do you implement a reusable UVM agent that supports
both active and passive modes?
Solution :
A configurable UVM agent can act as a driver (active mode) or a monitor
(passive mode) based on test needs.
1. Implement a Configurable Agent
class my_agent extends uvm_agent;
`uvm_component_utils(my_agent)

my_monitor mon;
my_driver drv;
my_sequencer seq;
uvm_active_passive_enum is_active;

function new(string name, uvm_component parent);

super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);
mon = my_monitor::type_id::create("mon", this);
if (is_active == UVM_ACTIVE) begin
drv = my_driver::type_id::create("drv", this);
seq = my_sequencer::type_id::create("seq", this);
end
endfunction
endclass
2. Set Active or Passive Mode in the UVM Test
uvm_config_db#(uvm_active_passive_enum)::set(this,
"uvm_test_top.env.agent", "is_active", UVM_PASSIVE);
47. How do you verify AXI interconnect bandwidth utilization in
an SoC?
Solution :
Verifying AXI bandwidth utilization ensures that transactions meet
performance targets.
1. Measure Bus Utilization Using SystemVerilog Assertions
property p_axi_bandwidth_utilization;
@(posedge clk) disable iff (!rst)
(awvalid && awready) |-> ##[1:10] (wvalid && wready);
endproperty
ASSERT_AXI_BANDWIDTH: assert property (p_axi_bandwidth_utilization);

2. Functional Coverage for Different Data Throughput Scenarios

covergroup axi_bw_cg;
txn_size: coverpoint txn_size { bins small = {[1:32]}; bins large =
{[33:256]}; }
txn_rate: coverpoint txn_rate { bins low = {[0:10]}; bins high =
{[11:100]}; }
cross txn_size, txn_rate;
endgroup

48. How do you handle back-to-back sequence execution in a

UVM testbench?
Solution :
In complex testbenches, back-to-back sequences need to be synchronized
to avoid race conditions.
1. Use Sequence Arbitration to Enforce Order
class ordered_sequence extends uvm_sequence#(transaction);
`uvm_object_utils(ordered_sequence)

function new(string name = "ordered_sequence");

super.new(name);
endfunction

task body();
transaction tr;
repeat (5) begin
tr = transaction::type_id::create("tr");
start_item(tr);
assert(tr.randomize());
finish_item(tr);
end
endtask
endclass

2. Use UVM Raise/Drop Objections to Control Sequence Execution

task run_phase(uvm_phase phase);
phase.raise_objection(this);
seq1.start(p_sequencer);
seq2.start(p_sequencer);
phase.drop_objection(this);
endtask

49. How do you implement a UVM testbench that supports both

functional and directed testing?
Solution :
A testbench should support both randomized and directed verification.
1. Implement a Hybrid Test with Conditional Execution
class hybrid_test extends uvm_test;
`uvm_component_utils(hybrid_test)

function void build_phase(uvm_phase phase);

if (functional_mode)
seq = functional_seq::type_id::create("seq");
else
seq = directed_seq::type_id::create("seq");
endfunction
endclass

2. Functional Coverage to Measure Effectiveness of Functional and

Directed Tests

covergroup test_mode_cg;
mode: coverpoint test_mode { bins functional = {0}; bins directed =
{1}; }
endgroup

50. How do you ensure robust checking of register accesses in a

UVM testbench?
Solution :
UVM provides a Register Abstraction Layer (RAL) to automate register
verification.
1. Implement Read/Write Register Sequences
class reg_rw_seq extends uvm_reg_sequence;
`uvm_object_utils(reg_rw_seq)

function new(string name = "reg_rw_seq");

super.new(name);
endfunction

task body();
uvm_status_e status;
bit [31:0] read_data;

reg_model.ctrl_reg.write(status, 32'hA5A5A5A5);
reg_model.ctrl_reg.read(status, read_data);

if (read_data !== 32'hA5A5A5A5)

`uvm_error("REG_SEQ", "Register Read-Write Mismatch!");
endtask
endclass

2. Functional Coverage for Register Accesses

covergroup reg_access_cg;
addr: coverpoint reg_model.addr;
access_type: coverpoint reg_model.access;
cross addr, access_type;
endgroup
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