Gray Code:

The reflected binary code or Gray code is an ordering of the binary numeral system such that two successive
values differ in only one bit (binary digit). Gray codes are very useful in the normal sequence of binary
numbers generated by the hardware that may cause an error or ambiguity during the transition from one
number to the next. So, the Gray code can eliminate this problem easily since only one bit changes its value
during any transition between two numbers.
Gray code is not weighted that means it does not depends on positional value of digit. This is cyclic variable
code that means every transition from one value to the next value involves only one bit change.

Gray code also known as reflected binary code, because the first (n/2) values compare with those of the last
(n/2) values, but in reverse order.

Binary to Gray code conversion:

Step 1: Record the MSB as it is.
Step 2: Add the MSB to the next bit, record the sum and neglect the carry. (Also perform X-OR)
Step 3: Repeat the process.
Ex: Convert 1001 to gray code.
Soln: 1011-1110

Table for Binary to Gray code:

Decimal code Binary Code Gray Code
B3 B2 B1 B0 G3 G1 G2 G0
0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000

Computer Instructions
Computer instructions are a set of machine language instructions that a particular processor understands and
executes. A computer performs tasks on the basis of the instruction provided.
An instruction comprises of groups called fields. These fields include:
1. The Operation code (Opcode) field which specifies the operation to be performed.

Compiled By: - Er. Sohan Acharya

 2. The Address field which contains the location of the operand, i.e., register or memory location.
3. The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction
2. Register - reference instruction
3. Input-Output instruction

Memory - reference instruction:

In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify the
addressing mode 'I'.
Register - reference instruction:

The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit (bit 15) of
the instruction.
Input-Output instruction:

Just like the Register-reference instruction, an Input-Output instruction does not need a reference to memory
and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12
bits are used to specify the type of the input-output operation or test performed.

Alphanumeric characters:
Alphanumeric characters comprise the combination of the twenty-six characters of the alphabet (from A to Z)
and the numbers 0 to 9. Therefore, 1, 2, q, f, m, p, and 10 are all examples of alphanumeric characters.
Symbols like *, & and @ are also considered alphanumeric characters.

These characters can also be used in combination. Examples of alphanumeric characters made of the
combination of special symbols, numbers, and the characters of the alphabet are &AF54hh, jjHF47, @qw99O.

Compiled By: - Er. Sohan Acharya

The characters of the alphabet can either be in lower case or upper case. The context of use determines
whether or not case sensitivity is applied.

Since computers (or central processing units, to be specific) use machine language in the form of numbers to
communicate, computer programmers need to write their instructions using numbers rather than alphabet
characters. To do this, programmers use numeric representations of what humans see as alphabet characters.
You’ve probably seen or heard of binary code that uses only 0s and 1s to represent an alphanumeric
character. Computer programmers can use a series of 0s and 1s to represent any character they wish. For
example, in binary, the letter ‘A’ would be written as 01000001.

Another way computer programmers represent alphanumeric characters is to use ASCII. ASCII stands for
American Standard Code for Information Interchange.

Modulo:
When we divide two integers we will have an equation that looks like the following:
A/B = Q remainder R
Where,
A is the dividend
B is the divisor
Q is the quotient
R is the remainder

Sometimes, we are only interested in what the remainder is when we divide A by B.

For these cases there is an operator called the modulo operator (abbreviated as mod).

Using the same A, B, Q, and R as above, we would have: A mod B = R

We would say this as A modulo B is equal to R.
Where B is referred to as the modulus.

Compiled By: - Er. Sohan Acharya

Modulo2:
In modulo 2, when we divide any integer value it will give remainder either 0 or 1.
Suppose, if we divide 0 to 5 numbers using modulo 2, then result will be,
0/2 = 0
1/2 = 1
2/2 = 0
3/2 = 1
4/2 = 0
5/2 = 1

In modulo 2, the remainders from 0 and changes to 1. Again 1 changes to 0. This cycle sequence repeats for
the n number of integer.
In programming we use % to check the remainder using given modulo. For the 0 to 5 numbers, remainder will
be using modulo2.
0%2 = 0
1%2 = 0
2%2 = 1
2%2 = 0
3%2 = 1
4%2 = 0
5%2 = 1

Note: Modulo 2 arithmetic is performed digit by digit on binary numbers. Binary arithmetic is also known as modulo2
arithmetic.

BCD or Binary Coded Decimal:

Binary Coded Decimal, or BCD, is another process for converting decimal numbers into their binary
equivalents.

 It is a form of binary encoding where each digit in a decimal number is represented in the form of
bits.
 This encoding can be done in either 4-bit or 8-bit (usually 4-bit is preferred).
 It is a fast and efficient system that converts the decimal numbers into binary numbers as
compared to the existing binary system.
 These are generally used in digital displays where is the manipulation of data is quite a task.
 Thus BCD plays an important role here because the manipulation is done treating each digit as a
separate single sub-circuit.

Consider the following truth table and focus on how these are represented.
Truth Table for Binary Coded Decimal
DECIMAL NUMBER BCD
0 0000
1 0001

Compiled By: - Er. Sohan Acharya

 2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

In the BCD numbering system, the given decimal number is segregated into chunks of four bits for each
decimal digit within the number. Each decimal digit is converted into its direct binary form (usually
represented in 4-bits).
It is noticeable that the BCD is nothing more than a binary representation of each digit of a decimal number.
It cannot be ignored that the BCD representation of the given decimal number uses extra bits, which makes it
heavy-weighted.

Parity method for error detection:

Error is a condition when the output information does not match with the input information. During
transmission, digital signals suffer from noise that can introduce errors in the binary bits travelling from one
system to other. That means a 0 bit may change to 1 or a 1 bit may change to 0.

Whenever a message is transmitted, it may get scrambled by noise or data may get corrupted. To avoid this,
we use error-detecting codes which are additional data added to a given digital message to help us detect if an
error occurred during transmission of the message. A simple example of error-detecting code is parity check.

To detect and correct the errors, additional bits are added to the data bits at the time of transmission.
 The additional bits are called parity bits. They allow detection or correction of the errors.
 The data bits along with the parity bits form a code word.

Compiled By: - Er. Sohan Acharya

It is the simplest technique for detecting and correcting errors. The MSB of an 8-bits word is used as the parity
bit and the remaining 7 bits are used as data or message bits. The parity of 8-bits transmitted word can be
either even parity or odd parity.

Even parity: Even parity means the number of 1's in the given word including the parity bit should be even
(2,4,6,....).
Odd parity: Odd parity means the number of 1's in the given word including the parity bit should be odd
(1,3,5,....).

The parity bit can be set to 0 and 1 depending on the type of the parity required.
 For even parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is even.
 For odd parity, this bit is set to 1 or 0 such that the no. of "1 bits" in the entire word is odd.

Message (XYZ) P(Odd) P(Even)

000 1 0
001 0 1
010 0 1
011 1 0
100 0 1
101 1 0
110 1 0
111 0 1

Parity checking at the receiver can detect the presence of an error if the parity of the receiver signal is
different from the expected parity. That means, if it is known that the parity of the transmitted signal is always
going to be "even" and if the received signal has an odd parity, then the receiver can conclude that the
received signal is not correct. If an error is detected, then the receiver will ignore the received byte and
request for retransmission of the same byte to the transmitter.

Compiled By: - Er. Sohan Acharya

Boolean algebra: Boolean algebra is a branch of mathematics that deals with operations on logical values
with binary variables. It is used to analyze and simplify the digital (logic) circuits. It uses only the binary
numbers i.e. 0 and 1. It is also called as Binary Algebra or logical Algebra. Boolean algebra was invented
by George Boole in 1854.

Rule in Boolean algebra

Following are the important rules used in Boolean algebra.
 Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW.
 Complement of a variable is represented by an overbar (-). Thus, complement of variable B is
represented as . Thus if B = 0 then = 1 and B = 1 then = 0.
 ORing of the variables is represented by a plus (+) sign between them. For example ORing of A, B, C
is represented as A + B + C.
 Logical ANDing of the two or more variable is represented by writing a dot between them such as
A.B.C. Sometime the dot may be omitted like ABC.

Boolean Laws:
There are six types of Boolean Laws.
1. Commutative law
Commutative law states that changing the sequence of the variables does not have any effect on the
output of a logic circuit.

2. Associative law
This law states that the order in which the logic operations are performed is irrelevant as their effect is the
same.

3. Distributive law
Distributive Law states that the multiplication of two variables and adding the result with a variable will
result in the same value as multiplication of addition of the variable with individual variables.

A+(B.C) = (A+B).(A+C)
4. AND law
These laws use the AND operation. Therefore they are called as AND laws.

5. OR law
These laws use the OR operation. Therefore they are called as OR laws.

Compiled By: - Er. Sohan Acharya

 6. INVERSION law
This law uses the NOT operation. The inversion law states that double inversion of a variable results in the
original variable itself.

DeMorgan’s Theorem:
DeMorgan’s Theorems are basically two sets of rules or laws developed from the Boolean expressions of
AND, OR and NOT using two input variables, A and B. These two rules or theorems allow the input variables to
be negated and converted from one form of a Boolean function into an opposite form.

DeMorgan’s First Theorem: DeMorgan’s First theorem proves that when two (or more) input variables
are AND’ed and negated, they are equivalent to the OR of the complements of the individual variables. Thus
the equivalent of the NAND function will be a negative-OR function, proving that (A.B)’ = A’+B’. We can show
this operation using the following table.
Verifying DeMorgan’s First Theorem using Truth Table
Inputs Truth Table Outputs For Each Term
B A A.B (A.B)’ A’ B’ A’ + B’
0 0 0 1 1 1 1
0 1 0 1 0 1 1
1 0 0 1 1 0 1
1 1 1 0 0 0 0

We can also show that (A.B)’ = A’+B’ using logic gates as shown.

DeMorgan’s First Law Implementation using Logic Gates

The top logic gate arrangement of: (A.B)’ can be implemented using a standard NAND gate with
inputs A and B. The lower logic gate arrangement first inverts the two inputs producing A’ and B’. These then
become the inputs to the OR gate. Therefore the output from the OR gate becomes: A’+B’

Compiled By: - Er. Sohan Acharya

Then we can see here that a standard OR gate function with inverters (NOT gates) on each of its inputs is
equivalent to a NAND gate function. So an individual NAND gate can be represented in this way as the
equivalency of a NAND gate is a negative-OR.

DeMorgan’s Second Theorem: DeMorgan’s Second theorem proves that when two (or more) input variables
are OR’ed and negated, they are equivalent to the AND of the complements of the individual variables. Thus
the equivalent of the NOR function is a negative-AND function proving that (A+B)’ = A’.B’, and again we can
show operation this using the following truth table.
Verifying DeMorgan’s Second Theorem using Truth Table
Inputs Truth Table Outputs For Each Term
B A A+B (A+B)’ A’ B’ A’.B’
0 0 0 1 1 1 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 0 0 0 0

We can also show that (A+B)’ = A’.B’ using the following logic gates example.
DeMorgan’s Second Law Implementation using Logic Gates

The top logic gate arrangement of: (A+B)’ can be implemented using a standard NOR gate function using
inputs A and B. The lower logic gate arrangement first inverts the two inputs, thus producing A’ and B’. Thus
then become the inputs to the AND gate. Therefore the output from the AND gate becomes: A’.B’

Then we can see that a standard AND gate function with inverters (NOT gates) on each of its inputs produces
an equivalent output condition to a standard NOR gate function, and an individual NOR gate can be
represented in this way as the equivalency of a NOR gate is a negative-AND.

Universality of NAND or NOR gates:

A universal gate is a logic gate which can implement any Boolean function without the need to use any other
type of logic gate. The NOR gate and NAND gate are universal gates. This means that you can create any
logical Boolean expression using only NOR gates or only NAND gates.
NAND Gate as a Universal Gaste:

Compiled By: - Er. Sohan Acharya

 1. NOT gate using only NAND gate: This is the circuit diagram of a NAND gate used to make work like a
NOT gate.

2. AND gate using only NAND gate: The below diagram is of an AND gate made from NAND gate.

3. OR gate using only NAND gate: The below diagram is of an OR gate made from combinations of NAND
gates, arranged in a proper manner.

NOR Gate as a Universal Gate:

1. NOT gate using only NOR gate: The below diagram is of a NOT gate made by using a NOR gate.

2. AND gate using only NOR gate: The above diagram as the name suggests is of AND gate using only NOR
gate.

3. OR gate using only NOR gate: The below diagram is of an OR gate made by only using NOR gates. The
output of this gate is exactly similar to that of a single OR gate.

Tristate Logic:
In digital electronics three-state, tri-state, or 3-state logic allows an output port to assume a high
impedance state, effectively removing the output from the circuit, in addition to the 0 and 1 logic levels.

Compiled By: - Er. Sohan Acharya

 This allows multiple circuits to share the same output line or lines (such as a bus which cannot listen to
more than one device at a time).
Three-state outputs are implemented in many registers, bus drivers, and flip-flops in
the 7400 and 4000 series as well as in other types, but also internally in many integrated circuits. Other typical
uses are internal and external buses in microprocessors, computer memory, and peripherals. Many devices
are controlled by an active-low input called OE (Output Enable) which dictates whether the outputs should be
held in a high-impedance state or drive their respective loads (to either 0- or 1-level).
The term tri-state should not be confused with ternary logic (3-value logic).
INPUT OUTPUT
A B C
0 0 Z (high impedance)
1 Z (high impedance)
0 1 0
1 1

A tristate buffer can be thought of as a switch. If B is on, the switch is closed. If B is off, the switch is open.

Venn diagram:
A Venn diagram is a visual representation of the outputs of a logic gate with different inputs. A Venn
diagram can be easily created with the truth tables.
Venn diagrams look exactly like the traditional Venn diagram.

Each space represents the input type and each circle represents an input of 1. The area that is not
inside either of the circles is 00. The area inside one circle would be 10 and 01. The area inside both the circles
then would be 11. This is the layout for a two input logic gate.

Compiled By: - Er. Sohan Acharya

To represent the outputs, the spaces are either filled in or not. If the area is filled in, it means that the input of
that area has an output of 1. If it is not filled in and left empty, the output would be 0.

Here are a couple of examples of Venn diagrams for different gates.

Test Vector:
Test vectors mean a listing of all possible inputs and their expected outputs in order to check the
correctness of a system. Logic gates may generate a wrong output signal because of a fault in the circuitry that
implements the gate.
Most circuits use logic gates as the basic building blocks. A good model for representing faults in such
circuits is to assume that all faults appear as some wires (input and output of gates) being permanently stuck
at logic value 0 or 1. Consider a wire w has an undesirable signal that always corresponds to the logic value 0

Compiled By: - Er. Sohan Acharya

by saying that w is stuck at 0, which is denoted by w/0. If w has an undesirable signal that is always equal to
logic 1, then w is stuck at 1, which is denoted as w/1.
A circuit can be faulty because it has either a single fault or possible many faults. Dealing with multiple
faults is difficult because each fault can occur many different ways. A practical approach is to consider single
fault only. A fault is detected if the output value produced by the faulty circuit is different from the value
produced by the good circuit when an appropriate test is applied as input. Each test is supposed to able to
detect the occurrence of one or more faults. A complete set of tests used for a given circuits is referred to as
the test set.

Which faults will be detected by applying inputs w1w2w3 = 000?

In the above circuit, there is total 5 wires and faults may be due to any one of these 5 wires. So we
check each wire for input 0 and 1.
Test Fault Detected
w1w2w3 a/0 a/1 b/0 b/1 c/0 c/1 d/0 d/1 f/0 f/1
000 √ √ √
001 √ √ √ √
010 √ √ √ √
011 √ √ √ √
100 √ √
101 √ √
110 √ √
111 √
When, w1w2w3 are 000 correct output is 0, but a faulty circuit will give you output 1. This fault may be
due to wire ‘a’ stuck in 1, or wire ‘d’ stuck in 1 or wire f stuck in 1.

Combinational circuit design procedure:

A Combinational Circuit consist of logic gates whose outputs at any instant of time are determined
directly from the present combination of inputs without regard to previous input.
Here we are going to learn how to construct and analyze any type of combinational circuit using four
general steps.
Following are the four steps to construct and analyze any combinational circuit.
 Step-1: Identify the number of inputs and outputs of the circuit.
First of all, we have to think about the inputs and outputs of the circuit by considering which type of
logical operation we want to perform with the circuit.
For example, we have to create a circuit that can add two bits. For this, we require two inputs (one for
the first bit (A) another for the second bit (B)) and two outputs one for sum (S) of two bits and another for
carry (C).

Compiled By: - Er. Sohan Acharya

 In total, we require 2 inputs and 2 outputs. So here our first step is completed.
 Step-2: Creating the Truth Table.
In this step we have to create truth table for our circuit so for this first we will create input columns
and list all the possible combinations of inputs. In our case 2 bits can have maximum 4 combinations.
Now in output, we have two columns (Sum and Carry) as discussed earlier. Now we have to fill output
columns in such a way that for which logical operation we are constructing circuit.
In our circuit, we want addition so we will add those input bits and write the sum of those bits in (Sum)
column and if carry is generated we will write 1 else write 0 in (Carry) column.

 Step-3: Simplify the Boolean function for each output.

In this step, we have to just create a simplified Boolean function according to inputs and outputs of the
truth table obtained in the previous step.
For Sum,
Sum = A'B + AB' = A XOR B
For Carry,
Carry = AB = A AND B

 Step-4: Constructing circuit using Boolean function obtained from third step.
For sum, we have obtained (A XOR B) so we will connect A and B to the inputs of XOR gate and take its
output as a sum. For carry, we have obtained (A AND B) so we will connect A and B to the inputs of AND
gate and take its output as a carry.

Compiled By: - Er. Sohan Acharya

 Now in this circuit, if you provide input at A and B ends. You will get the output on sum and carry ends
according to truth table we have created above. So here we have completed our four steps for creating
the combinational circuit.

Adder and Subtractors:

Half Adder:

It is an arithmetic combinational logic circuit designed to perform addition of two single bits. It contain
two inputs and produces two outputs. Inputs are called Augend and Added bits and Outputs are called Sum
and Carry.

Let us observe the addition of single bits,

0+0=0
0+1=1
1+0=1
1+1=10

Since 1+1=10, the result must be two bit output. So, Above can be rewritten as,
0+0=00
0+1=01
1+0=01
1+1=10

The result of 1+1 is 10, where ‘1’ is carry-output (Cout) and ‘0’ is Sum-output (Normal Output).

Truth Table of Half Adder:

Next Step is to draw the Logic Diagram. To draw Logic Diagram, We need Boolean Expression, which
can be obtained using K-map. Since there are two output variables ‘S’ and ‘C’, we need to define K-map for
each output variable.

Compiled By: - Er. Sohan Acharya

K-map for output variable Sum ‘S’:

K-map is of Sum of products form. The equation obtained is

S = AB' + A'B
Which can be logically written as,
S = A XOR B
K-map for output variable Carry ‘C’:

The equation obtained from K-map is,

C = AB =A AND B

Compiled By: - Er. Sohan Acharya

Using the Boolean Expression, we can draw logic diagram as follows,

Limitations:
Adding of Carry is not possible in half adder.

Full Adder:
To overcome the above limitation faced with Half adders, Full Adders are implemented. It is a
arithmetic combinational logic circuit that performs addition of three single bits. It contains three inputs (A, B,
Cin) and produces two outputs (Sum and Cout). Where, Cin -> Carry In and Cout -> Carry Out

Truth table of Full Adder:

Compiled By: - Er. Sohan Acharya

K-map Simplification for output variable Sum ‘S’:

The equation obtained is,

S = A'B'Cin + AB'Cin' + ABC + A'BCin'
The equation can be simplified as,
S = B'(A'Cin+ACin') + B(AC + A'Cin')
S = B'(A XOR Cin) + B (A XNOR Cin)
S = A XOR B XOR CIN

K-map Simplification for output variable ‘Cout‘:

The equation obtained is,

Cout = BCin + AB + ACin

Logic Diagram of Full Adder:

Compiled By: - Er. Sohan Acharya

Half Subtractor:

It is a combinational logic circuit designed to perform subtraction of two single bits. It contains two
inputs (A and B) and produces two outputs (Difference and Borrow-output).
Truth Table of Half Subtractor:

K-map Simplification for output variable ‘D’:

The equation obtained is,

D = A'B + AB'
Which can be logically written as,
D = A XOR B
K-map Simplification for output variable ‘Bout‘:

Compiled By: - Er. Sohan Acharya

The equation obtained from above K-map is,
Bout = A'B

Logic Diagram of Half Subtractor:

Full Subtractor
It is a Combinational logic circuit designed to perform subtraction of three single bits. It contains three
inputs (A, B, Bin) and produces two outputs (D, Bout). Where, A and B are
called Minuend and Subtrahend bits. And, Bin -> Borrow-In and Bout -> Borrow-Out

Truth Table of Full Subtractor:

Compiled By: - Er. Sohan Acharya

K-map Simplification for output variable ‘D’:

The equation obtained from above K-map is,

D = A'B'Bin + AB'Bin' + ABBin + A'BBin'
Which can be simplified as,
D = B'(A'Bin + ABin') + B(ABin + A'Bin')
D = B'(A XOR Bin) + B(A XOR Bin)'
D = A XOR B XOR BIN

K-map Simplification for output variable ‘Bout‘:

The equation obtained is,

Bout = BBin + A'B + A'Bin

Logic Diagram of Full Subtractor:

Compiled By: - Er. Sohan Acharya

Code Conversion:
The Code converter is used to convert one type of binary code to another. There are different types of
binary codes like BCD code, gray code, excess-3 code, etc.

Binary to BCD code converter:

In BCD code, 0 to 9 numbers represent the equivalent binary numbers. For the numbers above 10, LSB
of a decimal number is represented by its equivalent binary number and MSB of a decimal number is also
represented by their equivalent binary numbers.
The following truth table shows the conversion between the binary code input and the BCD code
output. As you see from the table, the 4-bit binary number is converted into 5-bit BCD code. Decimal code is
added in the table to understand the equivalence of Binary and BCD code.

The converter has 5 outputs D0, D1, D2, D3 and D4. From the truth table, the minterms can be obtained
for each output.
D4 = ∑m(10, 11, 12, 13, 14, 15)
D3 = ∑m(8, 9)
D2 = ∑m(4, 5, 6, 7, 14, 15)
D1 = ∑m(2, 3, 6, 7, 12, 13)
D0 = ∑m(1, 3, 5, 7, 9, 11, 13, 15)

The minterms are plotted in the karnaugh map and the simplified boolean expressions are obtained.

Compiled By: - Er. Sohan Acharya

 For D4 Output: ∑m(10, 11, 12, 13, 14, 15)

 For D3 Output: ∑m(8, 9)

 For D2 Output: ∑m(4, 5, 6, 7, 14, 15)

 For D1 Output: ∑m(2, 3, 6, 7, 12, 13)

Compiled By: - Er. Sohan Acharya

  For D1 Output: ∑m(1, 3, 5, 7, 9, 11, 13, 15)

The digital logic circuit for Binary to BCD code converter is designed from the simplified output
expressions obtained from karnaugh map.

BCD to Excess-3 code converter:

For this conversion process, 4-bit BCD code is considered as input, which is converted into 4-bit Excess-
3 code. Since 4-bit is considered for BCD code, the output is produced only for the inputs from 0 to 9.

Compiled By: - Er. Sohan Acharya

 The truth table shown below has only the valid 4-bit BCD codes. For the remaining input combinations,
the output cannot be predicted. So they are don’t care outputs.

From the truth table, the minterms are obtained for each outputs(E3, E2, E1, E0).
E3 = ∑m(5, 6, 7, 8, 9)
E2 = ∑m(1, 2, 3, 4, 9)
E1 = ∑m(0, 3, 4, 7, 8)
E0 = ∑m(0, 2, 4, 6, 8)

The minterms of each output in plotted in k-map and simplified expression is obtained.

Compiled By: - Er. Sohan Acharya

The combinational logic circuit for BCD code to Excess-3 code conversion is drawn from the obtained boolean
expressions.

BCD to Gray code converter:

The truth table having the conversion from BCD code to gray code is shown below. Since the BCD code
has only 4 bits, a total of 9 BCD digits have been considered. The output is unpredictable for other input
combinations.

From the minterms of each output G3, G2, G1, G0, the karnaugh map is implemented to simplify the
function.
G3 = ∑m(8, 9) + d(10,11,12,13,14,15)

Compiled By: - Er. Sohan Acharya

 G2 = ∑m(4, 5, 6, 7, 8, 9) + d(10,11,12,13,14,15)
G1 = ∑m(2, 3, 4, 5) + d(10,11,12,13,14,15)
G0 = ∑m(1, 2, 5, 6, 9) + d(10,11,12,13,14,15)

The code converter circuit for BCD to gray code is drawn as below from the obtained expression.

Compiled By: - Er. Sohan Acharya

INVERT-AND
INVERT-AND mean INVERTER connected to the input of AND gate. According to DE Morgan’s law,
Inverting the inputs of the AND gate convert it into NOR gate. INVERT-AND symbol is given below.

(A’.B’.C’ ) = (A + B + C )’

INVERT-AND symbol consists of AND gate with a bubble at each input for complementation
(inversion). These symbols are used for converting a circuit into NOR gates.

Two-Level Implementation using NOR Gate:

The maximum number of levels that are present between inputs and output is two in two level logic.
Implementing Two-Level logic using NOR gate requires the Boolean expression to be in Product of Sum (POS) form. In
Product of Sum form, 1st level of the gate is OR gate and 2nd level of the gate is AND gate.

To implement a Boolean function using NOR gate, there are basically three step;
1. Product of Sum Form: First, you need to have a simplified Product of Sum expression for the function you need
to implement. Simplified Product of Sum expression can be made using Karnaugh Map (K-map).
Suppose we have simplified POS expression.
F = (A+B)(C+D)
Draw its logic diagram using AND-OR NOT gates as shown in the figure given below.

2. Mixed Notation: Next step is to draw the above-mentioned logic diagram using OR-Invert and Invert-AND gates.
OR-Invert should replace OR gates and invert-AND replaces AND gates. This schematic is said to be in mixed
notation and its schematic is given below.

A bubble means complement. Two bubbles along a line mean double complementation and they cancel
each other. However, a single bubble along a line should be compensated by making a complemented input if
available.

Compiled By: - Er. Sohan Acharya

NOR Gate Conversion: The last step is to redraw the whole schematic replacing OR-Invert and Invert-AND
gate symbol by NOR gate symbol because OR-Invert and Invert-AND are equivalent to NOR gate. The final
schematic is shown in the figure given below.

Example:
F = (A+B)(B+C)D
This function is in simplified Product of Sum form. First, we need to draw its OR-AND schematic.

Now we convert the above-given schematic into mixed notation by converting OR gate into OR-INVERT and AND
gate into INVERT-AND.

Input line D to the input of AND gate has a single bubble. To compensate this bubble we need complement the
input D. Now replace every OR-Invert and Invert-AND with NOR gate as shown in the figure given below.

Compiled By: - Er. Sohan Acharya

Multi-level Implementation using NOR Gate: Schematic having more than two levels of gates is known as a
multi-level schematic. We can implement multi-level POS expression using NOR gate. The conversion of multi-level
expression into NOR gate has the same method as two-level implementation.
The multi-level expression can be converted into two-level expression but for the sake of realization, we will implement
a multi-level expression.

Suppose a 4-level function:

F = ( A + B ( C + D )) ( B + D’ )

First, we will draw its schematic using AND, OR, NOT gates.

Notice the OR-AND pattern like two-level implementation. It can be easily converted since the bubble cancels each
other.

Now we will convert it into mixed notation for NOR.

The two bubbles along a single line cancel each other. However, there is a single bubble at the 2nd level gate’s input. So
we will complement the input B to compensate the bubble.

Now redraw the whole schematic replacing OR-Invert and Invert-AND with NOR gate symbol as shown in the figure
below.

INVERT-OR
INVERT-OR means Inverter (NOT gate) connected to the input of OR gate. According to DE Morgan’s law, Inverting the
inputs to the OR gate makes it a NAND gate. So INVERT-OR symbol represents NAND gate and it is given in the figure
below.

Compiled By: - Er. Sohan Acharya

INVERT-OR symbol consists of OR gate with small circles (bubble) at the input for inversion.
These both symbols are used for converting a schematic into NAND gates. When both of these symbols are used in a
schematic the circuit is known to be in mixed notation.

Two-Level Implementation using NAND Gate: Two-level implementation means that any path from input
to output contains maximum two levels hence the name two-level for the two levels of gates.
Implementing a two-level schematic with NAND gates require the expression to be in Sum of Product (SOP)
form. In Sum of Product form, the 1st level of the gate is AND gate and the 2nd level of the gate is OR gate. It can be
easily converted into NAND gates.

To convert any function into two-level NAND schematic there are 3 steps;

Sum of Product Form: First, you need to have simplified Sum of Product (SOP) form for the Boolean function.
Karnaugh map (K-map) or Boolean algebraic theorems can be used to get a Simplified SOP expression.
Suppose an SOP function F = A B + C D
This SOP function is in Simplified SOP form and its AND-OR schematic is given below.

Mixed Notation: 2nd step is to convert the AND-OR schematic into mixed notation. In mixed notation for NAND
gate, AND gate is converted into AND-invert and OR gate is converted into INVERT-OR. Mixed notation design
for the above function is given below.

Compiled By: - Er. Sohan Acharya

NAND Gate Conversion & Example: The third step is to convert the AND-INVERT and INVERT-OR symbols into
its equivalent NAND gate symbol. NAND gate schematic of above function is given below.

Example
Suppose a function F = A B + B C + D to be implemented using NAND gates

This function is in simplified Sum of Product form. First, we need to draw its AND-OR schematic.

Now we convert the above-given schematic into mixed notation by converting AND gate into AND-INVERT and OR gate
into INVERT-OR.

Notice the single input D line to the OR gate. There is one bubble on this line. To compensate this bubble we need to
complement the input D. Then convert AND-INVERT and INVERT-OR symbol into NAND symbol as shown in the figure.

MULTI-LEVEL Implementation using NAND Gate: Schematic having more than two levels of gates is known
as a multi-level schematic. We can implement multi-level SOP expression using NAND gate. The conversion of multi-level
expression into NAND gate has the same method as two-level implementation.
The multi-level expression can be converted into two-level expression but for the sake of realization, we will
implement a multi-level expression.
Suppose a multi-level function be;
F = A ( B + CD ) + BD’
This is a four-level function

Compiled By: - Er. Sohan Acharya

First, we will draw its AND-OR schematic

Notice the AND-OR pattern. So it can be easily converted into NAND gates. Now we will convert this into mixed notation
i.e. AND gate will be converted into AND-INVERT and OR will be converted into INVERT-OR as shown in the figure given
below.

Notice the 3rd line of input B, there is a single bubble. To compensate this bubble, either an inverter should be added or
the input B should be complimented.
Then redraw the whole schematic using all NAND gates by replacing AND-INVERT and INVERT-OR with NAND gates as
shown in the figure below.

Parity Generator and Checker:

A Parity Generator is a combinational logic circuit that generates the parity bit in the transmitter. On the other hand, a
circuit that checks the parity in the receiver is called Parity Checker. A combined circuit or device of parity generators
and parity checkers are commonly used in digital systems to detect the single bit errors in the transmitted data.

Even Parity and Odd Parity:

The sum of the data bits and parity bits can be even or odd. In even parity, the added parity bit will make the total
number of 1s an even number, whereas in odd parity, the added parity bit will make the total number of 1s an odd
number.

Parity Generator:

Compiled By: - Er. Sohan Acharya

It is combinational circuit that accepts an n-1 bit data and generates the additional bit that is to be transmitted with the
bit stream. This additional or extra bit is called as a Parity Bit.

Even Parity Generator:

In even parity bit scheme, the parity bit is ‘0’ if there are even number of 1s in the data stream and the parity bit is ‘1’ if
there are odd number of 1s in the data stream.

Let us assume that a 3-bit message is to be transmitted with an even parity bit. Let the three inputs A, B and C are
applied to the circuit and output bit is the parity bit P. The total number of 1s must be even, to generate the even parity
bit P.

The figure below shows the truth table of even parity

generator in which 1 is placed as parity bit in order
to make all 1s as even when the number of 1s in the
truth table is odd.

The K-map simplification for 3-bit message even parity

generator is

From the above truth table, the simplified expression

of the parity bit can be written as

The above expression can be implemented by using two Ex-OR gates. The logic diagram of even parity generator with
two Ex – OR gates is shown below. The three bit message along with the parity generated by this circuit which is
transmitted to the receiving end where parity checker circuit checks whether any error is present or not.

To generate the even parity bit for a 4-bit data, three Ex-OR gates are required to add the 4-bits and their sum will be
the parity bit.

Compiled By: - Er. Sohan Acharya

Odd Parity Generator:

In odd parity bit scheme, the parity bit is ‘1’ if there are even number of 1s in the data stream and the parity bit is ‘0’ if
there are odd number of 1s in the data stream. Let us discuss both even and odd parity generators.

Let us consider that the 3-bit data is to be transmitted with

an odd parity bit. The three inputs are A, B and C and P is
the output parity bit. The total number of bits must be odd
in order to generate the odd parity bit.

In the given truth table below, 1 is placed in the parity bit in

order to make the total number of bits odd when the total
number of 1s in the truth table is even.

The truth table of the odd parity generator can be simplified

by using K-map as

The output parity bit expression for this generator circuit is

obtained as

The above Boolean expression can be implemented by using one Ex-OR gate and one Ex-NOR gate in order to design a 3-
bit odd parity generator.

Compiled By: - Er. Sohan Acharya

The logic circuit of this generator is shown in below
figure, in which two inputs are applied at one Ex-OR
gate, and this Ex-OR output and third input is applied to
the Ex-NOR gate, to produce the odd parity bit. It is also
possible to design this circuit by using two Ex-OR gates
and one NOT gate.

Parity Checker:
It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even parity checker or odd
parity checker depending on the type of parity generated at the transmission end. When this circuit is used as even
parity checker, the number of input bits must always be even.

Even Parity Checker:

Consider that three input message along with even parity bit is generated at the transmitting end. These 4 bits are
applied as input to the parity checker circuit, which checks the possibility of error on the data. Since the data is
transmitted with even parity, four bits received at circuit must have an even number of 1s.

If any error occurs, the received message consists of odd

number of 1s. The output of the parity checker is denoted
by PEC (Parity Error Check).

The below table shows the truth table for the Even Parity
Checker in which PEC = 1 if the error occurs, i.e., the four
bits received have odd number of 1s and PEC = 0 if no error
occurs, i.e., if the 4-bit message has even number of 1s.

The above truth table can be simplified using K-map as

shown below.

Compiled By: - Er. Sohan Acharya

The above logic expression for the even parity checker can be implemented by using three Ex-OR gates as shown in
figure. If the received message consists of five bits, then one more Ex-OR gate is required for the even parity checking.

Odd Parity Checker: Consider that a three bit message along

with odd parity bit is transmitted at the transmitting end. Odd
parity checker circuit receives these 4 bits and checks whether
any error are present in the data.

If the total number of 1s in the data is odd, then it indicates no

error, whereas if the total number of 1s is even then it indicates
the error since the data is transmitted with odd parity at
transmitting end.

The below figure shows the truth table for odd parity generator
where CP =1 if the 4-bit message received consists of even
number of 1s (hence the error occurred) and CP= 0 if the
message contains odd number of 1s (that means no error).

Compiled By: - Er. Sohan Acharya

The expression for the PEC in the above truth table can be simplified
by K-map as shown below.

After simplification, the final expression for the PEC is obtained as

PEC = (A Ex-NOR B) Ex-NOR (C Ex-NOR P)

The expression for the odd parity checker can be designed by using
three Ex-NOR gates as shown below.

Compiled By: - Er. Sohan Acharya

Binary Adder and Subtractor: In Digital Circuits, A Binary Adder-Subtractor is one which is capable of both
addition and subtraction of binary numbers in one circuit itself. The operation being performed depends upon
the binary value the control signal holds. It is one of the components of the ALU (Arithmetic Logic Unit).

This Circuit requires prerequisite knowledge of XOR Gate, Binary Addition and Subtraction, Full Adder.
Lets consider two 4-bit binary numbers A and B as inputs to the Digital Circuit for the operation with digits

A3 A2 A1 A0 for A
B3 B2 B1 B0 for B

The circuit consists of 4 full adders since we are performing operation on 4-bit numbers. There is a control line
K that holds a binary value of either 0 or 1 which determines that the operation being carried out is addition or
subtraction.

As shown in the figure, the first full adder has control line directly as its carry input (Cin), the input A0 is
directly input in the full adder. The third input is the XOR of B0 and K. The two outputs produced are
Sum/Difference (S0) and Carry (C0).

If the Value of K=0, the output of B XOR K=B.

B K B XOR K = B
0 0 0
1 0 1
The operation is A+B0 which is simple binary addition. This suggests that When K=0, the operation
being performed on the four bit numbers is addition.

̅.
Similarly, If the value of K=1, the output of B XOR K=𝑩
B K B XOR K = 𝑩 ̅
0 1 1
1 1 0

Compiled By: - Er. Sohan Acharya

 Thus the operation would be A+𝐵0 ̅̅̅̅. Now 2’s complement subtraction for two numbers A and B0 is
̅̅̅̅. This suggests that when K=1, the operation being performed on the four bit numbers is
given by A+𝐵0
subtraction.

Then C0 is serially passed to another full adder as one of its output. The sum/difference S0 is recorded as the
least significant bit of the sum/difference. A1, A2, A3 are direct inputs to the second, third and fourth full
adders. Then the third input is the B1, B2, B3 XORed with K to the second, third and fourth full adder
respectively. The carry C1, C2 are serially passed to the successive full adder as one of the inputs. C3 becomes
the total carry to the sum/difference. S1, S2, S3 are recorded to form the result with S0.
For an n-bit binary adder-Subtractor, we use n number of full adders.

Example: Perform binary addition and subtraction of given 4-bit binary value using binary adder and
Subtractor. A = 1001 and B = 0011.
Solution:

Binary addition: Binary subtraction:

For, FA0: k=0=Cin For, FA0: k=1=Cin
A0=1, B0=1, Cin=0 A0=1, ̅̅̅̅
𝐵0=0, Cin=1
So, S0=0, C0=1 So, S0=0, C0=1

For, FA1: For, FA1:

A1=0, B1=1, C0=1 A1=0, ̅̅̅̅
𝐵1=0, C0=1
So, S1=0, C1=1 So, S1=1, C1=0

For, FA2: For, FA2:

A2=0, B2=0, C1=1 A2=0, ̅̅̅̅
𝐵2=1, C1=0
So, S2=1, C2=0 So, S2=1, C2=0

For, FA3: For, FA3:

A3=1, B3=0, C2=0 A3=1, ̅̅̅̅
𝐵3=1, C2=0
So, S3=1, C3=0 So, S3=0, C3=1

Hence, S3 S2 S1 S0 = 1100 Hence, S3 S2 S1 S0 = 0110

Compiled By: - Er. Sohan Acharya

BCD-Adder/ Decimal-Adder: The BCD-Adder is used in the computers and the calculators that perform
arithmetic operation directly in the decimal number system. The BCD-Adder accepts the binary-coded form of
decimal numbers. The Decimal-Adder requires a minimum of nine inputs and five outputs.
There is the following table used in designing of BCD-Adder.

From the above table, it is clear that if the produced sum from 1 to 9 in the Binary and the BCD code is same.
But for 10 to 19 decimal numbers, both the codes are different. In the above table, the binary sum
combinations from 10 to 19 give invalid BCD. There are the following points that help the circuit to identify the
invalid BCD.
1. It is obvious from the table that a correction is needed when the 'Binary Sum' has an output carry K=1.
2. The other six combinations from 10 to 15 need correction in which the bit on the Z8 position is 1.
3. In the Binary sum of 8 and 9, the bit on the Z8 position is also 1. So, the second step fails, and we need
to modify it.
4. To distinguish these two numbers, we specify that the bit on the Z4 or Z2 position also needs to be 1
with the bit of Z8.
5. The condition for a correction and an output carry can be expressed by the Boolean function:
C=K+Z8.Z4+Z8.Z2
Once the circuit found the invalid BCD, the circuit adds the binary number of 6 into the invalid BCD
code to make it valid.

Compiled By: - Er. Sohan Acharya

In the shown diagram,
1. We take a 4-bit Binary-Adder, which takes addend
and augend bits as an input with an input
carry 'Carry in'.
2. The Binary-Adder produces five outputs, i.e., Z8, Z4,
Z2, Z1, and an output carry K.
3. With the help of the output carry K and Z8, Z4, Z2, Z1
outputs, the logical circuit is designed to identify the
Cout.
4. The Z8, Z4, Z2, and Z1 outputs of the binary adder
are passed into the 2nd 4-bit binary adder as an
Augend.
5. The addend bit of the 2nd 4-bit binary adder is
designed in such a way that the 1st and the 4th bit of
the addend number are 0 and the 2nd and the 3rd bit
are the same as Cout. When the value of Cout is 0, the
addend number will be 0000, which produce the same result as the 1st 4-bit binary number. But when
the value of the Cout is 1, the addend bit will be 0110, i.e., 6, which adds with the augend to get the
valid BCD number.
Example: 1001+1000
1. First, add both the numbers using a 4-bit binary adder
and pass the input carry to 0.
2. The binary adder produced the result 0001 and
carried output K = 1.
3. Then, find the Cout value to identify that the produced
BCD is invalid or valid using the expression
Cout=K+Z8.Z4+Z8.Z2.
K Z8 Z4 Z2 Z8.Z4 Z8.Z2 Cout=K+Z8.Z4+Z8.Z2
1 0 0 0 0 0 1

4. The value of Cout is 1, which expresses that the

produced BCD code is invalid. Then, add the output of
the 1st 4-bit binary adder with 0110.
= 0001+0110
= 0111
5. The BCD is represented by the carry output as:
BCD=Cout Z8 Z4 Z2 Z1=1 0 1 1 1

Compiled By: - Er. Sohan Acharya

Magnitude Comparator: A magnitude digital Comparator is a
combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is
equal (A = B), less than (A < B) or greater than the other binary
number (A > B).

1-bit Magnitude Comparator: A comparator that compares two binary bits and produces three outputs based
on the relative magnitudes of given binary bits is called a 1-bit magnitude comparator.
Truth Table:
A B A<B A>B A=B
0 0 0 0 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 1
The truth table derives the expressions of A<B, A>B and A=B as below
A<B = A’B
A>B = AB’
A=B = A’B’+AB = A XNOR B

With these expressions, the Circuit diagram can be as follows:

2-bit Magnitude Comparator:

A comparator that compares two binary numbers (each number having 2 bits) and produces three outputs
based on the relative magnitudes of given binary bits is called a 2-bit magnitude comparator.

A1 A0 B1 B0 A<B A=B A>B

0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0

Compiled By: - Er. Sohan Acharya

 0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0

From the above truth table K-map for each output can be drawn as follows:

From the above K-maps logical expressions for each output can be expressed as follows:
A > B: A1.B1’ + A0.B1’.B0’ + A1.A0.B0’
A = B: A1’.A0’.B1’.B0’ + A1’.A0.B1’.B0 + A1.A0.B1.B0 + A1.A0’.B1.B0’
: A1’.B1’ (A0’.B0’ + A0.B0) + A1.B1 (A0.B0 + A0’.B0’)
: (A0.B0 + A0’.B0’) (A1.B1 + A1’.B1’)
: (A0 EX-NOR B0) (A1 EX-NOR B1)
A < B: A1’.B1 + A0’.B1.B0 + A1.’A0’.B0

Compiled By: - Er. Sohan Acharya

By using these Boolean expressions, we can implement a logic circuit for this comparator as given below:

4-bit Magnitude Comparator: A comparator that compares two binary numbers (each number having 4 bits)
and produces three outputs based on the relative magnitudes of given binary bits is called a 4-bit magnitude
comparator.
The input bits can be termed as A = A3 A2 A1 A0 and B = B3 B2 B1 B0

In a 4-bit comparator the condition of A>B can be possible in the following four cases:
1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

Similarly the condition for A<B can be possible in the following four cases:
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

The condition of A=B is possible only when all the individual bits of one number exactly coincide with
corresponding bits of another number.
1. (A = B) = (A3 Ex-Nor B3) (A2 Ex-Nor B2) (A1 Ex-Nor B1)(A0 Ex-Nor B0)

Compiled By: - Er. Sohan Acharya

By using these Boolean expressions, we can implement a logic circuit for this comparator as given below:

Cascading Comparator: A comparator performing the

comparison operation to more than four bits by cascading two
or more 4-bit comparators is called cascading comparator.
When two comparators are to be cascaded, the outputs of the
lower-order comparator are connected to corresponding
inputs of the higher-order comparator.

Decoder and Encoder: Binary code of N digits can be used to store 2N distinct elements of coded
information. This is what encoders and decoders are used for.

Encoder: An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2N input lines and ‘N’ output lines, hence it encodes the information from 2^n inputs into an n-
bit code. It will produce a binary code equivalent to the input, which is active High.

Compiled By: - Er. Sohan Acharya

4: 2 Encoder: The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. At any
time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the output. The
figure below shows the logic symbol of 4 to 2 encoder:

The Truth table of 4 to 2 encoder is as follows:

Logical expression for A1 and A0:

A1 = Y3 + Y2
A0 = Y3 + Y1
The above two Boolean functions A1 and A0 can be implemented using two input OR gates:

8: 3 Encoder (Octal to Binary): The 8 to 3 Encoder or octal to Binary encoder consists of 8 inputs, Y7 to Y0
and 3 outputs, A2, A1 & A0. Each input line corresponds to each octal digit and three outputs generate
corresponding binary code.

Compiled By: - Er. Sohan Acharya

The figure below shows the logic symbol of octal to binary encoder:

The truth table for 8 to 3 encoder is as follows:

Logical expression for A2, A1 and A0:

A2 = Y7 + Y6 + Y5 + Y4
A1 = Y7 + Y6 + Y3 + Y2
A0 = Y7 + Y5 + Y3 + Y1

Compiled By: - Er. Sohan Acharya

The above two Boolean functions A2, A1 and A0 can be implemented using four input OR gates:

Decimal to BCD Encoder: The decimal to binary encoder usually consists of 10 input lines and 4 output lines.
Each input line corresponds to the each decimal digit and 4 outputs correspond to the BCD code. This encoder
accepts the decoded decimal data as an input and encodes it to the BCD output which is available on the
output lines. The figure below shows the logic symbol of decimal to BCD encoder:

The truth table for decimal to BCD encoder is as follows:

Compiled By: - Er. Sohan Acharya

Logical expression for A3, A2, A1 and A0:
A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1

The above two Boolean functions can be implemented using OR gates:

Priority Encoder: A 4 to 2 priority encoder has 4 inputs, Y3, Y2, Y1 & Y0 and 2 outputs, A1 & A0. Here, the
input, Y3 has the highest priority, whereas the input, Y0 has the lowest priority. In this case, even if more than
one input is ‘1’ at the same time, the output will be the (binary) code corresponding to the input, which is
having higher priority.
The truth table for priority encoder is as follows:

Compiled By: - Er. Sohan Acharya

The above two Boolean functions can be implemented as:

Drawbacks of Normal Encoders:

 There is an ambiguity, when all outputs of encoder are equal to zero.

Compiled By: - Er. Sohan Acharya

  If more than one input is active High, then the encoder produces an output, which may not be the
correct code.
So, to overcome these difficulties, we should assign priorities to each input of encoder. Then, the output of
encoder will depend upon active High inputs, which has higher priority.
Uses of Encoders:
 Encoders are very common electronic circuits used in all digital systems.
 Encoders are used to translate the decimal values to the binary in order to perform the binary
functions such as addition, subtraction, multiplication, etc.
 Other applications especially for Priority Encoders may include detecting interrupts in microprocessor
applications.

Decoders: A decoder does the opposite job of an encoder. It is a combinational circuit that converts n lines of input
into 2n lines of output.

There are various types of decoders which are as follows:

2 to 4 line decoder: In the 2 to 4 line decoder, there is a total 3
inputs, i.e., A0, and A1 and E and 4 outputs, i.e., Y0, Y1, Y2, and Y3. For
each combination of inputs, when the enable 'E' is set to 1, one of
these four outputs will be 1. The block diagram and the truth table
of the 2 to 4 line decoder are given below.

Truth Table: The logical expression of the term Y0, Y0, Y2, and Y3 is
as follows:
Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Compiled By: - Er. Sohan Acharya

Logical circuit of the above expressions is given below:

3 to 8 line decoder: The 3 to 8 line decoder is also known

as binary to Octal Decoder. In a 3 to 8 line decoder, there is a
total of 8 outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and 3
outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'.
Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of
these four outputs will be 1. The block diagram and the truth
table of the 3 to 8 line encoder are given below.
Block Diagram:

Truth Table: The logical expression of the term Y0,

Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Compiled By: - Er. Sohan Acharya

Logical circuit of the above expressions is given below:

Multiplexer: A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply,
the multiplexer is a multi-input and single-output combinational circuit. The binary information is received
from the input lines and directed to the output line. On the basis of the values of the selection lines, one of
these data inputs will be connected to the output.
Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of 2N possible
combinations of inputs. A multiplexer is also treated as Mux.
There are various types of the multiplexer which are as follows:
2x1 Multiplexer: In 2x1 multiplexer, there are only two inputs,
i.e., A0 and A1, 1 selection line, i.e., S0 and single outputs, i.e., Y.
On the basis of the combination of inputs which are present at
the selection line S0, one of these 2 inputs will be connected to
the output. The block diagram and the truth table of the 2×1
multiplexer are given below.

Compiled By: - Er. Sohan Acharya

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1
Logical circuit of the above expression is given below:

4×1 Multiplexer: In the 4×1 multiplexer, there is a total of four inputs, i.e.,
A0, A1, A2, and A3, 2 selection lines, i.e., S0 and S1 and single output, i.e., Y.
On the basis of the combination of inputs that are present at the selection
lines S0 and S1, one of these 4 inputs are connected to the output. The block
diagram and the truth table of the 4×1 multiplexer are given below.

Truth Table:

Compiled By: - Er. Sohan Acharya

The logical expression of the term Y is as follows:
Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
Logical circuit of the above expression is given below:

8 to 1 Multiplexer: In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7,
3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of
the combination of inputs that are present at the selection lines S 0, S1, and
S2, one of these 8 inputs are connected to the output. The block diagram
and the truth table of the 8×1 multiplexer are given below.

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0 + S0.S1'.S2'.A1 + S0'.S1.S2'.A2+S0.S1.S2'.A3 + S0'.S1'.S2 A4 + S0.S1'.S2 A5 + S0'.S1.S2 .A6 + S0.S1.S3.A7

Compiled By: - Er. Sohan Acharya

Logical circuit of the above expression is given below:

De-multiplexer: A De-multiplexer is a combinational circuit that has only 1 input line and 2N output lines.
Simply, the multiplexer is a single-input and multi-output combinational circuit. The information is received
from the single input lines and directed to the output line. On the basis of the values of the selection lines, the
input will be connected to one of these outputs. De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of 2n possible
combinations of outputs. De-multiplexer is also treated as De-mux.
There are various types of De-multiplexer which are as follows:
1×2 De-multiplexer: In the 1 to 2 De-multiplexer, there are
only two outputs, i.e., Y0, and Y1, 1 selection lines, i.e., S0, and
single input, i.e., A. On the basis of the selection value, the
input will be connected to one of the outputs. The block
diagram and the truth table of the 1×2 multiplexer are given
below.

Compiled By: - Er. Sohan Acharya

Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:

1×4 De-multiplexer: In 1 to 4 De-multiplexer, there are total of four outputs,

i.e., Y0, Y1, Y2, and Y3, 2 selection lines, i.e., S0 and S1 and single input, i.e., A. On
the basis of the combination of inputs which are present at the selection lines
S0 and S1, the input be connected to one of the outputs. The block diagram and
the truth table of the 1×4 multiplexer are given below.
Truth Table:

The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

Compiled By: - Er. Sohan Acharya

Logical circuit of the above expressions is given below:

1×8 De-multiplexer: In 1 to 8 De-multiplexer, there are total of eight

outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3 selection lines, i.e., S0, S1and
S2 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S0, S1 and S2, the input will be connected to
one of these outputs. The block diagram and the truth table of the 1×8 de-
multiplexer are given below.
Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

Compiled By: - Er. Sohan Acharya

Logical circuit of the above expressions is given below:

ROM: Its non-volatile memory, i.e., the information stored in it, is not lost even if the
power supply goes off. It’s used for the permanent storage of information. A stored
array of binary data which can be read only, but not changed.

For each combination of inputs on the ‘n’ input lines, the corresponding pattern
of 0’s and 1’s (a word) is generated on the ‘m’ output lines.

2n x m ROM:

Compiled By: - Er. Sohan Acharya

Logic construction of a 32x4 ROM:

Q) Implement using ROM:

𝐹1 (𝐴1 , 𝐴0 ) = ∑(1,2,3)
𝐹2 (𝐴1 , 𝐴0 ) = ∑(0,2)
Solution,
Truth table using above min terms,
𝑨𝟏 𝑨𝟎 𝑭𝟏 𝑭𝟐
0 0 0 1
0 1 1 0
1 0 1 1
1 1 1 0

Combinational circuit is,

Compiled By: - Er. Sohan Acharya

Q) Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output
binary number equal to the square of the input number.
Solution:
Derive the truth table for thecombinational circuit,

From the above truth table, we can see that, B0 = A0 and B1 = 0.

ROM Truth Table,

Combinational Circuit is,

Compiled By: - Er. Sohan Acharya

PLA (Programmable Logic Array): PLA is a programmable logic device that has both Programmable AND
array & Programmable OR array. Hence, it is the most flexible PLD. The block diagram of PLA is shown in the
following figure.

Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we
can generate only the required product terms by using these AND gates.
Here, the inputs of OR gates are also programmable. So, we can program any number of required product
terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PAL
will be in the form of sum of products form.

Q. Implement the following two Boolean functions with a PLA:

𝑭𝟏 = ∑(𝟎, 𝟏, 𝟐, 𝟒) 𝑭𝟐 = ∑(𝟎, 𝟓, 𝟔, 𝟕)

Solution:
Create truth table for above Boolean functions,
Inputs Outputs
A B C F1 F2
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 0
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 1

Compiled By: - Er. Sohan Acharya

Simplifying above truth table using K-Map,

PLA programming Table:

PLA Implementation

Q. implement the following function using PLA.

𝑭𝟏 = ∑(𝟎, 𝟏, 𝟐, 𝟒) 𝑭𝟐 = ∑(𝟎, 𝟓, 𝟔, 𝟕) 𝑭𝟑 = ∑(𝟎, 𝟑, 𝟓, 𝟕)
Solution:
Create truth table for above Boolean functions,

Compiled By: - Er. Sohan Acharya

 Inputs Outputs
A B C F1 F2 F3
0 0 0 1 1 1
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 0 0 1
1 0 0 1 0 0
1 0 1 0 1 1
1 1 0 0 1 0
1 1 1 0 1 1

Simplifying above truth table using K-Map,

Compiled By: - Er. Sohan Acharya

 Sequential Circuit
The combinational circuit does not use any memory. Hence the previous state of input does not have any
effect on the present state of the circuit. But sequential circuit has memory so output can vary based on input
and previous output. This type of circuits uses input, previous output, clock and a memory element.

Event Driven Model: Event driven sequential circuits differ from combinatorial circuits in that the outputs of
the circuit depend not only on the present state of the inputs but also on the past history of the inputs. Thus a
sequential circuit has memory. Memory is provided for each bit needed to define a state by using a bit storage
device such as a flip-flop.

SR (Set-Reset) Latch: A Latch is one kind of a logic circuit, and it is also

known as a bistable-multivibrator. Because it has two stable states namely
active high as well as active low. It works like a storage device by holding
the data through a feedback line. It stores 1-bit of data as long as the
apparatus is activated.

SR Latch with NAND gate:

Case-1: (S=R=0) S’=R’=1

 If Q = 1, Q and R’ inputs for NAND
gate are both 1
 If Q = 0, Q and R’ inputs for NAND
gate are 0 and 1 respectively.

Case-2: (S=1, R=0) S’=0, R’=1

 As S’=0, the output of 1st NAND gate, Q = 1(SET state). In
2nd NAND gate, as Q and R’ inputs are 1, Q’=0.

Case-3: (S=0, R=1) S’=1, R’=0

 As R’=0, the output of 2nd NAND gate, Q’ = 1. In 1st NAND
gate, as Q and S’ inputs are 1, Q=0(RESET state).

Case-3: (S=R=1) S’=R’=0

Compiled By: - Er. Sohan Acharya

  When S=R=1, both Q and Q’ becomes 1 which is not allowed. So, the input condition is
prohibited.

Flip-Flop: Flip-flop is a circuit that maintains a state until directed by input to change the state. A basic flip-
flop can be constructed using four-NAND or four-NOR gates.
Types of flip-flops:
1. SR Flip Flop
2. JK Flip Flop
3. D Flip Flop
4. T Flip Flop

1. SR Flip Flop: The Clocked SR flip flop consists of 4 NAND gates, two inputs(S and R) and two outputs (Q and
Q’). The clock pulse is given at the inputs of gate A and B.

S.N. Condition Operation

1 S = R = 0 : No change If S = R = 0 then output of NAND gates C and D are forced to become 1.

Hence R' and S' both will be equal to 1. Since S' and R' are the input of the
basic S-R latch using NAND gates, there will be no change in the state of
outputs.
2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-B i.e. R' = 0 and E = 1 the output of NAND-A i.e.
S' = 1.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.
3 S = 1, R = 0, E = 1 Output of NAND-B i.e. R' = 1 and output of NAND-A i.e. S' =0.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the set
condition.
4 S = 1, R = 1, E = 1 As S = 1, R = 1 and E = 1, the output of NAND gates A and B both are 0 i.e. S'
= R' = 0.
Hence the invalid condition will occur in the basic NAND latch.

Compiled By: - Er. Sohan Acharya

 Simplified truth table of SR
Flip Flop

Truth table of SR Flip Flop

2. JK Flip Flop: One of the most useful and versatile flip flop is the JK flip flop the unique features of a JK flip
flop are:
 If the J and K input are both at 1 and the clock pulse is applied, then the output will change state,
regardless of its previous condition.
 If both J and K inputs are at 0 and the clock pulse is applied there will be no change in the output.
There is no indeterminate condition, in the operation of JK flip flop i.e. it has no ambiguous state. The
circuit diagram for a JK flip flop is shown in Figure :

These J and K inputs disable the NAND gates, therefore clock pulse have no effect on the flip flop. In other
words, Q returns it last value.
When J = 0 and K = 1: The upper NAND gate is disabled the lower NAND gate is enabled if Q is 1 therefore, flip
flop will be reset (Q = 0, Q =1) if not already in that state. So, Q+1 = 0.
When J = 1 and K = 0: The lower NAND gate is disabled and the upper NAND gate is enabled if Q is at 1, As a
result we will be able to set the flip flop (Q = 1, Q = 0) if not already set. So, Q+1 = 1.
When J = 1 and K = 1: If Q = 0 the lower NAND gate is disabled the upper NAND gate is enabled. This will set
the flip flop and hence Q will be 1. On the other hand if Q = 1, the lower NAND gate is enabled and flip flop will
be reset and hence Q will be 0. In other words, when J and K are both high, the clock pulses cause the JK flip
flop to toggle. Truth table of JK is shown below:

Compiled By: - Er. Sohan Acharya

3. Delay/ D Flip Flop: Delay Flip Flop or D Flip Flop is the
simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input. The input data
is appearing at the output after some time. Due to this data
delay between i/p and o/p, it is called delay flip flop. S and R
will be the complements of each other due to NAND inverter.
Hence S = R = 0 or S = R = 1, these input condition will never
appear.

S.N. Condition Operation

1 E=0
Latch is disabled. Hence no change in output.

Compiled By: - Er. Sohan Acharya

 2 E = 1 and D = 0
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the present
state, the next state is Qn+1 = 0. This is the reset condition.
3 E = 1 and D = 1
If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Q n+1 = 1
irrespective of the present state.

4. Toggle/T Flip Flop: Toggle flip flop is basically a JK

flip flop with J and K terminals permanently
connected together. It has only input denoted by T as
shown in the Symbol Diagram. The symbol for
positive edge triggered T flip flop is shown in the
Block Diagram.

S.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every

leading edge of clock signal.

Master Slave Flip Flop: The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected
together in a series configuration. Out of these, one acts as the “master” and the other as a “slave”. The
output from the master flip flop is connected to
the two inputs of the slave flip flop whose output
is fed back to inputs of the master flip flop.
In addition to these two flip-flops, the circuit also
includes an inverter. The inverter is connected to
clock pulse in such a way that the inverted clock
pulse is given to the slave flip-flop. In other words
if CP=0 for a master flip-flop, then CP=1 for a
slave flip-flop and if CP=1 for master flip flop then
it becomes 0 for slave flip flop.

Compiled By: - Er. Sohan Acharya

Working of a master slave flip flop:

 When the clock pulse goes to 1, the slave is isolated. The slave flip-flop is isolated until the CP goes to
0. When the CP goes back to 0, information is passed from the master flip-flop to the slave and output
is obtained.
 Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so
the master responds before the slave.
 If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces
the slave to reset, thus the slave copies the master.
 If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative
transition of the clock sets the slave, copying the master.
 If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the
negative transition of the clock.
 If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then output Q will toggle as long as CLK remains
high which makes the output unstable or uncertain. This is called a race around condition in J-K flip-flop. We
can overcome this problem by making the clock =1 for very less duration. The circuit used to overcome race
around conditions is called the Master Slave JK flip flop.

State Diagram: The state diagram is the pictorial

representation of the behavior of sequential circuits. It
clearly shows the transition of states from the present state
to the next state and output for a corresponding input.

 In this diagram, each present state is represented

inside a circle.
 The transition from the present state to the next
state is represented by a directed line connecting the
circles.
 If the directed line connects the circle itself, which
indicates that there is no change in the state (the next
state is the same as the present state).
 The input value, which causes the transition to occur
is labeled first ‘1/’. The output produced for the
corresponding input is labeled second ‘/0’.

Stable Table: The information contained in the state diagram is transformed into a table called a state table or
state synthesis table. Although the state diagram describes the behavior of the sequential circuit, in order to
implement it in the circuit, it has to be transformed into the tabular form.
The below table shows the state table for Mealy state machine model. As you can see, it has the
present state, next state and output. The present state is the state before the occurrence of the clock pulse.

Compiled By: - Er. Sohan Acharya

 After the application of the clock pulse, depending on the input(X = 0 or 1), the state changes. It is
indicated in the ‘next state’ column. The output produced for each input is represented in the last column.

State Reduction: While designing a sequential circuit, it is very important to remove the redundant states. The
removal of redundant states will reduce the number of flip flops and logic gates, thereby reducing the cost and
size of the sequential circuit.
The two states are said to be redundant if the output and the next state produced for each and every
input are the same. In that case, one of the redundant states can be removed without altering the input-
output relationship. This method is called the state elimination method.
Let us learn with examples here.

In the above stable table1, state a & e found to be having similar states. Here we have found, states b
and e are redundant. Replace e by b and remove the state e. Which is shown in stable table2.

Problems (State diagram into circuit using flip flops):

To convert state diagrams into circuit using flip flop we need to have Excitation tables of flip flops. The
excitation table has the minimum inputs, which will excite or trigger the flip flop to go from its present state to
the next state. It is derived from the truth table.

Compiled By: - Er. Sohan Acharya

Excitation tables:

Compiled By: - Er. Sohan Acharya

Compiled By: - Er. Sohan Acharya
Compiled By: - Er. Sohan Acharya
Compiled By: - Er. Sohan Acharya
Analysis of Clocked Sequential Circuits:
The clocked sequential circuits have flip-flops or gated latches for its memory elements. There is a
periodic clock connected to the clock inputs of all the memory elements of the circuit to synchronize all the
internal changes of state. Hence the operation of the circuit is controlled and synchronized by the periodic
pulse of the clock.

Analysis with D Flip-Flops:

 The input equation of a D Flip-flop is given by DA = A ⊕ x ⊕ y. DA means a D Flip-flop with output A.
 The x and y variables are the inputs to the circuit. No output equations are given, which implies that
the output comes from the output of the flip-flop.
 The state table has one column for the present state of flip-flop 'A' two columns for the two in-puts,
and one column for the next state of A.

Compiled By: - Er. Sohan Acharya

  The next-state values are obtained from the state equation A(t + 1) = A ⊕ x ⊕ y.
 The expression specifies an odd function and is equal to 1 when only one variable is 1 or when all three
variables are 1.

Synchronous VS Asynchronous Sequential Circuit

Synchronous Sequential Circuit Asynchronous Sequential Circuit
Synchronous sequential circuits are digital circuits Asynchronous sequential circuits are digital circuits
governed by clock signals. that are not driven by clock. They can be called
as self-timed circuits.

Block Diagram of Synchronous Sequential Circuit Block Diagram of Asynchronous Sequential Circuit
The transition from one state to another takes place The transition from one state to another takes place
only by the application of specified clock signal*, even immediately once the inputs change.
if the inputs change.
Synchronous sequential circuits are also known
as clocked sequential circuit.
The states of synchronous sequential circuits are There are chances for the asynchronous circuits to
always predictable and thus reliable. enter into a wrong state because of the time
difference between the arrivals of inputs. This is
called as race condition.

Compiled By: - Er. Sohan Acharya

 It is easy to design synchronous sequential circuits. The presence of feedback among logic gates causes
instability issues making the design of asynchronous
sequential circuits difficult.
The distributed clock signal consumes large power Power consumption and heat dissipation are
and dissipates large amount of heat. comparatively lower.

Triggering
Triggering basically means switching. The way in which a switch or an event is triggered can be
different, based on the user's requirements.
Edge and Level Triggering, are both common terms when using sequential circuits (flip flops) triggered
by an external or internal clock signal.

Level Triggering:

You can notice two voltage levels, VH and VL. Those are the two levels at which the event can be
triggered. Consider you want to turn on an LED at the positive clock level. What it means is that the LED can
turn on at any moment when the voltage is at VH. This is known as level triggering, where the event is
triggered whenever a clock level is encountered. The event may start at any moment during the time for
which the clock signal is at the given level.

EDGE TRIGGERING:

In the image you notice two edges, Rising Edge and Falling Edge, respectively. When an event is triggered at a
rising/falling edge, it is said to be edge triggered.
Consider the LED you wanted to turn on, but now by (rising) edge triggering. It means that the LED
turns on every time the clock makes a transition from VH to VL, and not when it is at the respective levels. The
voltage level of the clock doesn't matter much and the LED turns on the moment there is a transition from low
voltage level to high voltage level.

Registers:
Registers are a type of computer memory used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU. The registers used by the CPU are often termed as
Processor registers.

Compiled By: - Er. Sohan Acharya

 A processor register may hold an instruction, a storage address, or any data (such as bit sequence or
individual characters).
The computer needs processor registers for manipulating data and a register for holding a memory
address. The register holding the memory location is used to calculate the address of the next instruction after
the execution of the current instruction is completed.
Following is the list of some of the most common registers used in a basic computer:
Register Symbol Number of bits Function
Data register DR 16 Holds memory operand
Address register AR 12 Holds address for the memory
Accumulator AC 16 Processor register
Instruction register IR 16 Holds instruction code
Program counter PC 12 Holds address of the instruction
Temporary register TR 16 Holds temporary data
Input register INPR 8 Carries input character
Output register OUTR 8 Carries output character

Shift Registers:
Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple
bits of data, we need multiple flip flops. N flip flops are to be connected in an order to store n bits of data. A
Register is a device which is used to store such information. It is a group of flip flops connected in series used
to store multiple bits of data.
The information stored within these registers can be transferred with the help of shift registers. Shift
Register is a group of flip flops used to store multiple bits of data. The bits stored in such registers can be
made to move within the registers and in/out of the registers by applying clock pulses. An n-bit shift register
can be formed by connecting n flip-flops where each flip flop stores a single bit of data.
Shift registers are basically of 4 types. These are:
1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

1. Serial In Parallel Out Register (SIPO): The shift register, which allows serial input (one bit after the
other through a single data line) and produces a parallel output is known as Serial-In Parallel-Out shift
register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists of
four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock signal
to all the 4 flip flops in order to RESET them. The output of the first flip flop is connected to the input of
the next flip flop and so on. All these flip-flops are synchronous with each other since the same clock
signal is applied to each flip flop.

Compiled By: - Er. Sohan Acharya

 Let us now understand how data is stored in a shift register.
Suppose we have to insert ‘1111’ inside the shift register. Initially, as the device is in reset mode
thus the output of each register will be low, thereby providing output of all the 4 registers as 0000.
 Now beginning with LSB of the data to be inserted so 1 is provided as input to the circuit i.e., D3
= 1. But as initially the output of all the flip-flops were 0. Therefore, D2, D1 and D0 will be 0.
While input D3 = 1 will cause Q3 to be 1. Thus the overall output will be 1000.
 Further, when another data input bit i.e., 1 is provided at D3. Then again this will cause Q3 to
be 1, but as Q3 is provided as input to D2. Therefore, this will cause Q2 to be 1, while rest all
other outputs will be 0. Thus for a second falling edge, we will get 11 at the stored bit inside the
register, thereby giving the overall output as 1100.
 Similarly, when 3rd input bit ‘1’ is provided then previous output Q2 will cause the input D1 to
be 1. This will provide output Q3, Q2 and Q1 as 1 while Q0 will still remain 0. Thus the overall
output will be 1110.
 Furthermore, when MSB of the data is provided as input, then 1 at Q1 will cause D0 input to be
logic high. So, this will cause Q0 to be 1.
Thus in this way shift register stores ‘1111‘ thereby showing in the output.

2. Serial In Parallel Out (SIPO): The shift register, which allows serial input (one bit after the other
through a single data line) and produces a parallel output is known as Serial-In Parallel-Out shift
register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists of
four D flip-flops which are connected. The clear (CLR) signal is connected in addition to the clock signal
to all the 4 flip flops in order to RESET them. The output of the first flip flop is connected to the input of

Compiled By: - Er. Sohan Acharya

 the next flip flop and so on. All these flip-flops are synchronous with each other since the same clock
signal is applied to each flip flop.
Let us now understand how data is stored in a shift register.
Suppose we have to insert ‘1111’ inside the shift register. Initially, as the device is in reset mode
thus the output of each register will be low, thereby providing output of all the 4 registers as 0000.
 Now beginning with LSB of the data to be inserted so 1 is provided as input to the circuit i.e., D3
= 1. But as initially the output of all the flip-flops were 0. Therefore, D2, D1 and D0 will be 0.
While input D3 = 1 will cause Q3 to be 1. Thus the output will be D3=1, D2=0, D1=0 and D0=0.
 Further, when another data input bit i.e., 1 is provided at D3. Then again this will cause Q3 to
be 1, but as Q3 is provided as input to D2. Therefore, this will cause Q2 to be 1, while rest all
other outputs will be 0. Thus for a second falling edge, we will get D3=1 and D2=1. D1 and D2
remains 0, thereby giving the overall output as 1100.
 Similarly, when 3rd input bit ‘1’ is provided then previous output Q2 will cause the input D1 to
be 1. This will provide output Q3, Q2 and Q1 as 1 while Q0 will still remain 0. Thus the overall
output will be 1110.
 Furthermore, when MSB of the data is provided as input, then 1 at Q1 will cause D0 input to be
logic high. So, this will cause Q0 to be 1.
Thus in this way shift register stores ‘1111‘ thereby showing in the output.

3. Parallel In Serial Out (PISO): The shift register, which allows parallel input (data is given separately to
each flip flop and in a simultaneous manner) and produces a serial output is known as Parallel-In Serial-
Out shift register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit consists of
four D flip-flops which are connected. The clock input is directly connected to all the flip flops but the
input data is connected individually to each flip flop through a multiplexer at the input of every flip
flop. The output of the previous flip flop and parallel data input are connected to the input of the MUX
and the output of MUX is connected to the next flip flop. All these flip-flops are synchronous with each
other since the same clock signal is applied to each flip flop.

Compiled By: - Er. Sohan Acharya

 A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.

4. Parallel In Serial Out (PISO): The shift register, which allows parallel input (data is given separately to
each flip flop and in a simultaneous manner) and also produces a parallel output is known as Parallel-In
parallel-Out shift register.
The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists of
four D flip-flops which are connected. The clear (CLR) signal and clock signals are connected to all the 4
flip flops. In this type of register, there are no interconnections between the individual flip-flops since
no serial shifting of the data is required. Data is given as input separately for each flip flop and in the
same way, output also collected individually from each flip flop.

A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like SISO Shift
register it acts as a delay element.

Counter
A Counter is a device which stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal. Counters are used in digital electronics for
counting purpose, they can count specific event happening in the circuit. For example, in UP counter a counter
increases count for every rising edge of clock. Not only counting, a counter can follow the certain sequence
based on our design like any random sequence 0, 1,3,2… .They can also be designed with the help of flip flops.
Counters are broadly divided into two categories;
1. Asynchronous counter
2. Synchronous counter

Compiled By: - Er. Sohan Acharya

1. Asynchronous counter: In asynchronous counter we don’t use universal clock, only first flip flop is
driven by main clock and the clock input of rest of the following flip flop is driven by output of previous
flip flops. We can understand it by following diagram;

It is evident from timing diagram that Q0 is changing as soon as the falling edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock pulse for
second flip flop) and so on. In this way ripples are generated through Q0, Q1, Q2, Q3 hence it is also
called RIPPLE counter.

2. Synchronous counter: Unlike the asynchronous counter, synchronous counter has one global clock
which drives each flip flop so output changes in parallel. The one advantage of synchronous counter
over asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does
not have cumulative delay because of same clock is given to each flip flop.

Compiled By: - Er. Sohan Acharya

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is dependent on
Q0. Q2 is dependent on Q1 and Q0, Q3 is dependent on Q2, Q1 and Q0.

Ripple Counter
Ripple counter is a special type of Asynchronous counter in which the clock pulse ripples through the
circuit. The N-MOD ripple counter forms by combining n number of flip-flops. The N-MOD ripple counter can
count 2n states, and then the counter resets to its initial value.
Based on their circuitry design, the counters are classified into the following types:
1. Up counter: The Up counter counts the state in ascending order (0, 1, 2, 3, 4, 5, ……).
2. Down counter: The Up counter counts the state in ascending order (……., 5, 4, 3, 2, 1).

Compiled By: - Er. Sohan Acharya

Binary Ripple Counter: A Binary counter is a 2-Mod counter which counts up to 2-bit state values, i.e., 22 = 4
values. The flip flops having similar conditions for toggling like T and JK are used to construct the Ripple
counter. Below is a circuit diagram of a binary ripple counter.

In the circuit design of the binary ripple counter, two JK flip flops are used. The high voltage signal is
passed to the inputs of both flip flops. This high voltage input maintains the flip flops at a state 1. In JK flip
flops, the negative triggered clock pulse use.

The outputs Q0 and Q1 are the LSB and MSB bits, respectively. The truth table of JK flip flop helps us to
understand the functioning of the counter.
When the high voltage to the inputs of the flip flops, the fourth condition is of the JK flip flop occurs.

The flip flops will be at the state 1 when we apply high voltage to the input of the flip-flop. So, the states of the
flip flops passes are toggled at the negative going end of the clock pulse. In simple words, the flip flop toggle
when the clock pulse transition takes place from 1 to 0.

Compiled By: - Er. Sohan Acharya

The state of the output Q0 change when the negative clock edge passes to the flip flop. Initially, all the flip
flops are set to 0. These flip flop changes their states when the passed clock goes from 1 to 0. The JK flip flop
toggles when the inputs of the flip flops are one, and then the flip flop changes its state from 0 to 1. For all the
clock pulse, the process remains the same.
The output of the first flip flop passes to the second flip flop as a clock pulse. From the above timing
diagram, it is clear that the state of the second flip flop is changed when the output Q0 goes transition from 1
to 0. The outputs Q0 and Q1 treat as LSB and MSB. The counter counts the values 00, 01, 10, 11. After
counting these values, the counter resets itself and starts counting again from 00, 01, 10, and 1. The count
values until the clock pulses are passed to J0K0 flip flop.

Modulus Counters
MOD counters are defined based on the number of states that the counter will sequence through

before returning back to its original value. For example, a 2-bit counter that counts from (00)2 to (11)2 in
binary, that is 0 to 3 in decimal, has a modulus value of 4 ( 00 → 01 → 10 → 11, and return back to 00 ) so
would therefore be called a modulo-4, or mod-4, counter. Note also that it has taken four clock pulses to get
from 00 to 11.
As in this simple example there are only two bits, (n = 2) then the maximum number of possible output
states (maximum modulus) for the counter is: 2n = 22 or 4. However, counters can be designed to count to any
number of 2n states in their sequence by cascading together multiple counting stages to produce a single
modulus or MOD-N counter.

Design Mod-N Synchronous Counter:

Step-1: Decision for number of flip-flops,
Example: If we are designing mod N counter and n number of flip-flops are required then n can be
found out by this equation.
N <= 2n
Suppose, we are designing Mod-10 counter Therefore, N= 10 and number of Flip flops (n) required is;
For n =3, 10<=8, which is false.
For n= 4, 10<=16, which is true.
Therefore number of FF required is 4 for Mod-10 counter.
Step-2: Choose the type of flip flop required to design a counter.
Step-3: Draw the state diagram for given mod-n counter.
Step-4: Draw the State table for each state using excitation table of chosen flip flop.
Step-5: Create K-Map for each input combination and simplify it to get the minimized Boolean expression.

Compiled By: - Er. Sohan Acharya

Step-6: Create circuit diagram
Using the Boolean expressions obtained in step 5, now we will draw the required counter circuit

Example 1: Design a mod–5 synchronous counters using JK flip-flop.

Solution,
Step 1: The number of flip-flops required to design a mod-5 counter can be calculated using the
formula: N<=2n, where n is equal to no. of flip-flop and N is the mod number. In this case, the possible
value on n which satisfies the above equation is 3. Hence, the required number of flip-flops is 3.
Step 2: The type of flip-flop required to design the counter is JK flip-flop.
Step 3: State diagram for mod-5 counter describing the state flow in current and next state as:

Step 4: Using the excitation table of JK flip-flop, we need to obtain the flip-flop inputs for each state that we
obtained in the third step and now we will enter it into a table as:

Step 5: Making K-Map for each input combination and simplifying it to get the minimized Boolean expression.

Compiled By: - Er. Sohan Acharya

Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required counter
circuit which can be shown as:

Example 2: Design a mod-10 synchronous counter/ Decade counter/ BCD counter using T flip-flop.
Solution,
A mod-10 counter counts from 0 to 9. Thus, following the steps given in the article - designing of
synchronous counter, a mod-10 counter can be designed as:

Step 1: The number of flip-flops required to design a mod-10 counter can be calculated using the
formula: N<=2n, where n is equal to no. of flip-flop and N is the mod number. In this case, the
possible value on n which satisfies the above equation is 4. Hence, the required number of flip-
flops is 4.

Step 2: The type of flip-flop required to design the counter is T flip-flop.

Step 3: Draw the state diagram for mod-10 counter describing the state flow in current and next state
as:

Step 4: Using the excitation table of T flip-flop, we need to obtain the flip-flop inputs for each state
that we obtained in the third step and now we will enter it into a table as:

Compiled By: - Er. Sohan Acharya

Compiled By: - Er. Sohan Acharya
Step 5: Making K-Map for each input combination and simplifying it to get the minimized Boolean
expression.

Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required counter
circuit which can be shown as:

Example 3: Design a mod -12 synchronous up counter using T flip-flop.

Solution,
A mod-12 up-counter counts from 0 to 11. As already seen in previous examples, we should follow
similar steps and hence a mod-12 counter can be designed as:

Step 1: The number of flip-flops required to design a mod-12 counter can be calculated using the
formula: N<=2n, where n is equal to no. of flip-flop and N is the mod number. In this case, the possible
value on n which satisfies the above equation is 4. Hence, the required number of flip-flops is 4.
Step 2: The type of flip-flop required to design the counter is T flip-flop.

Compiled By: - Er. Sohan Acharya

Step 3: We can draw the state diagram for mod-12 counter describing the state flow in current and next state
as:

Step 4: Using the excitation table of T flip-flop, we need to obtain the flip-flop inputs for each state that we
obtained in third step and now we will enter it into a table as:

Compiled By: - Er. Sohan Acharya

Step 5: Making K-Map for each input combination and simplifying it to get the minimized Boolean expression.

Step 6: Using the Boolean expressions obtained in step 5, now we will draw the required counter circuit which
can be shown as:

Johnson Counter
Johnson counter also known as creeping counter, is an example of synchronous counter. In Johnson
counter, the complemented output of last flip flop is connected to input of first flip flop and to implement n-
bit Johnson counter we require n flip-flop. It is one of the most important type of shift register counter. It is
formed by the feedback of the output to its own input. Johnson counter is a ring with an inversion. Another
name of Johnson counter are: creeping counter, twisted ring counter, walking counter, mobile counter and
switch tail counter.

Compiled By: - Er. Sohan Acharya

 Below is the diagram of the 4-bit Johnson counter. Like Ring counter, four D flip flops are used in the 4-
bit Johnson counter, and the same clock pulse is passed to all the input of the flip flops.

Truth Table:

The above table state that,

 The counter produces the output 0000 when there is no clock input passed (0).
 The counter produces the output 1000 when the 1st clock pulse is passed to the flip flops.
 The counter produces the output 1100 when the 2nd clock pulse is passed to the flip flops.
 The counter produces the output 1110 when the 3rd clock pulse is passed to the flip flops.
 The counter produces the output 1111 when the 4th clock pulse is passed to the flip flops.
 The counter produces the output 0111 when the 5th clock pulse is passed to the flip flops.
 The counter produces the output 0011 when the 6th clock pulse is passed to the flip flops.
 The counter produces the output 0001 when the 7th clock pulse is passed to the flip flops.

Timing Diagram:

Compiled By: - Er. Sohan Acharya

RAM (Random Access Memory)
RAM (Random Access Memory) is a part of computer’s Main Memory which is directly accessible by
CPU. RAM is used to Read and Write data into it which is accessed by CPU randomly. RAM is volatile in nature,
it means if the power goes off, the stored information is lost. RAM is used to store the data that is currently
processed by the CPU. Most of the programs and data that are modifiable are stored in RAM.
Integrated RAM chips are available in two form:
1. SRAM(Static RAM)
2. DRAM(Dynamic RAM)

The block diagram of RAM chip is given below.

 Address bus: An element in a computer that transmits the location of stored information. The address
bus allows the CPU to send the address to RAM, and the data bus allows the actual data transfer to the
CPU.
 𝐑/𝐖̅ : It performs Read operation, when 1 is applied and performs Write operation when 0 is applied.
 Chip Selection Lines: Chip select (CS) is the name of a control line in digital electronics used to select
one (or a set) of integrated circuits (commonly called "chips") out of several connected to the same
computer bus.
 Data bus: It is a group of conducting wires which carries Data only. Data bus is bidirectional because
data flow in both directions, from CPU to memory or Input/Output devices and from memory or
Input/Output devices to CPU.

Read/Write operation in Memory: A memory unit stores binary information in groups of bits called words.
Data input lines provide the information to be stored into the memory, Data output lines carry the
information out from the memory. The control lines Read and write specifies the direction of transfer of data.
Basically, in the memory organization, there are memory locations indexing from 0 to 𝟐𝒍 − 𝟏 where 𝒍 is the
address buses. We can describe the memory in terms of the bytes using the following formula:
𝑵 = 𝟐𝒍 𝑩𝒚𝒕𝒆𝒔
Where,
𝒍 is the total address buses
N is the memory in bytes
Memory Address Register (MAR) is the address register which is used to store the address of the memory
location where the operation is being performed.

Compiled By: - Er. Sohan Acharya

Memory Data Register (MDR) is the data register which is used to store the data on which the operation is
being performed.
Memory Read Operation: Memory read operation transfers the desired word to address lines and activates
the read control line. Description of memory read operation is given below:

In the above diagram initially, MDR can contain any garbage value and MAR is containing 2003 memory
address. After the execution of read instruction, the data of memory location 2003 will be read and the MDR
will get updated by the value of the 2003 memory location (3D).

Compiled By: - Er. Sohan Acharya

Memory Write Operation: Memory write operation transfers the address of the desired word to the address
lines, transfers the data bits to be stored in memory to the data input lines. Then it activates the write control
line. Description of the write operation is given below:

In the above diagram, the MAR contains 2003 and MDR contains 3D. After the execution of write instruction
3D will be written at 2003 memory location.

Timing Waveforms: The operation of the memory unit is controlled by an external device such as a central
processing unit (CPU). The CPU is usually synchronized by its own clock .The memory however doesn’t employ
an internal clock. Instead it’s read and write operations are specified by control inputs.

The access time of memory is the time required to select a word and read it. The cycle time of memory
is the time required to complete a write operation.

Compiled By: - Er. Sohan Acharya

 The read cycle shown in figure has an address for the memory provided by the CPU. The memory-enable
and read/write signals must be in their high level for a read operation. The memory places the data of the word
selected by the address into the output data lines within a 50-ns interval (or less) from the time that the memory

enable is activated. The CPU can transfer the data into one of its internal registers during the negative transition
of T3.The next T1 cycle is available for another memory request.
For a write operation, the CPU must provide the address and input data to the memory. This is done at
the beginning of TI. The memory enable and the read/write signals must be activated after the signals in the
address lines are stable in order to avoid destroying data in other memory words.

The memory enable signal switches to the high level and the read/write signal switches to the low level
to indicate a write operation. The two control signals must stay active for at least 50 ns. The address and data
signals must remain stable for a short time after the control signals are deactivated. At the completion of the
third clock cycle, the memory write operation is completed and the CPU can access the memory again with the
next TI cycle.

Memory Decoding
In addition to requiring storage components in a memory unit, there is a need for decoding circuits to
select the memory word specified by the input address.

The storage part of the cell is modeled by an SR latch with associated gate s to form a D latch. Actually,
the cell is an electronic circuit with four to six transistors. The select input enables the cell for reading or

Compiled By: - Er. Sohan Acharya

writing and the read/write input determines the operation of the cell when it is selected. A1 in the read/write
input provides the read operation by fanning a path from the latch to the output terminal. A0 in the
read/write input provides the write operation by forming a path from the input terminal to the latch.

The logical construction of a small RAM consists of four words of four bits each and Word X total of 16
binary cells. The small blocks labeled BC represent the binary cell with its three inputs and one output. A
memory with four words needs two address lines. The two address inputs go through a 2:4 decoder to select
one of the four words. The decoder is enabled with the memory-enable input.
When the memory enable is 0, all outputs of the decoder are 0 and none of the memory words are
selected. With the memory select at 1, one of the four words is selected, dictated by the value in the two
address lines.
Once a word has been selected, the read/write input determines the operation. During the read
operation the four bits of the selected word go through OR gates to the output terminals.
During the write operation, the data available in the input lines arc transferred into the four binary
cells of the selected word. The binary cells that are not selected are disabled and their previous binary values
remain unchanged.

Compiled By: - Er. Sohan Acharya

 When the memory select input that goes into the decoder is equal to 0 none of the words are selected
and the contents of all cells remain unchanged regardless of the value of the read/write input.

Output Hazard
A hazard, if exists, in a digital circuit causes a temporary fluctuation in output of the circuit. In other
words, a hazard in a digital circuit is a temporary disturbance in ideal operation of the circuit which if given
some time, gets resolved itself. These disturbances or fluctuations occur when different paths from the input
to output have different delays and due to this fact, changes in input variables do not change the output
instantly but do appear at output after a small delay caused by the circuit building elements, i.e., logic gates.
There are three different kinds of hazards found in digital circuits,
1. Static hazard
2. Dynamic hazard
3. Functional hazard

We will discuss only static hazards here to understand it completely.

Formally, a static hazard takes place when change in an input causes the output to change
momentarily before stabilizing to its correct value. Based on what is the correct value, there are two types of
static hazards, as shown below in the image:
1. Static-1 Hazard: If the output is currently at logic state 1 and after the input changes its state, the output
momentarily changes to 0 before settling on 1, then it is a Static-1 hazard.

Compiled By: - Er. Sohan Acharya

2. Static-0 Hazard: If the output is currently at logic state 0 and after the input changes its state, the output
momentarily changes to 1 before settling on 0, then it is a Static-0 hazard.

Detection of Static hazards using K-map:

Lets consider static-1 hazard first. To detect a static-1 hazard for a digital circuit following steps are
used:
 Step-1: Write down the output of the digital circuit, say Y.
 Step-2: Draw the K-map for this function Y and note all adjacent 1’s.
 Step-3: If there exists any pair of cells with 1’s which do not occur to be in the same group (i.e. prime
implicant), it indicates the presence of a static-1 hazard. Each such pair is a static-1 hazard.

Example: Consider the circuit shown below.

We have output, say F, as:

Lets draw the K-map for this Boolean function as follows:

The pair of 1’s encircled as green are not part of the grouping/pairing provided by the output of this
Boolean function. This will cause a static-1 hazard in this circuit.

Removal of static-1 hazard:

Compiled By: - Er. Sohan Acharya

 Once detected, a static-1 hazard can be easily removed by introducing some more terms (logic gates)
to the function (circuit). The most common idea is to add the missing group in the existing Boolean function,
as adding this term would not affect the function by any mean but it will remove the hazard. Since in above
example the pair of 1’s encircled with blue color causes the static-1 hazard, we just add this as a prime
implicant to the existing function as follows:

Note that there is no difference in number of minterms of this function. The reason is that the static-1
hazards are based on how we group 1’s (or 0’s for static-0 hazard) for a given set of 1’s in K-map. Thus it does
not make any difference in number of 1’s in K-map. The circuit would look like as shown below with the
change made for removal of static-1 hazard.

Similarly for Static-0 Hazards we need to consider 0’s instead of 1’s and if any adjacent 0’s in K-map are
not grouped into same group that may cause a static-0 hazard. The method to detect and resolve the static-0
hazard is completely same as the one we followed for static-1 hazard except that instead of SOP, POS will be
used as we are dealing with 0’s in this case.

Status Register
It also known as flag register, program status word, and condition code register — is defined as a
collective of flag bits inside a processor. A register is a processor circuit and is much like a memory location,
meaning data could be written and read from it. Types of flag,
1. Carry Flag (CY): After performing the addition of any two 8-bit numbers, the carry generated can be
either 0 or 1. That is only 1-bit. Thus to store the carry information 1-bit storage is enough.
2. Sign Flag (S): The S flag is set to 1, when the result thus produced against any logical or arithmetic
operations is negative, indicated by MS bit of 8-bit result being 1. It is reset to 0 otherwise if the result
is positive, indicated by MS bit of 8-bit result being 0.
3. Parity Flag (P): The P flag is set to 1, if the 8-bit result thus produced against any logical and arithmetic
operation has an even number of 1's in it. If there are odd number of 1's in the 8-bit result, the P flag is
reset to 0.
4. Zero flag (Z): The P flag is set to 1, if the 8-bit result thus produced against any logical and arithmetic
operation has an even number of 1's in it. If there are odd number of 1's in the 8-bit result, the P flag is
reset to 0.

Compiled By: - Er. Sohan Acharya

Register content and Flag status after Instructions: Basically, you are given a set of instructions and the initial
content of the registers and flags of 8085 microprocessor. You have to find the content of the registers and
flag status after each instruction.

Initially,

Below is the set of the instructions:

SUB A
MOV B, A
DCR B
INR B
HLT

Assumption: Each instruction will use the result of the previous instruction for registers. Following is the
description of each instruction with register content and flag status:
 Instruction-1: SUB A, instruction will subtract the content of the accumulator itself. It is used to clear
the content of the accumulator. After this operation the content of the registers and flags will be like
figure given below.

 Instruction-2: MOV B, A will copy the content from source register (A) to the destination register (B).
Since it is the Data Transfer instruction so it will not affect any flag. After this operation the content of
the registers and flags will be like figure given below.

 Instruction-3: DCR B, will decrease the content of the register B by 1. DCR operation doesn’t affect
Carry flag (CY).
B-00H 0 0 0 0 0 0 0 0
For DCR B takes the 2’s complement of the 01H, 2’s Complement of 01H:
0000 0001
1 1 1 1 1 1 1 0 (1's complement)
+1
-------------------
1111 1111
-------------------

Compiled By: - Er. Sohan Acharya

 +(00) 0 0 0 0 0 0 0 0
------------------------------
1111 1111
------------------------------
(FFH) this will be the content of the B. So after this operation the content of the registers and flag
will be like figure given below.

 Instruction-4: INR B will increase the content of the register B by 1. INR operation will affect Carry
flag (CY).
B(FFH)
1111 1111
+(01) 0000 0001
------------------
CY=1 0000 0000
------------------
(0 0 0 0 0 0 0 0) will be the content of the register B. So after this operation the content of the registers
and flag will be like figure given below.

HLT will terminate the execution of program.

Arithmetic Logic Units

Nibble Adder
Nibble represents 4-bits. So, the nibble adder is the circuit, which performs addition of 4-bits. A single
Full Adder performs the addition of two one bit numbers and also the carry input. For performing the addition
of binary numbers with more than one bit, more than one full adder is required and the number of Full Adders
depends on the number bits. A Parallel Adder, is a combination of Multiple Full Adders and is used for adding
all bits of the two numbers simultaneously. When we use 4 full adder for addition of 4 bit numbers, this circuit
is known as nibble adder.
The following figure shows a Parallel 4-bit Binary Adder, which has four full adders. The two binary
numbers to be added are ‘A3 A2 A1 A0‘ and ‘B3 B2 B1 B0‘ , which are applied to the corresponding inputs of
the Full Adders. This parallel adder produces their result as ‘C4 S3 S2 S1 S0‘, where C4 is the final carry.

Compiled By: - Er. Sohan Acharya

  The augend bits (A) and the addend bits (B) are designated by subscript numbers from right to left,
with subscript '0' denoting the low-order bit.
 The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C4 is the resultant
output carry generated by the last full-adder circuit.
 The output carry from each full-adder is connected to the input carry of the next-high-order full-adder.
 The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend bits.
 The n data bits for the A and B inputs come from different source registers. For instance, data bits for A
input comes from source register R1 and data bits for B input comes from source register R2.
 The arithmetic sum of the data inputs of A and B can be transferred to a third register or to one of the
source registers (R1 or R2).

Design of Arithmetic Circuit

ALU is a data processing component, which is an important part in Centre Process Unit (CPU). Different
kinds of computers have different ALUs. But all of the ALUs contain arithmetic unit and logic unit, which are
the basic structures. The basic component of the arithmetic section of an ALU is a parallel adder. A parallel
adder is constructed with a number of full adder circuits connected in cascade. By controlling the data inputs
to the parallel adder, it is possible to obtain different types of arithmetic operations. We can obtain arithmetic
operations, by controlling one set of inputs to a parallel adder externally.

4-bit Arithmetic Circuit for 8 Operation:

The number of bits in the parallel adder may be of any value. The input carry C in goes to the full adder
circuit in the least significant bit position and the C out comes from the full adder circuit in the most significant
bit position.

Compiled By: - Er. Sohan Acharya

 From the below eight figures (from (a) to (h)), we can see various type of eight operations can be
achieved by controlling the B input and Cin. So to design the circuit we need two parts, control circuit full
adders.

Fig: Eight operations obtained by controlling one set of inputs to a parallel adder

The conventional logic diagram of 4 bit arithmetic circuit is shown in figure below. The circuit that controls the
input B to provide various type of operation shown in figure 4 consists of two NAND gates, one OR gate and
one NOT gate. The circuit is called a true/complement, one/zero element.

Compiled By: - Er. Sohan Acharya

There are two selection lines S1 and S0 to control the B input. When S1S0=00 the output of the OR gate Y=0,
When S1S0=01 the output of the OR gate Y=B, When S1S0=10 the output of the OR gate Y=B’ and When S1S0=11
the output of the OR gate Y=B+B’=1

From the above figure, we can see that the parallel adder constitutes of four full adder .The carry into
the first stage is the input carry. The carry out of the fourth stage is the output carry. The selection variables
are S1, S0 and Cin. Variables S1S0 control all the B inputs to the full adder circuits. The A inputs go directly to the
other inputs of the full adder. The arithmetic circuit operation is given below in table.
Function Select B input Output Function
S1 S0 Cin
0 0 0 0 F=A Transfer A
0 0 1 0 F=A+1 Increment A
0 1 0 B F=A+B Add B to A
0 1 1 B F=A+B+1 Add B to A plus 1
1 0 0 B’ F=A+B’ Add 1’s complement of B to A
1 0 1 B’ F=A+B’+1 Add 2’s complement of B to A
1 1 0 All 1’s F=A-1 Decrement A
1 1 1 All 1’s F=A Transfer A

Fig: Logic diagram of 4 bit Arithmetic circuit for Eight operations

Status Register
The status register, flag register is a hardware register that contains information about the state of the
processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions
executing on the processor. The status register lets an instruction take action contingent on the outcome of a
previous instruction. Typically, flags in the status register are modified as effects of arithmetic and bit
manipulation operations.

Compiled By: - Er. Sohan Acharya

4 flag status register: The status register comprises the status bits. The bits of the status register are modified
according to the operations performed in the ALU. Register which is used to represent the status of certain
while performing arithmetic operation is known as flag register. It can hold either 0 or 1. The figure displays a
block diagram of an 8-bit ALU with a 4-bit status register.

 If the end carry C8 is 1, then carry (C) is set to 1. If C8 is 0, then C is cleared to 0.

 If the highest order bit F7 is 1, then Sign (S) is set to 1. If F7 is 0, then S is set to 0.
 If the output of ALU is 0, then zero (Z) is set to 1, otherwise, Z is set to 0.
 If the XOR of the last two carries is equal to 1, then overflow (V) is set to 1, otherwise, V is cleared to 0.
 The result of the 8-bit ALU operation is either 127 or -127.
 Z is a status bit used to indicate the result obtained after comparing A and B. Here, the XOR operation
is used to compare two numbers (Z = 0 if A = B).

The conditional branch instruction checks the conditions for branching using the status bits. Some of
the commonly used conditional branch instructions are shown in the table.

Mnemonic Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0

Compiled By: - Er. Sohan Acharya

 Branch if zero Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0

Thus, when the status condition is true, the program control is transferred to the address specified in
the instruction, otherwise, the control continues with the instructions that are in the subsequent locations.
The conditional instructions are also associated with the program control instructions such as jump, call, or
return.
The zero status bit checks if the result of the ALU is zero or not. The carry bit checks if the most
significant bit position of the ALU has a carryout. It is also used with rotate instruction to check whether or not
the bit is shifted from the end position of a register into a carry position.
The sign bit indicates the state of the most significant bit of the output from the ALU (S = 0 denotes
positive sign and S = 1 denotes negative sign). The branch if plus and branch if minus is used to check whether
the value of the most significant bit represents a sign or not. The overflow and underflow instructions are used
in conjunction with arithmetic operations performed on signed numbers.
The higher and lower words are used to denote the relations between unsigned numbers, whereas the
greater and lesser words are used to denote the relations between signed numbers.

Compiled By: - Er. Sohan Acharya