Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Name: Taslimbanu R Karadagi

USN: 2KA21EC057
CAN ID : CAN_33888934
College Name : Smt Kamala Sri Venkappa M Agadi College Engineering and
Technology,Lakshmeshwar-582116
Department : Electronics and Communication Engineering

Project: Design of an 3-8 decoder using Verilog System Verilog

Introduction

This report presents the RTL design and functional verification of a 3-to-8 Decoder using Verilog.
The design consists of three input lines and eight output lines, where each output is activated based
on the binary value of the input. The implementation was verified using EDAPlayground with the
Cadence Xcelium simulator.

A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 1 1 1 1 1 1 1 0

0 0 1 1 1 1 1 1 1 0 1

0 1 0 1 1 1 1 1 0 1 1

0 1 1 1 1 1 1 0 1 1 1

1 0 0 1 1 1 0 1 1 1 1

1 0 1 1 1 0 1 1 1 1 1

1 1 0 1 0 1 1 1 1 1 1

1 1 1 0 1 1 1 1 1 1 1

Truth Table of 3-to-8 Decoder

1.1. Specifications
Inputs:
• A (1-bit)
• B (1-bit)
• C (1-bit)

Outputs:
• Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 (8-bit, active-low outputs)

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Design Constraints:
• The decoder operates as a combinational circuit.
• Each output corresponds to a unique combination of the input bits.
Design Architecture for the 3-to-8 Decoder
The 3-to-8 decoder is a combinational circuit that takes three input bits and activates one of the
eight output lines based on the binary input combination.

1.2. Functional Description

• The decoder has three input lines: A, B, and C.
• It has eight output lines: Y0 to Y7 (active-low outputs).
• Only one output is active (low) at a time, depending on the input combination.
• It follows the one-hot encoding principle, where exactly one output is asserted at a time.

Block Diagram:

figure.1.1: Block diagram of 3 to 8 decoder

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

figure.1.2: Logic diagram of 3 to 8 decoder

1.3. RTL Code

design.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity decoder3to8 is

Port (

A : in STD_LOGIC_VECTOR(2 downto 0); -- 3-bit input

Y : out STD_LOGIC_VECTOR(7 downto 0) -- 8-bit output

);

end decoder3to8;

architecture Behavioral of decoder3to8 is

begin

process(A)

begin

Y <= (others => '0'); -- Default all outputs to '0'

case A is

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

when "000" => Y <= "00000001";

when "001" => Y <= "00000010";

when "010" => Y <= "00000100";

when "011" => Y <= "00001000";

when "100" => Y <= "00010000";

when "101" => Y <= "00100000";

when "110" => Y <= "01000000";

when "111" => Y <= "10000000";

when others => Y <= "00000000";

end case;

end process;

end Behavioral;

testbench.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity tb_decoder3to8 is

end tb_decoder3to8;

architecture testbench of tb_decoder3to8 is

signal A_tb : STD_LOGIC_VECTOR(2 downto 0);

signal Y_tb : STD_LOGIC_VECTOR(7 downto 0);

-- Instantiate the decoder

component decoder3to8

Port (

A : in STD_LOGIC_VECTOR(2 downto 0);

Y : out STD_LOGIC_VECTOR(7 downto 0)

);

end component;

begin

DUT: decoder3to8 port map(A => A_tb, Y => Y_tb);

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

process

begin

A_tb <= "000"; wait for 10 ns;

A_tb <= "001"; wait for 10 ns;

A_tb <= "010"; wait for 10 ns;

A_tb <= "011"; wait for 10 ns;

A_tb <= "100"; wait for 10 ns;

A_tb <= "101"; wait for 10 ns;

A_tb <= "110"; wait for 10 ns;

A_tb <= "111"; wait for 10 ns;

wait;

end process;

end testbench;

1.4. Simulation & Verification

Testbench Setup

• Input values A, B, C are provided.

• Output Y is observed.

• Multiple test cases validate functionality.

1.5. Simulation Results

Expected Output:

• A=0, B=0, C=0 → Y=11111110

• A=0, B=0, C=1 → Y=11111101

• A=0, B=1, C=0 → Y=11111011

• A=0, B=1, C=1 → Y=11110111

• A=1, B=0, C=0 → Y=11101111

• A=1, B=0, C=1 → Y=11011111

• A=1, B=1, C=0 → Y=10111111

• A=1, B=1, C=1 → Y=01111111

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Simulated Input-Output Waveforms

The design was simulated in GHDL3.0.0. The waveform confirmed correct decoder output values
for different test cases.

figure.1.3: Waveform of the 3 to 8 decoder

1.6. Results and Discussion

The 3-to-8 Decoder was successfully implemented and verified. The simulation results matched the
expected truth table, confirming the correctness of the design. The design was simulated in
GHDL3.0.0. The waveform confirmed correct decoder output values for different test cases.

EDA LINK: https://www.edaplayground.com/x/JCw5

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Evaluation Criteria for Block-Level Verification in UVM

2.1. Testbench Architecture

figure.2.1: Block diagram of UVM

design.sv

module binary_decoder(

input clk, reset,

input [2:0] in,

output reg [7:0] out);

always@(posedge clk or posedge reset) begin

if(reset) out <= 0;

else begin

case(in)

3'b000: out <= 8'b0000_0001;

3'b001: out <= 8'b0000_0010;

3'b010: out <= 8'b0000_0100;

3'b011: out <= 8'b0000_1000;

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

3'b100: out <= 8'b0001_0000;

3'b101: out <= 8'b0010_0000;

3'b110: out <= 8'b0100_0000;

3'b111: out <= 8'b1000_0000;

default: out <= 0;

endcase

end

end

endmodule

testbench.sv

`include "interface.sv"

`include "base_test.sv"

import uvm_pkg::*; // Import UVM library

`include "uvm_macros.svh" // Include UVM macro

module tb_top;

bit clk;

bit reset;

always #2 clk = ~clk;

add_if vif(clk, reset);

binary_decoder DUT(.clk(vif.clk), .reset(vif.reset), .in(vif.ip), .out(vif.out));

initial begin

clk = 0;

reset = 1;

#5;

reset = 0;

end

initial begin

// Set virtual interface in UVM configuration database

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

uvm_config_db#(virtual add_if)::set(null, "*", "vif", vif);

// Run the UVM test

run_test("base_test");

end

initial begin

// Dump waves

$dumpfile("dump.vcd");

$dumpvars(0);

end

endmodule

base_test.sv

import my_pkg::*; // This should match the package name

class base_test extends uvm_test;

`uvm_component_utils(base_test)

env env_o;

function new(string name = "base_test", uvm_component parent = null);

super.new(name, parent);

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

env_o = env::type_id::create("env_o", this);

endfunction

task run_phase(uvm_phase phase);

phase.raise_objection(this);

#100;

phase.drop_objection(this);

endtask

endclass

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

env.sv

class env extends uvm_env;

`uvm_component_utils(env)

agent agt; // Declare an agent

function new(string name = "env", uvm_component parent = null);

super.new(name, parent);

endfunction

function void build_phase(uvm_phase phase);

super.build_phase(phase);

agt = agent::type_id::create("agt", this); // Create agent instance

endfunction

endclass

agent.sv

class agent;

driver drv;

monitor mon;

generator gen;

mailbox gen_to_drv;

virtual add_if vif;

function new(virtual add_if vif, mailbox mon_to_sb);

gen_to_drv = new();

drv = new(gen_to_drv, vif);

mon = new(mon_to_sb, vif);

gen = new(gen_to_drv);

endfunction

task run();

fork

drv.run();

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

mon.run();

gen.run();

join_any

endtask

endclass

driver.sv

class driver;

virtual add_if vif;

mailbox gen_to_drv;

function new(mailbox gen_to_drv, virtual add_if vif);

this.gen_to_drv = gen_to_drv;

this.vif = vif;

endfunction

task run;

forever begin

transaction tr;

wait(!vif.reset);

tr = new();

@(posedge vif.clk);

gen_to_drv.get(tr);

vif.ip = tr.ip;

@(posedge vif.clk);

tr.out = vif.out;

end

endtask

endclass

transaction.sv

class transaction;

rand bit [2:0] ip;

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

bit [7:0] out;

constraint ip_limit {ip < 10;}

endclass

interface.sv

interface add_if(input logic clk, reset);

logic [2:0] ip;

logic [7:0] out;

endinterface

my_pkg.sv

package my_pkg;

`include "uvm_macros.svh"

import uvm_pkg::*;

`include "transaction.sv"

`include "generator.sv"

`include "driver.sv"

`include "monitor.sv"

`include "scoreboard.sv"

`include "agent.sv"

`include "env.sv"

endpackage : my_pkg

monitor.sv

class monitor;

virtual add_if vif;

mailbox mon_to_sb;

int i=1;

function new(mailbox mon_to_sb, virtual add_if vif);

this.vif = vif;

this.mon_to_sb = mon_to_sb;

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

endfunction

task run;

forever begin

transaction mon_tr;

wait(!vif.reset);

@(posedge vif.clk);

mon_tr = new();

mon_tr.ip = vif.ip;

@(posedge vif.clk);

mon_tr.out = vif.out;

mon_to_sb.put(mon_tr);

end

endtask

endclass

scoreboard.sv

class scoreboard;

int compare_cnt;

mailbox mon_to_sb;

int i,j;

function new(mailbox mon_to_sb);

this.mon_to_sb = mon_to_sb;

endfunction

task run;

forever begin

transaction tr;

tr = new();

mon_to_sb.get(tr);

j = tr.ip;

i = $pow(2,j);

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

if(i==tr.out)begin

$display("Matched: ip1 = %0d, out = %8b, expected out = %8b", tr.ip, tr.out,
i);

end

else begin

$display("NOT matched: ip1 = %0d, out = %8b, expected out = %8b", tr.ip,
tr.out, i);

end

compare_cnt++;

end

endtask

endclass

generator.sv

class generator;

int count;

mailbox gen_to_drv;

transaction tr;

function new(mailbox gen_to_drv);

this.gen_to_drv = gen_to_drv;

endfunction

task run;

repeat(count) begin

tr = new();

void'(tr.randomize());

gen_to_drv.put(tr);

end

endtask

endcl

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

2.2. Simulated Input-Output Waveforms

The design was simulated in Cadence Xcelium 23.09. The waveform confirmed correct decoder
output values for different test cases.

figure.2.2: UVM Waveform of the 3 to 8 decoder

2.3. Results and Discussion

The 3-to-8 Decoder was successfully verified using a UVM-based testbench. The testbench
architecture consisted of a driver, monitor, agent, environment, and scoreboard, ensuring a
structured verification approach. The stimulus was generated using UVM sequences, covering all
possible input cases.

• The UVM testbench successfully drove all input combinations and monitored the
corresponding output responses.

• The scoreboard compared the expected and actual outputs, and all test cases passed without
mismatches.

• The waveform analysis confirmed that the decoder correctly activated the expected output
for each input combination.

EDA LINK: https://www.edaplayground.com/x/WTXA

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Generate GDS using OpenROAD tool

Technology/Platform utilized: gf180

3.1. Instructions for the config.mk
export DESIGN_NICKNAME = decoder_3to8

export DESIGN_NAME = decoder_3to8

export PLATFORM = gf180

export VERILOG_FILES = $(sort $(wildcard

$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/decoder_3to8.v))

export SDC_FILE =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

#export PLACE_PINS_ARGS = -min_distance 4 -min_distance_in_tracks

export CORE_UTILIZATION = 0.5

#export CORE_ASPECT_RATIO = 1

#export CORE_MARGIN = 2

export PLACE_DENSITY = 0.1

export TNS_END_PERCENT = 100

#export EQUIVALENCE_CHECK ?= 0

#export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hd__tapvpwrvgnd*

#export FASTROUTE_TCL =
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl

export REMOVE_ABC_BUFFERS = 1

3.2. Instructions of the constraint.sdc

current_design decoder_3to8

set clk_name v_clk

#set clk_port_name clk

set clk_period 2.5

set clk_io_pct 0.2

#create_clock -name $clk_name -period $clk_period

set non_clock_inputs [lsearch -inline -all -not [all_inputs]]

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs

set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

figure.3.1: Layout of the Design

3.3. Performance Analysis

Power Measurement

Group Internal Switching Leakage Total

Power Power Power Power (Watts)
Sequential 0.00e+00 0.00e+00 0.00e+00 0.00e+00
0.0%
Combinational 1.25e-12 3.99e-13 4.11e-09 4.11e-09
38.2%
Clock 0.00e+00 0.00e+00 6.66e-09 6.66e-09
61.8%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00
0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00
0.0%
Total 1.25e-12 3.99e-13 1.08e-08 1.08e-08
100.0%

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Area Measurement

• Design Area: 4462 µ²

• Utilization: 2%

Timing Information

Delay Time Description

(ns) (ns)
0.00 0.00 v input external delay
0.00 0.00 v A[0] (in)
0.00 0.00 v A[1] (in)
0.00 0.00 v A[2] (in)
0.10 0.10 ^ inv1/Z (gf180mcu_fd_sc_mcu9t5v0 clkinv_2)
0.12 0.22 ^ and1/Z (gf180mcu_fd_sc_mcu9t5v0 and2_2)
0.15 0.37 ^ and2/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.18 0.55 ^ and3/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.20 0.75 ^ and4/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.22 0.97 ^ and5/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.25 1.22 ^ and6/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.27 1.49 ^ and7/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.30 1.79 ^ and8/Z (gf180mcu_fd_sc_mcu9t5v0 and3_2)
0.00 1.79 v Y[0] (out)
0.00 1.79 v Y[1] (out)
0.00 1.79 v Y[2] (out)
0.00 1.79 v Y[3] (out)
0.00 1.79 v Y[4] (out)
0.00 1.79 v Y[5] (out)
0.00 1.79 v Y[6] (out)
0.00 1.79 v Y[7] (out)

figure.3.2: Generated GDS

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Design of a 3-to-8 Decoder using Verilog/SystemVerilog/VHDL 2024-25

Conclusion

In this report, the RTL code of the 3-to-8 decoder has been designed in Verilog. The code is
successfully verified using UVM with a 100% test case pass. The design is further processed in the
OpenROAD tool to generate its GDS using the GF180 platform. The generated layout consumes
108 nW power and occupies 4462 sq. µm area. There are no setup and hold violations.

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