Combinational Logic circuits

The combinational logic circuits are the circuits that contain different
types of logic gates. Simply, a circuit in which different types of logic
gates are combined is known as a combinational logic circuit. The
output of the combinational circuit is determined from the present
combination of inputs, regardless of the previous input. The input
variables, logic gates, and output variables are the basic components of
the combinational logic circuit. There are different types of combinational
logic circuits, such as Adder, Subtractor, Decoder, Encoder, Multiplexer,
and De-multiplexer.

There are the following characteristics of the combinational logic circuit:

o At any instant of time, the output of the combinational circuits

depends only on the present input terminals.
o The combinational circuit doesn't have any backup or previous
memory. The present state of the circuit is not affected by the
previous state of the input.
o The n number of inputs and m number of outputs are possible in
combinational logic circuits.

The 'n' input variable comes from the external source while the 'm' output
variable goes to the external destination. In many applications, the source
or destinations are storage registers.
Half Adder in Digital Logic

Introduction:
A half adder is a digital logic circuit that performs binary addition of
two single-bit binary numbers. It has two inputs, A and B, and two
outputs, SUM and CARRY. The SUM output is the least significant bit
(LSB) of the result, while the CARRY output is the most significant bit
(MSB) of the result, indicating whether there was a carry-over from
the addition of the two inputs. The half adder can be implemented
using basic gates such as XOR and AND gates.
Sure, here’s a more in-depth explanation of the half adder circuit:
The half adder is a basic building block for more complex adder
circuits such as full adders and multiple-bit adders. It performs
binary addition of two single-bit inputs, A and B, and provides two
outputs, SUM and CARRY.
The SUM output is the least significant bit (LSB) of the result, which
is the XOR of the two inputs A and B. The XOR gate implements the
addition operation for binary digits, where a “1” is generated in the
SUM output only when one of the inputs is “1”.
The CARRY output is the most significant bit (MSB) of the result,
indicating whether there was a carry-over from the addition of the
two inputs. The CARRY output is the AND of the two inputs A and B.
The AND gate generates a “1” in the CARRY output only when both
inputs are “1”.
Half Adder (HA):
Half adder is the simplest of all adder circuits. Half adder is a
combinational arithmetic circuit that adds two numbers and
produces a sum bit (s) and carry bit (c) both as output. The addition
of 2 bits is done using a combination circuit called a Half adder. The
input variables are augend and addend bits and output variables are
sum & carry bits. A and B are the two input bits.
let us consider two input bits A and B, then sum bit (s) is the X-OR of
A and B. it is evident from the function of a half adder that it
requires one X-OR gate and one AND gate for its construction.
Truth Table:

Here we perform two operations Sum and Carry, thus we need two
K-maps one for each to derive the expression.

Logical Expression:

For Sum:

Sum = A XOR B
For Carry:

Carry = A AND B
Implementation:

Note: Half adder has only two inputs and there is no provision to
add a carry coming from the lower order bits when multi addition is
performed.
Advantages and disadvantages of Half Adder in Digital
Logic :

Advantages of Half Adder in Digital Logic :

1.Simplicity: A half viper is a straightforward circuit that requires a

couple of fundamental parts like XOR AND entryways. It is not
difficult to carry out and can be utilized in numerous advanced
frameworks.
2.Speed: The half viper works at an extremely rapid, making it
reasonable for use in fast computerized circuits.
Disadvantages of Half Adder in Digital Logic :
1.Limited Usefulness: The half viper can add two single-piece
numbers and produce a total and a convey bit. It can’t perform
expansion of multi-bit numbers, which requires the utilization of
additional intricate circuits like full adders.
2. Lack of Convey Info: The half snake doesn’t have a convey
input, which restricts its value in more mind boggling expansion
tasks. A convey input is important to perform expansion of multi-bit
numbers and to chain numerous adders together.
3. Propagation Deferral: The half snake circuit has a proliferation
delay, which is the time it takes for the result to change in light of an
adjustment of the info. This can cause timing issues in computerized
circuits, particularly in fast frameworks.

Application of Half Adder in Digital Logic:

 1. Arithmetic circuits: Half adders are utilized in number-
crunching circuits to add double numbers. At the point when
different half adders are associated in a chain, they can add multi-
bit double numbers.
2. Data handling: Half adders are utilized in information handling
applications like computerized signal handling, information
encryption, and blunder adjustment.
3. Address unraveling: In memory tending to, half adders are
utilized in address deciphering circuits to produce the location of a
particular memory area.

4. Encoder and decoder circuits: Half adders are utilized in

encoder and decoder circuits for computerized correspondence
frameworks.

5. Multiplexers and demultiplexers: Half adders are utilized in

multiplexers and demultiplexers to choose and course information.
6. Counters: Half adders are utilized in counters to augment the
count by one.
Full Adder in Digital Logic
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Full Adder is the adder that adds three inputs and produces two
outputs. The first two inputs are A and B and the third input is an
input carry as C-IN. The output carry is designated as C-OUT and the
normal output is designated as S which is SUM. The C-OUT is also
known as the majority 1’s detector, whose output goes high when
more than one input is high. A full adder logic is designed in such a
manner that can take eight inputs together to create a byte-wide
adder and cascade the carry bit from one adder to another. we use a
full adder because when a carry-in bit is available, another 1-bit
adder must be used since a 1-bit half-adder does not take a carry-in
bit. A 1-bit full adder adds three operands and generates 2-bit
results.
 Full Adder Truth Table:

Logical Expression for SUM: = A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’

+ A B C-IN = C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’) = C-IN XOR (A
XOR B) = (1,2,4,7)
Logical Expression for C-OUT: = A’ B C-IN + A B’ C-IN + A B C-IN’
+ A B C-IN = A B + B C-IN + A C-IN = (3,5,6,7)
0 seconds of 17 secondsVolume 0%

Another form in which C-OUT can be implemented: = A B + A

C-IN + B C-IN (A + A’) = A B C-IN + A B + A C-IN + A’ B C-IN = A B (1
+C-IN) + A C-IN + A’ B C-IN = A B + A C-IN + A’ B C-IN = A B + A C-
IN (B + B’) + A’ B C-IN = A B C-IN + A B + A B’ C-IN + A’ B C-IN = A
B (C-IN + 1) + A B’ C-IN + A’ B C-IN = A B + A B’ C-IN + A’ B C-IN =
AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)
 Full Adder logic circuit.

Implementation of Full Adder using Half Adders:

2 Half Adders and an OR gate is required to implement a Full Adder.
With this logic circuit, two bits can be added together, taking a carry
from the next lower order of magnitude, and sending a carry to the
next higher order of magnitude.
Implementation of Full Adder using NAND gates:
Implementation of Full Adder using NOR gates:

NOR gates are required to implement a Full Adder.

In the logic expression above, one would recognize the logic

expressions of a 1-bit half-adder. A 1-bit full adder can be
accomplished by cascading two 1-bit half adders.
Advantages and Disadvantages of Full Adder in Digital Logic
Advantages of Full Adder in Digital Logic:
1. Flexibility: A full snake can add three information bits, making it
more flexible than a half viper. It can likewise be utilized to add
multi-bit numbers by binding different full adders together.
2. Carry Info: The full viper has a convey input, which permits it to
perform expansion of multi-bit numbers and to chain different
adders together.
3. Speed: The full snake works at an extremely fast, making it
reasonable for use in rapid computerized circuits.
Disadvantages of Full Adder in Digital Logic:
1. Complexity: The full snake is more mind boggling than a half
viper and requires more parts like XOR, AND, or potentially
entryways. It is likewise more challenging to execute and plan.
2. Propagation Deferral: The full viper circuit has a proliferation
delay, which is the time it takes for the result to change in light of an
adjustment of the info. This can cause timing issues in computerized
circuits, particularly in fast frameworks.

Application of Full Adder in Digital Logic:

1. Arithmetic circuits: Full adders are utilized in math circuits to

add twofold numbers. At the point when different full adders are
associated in a chain, they can add multi-bit paired numbers.
2. Data handling: Full adders are utilized in information handling
applications like advanced signal handling, information encryption,
and mistake rectification.

3. Counters: Full adders are utilized in counters to addition or

decrement the count by one.
4. Multiplexers and demultiplexers: Full adders are utilized in
multiplexers and demultiplexers to choose and course information.
5. Memory tending to: Full adders are utilized in memory
addressing circuits to produce the location of a particular memory
area.
6. ALUs: Full adders are a fundamental part of Number juggling
Rationale Units (ALUs) utilized in chip and computerized signal
processors.

Difference between the Half adder and full adder:

S.No. Parameters Half Adder Full Adder

Half Adder is a A full adder is a combinational logic

combinational logic circuit that performs an addition
circuit that adds two operation on three one-bit binary
1-bit digits. The half numbers. The full adder produces a
adder produces a sum sum of the three inputs and carry
1. Description of the two inputs. value.

2. Previous The previous carry is The previous carry is used.

S.No. Parameters Half Adder Full Adder

carry not used.

In Half adder, there

In full adder, there are three input
are two input bits ( A,
bits (A, B, C-in).
3. Inputs B).

The generated output

The generated output is of two bits-
is of two bits-Sum and
Sum and Carry from the input of 3
Carry from the input
bits.
4. Outputs of 2 bits.

A half adder circuit

cannot be used in the A full adder circuit can be used in
same way as a full place of a half adder circuit.
5. Used as adder circuit.

It is simple and easy to The design of a full adder is not as

6. Feature implement simple as a half adder.

Logical Expression for

Logical Expression for Full adder is :
Logical half adder is : S=a⊕b ;
S=a⊕b⊕Cin; Cout=(a*b)+(Cin*(a⊕b)).
7. Expression C=a*b.

It consists of one EX-

It consists of two EX-OR, two AND
OR gate and one AND
gates, and one OR gate.
8. Logic gates gate.

9. Applications It is used in It is used in Multiple bit addition,

Calculators,
S.No. Parameters Half Adder Full Adder

computers, digital
measuring devices, digital processors, etc.
etc.

Alternate There is no alternate Full adder is also known as ripple-

10. name name for half adder. carry adder.

Half Subtractor in Digital Logic

A half subtractor is a digital logic circuit that performs binary
subtraction of two single-bit binary numbers. It has two inputs, A
and B, and two outputs, DIFFERENCE and BORROW. The
DIFFERENCE output is the difference between the two input bits,
while the BORROW output indicates whether borrowing was
necessary during the subtraction.
The half subtractor can be implemented using basic gates such as
XOR and NOT gates. The DIFFERENCE output is the XOR of the two
inputs A and B, while the BORROW output is the NOT of input A and
the AND of inputs A and B.
Half Subtractor
Half subtractor is a combination circuit with two inputs and two
outputs that are different and borrow. It produces the difference
between the two binary bits at the input and also produces an
output (Borrow) to indicate if a 1 has been borrowed. In the
subtraction (A-B), A is called a Minuend bit and B is called a Subtrahend
bit.
Truth Table

The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB'
Borrow = A'B
Implementation

Logical Expression
Difference = A XOR B
Borrow = \overline{A}B

Advantages of Half Adder and Half Subtractor

1. Simplicity: The half adder and half subtractor circuits are simple
and easy to design, implement, and debug compared to other
binary arithmetic circuits.
2. Building blocks: The half adder and half subtractor are basic
building blocks that can be used to construct more complex
arithmetic circuits, such as full adders and subtractors, multiple-
bit adders and subtractors, and carry look-ahead adders.
3. Low cost: The half adder and half subtractor circuits use only a
few gates, which reduces the cost and power consumption
compared to more complex circuits.
4. Easy integration: The half adder and half subtractor can be
easily integrated with other digital circuits and systems.
Disadvantages of Half Adder and Half Subtractor

1. Limited functionality: The half adder and half subtractor can

only perform binary addition and subtraction of two single-bit
numbers, respectively, and are not suitable for more complex
arithmetic operations.
2. Inefficient for multi-bit numbers: For multi-bit numbers,
multiple half adders or half subtractors need to be cascaded,
which increases the complexity and decreases the efficiency of
the circuit.
3. High propagation delay: The propagation delay of the half
adder and half subtractor is higher compared to other arithmetic
circuits, which can affect the overall performance of the system.

Application of Half Subtractor in Digital Logic:

1. Calculators: Most mini-computers utilize advanced rationale
circuits to perform numerical tasks. A Half Subtractor can be utilized
in a number cruncher to deduct two parallel digits from one another.
2. Alarm Frameworks: Many caution frameworks utilize
computerized rationale circuits to identify and answer interlopers. A
Half Subtractor can be utilized in these frameworks to look at the
upsides of two parallel pieces and trigger a caution in the event that
they are unique.
3. Automotive Frameworks: Numerous advanced vehicles utilize
computerized rationale circuits to control different capabilities, like
the motor administration framework, stopping mechanism, and
theater setup. A Half Subtractor can be utilized in these frameworks
to perform computations and examinations.

4. Security Frameworks: Advanced rationale circuits are usually

utilized in security frameworks to identify and answer dangers. A
Half Subtractor can be utilized in these frameworks to look at two
double qualities and trigger a caution in the event that they are
unique.
5. Computer Frameworks: Advanced rationale circuits are utilized
broadly in PC frameworks to perform estimations and examinations.
A Half Subtractor can be utilized in a PC framework to deduct two
paired values from one another.

Full Subtractor in Digital Logic

A full subtractor is a combinational circuit that performs
subtraction of two bits, one is minuend and other is subtrahend,
taking into account borrow of the previous adjacent lower minuend
bit. This circuit has three inputs and two outputs. The three
inputs A, B and Bin, denote the minuend, subtrahend, and previous
borrow, respectively. The two outputs, D and Bout represent the
difference and output borrow, respectively. Although subtraction is
usually achieved by adding the complement of subtrahend to the
minuend, it is of academic interest to work out the Truth Table and
logic realisation of a full subtractor; x is the minuend; y is the
subtrahend; z is the input borrow; D is the difference; and B denotes
the output borrow. The corresponding maps for logic functions for
outputs of the full subtractor namely difference and borrow.

Here’s how a full subtractor works:

1. First, we need to convert the binary numbers to their two’s
complement form if we are subtracting a negative number.
2. Next, we compare the bits in the minuend and subtrahend at the
corresponding positions. If the subtrahend bit is greater than or
equal to the minuend bit, we need to borrow from the previous
stage (if there is one) to subtract the subtrahend bit from
the minuend bit.
3. We subtract the two bits along with the borrow-in to get the
difference bit. If the minuend bit is greater than or equal to the
subtrahend bit along with the borrow-in, then the difference bit is 1,
otherwise it is 0.
4. We then calculate the borrow-out bit by comparing the minuend
and subtrahend bits. If the minuend bit is less than the subtrahend
bit along with the borrow-in, then we need to borrow for the next
stage, so the borrow-out bit is 1, otherwise it is 0.
The circuit diagram for a full subtractor usually consists of two half-
subtractors and an additional OR gate to calculate the borrow-out
bit. The inputs and outputs of the full subtractor are as follows:
Inputs:
A: minuend bit
B: subtrahend bit
Bin: borrow-in bit from the previous stage
Outputs:
Diff: difference bit
Bout: borrow-out bit for the next stage
Truth Table –
From above table we can draw the K-Map as shown for “difference”

and “borrow”.

Logical expression for difference –

D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin
Logical expression for borrow –
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= A’B’Bin +A’BBin’ + A’BBin + A’BBin + A’BBin + ABBin
= A’Bin(B + B’) + A’B(Bin + Bin’) + BBin(A + A’)
= A’Bin + A’B + BBin

OR
Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= Bin (AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B
Logic Circuit for Full Subtractor –

Implementation of Full Subtractor using Half Subtractors – 2 Half

Subtractors and an OR gate is required to implement a Full
Subtractor.

Parallel Adder and Parallel Subtractor

Parallel Adder –
A single full adder performs the addition of two one bit numbers
and an input carry. But a Parallel Adder is a digital circuit capable
of finding the arithmetic sum of two binary numbers that
is greater than one bit in length by operating on corresponding
pairs of bits in parallel. It consists of full adders connected in a
chain where the output carry from each full adder is connected to
the carry input of the next higher order full adder in the chain. A n
bit parallel adder requires n full adders to perform the
operation. So for the two-bit number, two adders are needed
while for four bit number, four adders are needed and so on.
Parallel adders normally incorporate carry lookahead logic to
ensure that carry propagation between subsequent stages of
addition does not limit addition speed.

Working of parallel Adder –

1. As shown in the figure, firstly the full adder FA1 adds A1 and B1
along with the carry C1 to generate the sum S1 (the first bit of
the output sum) and the carry C2 which is connected to the next
adder in chain.
2. Next, the full adder FA2 uses this carry bit C2 to add with the
input bits A2 and B2 to generate the sum S2(the second bit of
the output sum) and the carry C3 which is again further
connected to the next adder in chain and so on.
3. The process continues till the last full adder FAn uses the carry
bit Cn to add with its input An and Bn to generate the last bit of
the output along last carry bit Cout.
Parallel Subtractor –
A Parallel Subtractor is a digital circuit capable of finding the
arithmetic difference of two binary numbers that is greater than
one bit in length by operating on corresponding pairs of bits in
parallel. The parallel subtractor can be designed in several ways
including combination of half and full subtractors, all full
subtractors or all full adders with subtrahend complement input.
Working of Parallel Subtractor –
1. As shown in the figure, the parallel binary subtractor is formed
by combination of all full adders with subtrahend complement
input.
2. This operation considers that the addition of minuend along with
the 2’s complement of the subtrahend is equal to their
subtraction.
3. Firstly the 1’s complement of B is obtained by the NOT gate and
1 can be added through the carry to find out the 2’s complement
of B. This is further added to A to carry out the arithmetic
subtraction.
4. The process continues till the last full adder FAn uses the carry
bit Cn to add with its input An and 2’s complement of Bn to
generate the last bit of the output along last carry bit Cout.
Advantages of parallel Adder/Subtractor –
1. The parallel adder/subtractor performs the addition operation
faster as compared to serial adder/subtractor.
2. Time required for addition does not depend on the number of
bits.
3. The output is in parallel form i.e all the bits are added/subtracted
at the same time.
4. It is less costly.
Disadvantages of parallel Adder/Subtractor –
1. Each adder has to wait for the carry which is to be generated
from the previous adder in chain.
2. The propagation delay( delay associated with the travelling of
carry bit) is found to increase with the increase in the number of
bits to be added.

Binary Adder-Subtractor
A Binary Adder-Subtractor is a special type of circuit that is used to
perform both operations, i.e., Addition and Subtraction. The operation
which is going to be used depends on the values contained by the control
signal. In Arithmetic Logical Unit, it is one of the most important
components.

To work with Binary Adder-Subtractor, it is required that we have

knowledge of the XOR gate, Full-Adder, Binary Addition, and subtraction.

For example, we will take two 4-bit binary numbers 'X' and 'Y' for the
operation with digits.

X0 X1 X2 X3 for X
Y0 Y1 Y2 Y3 for Y

The Binary Adder-Subtractor is a combination of 4 Full-Adder, which is

able to perform the addition and subtraction of 4-bit binary numbers. The
control line determines whether the operation being performed is either
subtraction or addition. This determination is done by the binary values 0
and 1, which is hold by K.
In the above diagram, the control lines of the first Full-Adder is directly
coming as its input(input carry C0). The X 0 is the least significant bit of A,
which is directly inputted in the Full-Adder. The result produced by
performing the XOR operation of Y 0 and K is the third input of the Binary
Adder-Subtractor. The sum/difference(S0) and carry(C0) are the two
outputs produced from the First Full-adder.

When the value of K is set to true or 1, the Y 0⨁K produce the complement
of Y0 as the output. So the operation would be X+Y 0', which is the 2's
complement subtraction of X and Y. It means when the value of K is 1; the
subtraction operation is performed by the binary Adder-Subtractor.

In the same way, when the value of K is set to 0, the Y 0⨁K produce Y0 as
the output. So the operation would be X+Y 0, which is the binary addition
of X and Y. It means when the value of K is 0; the addition operation is
performed by the binary Adder-Subtractor.

The carry/borrow C0 is treated as the carry/borrow input for the second

Full-Adder. The sum/difference S0 defines the least significant bit of the
sum/difference of numbers X and Y. Just like X 0, the X1, X2, and X3 are
faded directly to the 2nd, 3rd, and 4th Full-Adder as an input. The outputs
after performing the XOR operation of Y1, Y2, and Y3 inputs with K are the
third inputs for 2nd, 3rd, and 4th Full-Adder. The carry C1, C2 are passed as
the input to the Full-Adder.
Cout is the output carry of the sum/difference. To form the final result, the
S1, S2, S3 are recorded with s0. We will use n number of Full-Adder to
design the n-bit binary Adder-Subtractor

Multiplexer
A multiplexer is a combinational circuit that has 2 n input lines and a single
output line. Simply, the multiplexer is a multi-input and single-output
combinational circuit. The binary information is received from the input
lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2 n input lines.
So, there is a total of 2N possible combinations of inputs. A multiplexer is
also treated as Mux.

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection
line, i.e., S0 and single outputs, i.e., Y. On the basis of the combination of
inputs which are present at the selection line S 0, one of these 2 inputs will
be connected to the output. The block diagram and the truth table of the
2×1 multiplexer are given below.

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Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and
A3, 2 selection lines, i.e., S0 and S1 and single output, i.e., Y. On the basis
of the combination of inputs that are present at the selection lines S 0 and
S1, one of these 4 inputs are connected to the output. The block diagram
and the truth table of the 4×1 multiplexer are given below.

De-multiplexer
A De-multiplexer is a combinational circuit that has only 1 input line and
2N output lines. Simply, the multiplexer is a single-input and multi-output
combinational circuit. The information is received from the single input
lines and directed to the output line. On the basis of the values of the
selection lines, the input will be connected to one of these outputs. De-
multiplexer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs.
So, there is a total of 2 n possible combinations of inputs. De-multiplexer is
also treated as De-mux.

There are various types of De-multiplexer which are as follows:

1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1
selection lines, i.e., S0, and single input, i.e., A. On the basis of the
selection value, the input will be connected to one of the outputs. The
block diagram and the truth table of the 1×2 multiplexer are given below.

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Block Diagram:

Truth Table:
The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

Logical circuit of the above expressions is given below:

1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and
Y3, 2 selection lines, i.e., S0 and S1 and single input, i.e., A. On the basis of
the combination of inputs which are present at the selection lines S 0 and
S1, the input be connected to one of the outputs. The block diagram and
the truth table of the 1×4 multiplexer are given below.

Block Diagram:
Truth Table:

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The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

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Logical circuit of the above expressions is given below:

1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3,
Y4, Y5, Y6, and Y7, 3 selection lines, i.e., S 0, S1and S2 and single input, i.e., A.
On the basis of the combination of inputs which are present at the
selection lines S0, S1 and S2, the input will be connected to one of these
outputs. The block diagram and the truth table of the 1×8 de-multiplexer
are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

Logical circuit of the above expressions is given below:

1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer
We can implement the 1×8 de-multiplexer using a lower order de-
multiplexer. To implement the 1×8 de-multiplexer, we need two 1×4 de-
multiplexer and one 1×2 de-multiplexer. The 1×4 multiplexer has 2
selection lines, 4 outputs, and 1 input. The 1×2 de-multiplexer has only 1
selection line.

For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-
multiplexer produces two outputs. So, in order to get the final output, we
have to pass the outputs of 1×2 de-multiplexer as an input of both the
1×4 de-multiplexer. The block diagram of 1×8 de-multiplexer using 1×4
and 1×2 de-multiplexer is given below.

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1 x 16 De-multiplexer
In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y 0, Y1, …, Y16, 4
selection lines, i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis
of the combination of inputs which are present at the selection lines S 0, S1,
and S2, the input will be connected to one of these outputs. The block
diagram and the truth table of the 1×16 de-multiplexer are given below.
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3

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Logical circuit of the above expressions is given below:

1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer
We can implement the 1×16 de-multiplexer using a lower order de-
multiplexer. To implement the 1×16 de-multiplexer, we need two 1×8 de-
multiplexer and one 1×2 de-multiplexer. The 1×8 multiplexer has 3
selection lines, 1 input, and 8 outputs. The 1×2 de-multiplexer has only 1
selection line.

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For getting 16 data outputs, we need two 1×8 de-multiplexer. The 1×8
de-multiplexer produces eight outputs. So, in order to get the final output,
we need a 1×2 de-multiplexer to produce two outputs from a single input.
Then we pass these outputs into both the de-multiplexer as an input. The
block diagram of 1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer
is given below.
Block Diagram:

Truth Table:

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The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

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Logical circuit of the above expression is given below:

8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4,
A5, A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y.
On the basis of the combination of inputs that are present at the selection
lines S0, S1, and S2, one of these 8 inputs are connected to the output. The
block diagram and the truth table of the 8×1 multiplexer are given below.
Block Diagram:

Truth Table:
The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2
A5+S0'.S1.S2 .A6+S0.S1.S3.A7

Logical circuit of the above expression is given below:

8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer.
To implement the 8×1 multiplexer, we need two 4×1 multiplexers and
one 2×1 multiplexer. The 4×1 multiplexer has 2 selection lines, 4 inputs,
and 1 output. The 2×1 multiplexer has only 1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1
multiplexer produces one output. So, in order to get the final output, we
need a 2×1 multiplexer. The block diagram of 8×1 multiplexer using 4×1
and 2×1 multiplexer is given below.
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16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4
selection lines, i.e., S0, S1, S2, and S3 and single output, i.e., Y. On the basis
of the combination of inputs that are present at the selection lines S 0, S1,
and S2, one of these 16 inputs will be connected to the output. The block
diagram and the truth table of the 16×1
Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S

0 '.S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '
+A11.S0.S1'.S2.S3+A12 S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

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16×1 multiplexer using 8×1 and 2×1 multiplexer
We can implement the 16×1 multiplexer using a lower order multiplexer.
To implement the 8×1 multiplexer, we need two 8×1 multiplexers and
one 2×1 multiplexer. The 8×1 multiplexer has 3 selection lines, 4 inputs,
and 1 output. The 2×1 multiplexer has only 1 selection line.

For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1

multiplexer produces one output. So, in order to get the final output, we
need a 2×1 multiplexer. The block diagram of 16×1 multiplexer using
8×1 and 2×1 multiplexer is given below.
 .

Difference between Multiplexer and Demultiplexer

Both multiplexer and demultiplexer are types of combinational digital circuit

that are used in several large-scale digital systems. However, there are many
differences between a multiplexer and a demultiplexer, which are highlighted
in the following table −

Basis of Multiplexer Demultiplexer

Difference

A multiplexer is a A demultiplexer is a
combinational digital combinational digital
Definition circuit that takes multiple circuit that takes single
data inputs and provides input and provides
only single output. multiple outputs.

Abbreviated The abbreviation used to The abbreviation used to

 Basis of Multiplexer Demultiplexer
Difference

represent the multiplexer represent the

name
is MUX. demultiplexer is DEMUX.

Multiplexer has 2n input Demultiplexer has 1

Input and lines and 1 output line. input line and 2n output
output lines Where, n is the number of lines. Where, n is the
select lines. number of select lines.

Multiplexer is also known Demultiplexer is also

Also known as as a "data selector". known as "data
distributor".

The operating principle of The operating principle

Operating
the multiplexer is "many of a demultiplexer is "ne
principle
to one". to many".

Multiplexer acts as a Demultiplexer acts as a

Acts as digital multi-position digital circuit.
switch.

A multiplexer performs A demultiplexer

Conversion
parallel to serial performs serial to
technique
conversion. parallel conversion.

In case of multiplexer, the In demultiplexer, the

function of control signal function of control signal
Function of
is to select a specific input is to deliver the single
control signal
that has to be transmitted input signal over the
at the output. multiple output lines.

Examples Examples of some Some common

 Basis of Multiplexer Demultiplexer
Difference

common multiplexers are demultiplexers are −

−
 1:2 Demultiplexer
 8:1 Multiplexer  1:4 Demultiplexer
 16:1 Multiplexer  1:8 Demultiplexer
 32:1 Multiplexer  1:16 Demultiplexer

In practice, the In practice, the

multiplexer increases the demultiplexer takes the
efficiency of the output of a multiplexer
Practical
communication system by and convert in its
importance
enabling the data original form at the
transmission using a receiver end.
single line.

A multiplexer is used at The demultiplexer is

Usage in
the transmitter end in the used at the receiver end
time-division
time-division multiplexing in the time-division
multiplexing
(TDM). multiplexing.

The multiplexers are The demultiplexers are

commonly used in used in communication
communication systems, systems, reconstruction
Applications telephone networks, of parallel data, ALU,
computer memories, etc. etc.
Implimentation of Boolean equation using
multiplexer
Example 1

Use a 4:1 multiplexer to implement the following two variable logic function.

F(A+B)=∑m(0,1,3)�(�+�)=∑�(0,1,3)

Solution

The truth table of the 4:1 multiplexer for the given logic function is as follows
−

Select Lines Output

S1 = A S0 = B Y

0 0 1

0 1 1

1 0 0

1 1 1

Using this truth table, we can draw the logic block diagram to realize the
function F using a 4:1 MUX which is shown in Figure-2.
Explanation
Here, the inputs A and B are applied to the select lines S 1, and
S0 respectively. From the truth table, it is clear that the function F = 1, when
AB = 00, 01, 11. Thus, we connect logic 1 to the data input lines I 0, I1, and I3,
and the logic 0 is connected to the data input line I 2.

Example 2

Implement the following two variable logic function by using a 4:1 MUX.

F(A,B)=∑m(1,3)�(�,�)=∑�(1,3)

Solution

The truth table of the 4:1 multiplexer for the given logic function is as follows,

Select Lines Output

S1 = A S0 = B Y

0 0 0

0 1 1

1 0 0

1 1 1
Using this truth table, we can draw the logic block diagram to realize the
function F using a 4:1 MUX which is shown in Figure-3.

Explanation
Here, the inputs A and B are applied to the select lines S 1, and
S0 respectively. From the truth table, it is clear that the given Boolean
function F = 1, when AB = 01, 11. Hence, we connect logic 1 to the data
input lines I1 and I3, and the logic 0 is connected to the remaining data input
lines, i.e. I0 and I2.

Encoders
The combinational circuits that change the binary information into N
output lines are known as Encoders. The binary information is passed in
the form of 2N input lines. The output lines define the N-bit code for the
binary information. In simple words, the Encoder performs the reverse
operation of the Decoder. At a time, only one input line is activated for
simplicity. The produced N-bit output code is equivalent to the binary
information.
There are various types of encoders which are as follows:

4 to 2 line Encoder:
In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3,
and two outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to
true at a time to get the respective binary code in the output side. Below
are the block diagram and the truth table of the 4 to 2 line encoder.

Block Diagram:
Truth Table:

The logical expression of the term A0 and A1 is as follows:

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A1=Y3+Y2
A0=Y3+Y1

Logical circuit of the above expressions is given below:

8 to 3 line Encoder:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8
to 3 line encoder, there is a total of eight inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5,
Y6, and Y7 and three outputs, i.e., A 0, A1, and A2. In 8-input lines, one
input-line is set to true at a time to get the respective binary code in the
output side. Below are the block diagram and the truth table of the 8 to 3
line encoder.

Block Diagram:

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Truth Table:

The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1
Logical circuit of the above expressions is given below:

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Decimal to BCD Encoder

The Octal to Binary Encoder is also known as 10 to 4 line Encoder. In 10
to 4 line encoder, there are total of ten inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6,
Y7, Y8, and Y9 and four outputs, i.e., A 0, A1, A2, and A3. In 10-input lines,
one input-line is set to true at a time to get the respective BCD code in
the output side. The block diagram and the truth table of the decimal to
BCD encoder are given below.
Block Diagram:

Truth Table:

The logical expression of the term A0, A1, A2, and A3 is as follows:

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1
Logical circuit of the above expressions is given below:

Priority Encoder:
4 to 2 line Priority Encoder:
In this priority encoder, there are total of 4 inputs, i.e., Y 0, Y1, Y2, and Y3,
and two outputs, i.e., A0 and A1. The Y3 has high and Y0 has low priority
inputs. When more than one input is '1' at the same time, the output will
be the (binary) code corresponding to the higher priority input. Below is
the truth table of the 4 to 2 line priority encoder.

Truth Table:
The logical expression of the term A 0 and A1 can be found using K-
map as:

A1=Y3+Y2
A0=Y3+Y2'.Y1

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Logical circuit of the above expressions is given below:

Uses of Encoders:
1. These systems are very easy to use in all digital systems.
2. Encoders are used to convert a decimal number into the binary number.
The objective is to perform a binary operation such as addition,
subtraction, multiplication, etc.

Decoder
The combinational circuit that change the binary information into
2N output lines is known as Decoders. The binary information is passed in
the form of N input lines. The output lines define the 2 N-bit code for the
binary information. In simple words, the Decoder performs the reverse
operation of the Encoder. At a time, only one input line is activated for
simplicity. The produced 2N-bit output code is equivalent to the binary
information.
There are various types of decoders which are as follows:

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and
A1 and E and four outputs, i.e., Y 0, Y1, Y2, and Y3. For each combination of
inputs, when the enable 'E' is set to 1, one of these four outputs will be 1.
The block diagram and the truth table of the 2 to 4 line decoder are given
below.

Block Diagram:
Truth Table:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

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Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3
to 8 line decoder, there is a total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5,
Y6, and Y7 and three outputs, i.e., A 0, A1, and A2. This circuit has an enable
input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of
these four outputs will be 1. The block diagram and the truth table of the
3 to 8 line encoder are given below.
Block Diagram:

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Truth Table:

The logical expression of the term Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as
follows:
Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

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4 to 16 line Decoder
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y 0, Y1, Y2,
……, Y16 and four inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder
can be constructed using either 2 to 4 decoder or 3 to 8 decoder. There is
the following formula used to find the required number of lower-order
decoders.

Required number of lower order decoders=m2/m1

m1 = 8
m2 = 16

Required number of 3 to 8 decoders= =2

Block Diagram:
Truth Table:

The logical expression of the term A0, A1, A2,…, A15 are as follows:

Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Logical circuit of the above expressions is given below:

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