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Lab4_Tutorial_F2020

This document outlines a lab tutorial for designing a 4-bit Adder/Subtractor Unit (ASU) and a Combinatorial Unit using VHDL in a digital systems course. It provides step-by-step instructions for creating the necessary files, compiling the code, and simulating the results to match a student's ID. The lab culminates in connecting the ASU and Combinatorial Unit in a block diagram and ensuring the final simulation aligns with the student's number.

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Mohammed Ali
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7 views

Lab4_Tutorial_F2020

This document outlines a lab tutorial for designing a 4-bit Adder/Subtractor Unit (ASU) and a Combinatorial Unit using VHDL in a digital systems course. It provides step-by-step instructions for creating the necessary files, compiling the code, and simulating the results to match a student's ID. The lab culminates in connecting the ASU and Combinatorial Unit in a block diagram and ensuring the final simulation aligns with the student's number.

Uploaded by

Mohammed Ali
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

LAB 4 TUTORIAL
ADDER AND SUBTRACTOR UNIT

OVERVIEW

In this lab we will:


1. Use VHDL code to design a 4-bit Adder/Subtractor Unit (ASU) that multiplexes add
and subtract operations with a common Cin input.
2. Design a combinatorial circuit that takes the decoded output of the ASU as input,
and consequently outputs individual digits of your student number.

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

PROCEDURE

1. 4-bit (Adder/Subtractor Unit) ASU

Please follow the following instructions to implement the 4-bit ASU:


1. Create a new folder “Lab4” in your “BME328” folder.
2. Open the Quartus II software, and using the new project wizard, create a new project
“Lab4” in your “Lab4” folder.
MAKE SURE THAT YOU CHOOSE THE “EP2C35F672C6” DEVICE IN THE
PROJECT WIZARD.
3. Create a new VHDL file in your “Lab4” project (File > New > VHDL File).
4. Type the following in the Text Editor and save file as “ASU.vhd”:

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

5. Set “ASU.vhd” as the top-level entity. You can do this by right-clicking on “ASU.vhd”
in the “Files” section of the project navigator (located at the right of your Quartus II
window) and selecting “Set at Top-Level Entity”.
6. Start the compiler. Fix any errors and re-compile. Once the compiler compiles
without any errors, move to the next step.
7. Create a symbol for your “ASU.vhd” file. You can do this by right clicking on
“ASU.vhd” in the “Files” section of the project navigator (located at the right of your
Quartus II window) and selecting “Create Symbol Files for Current File”.
8. Create a new University Program VWF (File > New > University Program VWF).
9. Simulate “ASU.vhd” and make sure that your simulation results match the results
shown below.
10. Save the VWF file as “ASU.vwf” in your “Lab4” folder and take a screenshot of your
results.

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

2. Combinatorial Unit C

In this part of the lab we are required to create a Combinatorial Unit that takes as input the
output S from the ASU and consequently outputs individual digits of your student number.
I will use my student number as an example: 500414487
S = 0 corresponds to the first digit, in my case it is 5.
S= 1 corresponds to the second digit in my case it is 0.
And so on until we get to
S = 8 which corresponds to the 9th digit, in my case it is 7.
For all other values of S, we want to display 0.
Based on this please follow the following instructions to complete the lab:
1. fill out the truth table given the lab manual with your student ID. Below is an example
using my using.

ASU Sum Student ID Student ID


Output
(4-bit Binary) (4-bit Binary) (Decimal)
S3 S2 S1 S0 L3 L2 L1 L0
0 0 0 0 0 1 0 1 5
0 0 0 1 0 0 0 0 0
0 0 1 0 0 0 0 0 0
0 0 1 1 0 1 0 0 4
0 1 0 0 0 0 0 1 1
0 1 0 1 0 1 0 0 4
0 1 1 0 0 1 0 0 4
0 1 1 1 1 0 0 0 8
1 0 0 0 0 1 1 1 7
1 0 0 1 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 0
1 1 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

2. Minimize the outputs L3, L2, L1, L0 in your truth table using K-maps. Below is an
example using my student ID.

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

3. Use the VHDL code below to implement your Combinatorial Unit C. Remember to
replace the L(3), L(2), L(1), and L(0) output assignment functions in the code with
your minimized functions.
4. Save the VHDL file as “C.vhd”.

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

6. Set “C.vhd” as the top-level entity. You can do this by right-clicking on “C.vhd” in the
“Files” section of the project navigator (located at the right of your Quartus II window)
and selecting “Set at Top-Level Entity”.
7. Start the compiler. Fix any errors and re-compile. Once the compiler compiles
without any errors, move to the next step.
8. Create a symbol for your “C.vhd” file. You can do this by right clicking on “C.vhd” in
the “Files” section of the project navigator (located at the right of your Quartus II
window) and selecting “Create Symbol Files for Current File”.
9. Create a new University Program VWF (File > New > University Program VWF).
10. Simulate “C.vhd” and make sure that your simulation results match your student
number.
11. Save the VWF file as “C.vwf” in your “Lab4” folder and take a screenshot of your
results.

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MOUSA AL-QAWASMI

BME 328 – DIGITAL SYSTEMS (FALL 2020)

Finally, we need to connect the ASU and Combinatorial Unit C:


1. Create a new Block Diagram/Schematic File in your “Lab4” project (File > New >
Block Diagram/Schematic File.
2. Build the circuit shown below.
3. Save your file as “CombinedASU1.bdf”

4. Set “CombinedASU1.bdf” as the top-level entity. You can do this by right-clicking on


“CombinedASU1.bdf” in the “Files” section of the project navigator (located at the
right of your Quartus II window) and selecting “Set at Top-Level Entity”.
5. Start the compiler. Fix any errors and re-compile. Once the compiler compiles
without any errors, move to the next step.
6. Create a new University Program VWF (File > New > University Program VWF).
7. Simulate “CombinedASU1.bdf” and make sure that your simulation results match
your student number.
8. Save the VWF file as “CombinedASU1.bdf” in your “Lab4” folder and take a
screenshot of your results.

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