PLC’s programming with examples

Ireneusz Dominik
Stanisław Flaga
Revisers:
prof. dr hab. inż. Janusz Kwaśniewski
prof. Yurij Shalapko

Cover design: Ireneusz Dominik, Stanisław Flaga

Printed by: Delta J.A. JAGŁA

+48 601 68 25 00

© Copyright by Ireneusz Dominik, Stanisław Flaga, Cracow 2011

All rights reserved

Printed in Poland

The book was corrected by Professional English (www.profenglish.com).

This book cannot be copied and distributed by means of electronic, mechanical, copying
or recording devices and without the written agreement of a copyright holder.

ISBN 978-83-62139-34-7
 Contents

1. Introduction ....................................................................................................7
2. CX Programmer .............................................................................................8
2.1. Introduction to CX Programmer ............................................................................8
2.2. Creating a new project...........................................................................................9
2.3. Software configuration ........................................................................................ 11
2.4. Toolbars............................................................................................................... 13
3. Comparison instructions .............................................................................. 17
3.1. Instruction MCMP – Multiple Compare.............................................................. 17
3.2. Instruction TCMP – Table Compare ...................................................................22
3.3. Instruction BCMP – Unsigned Block Compare .................................................. 26
3.4. Instruction ZCP – Area Range Compare ............................................................. 29
4. Data movement instructions ........................................................................32
4.1. Instruction SFT – usage of a shift register ........................................................... 32
4.2. Instruction SFTR – usage of a reversible shift register .......................................35
4.3. Instruction SLD – One Digit Shift Left ............................................................... 39
4.4. Instruction SRD – One Digit Shift Right ............................................................. 42
4.5. Instruction ROL – Rotate Left .............................................................................45
4.6. Instruction ROR – Rotate Right...........................................................................48
4.7. Instruction RORL – Double Rotate Right ............................................................ 52
4.8. Instruction NSFL – Shift N-bit data left .............................................................. 53
4.9. Instruction NSFR – Shift N-bit data right ............................................................ 56
4.10. Instruction NASL – Shift N-Bits Left ..................................................................59
4.11. Instruction NASR – Shift N-bits Right.................................................................64
5. Incrementation, decrementation PLC......................................................... 68
5.1. Instruction ++ – incrementing of the 4-digit hexadecimal number ..................... 68
5.2. Instruction -- – decrementing of the 4-digit hexadecimal number ...................... 71
5.3. Instruction ++B – incrementing of the 4-digit BCD number .............................. 74
5.4. Instruction --B – decrementing of the 4-digit BCD number ................................ 77

5
 6. Data copying PLC ......................................................................................... 80
6.1. Instruction MOV – Transfers a word of data to a specified word. ...................... 80
6.2. Instruction MVN – Transfers the complement of a word of data to a specified
word. ............................................................................................................................. 83
6.3. Instruction MOVB – Transfers a specified bit. ................................................... 86
6.4. Instruction XFRB – Multiple Bit Transfer .......................................................... 89
6.5. Instruction XFER – transferring a specified number of consecutive words ........92
6.6. Instruction BSET– copying the same word to the range of consecutive words. ..96
6.7. Instruction XCHG – data Exchange ....................................................................98
6.8. Instruction XCGL – double data Exchange....................................................... 101
6.9. Instruction DISTC – single word distribution ................................................... 104
6.10. Instruction COLLC – data collection ................................................................ 107
6.11. Instruction MOVR – moving to Register .......................................................... 110
6.12. Instruction MOVRW– moving to timer/counter PV to Register ....................... 112
7. Sequence control instructions ....................................................................115
7.1. Instructions JMP and JME – Jump and Jump End ............................................ 115
7.2. Instruction CJP – Conditional Jump ..................................................................119
7.3. Instruction CJPN – Conditional Jump Not ........................................................ 121
7.4. Instructions JMP0 and JME0 – Multiple Jump and Jump End ......................... 124
8. Summary .....................................................................................................128
Bibliography ............................................................................................................. 129

6
1. Introduction

In modern industry the Programmable Logic Controllers (PLCs) are the most
important devices without which there would have been no mass production and our
technical civilisation as we know it today. PLCs in industry are as important as standard
PCs in our offices and homes. During the time the prices of PLCs have reached the level
when it is both convenient and reasonable to use them in all kinds of installations: ranging
from the advanced controlling of industry processes to the very simple home solutions e.g.:
heating installations.
The presented book comes into being on the basis of student tutorials held for the
Digital Control class at the Department of Process Control at the Faculty of Mechanical
Engineering and Robotics at The University of Science and Technology AGH in Cracow.
Both authors work at AGH as academic lecturers. Many years of specialization in PLCs
programming together with experienced gathered in industry in starting up installations
based on controllers have given them the knowledge which is presented in the book. Also
the AGH students made a contribution to this book, especially to make PLCs programming
easier to understand for beginners.
The book concerns programming the controllers of the Japanese manufacturer
OMRON, which belongs to the leading automation equipment manufacturers. On the
market there is still lack of practical books and the main aim of our book is to present
examples of particular instructions with their descriptions. The more advanced the
examples are, the more specialised commands they include, and this is the area, where for
many users problems occurred. The authors believe that the information gathered in the
presented book help the users overcome these problems.
This book is dedicated to automation and computer science students and engineers,
who deal with applying programmable logic controllers in practice.
Any remarks that you may have concerning this book, as well as remarks concerning
its further editions, please send to the following address: [email protected] or
[email protected]. In the following editions there will be more examples and more
information about other controllers.
Cracow, 15th of November 2011

7
2. CX Programmer

2.1. Introduction to CX Programmer

To program PLC controllers and other programmable devices made by
Omron, a company pack of software called CX-One is used. One of its elements is
a program called CX-Programmer shown in Figure 2.1, which currently
is a standard PLC programmer for the Omron company.

Figure 2.1. Main elements of CX-Programmer application

8
 An undervalued advantage of the package is access to a simulator. In the
simulator all instructions of a given PLC have been implemented. Together with
the simulation of the touch screen panel included in the package (created in CX-
Designer) it enables creating a fully equipped simulator mode: the interface (panel
simulator) connected with the controller simulator runs in real time.
In companies engaged in industrial automatics, due to economical reasons,
older version of this type of software can be found. They are called SysWin, but
new PLC versions cannot be programmed with SysWin.
CX-One in an educational version (without any activation key) which can be
downloaded for free from the publisher's website www.btc.pl/pliki/psplc.zip
(permission granted by the Omron representative in Poland). CX-One can be used
to program all kinds of Omron controllers, e.g.: CJ, CS series. The main restriction
in the educational version is lack of possibility to make the code bigger than 2k
steps. This version cannot be used to conduct commercial activity.

2.2. Creating a new project

To create a new project choose File → New, which is also available on the
toolbar (Figure 2.2). A dialogue window that appears allows you to name the
project, choose the correct type of the PLC controller and adjust the parameters of
PC → PLC communication. In this case we choose the CJ1M controller.
Communication options are not significant as long as we use a built-in simulator.
As an example, we will create a program which turns on the lamp when the Start
button is pressed, and turns off the lamp after pressing the Stop button.

Figure 2.2. Creating a new project

9
 First of all, we put New contact from the diagram toolbar (or press C on the
keyboard). We name it Start and attach an address to it: 1.01 Figure 2.3.

Figure 2.3. CX-Programmer window

Then we choose a New PLC Instruction (press I). First we need to choose the
instruction by entering its abbreviation, in our case SET (it turns on the specific
bit) and then we enter the name of the bit which should be turned on: Add1. We
press OK, and in the newly opened dialogue window, we write the address of the
bit, e.g.: 1.02.

Figure 2.4. CX-Programmer window

10
 To go to the next line we press arrow down key. Now we put Stop with the
address e.g.:1.03, and the RSET instruction which turns off our bit Add1. In the last
line we finally put the contact Add1, with the same address we chose using the SET
and RSET functions: 10.02. In the last step we address the output by using the New
Coil button (or press O). In order to perform a simulation we use the Work On-line
Simulator button (or press Ctrl + Shift + W). Our program is transferred
automatically to the virtual PLC and we can enjoy programming without hardware.
To turn on the Start contact we must double click the left contact and enter
value 1. It turns on the SET instruction and our lamp is on. To turn off the lamp we
need to 'press' the stop button, so we double click the left stop contact and enter
value 1 (Figure 2.4).
To finish the simulation we simply press the Work On-line Simulator button
again.

2.3. Software configuration

The way of changing the most useful options is shown in Figure 2.5.

Figure 2.5. Options window - Ladder Information

11
 When a new project is created, configuration of the programming environment
can be performed. Standard options allow to program controllers easily but it is
also possible to adjust the user environment to one's preferences.
The configuration option available in menu Tools → Options allows to
change appearance, the number of projected components, fonts, type of a default
PLC controller and many more. Some elements of the configuration, except for the
bookmark Diagrams in the Options window, are also available on toolbars.

Figure 2.6. Options window - diagrams

Settings available in the Ladder Information bookmark in the Options

window (Figure 2.6) should be chosen in the way which enables us to document the
work and make it easier to work. Options which are available there allow us to
determine the number of projected information and its position on the ladder
scheme.
The Appearance bookmark in the Options window affects the way of
appearance of the ladder scheme elements. While changing these elements
attention should be paid to the On/Off line mode. It is important to note the
differences between them – it may make turning on programs (finding mistakes)
more difficult.
Meanings of particular parameters of Diagrams are shown in Figure 2.6. An
easy method of getting to know their way of functioning is to create a short ladder

12
scheme with lines and program comments and to define identity (variables names)
and eventually one by one turning on particular options.

2.4. Toolbars
There are many buttons available on toolbars which make using the CX-
Programmer much easier. Toolbars are divided into groups:

1) A standard group, containing files service, prints and basic editing

options such as copy or paste (Fig. 2.7):

Figure 2.7. CX-Programmer – standard toolbar

2) A symbol table, which simplifies managing symbol arrays (Fig. 2.8)

Figure 2.8. CX-Programmer - toolbar

13
 3) A diagram group, containing basic ladder scheme elements (Fig. 2.9)

Figure 2.9. CX-Programmer – diagram toolbar

4) An insert group, containing kits which add additional elements

(controller, program, section, symbol) to a project (Fig. 2.10).

14
 Figure 2.10. CX-Programmer – insert toolbar

5) PLC, which allows controller management and simplifies turning on/of the
software (Fig. 2.11)

Figure 2.11. CX-Programmer – PLC toolbar

15
 6) A program to manage the program (Fig. 2.12),

Figure 2.12. CX-Programmer – program toolbar

16
3. Comparison instructions

3.1. Instruction MCMP – Multiple Compare

The instruction compares the content of 16 consecutive words (D1 through
D1+15) with other 16 consecutive words (D2 through D2+15) and turns ON the
corresponding bits in the R word where compared words are not equal. The ladder
diagram and instruction list are shown in Figure 3.1.

a)

b)

c)

Figure 3.1. The MCMP instruction: a) ladder diagram, b) instruction list, c) local symbols

17
 Variations of the instruction:

- executed in each cycle for the ON condition MCMP,

- executed once for upward differentiation @ MCMP,
- executed once for downward differentiation not supported,
- immediate refreshing not supported

Memory area for operand Word

Area D1 D2 R
CIO √ √
W √ √
H √ √
A √ √
T √ √
C √ √
D √ √
@D √ √
*D √ √
Constant (#) – –
DR – √
IR – –
addressing using √ √
IR

Flags set by the instruction:

P_ER, ON if the content of the Word is not a number, OFF in all other cases,
P_EQ, ON if Word = 0000 (the two 16-word sets contain the same data), OFF
in all other cases.

The instruction MCMP compares corresponding 2 words of the set of 32

words. The result of comparison is setting or clearing a corresponding bit in the R
word.

WORD2_1 = WORD2_2 -> WORD_R = #0000 = @ 0000 0000 0000 0000

WORD2_1 ≠ WORD2_2 -> WORD_R = #0004 = @ 0000 0000 0000 0100

18
 Figure 3.2. Instruction MCMP

With the execution of condition S words are compared in every cycle.

If you want to use an up-differentiated variation of the instruction, where a
specified word is incremented only once with the rising edge of execution
condition S, you must use the @MCMP instruction. The instruction compares
words only when we want to compare them (Figure 3.3).
The following example (Figure 3.3) uses counters for changing the values of
the words: C10, C11 and C25. The values in the counters change every second. We
can compare them (and 13 more words - from C10 to C25) with words from W210
to W225 by setting the value of S to 1. The results is obtained in W300.

19
a)

20
b)

c)

Figure 3.3. The program demonstrates the use of the MCMP instruction: a) ladder diagram,
b) instruction list, c) local symbols

21
 3.2. Instruction TCMP – Table Compare
It compares the source word (D) with the content of 16 consecutive words
(T through T+15) and turns ON the corresponding bit in the result word R where
compared words are equal. The ladder diagram and instruction list are shown in
Figure 3.4.

a)

b)

c)

Figure 3.4. The TCMP instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

- executed in each cycle for ON condition TCMP,
- executed once for upward differentiation @TCMP,
- executed once for downward differentiation not supported,
- immediate refreshing not supported

22
 Memory area for operand Word
Area W200 W300 W4
CIO √ √ √
W √ √ √
H √ √ √
A √ √ √
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) √ – –
DR √ – √
IR – – –
addressing using √ √ √
IR

Flags set by the instruction:

- P_ER, ON if the content of the Word is not a number, OFF in all other cases,
- P_EQ, ON if Word = 0000 (none of the 16 words in the table equals D), OFF
in all other cases.

Figure 3.5. Instruction TCMP

23
 a)

24
b)

c)

Figure 3.6. The program using the TCMP instruction: a) ladder diagram, b) instruction list,
c) local symbols
The TCMP instruction compares a table of 16 words T with a source word D.
As a result of this comparison it sets or clears the corresponding bit in the R word.

D = T2 -> WORD_R = 0004 Hex = b 0000 0000 0000 0100

D ≠ T2 -> WORD_R = 0000 Hex = b 0000 0000 0000 0000

25
 The instruction compares words only when we want to compare them. The
following example uses counters for changing the values of the words: C10, C11
and C15. The values in the counters change every second. We can compare them
(and 13 more words - from C10 to C25) with W200 by setting the value of S to 1.
We obtain the results in W300.

3.3. Instruction BCMP – Unsigned Block Compare

This instruction compares the Source data with 16 ranges which are defined by
16 lower and upper limits. The result of that comparison, if positive, changes the
corresponding bit in the result word. The ladder diagram and instruction list are
shown in Figure 3.7.

a)

b)

c)

Figure 3.7. The BCMP instruction: a) ladder diagram, b) instruction list, c) local symbols

26
 Variations of the instruction:
− executed in each cycle for the high state S BCMP,
− executed once for upward differentiation @BCMP,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operand Word

Area S B R
CIO √ √ √
W √ √ √
H √ √ √
A √ √ √
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) √ – –
DR √ – √
IR – – –
addressing using √ √ √
IR

This program firstly assigns values to areas in memory from W15 to W41
which will be lower and upper limits, and to W2 which will be a source word. The
instructions block which compares the source word to lower and upper limits and
stores its value in a result word (Figure 3.9).

a)

27
 b)

28
c)

Figure 3.8. The program demonstrating the use of the BCMP instruction: a) ladder diagram,
b) instruction list, c) local symbols

3.4. Instruction ZCP – Area Range Compare

Compares a 16-bit unsigned binary value with the range defined by the lower
and upper limit. Results are sent to the special flags. The ladder diagram and
instruction list are shown in Figure 3.4.1.
a)

b)

c)

Figure 3.9. The MCMP instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for ON condition ZCP(088),
− executed once for upward differentiation not supported,

29
 − executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operand Word

Area S B R
CIO √ √ √
W √ √ √
H √ √ √
A √ √ √
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) √ √ √
DR √ √ √
IR – – –
addressing using IR √ √ √

This instruction first assigns value to D10 and then when S is ON, compares it
to the lower and upper limit defined in the function block. Then we have 3
contacts: equal, bigger and smaller which lead to 3 coils. If the number is bigger,
the assigned coil is ON, if it is lower or equal, the same thing happens (Fig. 3.10,
3.11).

Figure 3.10. Ladder diagram of the ZCP instruction

30
Figure 3.11. The program showing the use of the ZCP instruction: instruction list, local
symbols

31
4. Data movement instructions

4.1. Instruction SFT – usage of a shift register

When execution condition S changes from OFF to ON, the SFT (010)
instruction shifts all the data from AreaStart to AreaEnd to the left by one bit (from
the rightmost bit to the leftmost bit), and the current ON/OFF status of I input is
stored in the rightmost bit. The ladder diagram and instruction list is shown in
Figure 4.1.

a)

b)

32
 c)

Figure 4.1. The SFT instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

- executed in each cycle for the high state SFT,
- executed once for upward differentiation not supported,
- executed once for downward differentiation not supported,
- immediate refreshing not supported
-
Memory area for operands: AreaStart and AreaEnd
Area AreaStart AreaEnd
CIO √ √
W √ √
H √ √
A √ √
T – –
C – –
D – –
@D – –
*D – –
Constant (#) – –
DR – –
IR – –
addressing using IR √ √

Flags set by the instruction:

− P_ER, ON if the indirect IR address for S or R is not in the CIO (common
input-output), A (auxiliary bit), H (holding bit), W (work) data areas, OFF
in all other cases.

A sample program is shown in Figure 4.2, where a 32 bit shift register (SFT) is
used. After pressing Start consecutive bits of the shift register are filled with
a current state of I input every 1 second (with the use of a P_1s flag). After filling

33
the whole register (which is detected by counting 32 pulses with the use of counter
CNT), the data from the register is negated and copied to the work area for words
W20 and W21 by means of the MVN block. The counting and the program are
stopped after copying the data (i.e. the Full bit is turned on), or during the First
Cycle (P_First_Cycle) execution. Simultaneously, counter CNT undergoes reset in
order to count and fill the shift register from the beginning after enabling Start
again.

a)

34
 b)

c)

Figure 4.2. The program fills the shift register with the use of the SFT instruction and
copies the negated data into the work area: a) ladder diagram, b) instruction list, c) local
symbols

4.2. Instruction SFTR – usage of a reversible shift

register
When the execution condition of the shift input bit (bit 14 of C) changes to
ON, all the data from St to E is moved in the designated shift direction (set by bit
12 of C) by 1 bit, and the ON/OFF status of the data input is placed in the
rightmost or leftmost bit (depending on the direction). The bit data shifted out of
the shift register is placed in the Carry Flag (P_CY). The ladder diagram and
instruction list are shown in Figure 4.3.

35
 Figure 4.3. The SFTR instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state SFTR,
− executed once for upward differentiation @SFTR,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operands C, S and E

Area C S E
CIO √ √ √
W √ √ √
H √ √ √
A √ √ √

36
 T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) – – –
DR √ – –
IR – – –
addressing using IR √ √ √

Flags set by the instruction:

− P_ER, ON if S is greater than E, OFF in all other cases,
− P_CY, ON if 1 is shifted into it. OFF when 0 is shifted into it, OFF if reset
is set to 1.

Figure 4.4. The structure of control word C for the SFTR instruction is as follows.

The register will be shifted right/left in every cycle.

A sample program is shown in Figure 4.5, where a 16 bit reversible shift
register is used. The register’s data is stored within the area defined by S and E.
The program works as follows:
After pressing Start the shift register is powered up and all bits of the shift
register W1 word are set to 0. The consecutive bits of control word W1 are set
manually.
− When Shift_Left is enabled, the data in the register will be shifted to the
left, and when Shift_Left is disabled, the data will be shifted to the right.
− Data_Input serves as an input for the register, delivering 1 when it is
enabled, and 0 when it is disabled.

− You can reset the whole register by enabling the Register_Reset.

− To start the process of registering data, enable Shift_On which enables a
14-th bit in the W1 control word. In combination with a 1 second clock

37
 (P_1s) it will read data from Data_Input every one second and write it into
an appropriate position in the shift register SFTR.

To stop the SFTR (reversible shift register) operation, Stop must be enabled.

a)

38
 b)

c)

Figure 4.5. The program realizing the counter counting upwards with the use of the SFTR
a) ladder diagram, b) instruction: instruction list, c) local symbols

4.3. Instruction SLD – One Digit Shift Left

The instruction SLD(074) shifts data between St and E by one digit (4 bits) to
the left. “0” is placed in the rightmost digit (bits 3 to 0 of St), and the content of the
leftmost digit (bits 15 to 12 of E) is lost. The ladder diagram and instruction list are
shown in Figure 4.6.

39
 a)

b)

c)

Figure 4.6. The SLD instruction: a) ladder diagram, b) instruction list, c) local
symbols

Variations of the instruction:

− executed in each cycle for ON condition SLD(074),
− executed once for upward differentiation @ SLD(074),
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √

40
 *D √
Constant (#) –
DR –
IR –
addressing using √
IR

Flags set by the instruction:

- ER, ON when St is greater than E, OFF in all other cases.

Program describing the basic idea of the SLD instruction. When we press the
Start button, the values of the starting word D0 and end word D1 are shifted left by
one digit (4 bits) only when there is a rising edge. After pushing the button 3 times,
we can observe that the bits which are pushed out are lost and the empty spots are
filled with 0 (Figure 4.7).
a)

41
 b)

c)

Figure 4.7. The program realizing a digit shift with the use of the SLD instruction: a) ladder diagram,
b) instruction list, c) local symbols

4.4. Instruction SRD – One Digit Shift Right

The SRD (075) is the instruction that shifts the data between St (Starting word)
and E (end word) by one digit (4 bits) to the right. In the leftmost digit (bits from
15 to 12 of E) “0” is placed. However, the content of the rightmost digit is lost and
these are the bits from 3 to 0 of St. The ladder diagram and instruction list are
shown in Figure 4.8.

a)

b)

42
 c)

Figure 4.8. The SRD instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for ON condition SRD(075),
− executed once for upward differentiation @SRD(075) ,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR –
IR –
addressing using √
IR

Flags set by the instruction:

- ER, ON when St is greater than E, OFF in all other cases.

The program describes the basic idea of the SRD instruction. When we press
the Start button the values of the starting word D0 and end word D1 are shifted
right by one digit (4 bits) only when there is a rising edge. After 3 times pushing
the button we can observe that the bits which are pushed out are lost and the empty
spots are filled by 0 (Figure 4.9).

43
 a)

b)

c)

Figure 4.9. The program realizing a digit shift with the use of the SRD instruction: a) ladder
b) diagram, instruction list, c) local symbols

44
 4.5. Instruction ROL – Rotate Left
The ROL(027) instruction shifts all bits which are present in the Word to the
left. It means that if the ROL(027) instruction is ON every single bit in the Word is
being moved to the leftmost bit, also including the Carry Flag (CY). The ladder
diagram and instruction list are shown in Figure 4.10 Figure 4.13.

Figure 4.10. The ROL instruction: a) ladder diagram, b) instruction list, c) local symbols

Figure 4.11. Monitoring the WORD’s binary value before executing a ROL instruction.

Figure 4.12. Monitoring the WORD’s binary value after executing a ROL instruction.

45
 When we have one bit on the 15th position in the WORD binary value then
after implementation of the ROL(027) instruction this bit is moved to the Carry
Flag (P_CY flag turns on).

Figure 4.13. A Carry Flag idea description

Variations of the instruction:

− executed in each cycle for ON condition ROL(027),
− executed once for upward differentiation @ROL(027),
− executed once for downward differentiation not supported
− immediate refreshing not supported

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing using √
IR

Flags set by the instruction:

− P_ER, OFF for all cases,
− P_EQ, ON when the shift result is 0, OFF in all other cases,
− P_CY, ON when 1 is shifted to the Carry Flag (CY), OFF in all other
cases,
− P_N, ON when the leftmost bit is 1 as a result of the shift, OFF in all other
cases.

46
 The program below creates a “walking one” idea on three bits using the
ROL(027) instruction. After setting Start on, it moves one bit leftward with the
time step of 1s. When the bit reaches the 3rd position, it is automatically moved at
the same time to the 0 position and the cycle repeats (Figure 4.14).

a)

D0(t0)

D0(t1)

D0(t2)

D0(t3)

b)

47
c)

d)

Figure 4.14. The program realizing the concept of a “walking one” with the use of the ROL
instruction): a) monitoring of D0 variable during program execution, b) local symbols,
b) ladder diagram, c) instruction list, d) local symbols.

4.6. Instruction ROR – Rotate Right

The ROR(028) instruction shifts all bits which are present in the Word to the
right. It means that if the ROR(028) instruction is turned ON every single bit in the
Word is moved to the rightmost bit, also including the Carry Flag (CY). The ladder
diagram and instruction list are shown in Figure 4.15 Figure 4.17

48
 Figure 4.15. The ROR instruction: a) ladder diagram, b) instruction list, c) local symbols

Figure 4.16. Monitoring the WORD’s binary value before executing the ROR instruction

Figure 4.17. Monitoring the WORD’s binary value after executing the ROR instruction

When we have one bit in the 0 position in the WORD binary value, then after
the implementation of the ROR(028) instruction this bit is moved to the Carry Flag
(P_CY flag turns on).

Figure 4.18. A Carry Flag idea description

Variations of the instruction:

− executed in each cycle for ON condition ROR(028),
− executed once for upward differentiation @ROR(028),
− executed once for downward differentiation not supported

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √

49
 C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing using √
IR

Flags set by the instruction:

− P_ER, OFF for all cases,

− P_EQ, ON when the shift result is 0, OFF in all other cases,
− P_CY, ON when 1 is shifted to the Carry Flag (CY), OFF in all other
cases,
− P_N, ON when the leftmost bit is 1 as a result of the shift, OFF in all other
cases.

The program below creates a “walking one” idea on all sixteen address bits
using the ROR(028) instruction. After setting Start on it moves one bit rightward
with the time step of 1s. When the bit is moved from the 0 position to the Carry
Flag, then the Carry Flag activates and automatically moves the bit to the 15th
position and the cycle repeats (Figure 4.19)
a)

D0(t0)

D0(t1)

D0(t2)

D0(t3)

50
b)

c)

d)

Figure 4.19. The program realizing the concept of a “walking one” with the use of the ROR
instruction: a) monitoring the WORD’s b) ladder diagram, c) instruction list, d) local
symbols

51
 4.7. Instruction RORL – Double Rotate Right
The RORL(573) instruction shifts all bits which are present in the Word and
Word+1 variables to the right. It means that if RORL(573) instruction is turned ON
every single bit in the Word address and in the successive Word in the memory is
moved to the rightmost bit, also including the Carry Flag (CY). The ladder diagram
and instruction list are shown in Figure 4.20.

Figure 4.20. The RORL instruction: a) ladder diagram, b) instruction list, c) local symbols
Variations of the instruction:
− executed in each cycle for ON condition RORL(573),
− executed once for upward differentiation @RORL(573),
− executed once for downward differentiation not supported
Memory area for operand Word
Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR –
IR –
addressing using √
IR

52
 Flags set by the instruction:
− P_ER, OFF for all cases,
− P_EQ, ON when the shift result is 0, OFF in all other cases,
− P_CY, ON when 1 is shifted to the Carry Flag (CY), OFF in all other cases,
− P_N, ON when the leftmost bit is 1 as a result of the shift, OFF in all other
cases.
In Figure 4.21. we can see a simple program where the RORL(573) instruction
is used. After starting the program the sample values are moved to the Word (D0)
and Word+1 (D1) memory (the result in Figure 2). Then by setting Start on we
activate the RORL instruction which moves all D0 and D1 bits one bit to the right.
a)

b)

c)

Figure 4.21. The program using the RORL instruction: a) ladder diagram, b) instruction list,
c) local symbols

4.8. Instruction NSFL – Shift N-bit data left

The NSFL shifts the specified number of bits. It shifts data in the word D the,
starting from the initial bit C with the length of N. All bits will be shifted by one
position to the left. The ladder diagram and instruction list are shown in Figure
4.22.

53
 Figure 4.22. NSFL instruction: a) ladder diagram, b) instruction list, c) local symbols
Variations of the instruction:
− executed in each cycle for the high state NSFL,
− executed once for upward differentiation @NSFL,
− executed once for downward differentiation S not supported,
− immediate refreshing not supported

Memory area for operand Word

Area D C N
CIO √ √ √
W √ √ √
H √ √ √
A √ √ √
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) – √ √
DR – √ √
IR – – –
addressing using √ √ √
IR

54
 Flags set by the instruction:
− P_ER, ON if in the C is not in the range of 0000 – 000F (in hexadecimal
code), OFF in all other cases,
− P_CY, ON if there will be set 1 by the Carry Flag
If the data length is equal to 0 the beginning bit will be copied to the Carry
Flag (CY) without changing its own contents.

Figure 4.23. Instruction NSFL

NSFL instruction gives us an opportunity to create a “walking one”. The
program consists of the NSFL function which operates on the W10 register. First
there is assignment of the first bit at the rightmost position. Then all the bits are
shifted to the left. When the assignment occurs, bits are set again to the starting
position with the MOV instruction (Figure 4.24).

a)

55
 b)

c)

Figure 4.24. The program realizing the counter counting upwards with the use of the NSFL
a) ladder diagram, b) instruction list, c) local symbols

4.9. Instruction NSFR – Shift N-bit data right

The NSFR instruction shifts the specified number of bits. It shifts data in the
word D the, starting from the initial bit C with the length of N. All bits will be
shifted by one position to the right. The ladder diagram and instruction list are
shown in Figure 4.25.

56
Figure 4.25. NSFR instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state NSFR,
− executed once for upward differentiation @NSFR,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operand Word

Area D C N
CIO √ √ √
W √ √ √
H √ √ √
A √ √ √
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) - √ √
DR - √ √
IR – – –
addressing using √ √ √
IR

Flags set by the instruction:

− P_ER, ON if in the C it is not in the range of 0000 – 000F (in hexadecimal
code), OFF in all other cases,

57
 − P_CY, ON if there will be set 1 by the Carry Flag
If the data length is equal to 0 the beginning bit will be copied to the Carry
Flag (CY) without changing its own contents (Figure 4.26).

Figure 4.26. Instruction NSFR

The NSFR instruction gives us an opportunity to create a “walking one” in a

similar way as the NSFL but in the opposite direction. The program consists of the
NSFR function which operates on the W10 register. First there is assignment of the
first bit at the leftmost position. Then all the bits are shifted to the right. When the
assignment occurs, bits are set again to the starting position with the MOV
instruction (Figure 4.27).

a)

58
 b)

c)

Figure 4.27. The program realizing the counter counting upwards with the use of the NSFR
a) ladder diagram, b) instruction list, c) local symbols

4.10. Instruction NASL – Shift N-Bits Left

The NASL(580) instruction shifts a 16 bit WORD to the left. The number of
bits to be shifted depends on the control word. If the control word equals 0, then
the bits will not be shifted. The structure of the control bit is also important. If the
leftmost bit of the control word is equal to 8 hex, then the bits at the right of the
shifted word will be filled with ones.
Otherwise they will be filled with zeros. The ladder diagram and instruction
are shown list are shown in Figure 4.28.

59
Figure 4.28. The NASL instruction: a) ladder diagram, b) instruction list, c) local symbols
Variations of the instruction:
− executed in each cycle for the high state NASL,
− executed once for upward differentiation @NASL,
− executed once for downward differentiation not supported,
− immediate refreshing not supported
Memory area for operand Word
Area D C
CIO √ √
W √ √
H √ √
A √ √
T √ √
C √ √
D √ √
@D √ √
*D √ √
Constant (#) – Specified
values only
DR √ –

60
 IR – –
addressing using √ √
IR

Flags set by the instruction:

− P_ER, ON if in the C it is not in the range of 0000 – 000F (in hexadecimal
code), OFF in all other cases,
− P_EQ ON if the result of the shift is equal to 0, in OFF all other cases,
− P_CY, ON if 1 will be set by the Carry Flag
− Negative Flag, ON if the leftmost bit is equal to 1 when the shift occurred,
OFF in all other cases.
If the contents of the control word are out of range, then the error flag will
occur.
If the bits are shifted outside the words, the last word will be shifted into the
Carry Flag (CY) and the remaining data will be lost.
If the number of bits in the control word (specified to shift) is equal to 0, bits
will not be shifted (Figure 4.29, Figure 4.30).

Figure 4.29. Instruction NASL

Figure 4.30. Instruction NASL

61
 Using the NASL instruction, a program was created which fills the word with
1 (similarly to the “walking one”).
First, the rightmost bit was set at 1 in order to shift it to the left. Then using the
KEEP instruction and a signal generated each 0.2 s the bits in the the register W10
were shifted to the left according to the control word.
The control word was set to #8001 so it shifts the bit by one position and 8,
denoting that the bits in the right position of the shifted elements will be filled
with 1.
When bit is shifted outside the word, the Carry Flag occurrs, therefore
resetting the the register W10. The task is performed cyclically (Figure 4.31).

a)

62
b)

c)

Figure 4.31. The program realizing the counter counting upwards with the use of the NASL
instruction: a) ladder diagram, b) instruction list, c) local symbols

63
 4.11. Instruction NASR – Shift N-bits Right
The NASR (581) instruction shifts a 16 bit WORD to the right. The number of
bits to be shifted depends on the control word. If the control word equals 0, then
the bits will not be shifted. The structure of the control bit is also important. If
leftmost bit of the control word is equal to 8 hex, then the bits at the right of the
shifted word will be filled with ones. Otherwise they will be filled with zeros. The
ladder diagram and instruction list are shown in Figure 4.32.

a)

b)

c)

Figure 4.32. The NASR instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed each cycle for the high state NASR,

− executed once for upward differentiation @NASR,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

64
 Memory area for operand Word
Area D C
CIO √ √
W √ √
H √ √
A √ √
T √ √
C √ √
D √ √
@D √ √
*D √ √
Constant (#) – Specified
values only
DR √ –
IR – –
addressing using √ √
IR

Flags set by the instruction:

− P_ER, ON if in the C it is not in the range of 0000 – 000F (in hexadecimal
code), OFF in all other cases,
− P_EQ ON if the result of the shift is equal to 0, OFF in all other cases,
− P_CY, ON if 1 is set by the Carry Flag
− Negative Flag, ON if the leftmost bit is equal to 1 when the shift occurred,
OFF in all other cases.
If the contents of the control word are out of range, then the error flag will
occur.
If the bits are shifted outside the words, the last word will be shifted into the
Carry Flag (CY) and the remaining data is lost. If the number of bits in the control
word (specified to shift) is equal to 0, bits will not be shifted (Figure 4.33, Figure
4.34).

Figure 4.33. Instruction NASR

65
 Figure 4.34. Instruction NASR

Using the NASR instruction, the program which fills the word with ones is
created (similar to the “walking one” and to the NASL). First, the leftmost bit was
set to 1 in order to shift it to the right.
Then using KEEP instruction and signal generated each 0.2 s the bits in the
register W10 were shifted to the right according to the control word. The control
word was set to #8001 so it shifts the bit by the 1 position and 8, denotes that the
bits on the left position of the shifted elements will be filled with 1.
When bit was shifted outside the word, the Carry Flag occurred, therefore
resetting the the register W10. The task was created cyclically. Figure 4.35.

a)

66
b)

c)

Figure 4.35. The program realizing the counter counting upwards with use the of the NASR
instruction: a) ladder diagram, b) instruction list, c) local symbols

67
5. Incrementation, decrementation PLC

5.1. Instruction ++ – incrementing of the 4-digit

hexadecimal number
The ++(590) instruction adds 1 to the hexadecimal content of a Word. The
specified word will be incremented by 1 in every cycle as long as execution
condition S is ON. The ladder diagram and instruction list are shown in Figure 5.1.

a)

b)

Figure 5.1. ++ instruction: a) ladder diagram, b) instruction list,

Variations of the instruction:

− executed in each cycle for the high state ++,
− executed once for upward differentiation @++,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

68
 Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing using √
IR

Flags set by the instruction:

− P_ER, OFF in all cases,

− P_EQ, ON if a Word = 0000, OFF in all other cases,
− P_CY, ON if during execution a digit in Word goes from F to 0, OFF in all
other cases,
− P_N, ON if after execution bit 15 of a Word is ON, OFF in all other cases.

The instruction ++ adds 1 to the hexadecimal content of aWord:

WORD = WORD + 1

with execution condition S. The Word will be incremented by 1 in every cycle.

If you want to use the up-differentiated variation of the instruction, where the
specified word is incremented only once with a rising edge of execution condition
S, you must use the @++ instruction.
The instruction together with the CMP instruction allows to realize, e.g.: a
counter counting upwards which is shown in Figure 5.2. In the program the
changes of bit Counted are saved into the word Counter. After counting 4 times the
Finish bit is turned ON. The counter reset is realized in the First Cycle (
P_First_Cycle) or by the Reset bit.

69
 a)

b)

c)

Figure 5.2. The program realizing the counter counting upwards with the use of the @++
instruction: a) ladder diagram, b) instruction list, c) local symbols

70
 5.2. Instruction -- – decrementing of the 4-digit
hexadecimal number
The --(592) instruction subtracts 1 from the hexadecimal content of a Word. A
specified word will be decremented by 1 in every cycle as long as execution
condition S is ON. The ladder diagram and instruction list is shown in Figure 5.3.

a)

b)

c)

Figure 5.3. The -- instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state --,

− executed once for upward differentiation S @--,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

71
 Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing √
using IR

Flags set by the instruction:

− P_ER, OFF in all cases,

− P_EQ, ON if a Word = 0000, OFF in all other cases,
− P_CY, ON if during execution a digit in the Word goes from 0 to F, OFF
in all other cases,
− P_N, ON if after execution bit 15 of Word is ON, OFF in all other cases.

The instruction --B subtracts 1 from the hexadecimal content of a Word:

WORD = WORD – 1

with execution condition S. The Word will be decremented by 1 in every

cycle.

If you want to use the up-differentiated variation of the instruction, where the
specified word is decremented only once with a rising edge of execution condition
S, you must use the @-- instruction. The instruction together with the CMP
instruction allows to realize, e.g.: a counter counting downwards which is shown in
Figure 5.4. In the program the changes of bit Counted are saved into the word
Counter. After counting 4 times the Finish bit is turned ON. The counter reset is
realized in the First Cycle ( P_First_Cycle) or by the Reset bit (Figure 5.4).

72
 a)

b)

c)

Figure 5.4. The program realizing the counter counting downwards with the use of the @--
instruction: a) ladder diagram, b) instruction list, c) local symbols

73
 5.3. Instruction ++B – incrementing of the 4-digit BCD
number
The ++B(594) instruction adds 1 to the BCD content of a Word. A specified
word will be incremented by 1 in every cycle as long as execution condition S is
ON. The ladder diagram and instruction list are shown in Figure 5.5.

Figure 5.5. The ++B instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state ++B,

− executed once for upward differentiation @++B,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

74
 Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing using √
IR

Flags set by the instruction:

− P_ER, ON if the content of a Word is not BCD, OFF in all other cases,
− P_EQ, ON if a Word = 0000, OFF in all other cases,
− P_CY, ON if during execution Word = 9999 goes to Word = 0000, OFF in
all other cases.

The instruction ++B adds 1 to the BCD content of a Word:

WORD = WORD + 1

with execution condition S. The Word will be incremented by 1 in every cycle.

If you want to use the up-differentiated variation of the instruction, where the
specified word is incremented only once with a rising edge of execution condition
S, you must use the @++B instruction.
The instruction together with the CMP instruction allows to realize, e.g.: a
counter counting upwards which is shown in Figure 5.6. In the program the
changes of bit Counted are saved into the word Counter.
After counting 10 times the Finish bit is turned ON. The counter reset is
realized in the First Cycle ( P_First_Cycle) or by the Reset bit.

75
 a)

b)

c)

Figure 5.6. The program realizing the counter counting upwards with the use of the @++B
instruction: a) ladder diagram, b) instruction list, c) local symbols

76
 5.4. Instruction --B – decrementing of the 4-digit BCD
number
The --B(596) instruction subtracts 1 from the BCD content of a Word. A
specified word will be decremented by 1 in every cycle as long as execution
condition S is ON. The ladder diagram and instruction list is shown in Figure 5.7.

Figure 5.7. --B instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state --B,

− executed once for upward differentiation @--B,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

77
 The instruction --B subtracts 1 from the BCD content of a Word:

WORD = WORD – 1

with execution condition S. The Word will be decremented by 1 in every cycle

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing using √
IR

Flags set by the instruction:

− P_ER, ON if the content of a Word is not BCD, OFF in all other cases,
− P_EQ, ON if Word = 0000, OFF in all other cases,
− P_CY, ON if during execution Word = 0000 goes to Word = 9999, OFF in
all other cases.

If you want to use the up-differentiated variation of the instruction, where the
specified word is decremented only once with a rising edge of execution condition
S, you must use the @--B instruction.
The instruction together with the CMP instruction allows to realize, e.g.: a
counter counting downwards which is shown in Figure 5.8. In the program the
changes of the bit Counted are saved into the word Counter.
After counting 4 times the Finish bit is turned ON. The counter reset is
realized in the First Cycle ( P_First_Cycle) or by the Reset bit.

78
 a)

b)

c)

Figure 5.8. The program realizing the counter counting downwards with the use of the @--
B instruction: a) ladder diagram, b) instruction list, c) local symbols

79
6. Data copying PLC

6.1. Instruction MOV – Transfers a word of data to a

specified word.
The MOV(021) instruction transfers a source word S to a destination word D.
If S is a constant, the value can be used for data setting. The ladder diagram and
instruction list are shown in Figure 6.1.

a)

b)

c)

Figure 6.1. The MOV instruction: a) ladder diagram, b) instruction list, c) local symbols

80
 Variations of the instruction:
− executed in each cycle for the high state MOV(021)
− executed once for upward differentiation @MOV(021)
− executed once for downward differentiation not supported,
− immediate refreshing !MOV(021)

Combined Variations:
− executed once and the destination refreshed immediately for upward
differentiation !@MOV(021)

Memory area for operand Word

Area Word S Word D

CIO √ √
W √ √
H √ √
A √ √
T √ √
C √ √
D √ √
@D √ √
*D √ √
Constant (#) √ –
DR √ √
IR – –
addressing √ √
using IR

Flags set by the instruction:

− P_ER, is always OFF,

− P_EQ, ON if the data being transferred is 0000, OFF in all other cases,
− P_N, ON if the leftmost bit of the data being transferred is 1, OFF in all
other cases.

The instruction MOV copies the content of CIO 1000 to D100, with execution
condition A.
MOV(021) has an immediate refreshing variation (!MOV(021)). External
input bits can be specified for S and external output bits can be specified for D.
Input bits used for S will be refreshed just before execution, and output bits used
for D will be refreshed just after execution. Instruction MOV has plenty of
applications. One of them is creation of a “walking one” operation (Figure 6.2). In

81
the first cycle hex values #1, #2, #4, #8 are copied to words: D0, D1, D2 and D3
respectively. When the START bit is ON, the value from the counter (changed
every second) is copied to D10. Using indirect addressing the bits in word W200
are changed sequentially: 0-1-2-3.

a)

82
b)

c)

Figure 6.2. The program realizing a “walking one” operation with the use of the
MOV instruction and indirect addressing: a) ladder diagram, b) instruction list,
c) local symbols

6.2. Instruction MVN – Transfers the complement of a

word of data to a specified word.
The MVN(022) instruction inverts the bits in a source word S and transfers the
result to a destination word D. The content of S is left unchanged. The ladder
diagram and instruction list are shown in Figure 6.3.

83
a)

b)

c)

Figure 6.3. The MVN instruction: a) ladder diagram, b) instruction list, c) local symbols
Variations of the instruction:

− executed in each cycle for the high state MVN(022)

− executed once for upward differentiation @MVN(022)
− executed once for downward differentiation not supported
− immediate refreshing not supported

The instruction MVN inverts the status of the bits in CIO 200 and copies the
result to D100, with execution condition A. Instruction MVN has plenty of
applications.
Memory area for operand Word

Area Word S Word D

CIO √ √
W √ √
H √ √
A √ √
T √ √
C √ √
D √ √
@D √ √
*D √ √
Constant (#) √ –
DR √ √
IR – –
addressing using IR √ √

84
 Flags set by the instruction:
− P_ER, is always OFF,
− P_EQ, ON if the content of D is 0000 after execution, OFF in all other cases,
− P_N, ON if the leftmost bit of D is 1 after execution, OFF in all other cases.
One of them is creation of a “walking one” operation (Figure 6.4). In the first
cycle hex values #FFFE, #FFFD, #FFFB, #FFF7 are negated resulting in #1, #2,
#4, #8, and finally they are copied to words: D0, D1, D2 and D3 respectively.
When the START bit is ON, the value from the counter (changed every second) is
copied to D10. Using indirect addressing the bits in word W200 are changed
sequentially: 0-1-2-3 (Figure 6.4).
a)

85
b)

c)

Figure 6.4. The program with the use of the MVN instruction: a) ladder diagram, b)
instruction list, c) local symbols

6.3. Instruction MOVB – Transfers a specified bit.

The MOVB(082) instruction copies a specified bit (n) from S (source) to a

specified bit (m) in D (destination). The other bits in the destination word are left
unchanged. The ladder diagram and instruction list are shown in Figure 6.5.

86
 a)

b)

c)

Figure 6.5. The MOVB instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state MOVB(082)
− executed once for upward differentiation @MOVB(082)
− executed once for downward differentiation not supported
− immediate refreshing not supported

Memory area for operand Word

Area Word S
CIO √
W √
H √
A √
T √
C √

87
 D √
@D √
*D √
Constant (#) √
DR √
IR –
addressing √
using IR
Flags:
Error Flag – ER:
- ON if the rightmost and leftmost two digits of C are not within the specified
range of 00 to 0F.
- OFF in all other cases.
This program every second copies the first bit to the second, third and fourth
position and then starts again (Figure 6.6).
a)

88
b)

c)

Figure 6.6. The program with the use of the MOVB instruction: a) ladder diagram,
b) instruction list, c) local symbols

6.4. Instruction XFRB – Multiple Bit Transfer

The XFRB(062) instruction transfers up to 255 consecutive bits from the
source words (beginning with bit l of S) to the destination words (beginning with
bit m of D). Bits in the destination words that are not overwritten by the source bits
are left unchanged.

89
 The beginning bits and their numbers are specified in Control word, as shown
in Figure 6.4.1.
It is possible for the source words and destination words to overlap. By
transferring data which overlaps with several words, the data can be packed more
efficiently in the data area. (This is particularly useful when handling position data
for position control.) Since the source words and destination words can overlap,
XFRB(062) can be combined with ANDW(034) to shift m bits by n spaces. The
ladder diagram and instruction list are shown in Figure 6.7.

a)

b)

c)

Figure 6.7. The XFRB instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state XFRB(062)
− executed once for upward differentiation @XFRB(062)
− executed once for downward differentiation not supported
− immediate refreshing not supported

90
 Memory area for operand Word
Area Word S
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) √
DR √
IR –
addressing √
using IR

The program copies 21 bits from word W205 and W206 starting from the third
position to word W207 and W208 starting from the fifth place (Figure 6.8).

a)

b)

91
c)

Figure 6.8. The program with the use of the XFRB instruction: a) ladder diagram,
b) instruction list, c) local symbols

6.5. Instruction XFER – transferring a specified number

of consecutive words
The XFER(070) instruction copies a given number of words (N) beginning
from the S word up to the S+(N-1) word to the words from D to D+(N-1) The
ladder diagram and instruction list are shown in Figure 6.9.

a)

b)

c)

Figure 6.9. The XFER instruction: a) ladder diagram, b) instruction list, c) local symbols

92
 Variations of the instruction:
− executed in each cycle for the high state XFER(070)
− executed once for upward differentiation @XFER(070),
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Memory area for operand Word

Area Number Source Destination

CIO √ √ √
W √ √ √
H √ √ √
A √ √ √ (A448 to
a958)
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) √ – –
DR √ – –
IR – – –
addressing using IR √ √ √

Flags set by the instruction:

− P_ER, always OFF

The instruction XFER allows to copy a certain number of Source words to the
Destination words. A sample program which shows the functionality of this
instruction is shown in Figure 6.10.
The first switch of execution condition S from state ON to OFF stops the timer
and the value in the counter drops from 3 to 2. Now the current value from the
timer is saved in the D0 location. The decision where to write the current value is
made by comparing instructions and the MOV function. After changing execution
condition S to ON the timer continues counting.
The next change in S from state ON to OFF changes the value of the counter
to 1. The timer is stopped and the current value form the timer is written to the D1
location. The next change in S from state ON to OFF causes switching the counter
to the state ON and copying the values from D0 and D1 to D100 and D101. The
operation is made cyclically.

93
a)

94
b)

c)

Figure 6.10. The program realizing the copying of 2 words (values of timer after stopping
it) with the XFER instruction: instruction list, local symbols

95
 6.6. Instruction BSET– copying the same word to the
range of consecutive words.
The BSET(071) instruction copies the same word (S) to all of the destination
words, starting from the StartingWord (St) and up to EndingWord (E). The ladder
diagram and instruction list are shown in Figure 6.11.
a)

b)

c)

Figure 6.11. The BSET instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state BSET(071)
− executed once for upward differentiation @BSET(071),
− executed once for downward differentiation not supported,
− immediate refreshing not supported

96
 Memory area for operand Word
Area SourceWord StartingWord EndWord
CIO √ √ √
W √ √ √
H √ √ √
A √ √(A448 to √ (A448
a958) to a958)
T √ √ √
C √ √ √
D √ √ √
@D √ √ √
*D √ √ √
Constant (#) √ – –
DR √ – –
IR – – –
addressing using IR √ √ √
Flags set by the instruction:
- P_ER, On if the content of StartingWord is greater than EndWord, OFF in
all other cases.
The BSET instruction writes one value while execution condition S changes
from OFF to ON, copying it to the words from St to E. If you want to execute the
instruction with a rising edge, you need to use the @BSET instruction.The BSET
instruction might be helpful for writing the same value to more than one address. It
is a convenient way of clearing same part of the memory in this way. A sample
program with the BSET instruction is shown below. At the beginning the value
#1111 is set to the Source word. When execution condition S changes from OFF to
ON, the Source word is written to words with addresses form StartingWord to
EndWord. Additionally, the timer is started. After 4s the previous addresses are
filled with zeros (cleared) (Figure 6.12).
a)

97
b)

c)

Figure 6.12. The program realizing the copying of 2 words (values of timer after stopping
it) with the XFER instruction: a) ladder diagram, b) instruction list, c) local symbols

6.7. Instruction XCHG – data Exchange

The XCHG(073) instruction exchanges the contents of two specified words.
The values of these two specified word will be exchanged every cycle as long as
execution condition S is ON. The ladder diagram and instruction list are shown in
Figure 6.13.

Variations of the instruction:

− executed in each cycle for the high state XCHG,
− executed once for upward differentiation @XCHG,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

98
 a)

b)

c)

Figure 6.13. The XCHG instruction: a) ladder diagram, b) instruction list, c) local symbols

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR √
IR –
addressing using IR √

99
 Flags set by the instruction:
There are no flags affected by the instruction.

The instruction XCHG exchanges the contents of Word1 and Word2.

Word1 = Word2
Word2 = Word1
with execution condition S the contents of Word1 and Word2 will be
exchanged each cycle.
If you want to use the up-differentiated variation of the instruction, where the
specified words are exchanged only once with a rising edge of execution condition
S, you must use the @XCHG instruction. In the example shown in Figure 6.14,
the values of words Word1 and Word2 are set with the First Cycle using the
P_First_Cycle bit. Then if condition S is switched on, the values of Word1 and
Word2 are exchanged once (the @XCHG instruction). The exchange operation
may be performed using three consecutive MOV instructions, with an additional
temporary register.
a)

100
b)

c)

Figure 6.14. The program realizing the counter counting upwards with the use of the
@XCHG instruction: a) ladder diagram, b) instruction list, c) local symbols

6.8. Instruction XCGL – double data Exchange

The XCGL(562) instruction exchanges the contents of a pair of consecutive words
with another pair of consecutive words. The values of two pairs of words E1, E1+1 and E2,
E2+1 will be exchanged every cycle as long as execution condition S is ON. The ladder
diagram and instruction list are shown in Figure 6.15.

a)

b)

101
 c)

Figure 6.15. The XCGL instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for the high state XCGL,
− executed once for upward differentiation @XCGL,
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Table 6.8. Memory area for operand Word

Area Wo
rd
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) –
DR –
IR √
addressing √
using IR

Flags set by the instruction:

There are no flags affected by the instruction.
The instruction XCGL exchanges each cycle contents of Word1 with Word2 and
Word1_1 with Word2_1 with execution condition S .

Word1 = Word2
Word2 = Word1
Word1_1 = Word2_1
Word2_1=Word1_1
If you want to use the up-differentiated variation of the instruction, where the
specified words are exchanged only once with a rising edge of execution condition

102
S, you must use the @XCGL instruction. In the example shown in Figure 6.16 the
values of words Word1, Word1_1, Word2 and Word2_1 are set with the First
Cycle using the P_First_Cycle bit. Then if condition S is switched on, the values of
Word1 and Word2 are exchanged once (the @XCGL instruction).
The exchange operation may be performed using two XCHG operations.

a)

103
b)

c)

Figure 6.16. The program realizing the counter counting upwards with the use of the
@XCGL instruction: a) ladder diagram, b) instruction list, c) local symbols

6.9. Instruction DISTC – single word distribution

The DISTC(566) instruction transfers the source word (S) to a destination
word (D). The destination word is calculated by adding value of the offset (Of) to
the base address. The ladder diagram and instruction list are shown in Figure 6.17.

104
a)

b)

c)

Figure 6.17. The DISTC instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for ON condition DISTC,
− executed once for upward differentiation @DISTC,
− executed once for downward differentiation not supported,
− immediate refreshing specification not supported

Flags set by the instruction:

− P_ER, ON if Stack Push Operation is specified, but the stack pointer data
in Bs is not BCD,
− P_ER, ON if Stack Push Operation is specified and the stack pointer
indicates a word that exceeds the stack data area,
− P_EQ, ON if the source data is 0000,
− P_EQ, OFF in all other cases.

105
 Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) √
DR √
IR –
addressing √
using IR

The instruction DISTC adds an Offset value to the base address:

Destination word = Destination base address + Offset
with execution condition Start.

If you want to use the up-differentiated variation of the instruction, where the
specified word is transported only once with a rising edge of execution condition
Start, you must use the @DISTC instruction. This operation is shown in Figure
6.18. In the program the changes of the bit Start cause moving the value from
address D10 to the D25 address as the value of Offset is equal.

a)

106
b)

c)

Figure 6.18. The program showing the operation of the DISTC instruction: a) ladder
diagram, b) instruction list, c) local symbols

6.10. Instruction COLLC – data collection

The COLLC(567) instruction transfers the source word (S) to the destination word
(D). The source word is calculated by adding the value of the offset (Of) to the Source base
address (Bs). The ladder diagram and instruction list are shown in Figure 6.19.

a)

b)

107
 c)

Figure 6.19. The COLLC instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for ON condition COLLC,
− executed once for upward differentiation @COLLC,
− executed once for downward differentiation not supported,
− immediate refreshing specification not supported

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) √
DR √
IR –
addressing using IR √

Flags set by the instruction:

− P_ER, ON if the offset in Of is not BCD,
− P_ER, ON if LIFO or FIFO Stack Operation is specified and the stack
pointer indicates a word that exceeds the stack data area,
− P_ER, OFF in all other cases,
− P_EQ, ON if the source data is 0000,
− P_EQ, OFF in all other cases.

108
 The instruction COLLS adds Offset value to the base address:

Destination word address = Source base address + Offset

with execution condition Start

If you want to use the up-differentiated variation of the instruction, where a

specified word is transported only once with a rising edge of execution condition
Start, you must use the @COLLC instruction. The principle of operation of this
instruction is shown in Figure 6.20. In the program the changes of the bit Start
cause moving the value from address D6 to the D4 address as the value of Offset
equals 3.

a)

b)

c)

Figure 6.20. The program showing the operation of the COLLC instruction: a) ladder
diagram, b) instruction list, c) local symbols

109
 6.11. Instruction MOVR – moving to Register
The MOVR instruction sets the PLC memory address of a specified word, bit,
or timer/counter Completion Flag in a specified Index Register. The ladder diagram
and instruction list are shown in Figure 6.21.
a)

b)

c)

Figure 6.21. Instruction: a) ladder diagram, b) instruction list, c) local symbols

Variations of the instruction:

− executed in each cycle for ON condition MOVR(560),
− executed once for upward differentiation @MOVR(560),
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Operand Specifications
Area Source Destination
CIO √ -
W √ -
H √ -
A √ -
T √ -
C √ -
D √ -
@D √ -
*D √ -
Constant (#) - -
DR - -
IR – √
addressing using IR - -

110
 Flags set by the instruction:
− P_ER, OFF or unchanged,
− P_EQ, OFF or unchanged,
− P_N, OFF or unchanged.
The program works in the following way: after the Start contact is switched
on, the source bit in the MOVR instruction, which was initially set to 1, is changed
to 8 by means of the MOV instruction and then moved to IR0 (Figure 6.22).
a)

b)

c)

Figure 6.22. The program using the MOVR instruction: a) ladder diagram, b) instruction
list, c) local symbols

111
 It is also compared with the predefined value of 8 (the CMP instruction) and if
both values are the same, the Equals contact closes and initializes the timer. After
10 seconds, the whole system is automatically reset. The whole diagram is shown
below in Figure 6.22

6.12. Instruction MOVRW– moving to timer/counter PV

to Register
The MOVRW instruction sets the PLC memory address of a specified timer or
counter’s PV in the specified Index Register. The ladder diagram and instruction
list are shown in Figure 6.23.

a)

\b)

c)

Figure 6.23. The MOVRW instruction: a) ladder diagram, b) instruction list, c) local
symbols
Variations of the instruction:
− executed in each cycle for ON condition MOVR(561),
− executed once for upward differentiation @MOVR(561),
− executed once for downward differentiation not supported,
− immediate refreshing not supported

Flags set by the instruction:

− P_ER, OFF or unchanged,
− P_EQ, OFF or unchanged,
− P_N, OFF or unchanged

112
 Operand Specifications
Area Source Destination
CIO - -
W - -
H - -
A - -
T √ -
C √ -
D - -
@D - -
*D - -
Constant (#) - -
DR - -
IR – √
addressing using IR - -

After we close the Start contact, the timer begins to count down from 5
seconds (one unit corresponds to 100ms). At the same time the MOVRW
instruction moves each timer value to IR0 which is further taken from there and
compared by CMP with the Set Value (in this case 20, which is attained after 3
seconds).
Once this value has been reached in IR0, the Less Than or Equal contact
closes and lights up the Coil. The timer continues counting downwards until 0. By
re-opening the Start contact, we reset the timer as well as everything else. The
whole diagram is shown below in Figure 6.24.

a)

113
b)

c)

Figure 6.24. The program using the MOVRW instruction: a) ladder diagram, b) instruction
list, c) local symbols

114
7. Sequence control instructions

7.1. Instructions JMP and JME – Jump and Jump End

When the execution condition S=0 for JMP(004), program jumps directly to
the first JME(005) in the program with the same jump number (jump number 1 in
Figure 7.1.1). JMP(004) and JME(005) are used in pairs. The ladder diagram and
instruction list are shown in Figure 7.1.
During execution of the program when the JMP function is supplied with the
OFF signal, the execution of the program is switched to the point where the JME
function appears with the same N (jump number) as the one declared in the further
processed JMP function (the jump is executed).

a)

115
 b)

c)

Figure 7.1. JMP and JME instructions: a) ladder diagram, b) instruction list, c) local
symbols

If the function block is supplied with the ON signal the execution is done in a
manner of regular program execution, step by step.

Figure 7.2. Between the execution of function and lack of execution.

As shown in the Figure 7.2, the functions and operations between JMP and
JME are omitted when JMP is turned off (curved arrow) and are executed when the
function is turned ON (straight arrow). It means that outputs that are set to change
some value in between those functions stay the same when execution is jumped
and instructions are simply not executed. Therefore, CPU saves the cycle time by
skipping the instructions between JMP and JME.
The second mode is an operation in a loop where JME is declared first and
JMP is declared second. In such a case with the OFF condition for the JMP
instruction a permanent loop is created (curved arrow). To stop the loop execution
the ON condition for the JMP instruction must be applied (straight arrow) (Figure
7.3).

116
 Figure 7.3. Cyclical execution using JME and JMP

Variations of the instruction:

− Jumps when OFF JMP(004),
− Does not jump when ON JMP(004),
− Executed in each cycle for ON condition JME(005),
− Immediate refreshing not supported

Memory area for operand Word

Area JMP(004) JME(005)
CIO √ √
W √ –
H √ –
A √ –
T √ –
C √ –
D √ –
@D √ –
*D √ –
Constant (#) √ √
DR √ –
IR – –
addressing using IR √ –

This program was created using the JMP and JME functions. After starting the
simulation, we can see that INPUT1 is OFF, therefore JMP(004) is OFF, also
START is OFF and LED is turned OFF. Then, after forcing INPUT1 to high state,
the function JMP is turned on. START1 is set to high state causing LED to turn on.
Then we turn INPUT1 OFF, therefore JMP function is turned OFF. Then we force
START to low state and we can observe that LED is turned ON and working all the
time. As a remark we need to consider the fact that LED1 operated by switch

117
START1 is fully operational all the time regardless of the state of INPUT 1 (Figure
7.4).

a)

b)

c)

Figure 7.4. The program using the JMP and JME instructions: a) ladder diagram for all
inputs ON, b) instruction list, c) local symbols

118
 7.2. Instruction CJP – Conditional Jump
The operation of CJP(510) is basically the opposite of JMP(004). When the
execution condition S =1 for CJP(510) program execution jumps directly to the
first JME(005) in the program with the same jump number. CJP(510) and
JME(005) are used in pairs. The ladder diagram and instruction list are shown in
Figure 7.5.

a)

b)

c)

Figure 7.5. The CJP instruction: a) ladder diagram, b) instruction list, c) local symbols

Function CJP works in an opposite way as the JMP function. With the ON
signal there is a jump from CJP to JME line and with OFF signal there is no jump
and the program is executed without skipping parts of the code (Figure 7.7).

Variations of the instruction:

− Jumps when ON CJP(510),
− Does not jump when OFF CJP(510),
− Immediate refreshing not supported

119
 Figure 7.6. The operation of the Conditional Jump function

a)

b)

120
 c)

Figure 7.7. The program created with the use of the CJP and JME instructions: a) ladder
diagram for all inputs ON, b) instruction list, c) local symbols

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) √
DR √
IR –
addressing using IR √

In the example after starting the simulation, CJP is OFF and LED is OFF.
After turning ON INPUT1, the jump to JME is executed. We can see that even
after turning START ON, it does not influence LED state.

7.3. Instruction CJPN – Conditional Jump Not

The operation of CJPN(511) is almost identical to JMP(004). When the
execution condition S =0 for CJP(004), program execution jumps directly to the
first JME(005) in the program with the same jump number. CJPN(511) and

121
JME(005) are used in pairs. The ladder diagram and instruction list are shown in
Figure 7.8.

a)

b)

c)

Figure 7.8. The CJPN instruction: a) ladder diagram, b) instruction list, c) local symbols
The CJPN function works in the same way as JMP function because it jumps
to the JME when is turned OFF (curved line). With the condition ON it executes all
lines of the program (straight line) (Figure 7.9).

Figure 7.9. Instruction CJPN

122
 Variations of the instruction:
− Jumps when OFF CJPN(511),
− Does not jump when ON CJPN(511),
− Immediate refreshing not supported

Memory area for operand Word

Area Word
CIO √
W √
H √
A √
T √
C √
D √
@D √
*D √
Constant (#) √
DR √
IR –
addressing using IR √

When INPUT1 is OFF the CJPN is executed and the program jumps to JME. After
turning INPUT1 ON there is no jump. In this case after turning START ON LED is in ON
state as well (Figure 7.10).

a)

123
 b)

c)

Figure 7.10. The program created with the use of the CJPN and JME instructions: a) ladder
diagram for all inputs ON, b) instruction list, c) local symbols

7.4. Instructions JMP0 and JME0 – Multiple Jump and

Jump End
The JMP0 (515) instruction (Multiple Jump), when its execution condition is
OFF, it results in processing all the following instructions as NOP(000), up to the
next JME0(516) (Jump End) instruction. This means that the execution time of the
jumped instructions will be reduced but not eliminated. They are not executed and
their outputs (bits and words) maintain their previous status. Instructions
JMP0(515) and JME0(516) should be used in pairs. The number of these pairs in
the program is unlimited. The ladder diagram and instruction list are shown in
Figure 7.11.

Multiple pairs of JMP0(515) and JME0(516) instructions can be used in the

program, but these pairs cannot be nested. JMP0(515) and JME0(516) cannot be
used in block programs. JMP0(515) and JME0(516) pairs must be in the same tasks
because jumps between tasks are not allowed.

124
 Figure 7.11. JMP0 and JME0 instructions: a) ladder diagram, b) instruction list, c) local
symbols

Variations of the instruction:

− Jumps when OFF JMP0(515),
− Does Not Jump when ON JMP0(515),
− Executed Each Cycle for ON Condition JMP0(515),
− Immediate Refreshing not supported

Applicable Program Areas:

− Subroutines OK
− Interrupts OK

If you want to control a part of the program in order to run its instructions
depending on another value, you must use JMP0 and JME0 instructions.
Realization of those functions depends strictly on execution condition S (in the
program shown in Figure 7.12). When it is OFF, then all instructions that follow
the JMP0 instruction or go before the JME0 instruction are processed as
NOP(000). They are not executed and their output stays without a change. When
the execution condition is ON, than all the following instructions are executed.

125
a)

126
b)

c)

Figure 7.12. The program supplied with the JMP0 and JME0 instructions: a) ladder
diagram, b) instruction list, c) local symbols

127
8. Summary

This book is written mainly for automation and computer science students, but
also for engineers who begin work with PLCs. Therefore, explanations of basic
concepts are included, which should help less advanced readers to read it, and the
advanced ones to systematise their knowledge. That is why we hope that the book
will be found useful and practical, especially with so many examples.
During the last ten years the successor of the well-known PLC appeared in the
world market. It is named the PAC system, which stands for Programmable
Automation Controllers. The reason for the development of the PLCs is that newest
automation systems required to be networked, need more data storage, need to be
more user-friendly, be able to communicate with each other and require an open
standard. PLCs have been used traditionally for automation purposes but they have
not been designed to meet such extra requirements. PCs were always designed to
perform tasks like data storage, communication, number crunching etc. [1]. PAC
systems are more powerful than PLC systems and there is an increasing trend in the
industry to use them as automation controllers especially in more demanding
applications. The authors of the present book consider focusing on this subject in
their next publication.

128
 Bibliography

[1] Kwaśniewski J. Programmable logic controllers. Kraków, ROMA-POL,

2002

[2] Flaga S. Programowanie sterowników PLC w języku drabinkowym

[Programmable Logic Controllers (PLC) programming in ladder diagram].
Wydawnictwo BTC. ISBN 978-83-60233-56-6. 2010

[3] Omron W450-E1-06: CP1H CPU Unit Operation Manual. Japonia March
2009

129
130