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Unit - I Topic

The document outlines the basic architecture of a processor system, focusing on the 8085 microprocessor, which includes components such as the CPU, memory, and input/output interfaces. It details the bus structure, internal CPU operations, and the function of various registers and flags. Additionally, it explains the timing and execution of instructions, including memory read and instruction fetch operations.

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10 views23 pages

Unit - I Topic

The document outlines the basic architecture of a processor system, focusing on the 8085 microprocessor, which includes components such as the CPU, memory, and input/output interfaces. It details the bus structure, internal CPU operations, and the function of various registers and flags. Additionally, it explains the timing and execution of instructions, including memory read and instruction fetch operations.

Uploaded by

shwetakewat77
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Basic Processor Architecture

1
Processor System Architecture
The typical processor system consists of:
 CPU (central processing unit)
 ALU (arithmetic-logic unit)
 Control Logic
 Registers, etc…
 Memory
 Input / Output interfaces
Interconnections between these units:
 Address Bus
 Data Bus
 Control Bus
2
8085 Microprocessor Architecture

3
The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit)
communicates with the other units using a 16-bit address
bus, an 8-bit data bus and a control bus.

4
The 8085 Bus Structure

Address Bus
 Consists of 16 address lines: A0 – A15

 Operates in unidirectional mode: The address


bits are always sent from the MPU to peripheral
devices, not reverse.

 16 address lines are capable of addressing a


total of 216 = 65,536 (64k) memory locations.

 Address locations: 0000 (hex) – FFFF (hex)

5
The 8085 Bus Structure
Data Bus
 Consists of 8 data lines: D0 – D7

 Operates in bidirectional mode: The data bits are


sent from the MPU to peripheral devices, as well
as from the peripheral devices to the MPU.

 Data range: 00 (hex) – FF (hex)

Control Bus
 Consists of various lines carrying the control
signals such as read / write enable, flag bits.

6
The 8085: CPU Internal Structure

The internal architecture of the 8085 CPU is


capable of performing the following operations:

 Store 8-bit data (Registers, Accumulator)


 Perform arithmetic and logic operations (ALU)
 Test for conditions (IF / THEN)

 Sequence the execution of instructions

 Store temporary data in RAM during execution

7
The 8085: CPU Internal Structure

Simplified block diagram

8
The 8085: Registers

9
The 8085: CPU Internal Structure
Registers
 Six general purpose 8-bit registers: B, C, D, E, H, L
 They can also be combined as register pairs to
perform 16-bit operations: BC, DE, HL

 Registers are programmable (data load, move, etc.)


Accumulator
 Single 8-bit register that is part of the ALU !
 Used for arithmetic / logic operations – the result is
always stored in the accumulator.
10
The 8085: CPU Internal Structure
Flag Bits
 Indicate the result of condition tests.
 Carry, Zero, Sign, Parity, etc.
 Conditional operations (IF / THEN) are executed
based on the condition of these flag bits.
Program Counter (PC)
 Contains the memory address (16 bits) of the
instruction that will be executed in the next step.
Stack Pointer (SP)
 Contains the address (16 bits) of a memory
location in R/M memory, called the stack
11
• S-sign flag
– The sign flag is set if bit D7 of the accumulator is set after an
arithmetic or logic operation(result negative).
• Z-zero flag
– Set if the result of the ALU operation is 0. Otherwise is reset. This
flag is affected by operations on the accumulator as well as other
registers. (DCR B).
• AC-Auxiliary Carry
– This flag is set when a carry is generated from bit D3 and passed to
D4 . This flag is used only internally for BCD operations.
• P-Parity flag
– After an ALU operation if the result has an even no. of 1’s the p-
flag is set. Otherwise it is cleared. So, the flag can be used to
indicate even parity.
• CY-carry flag
– If an arithmetic operation results in a carry, the carry flag is set
otherwise it is reset. It also severs as a borrow flag for subtraction.

12
Example: Memory Read Operation

13
Cycles and States
– T- State: One subdivision of an operation. A T-
state lasts for one clock period.
• An instruction’s execution length is usually
measured in a number of T-states. (clock
cycles).
– Machine Cycle: The time required to complete one
operation of accessing memory, I/O, or
acknowledging an external request.
• This cycle may consist of 3 to 6 T-states.
– Instruction Cycle: The time required to complete
the execution of an instruction.
• In the 8085, an instruction cycle may consist of 1
to 6 machine cycles.
14
• The 8085 executes several types of instructions
with each requiring a different number of
operations of different types. However, the
operations can be grouped into a small set.
• The three main types are:
• Memory Read and Write.
• I/O Read and Write.
• Request Acknowledge.

• These can be further divided into various


operations (machine cycles).
15
Example: Instruction Fetch Operation

 All instructions (program steps) are stored in memory.


 To run a program, the individual instructions must
be read from the memory in sequence, and executed.

 Program counter puts the 16-bit memory address of the


instruction on the address bus
 Control unit sends the Memory Read Enable signal to
access the memory
 The 8-bit instruction stored in memory is placed on the data
bus and transferred to the instruction decoder
 Instruction is decoded and executed

16
Example: Instruction Fetch Operation

17
Example: Instruction Fetch Operation

18
Timing Diagram
Opcode Fetch Cycle
T1 T2 T3 T4

CLX

A15
20H High-Order Memory Address Unspecified
A8
Low-Order
AD7
05H 4FH Opcode
AD0
Memory Address

ALE

IO/M Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch

RD

19
Demultiplexing the Bus AD0-AD7

• Address on the high order bus(20H)


remains on bus for 3 clock period.
• However, the lower order address(05H) is
lost after first clock period.
• Address needs to be latched to identify
address after first clock period.

20
Schematic of Latching Low Order
Address Bus
A15 A15

8085
Microprocessor
A8
A8
ALE
Enable
AD7 G
D Q A7

AD0 74LS373
A0

D7

D0

21
Schematic to generate Control Signals
74LS32

IO/M
MEMR
RD

8085
WR MEMW

IOR
74LS04

IOW

22
Timing for Execution of the
Instruction MVI A,32H
M1 Opcode Fetch M2 Memory Read
T1 T2 T3 T4 T1 T2 T3

CLX

A15
20H High-Order Memory Address Unspecified 20H High- Order Memory Address
A8

AD7
00H 3EH Opcode 01H 32H Data
AD0
Low-Order Memory Address Memory Address

ALE

IO/M
Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch IO/M = 0, S1 = 1, S0 = 0 Status
S1, S0

RD

23

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