LAB-3

AIM:
Design and implement C-MOS inverter and plot its VTC- Curve or Dc- Sweep Analysis
and compare the results with a CMOS inverter designed with 180 nanometer technology.

APPARATUS REQUIRED: N-MOS, P-MOS, Connecting wires,Voltage Source, Ground,

Voltage Probes and 180 nm technology of nmos and pmos.

THEORY:
A CMOS inverter is a fundamental digital logic circuit consisting of a PMOS and an NMOS
transistor. When the input is high, the NMOS turns on, and the PMOS turns off, pulling the
output low. Conversely, when the input is low, the PMOS turns on, and the NMOS turns off,
pulling the output high. This complementary operation results in low power dissipation since
current flows only during switching. CMOS inverters provide high noise immunity, fast
switching speeds, and microprocessors, and modern integrated circuits.

CIRCUIT DIAGRAM:
For DC Analysis:
Voltage-Transfer Characteristic Curve:
FOR CMOS w =2u

CALCULATIONS:

PARAMETERS OUTPUT VOLTAGE{V}

VOL 0V

VOH 1.8 V

VIL 0.67 V
 VIH 1.12 V

VTH 760 mV

Noise Margin{H} 0.68 V

Noise Margin{L} 0.67 V

After taking 180n Technology:-

Concepts/Process :

· To get circuit symmetry at the condition of Kn = 2.5 * Kp we need to use 180nm

CMOS technology.

· To use this technology we need to use a library for this. So we need to put the
supported spice code in it.

· Now we have just repeated the process and again calculated the Noise Margin for
this.

CIRCUIT DIAGRAM:
Voltage-Transfer Characteristic Curve:
FOR CMOS w =5u

CALCULATIONS:

PARAMETERS OUTPUT VOLTAGE{V}

VOL 0V

VOH 1.8 V

VIL 0.72 V
 VIH 0.96 V

VTH 860 mV

Noise Margin{H} 0.84 V

Noise Margin{L} 0.72 V

CONCLUSION:
Pmos inverter works correctly but has high power dissipation and slower switching due
to resistive load.Cmos inverter,designed with 180nm technology ,offers sharper
transitions ,lower power dissipation,and higher speed due to its complementary transistor
configuration. As w decreases, resistance of pmos increases then Graph shifts towards
the left side.
 LAB-4

AIM:
Design and implement C-MOS inverter circuit and perform Transient Analysis to
measure its propagation delay and also calculate average power dissipation.

APPARATUS REQUIRED: N-MOS, P-MOS, Connecting wires,Voltage Source,

Ground, Pulse signal generator and 180 nm technology of nmos and pmos.

PROPAGATION DELAY:

Propagation delay is a key performance metric in digital circuits, describing the time
required for a signal to propagate through a logic gate.

High-to-Low Propagation Delay (t_{PHL}):

● The time taken for the output to transition from HIGH (logic 1, VOH) to LOW
(logic 0, VOL).

● Measured from the 50% transition point of the input falling edge to the 50%
transition point of the output falling edge.

Low-to-High Propagation Delay (t_{PLH}):

● The time taken for the output to transition from LOW (logic 0, VOL) to HIGH
(logic 1, VOH).

● Measured from the 50% transition point of the input rising edge to the 50%
transition point of the output rising edge.

Propagation delay(tp)=(t_{PHL}+t_{PLH})/2.

Faster circuits have lower tp,Higher capacitive load increases tpt_ptp, reducing speed.
CIRCUIT DIAGRAM:

For Transient Analysis:

For Propagation delay:

TRANSITION 50% I/P TIME(ns) 50% O/P TIME(ns) CAL_DELAY(ps)

T{phl} 2.0532 2.0676 14.4

T{plh} 3.1703 3.1406 29

Avg_delay - - 21.7

CONCLUSION:

Cmos inverter successfully switches between logic high and low states.Propagation delay
is measured and is influenced by transistor sizing and load capacitance.Average power
dissipation remains low compared to other inverter designs,making cmos inverter more
efficient.
 LAB-5

AIM:
To Design and implement Two input NAND and NOR gate using CMOS logic and
measure its propagation delay with respect to each input considering the worst case
scenario.

COMPONENTS USED:
Pmos transistor,Nmos transistor,dc supply,pulse signal generator,ground
connection,measurement tools.
PMOS transistors conduct when the input is LOW (0).
NMOS transistors conduct when the input is HIGH (1).

1. CMOS NAND Gate

A NAND gate gives a LOW output only when both inputs are HIGH.

● Logic: Y=(A.B)’
● CMOS Implementation:
○ Pull-up network (PUN): Two PMOS transistors in parallel.
○ Pull-down network (PDN): Two NMOS transistors in series.
● Worst case scenario
In this case we see high resistance across the network.And for that case we
observe that both nmos should be on and either of the pmos should be on.If we assume
the width of nmos to be Wn and of pmos to be Wp then we can say that Wp=2Wn.

For NAND operation we will take the effectiveness of it.Thus for parallel combination
we will get effective value 2Wp and for series combination we will get Wn/2.
Thus we get :
Wp=2(Wn)’=2*(Wn/2)=Wn
Thus Wp=Wn=4u.

2. CMOS NOR Gate

A NOR gate gives a HIGH output only when both inputs are LOW.

● Logic: Y=(A+B)’
● CMOS Implementation:
○ Pull-up network (PUN): Two PMOS transistors in series.
○ Pull-down network (PDN): Two NMOS transistors in parallel.
● Worst case scenario
In this case we see high resistance across the network.And for that case we
observe that both pmos should be on and either of the nmos should be on.If we assume
the width of nmos to be Wn/2 and of pmos to be Wp then we can say that Wp=2(Wn)’.
 For NOR operation we will take the effectiveness of it.Thus for parallel combination we
will get effective value Wn and for series combination we will get Wp/2.
Thus we get :
(Wp)’=2(Wn)
Wp/2=2Wn Wp=4Wn
Thus Wp=8u Wn=2u.

CIRCUIT DIAGRAM[NAND -LOGIC]:

1. Logic without Spice Netlist Data:

OUTPUT:
2. Logic with Spice Netlist Data:

OUTPUT:

CALCULATIONS:
For NAND Logic:-

1)Vin1=Pulse and Vin2=1

T_{plh}: Tfall-Trise = 5.168 - 5.135 = 0.035ns
 Input Fall and Output Rise

Input Rise and Output Fall

T_{phl}: Tfall-Trise = 4.107 - 4.042 = 0.065ns

T_{avg}: T_{plh}+ T_{phl}= (0.035+0.065)/2 =0.05ns

1)Vin1=1 and Vin2=Pulse

T_{plh}: 5.165 - 5.138 = 0.027ns

Input Fall and Output Rise

 Input Rise and Output Fall

T_{phl}: 4.094 - 4.041 = 0.053ns

T_{avg}: T_{plh}+ T_{phl}=(0.027+0.053)/2=0.04ns

CIRCUIT DIAGRAM[NOR -LOGIC]:

OUTPUT:

CALCULATIONS:
For NOR Logic:-

1)Vin1=1 and Vin2=Pulse

T_{plh}: Tfall-Trise = 1.19 - 1.13 = 0.06ns

Input Rise and Output Fall

 T_{phl}: Tfall-Trise =2.05-2.03=0.02ns
T_{avg}: T_{plh}+ T_{phl}= =(0.02+0.06)/2=0.04ns

1)Vin1=Pulse and Vin2=1

T_{plh}: 4.07 - 4.04=0.03ns

Input Fall and Output Rise

Input Rise and Output Fall

T_{phl}: 5.19 - 5.13=0.05ns

T_{avg}: T_{plh}+ T_{phl}=(0.03+0.05)/2=0.04ns

Tavg for Nor gate using cmos=(0.04+0.04)/2=0.04ns.

CONCLUSION:
In this lab, we successfully implemented NAND and NOR logic using CMOS circuits. By analyzing
their design and performance, we calculated the overall worst-case delays for both gates. This
experiment provided valuable insights into the working principles, timing characteristics, and
efficiency of CMOS-based logic gates, aiding in a deeper understanding of digital circuit design.
 LAB-6

AIM:
To Design and implement Two input XNOR gate using CMOS logic and measure its
propagation delay with respect to each input considering the worst case scenario.

COMPONENTS USED:
Pmos transistor,Nmos transistor,dc supply,pulse signal generator,ground
connection,measurement tools.
PMOS transistors conduct when the input is LOW (0).
NMOS transistors conduct when the input is HIGH (1).

1. CMOS XNOR Gate

An XNOR gate gives a HIGH output when both inputs are either HIGH or LOW.

, ● Logic:Y=(A⊕B)′Y=(A⊕B)′=A′B′
● CMOS Implementation:
○ Pull-up network (PUN): Consists of two parallel PMOS transistors for AB and
two parallel PMOS transistors for A'B'.
○ Consists of two series NMOS transistors for A'B and two series NMOS transistors
for AB'.
● Worst case scenario:
In this case we see high resistance across the network.And for that case we observe that
both nmos in parallel combination of either side should be on and one pmos of the parallel
combination should be on for that series combination.If we assume the width of nmos to be Wn
and of pmos to be Wp then we can say that Wp=2Wn.

For XNOR operation we will take the effectiveness of it.Thus for parallel combination we will
get effective value Wn/2 and for series combination of two parallel pmos is Wp/2 making only
one pmos on for each parallel combination. Thus we get :
Wp’=2(Wn)’ Wp/2=2(Wn/2)
Thus Wp=2Wn Now if Wn=2u Wp=4u.

PROCESS:
1) First check whether the circuit is working or not by using the pulse response in the circuit.
Here for input A=1,B=1 or A=0,B=0 we should get 1 and for rest input the output should be 0.

2) Then we will put one of the inputs to 1 and see the output.Here in this case we can see that
whenever there is shift in the input value there is shift in the output also.
3)With this then we will calculate the t_{phl} and t_{plh} values and take the average of it
the resultant will be the propagation delay for the XNOR circuit.
4)t_{phl}=The time taken for the output to transition from HIGH (logic 1, VOH ) to LOW
(logic 0, VOL ).
5) t_{plh}=The time taken for the output to transition from LOW (logic 0, VOL ) to HIGH
(logic 1, VOH ).
CIRCUIT DIAGRAM[XNOR -LOGIC]:

OUTPUT:
Input (A and B)

Output(A⊕B)′
CALCULATIONS:
For XNOR Logic:-

1) A=1 and B=pulse

T_{phl}:
Input rise(curser1) Output fall(curser2)

T_{plh}=tfall-trise=4.114-4.039=0.075ns
T_{plh}:
Input fall(curser1) Output rise(curser2)

T_{plh}=trise-tfall=5.18-5.14-=0.04ns
T_{avg}=T_{plh}+T_{phl}/2=(0.04+0.075)/2=0.0575ns

2) A=pulse and B=1

T_{phl}:-
Input rise(curser1) Output fall(curser2)

T_{phl}=tfall-trise=4.117-4.04=0.077ns
T_{plh}:
Input fall(curser1) Output rise(curser2)

T_{plh}=trise-tfall=5.16-5.14=0.02ns
T_{avg}=T_{plh}+T_{phl}/2=(0.077+0.02)/2=0.0485ns

Tavg for Xnor gate using cmos=(0.0575+0.0485)/2=0.053ns.

CONCLUSION:
In this lab, we successfully implemented the XNOR logic using a CMOS circuit.
Through this implementation, we analyzed the circuit's performance and evaluated its
overall worst-case delays. This experiment provided valuable insights into the design
and timing characteristics of CMOS-based XNOR gates, enhancing our understanding
of digital circuit optimization.