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Day-12 Sequential Circuits-2

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23 views11 pages

Day-12 Sequential Circuits-2

Day

Uploaded by

mirzayn85
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Date:- 12/04/2025

Day - 12
SEQUENTIAL CIRCUITS- 2

SRI VENKATA KASYAP CHALLAPALLI


CONTENT TABLE

S. No Topic

1. Race Around Condition

2. Methods to eliminate Race around condition

3. Asynchronous Inputs

4. Flip Flops
1. Race Around Condition
In J-K latch when J, K and Clock are equal to 1, toggling takes place, i.e. the
next state will be equal to the complement of the present state. See the timing
diagram of j-k latch. Here, T is the time period of the clock whereas delta t is the
propagation delay. The delay between input and output is called a propagation
delay. If J=K=1, and if clk=1 for a long period of time, then output Q will
toggle as long as CLK remains high which makes the output unstable or
uncertain. This is called a race around condition in J-K latch. This condition
also exists in T latch since it also has toggling options.

JK Latch timing diagram with race around condition

2. How to eliminate Race around condition


There are three methods to eliminate race around condition as described below:
Increasing the delay: The propagation delay (delta t) should be made greater
than the duration of the clock pulse (T). But it is not a good solution as
increasing the delay will decrease the speed of the system.
Use of master-slave JK configuration: If the flip flop is made to toggle over
one clock period then racing around condition can be eliminated. This is
done by using Master-Slave JK flip-flop.
Use of edge-triggered clock pulse: If the clock is high for a time interval less
than the propagation delay of the flip flop then racing around condition can
be eliminated. This is done by using the edge-triggered flip flop rather than
using the level-triggered flip-flop.
3. Asynchronous Inputs
There are two special inputs which are used to clear and preset the value of the
flip-flop asynchronously which are usually called CLEAR and PRESET
respectively. These inputs are called asynchronous or direct inputs because these
signal don't wait for the clock to come but can affect the output independent of
the clock.
These inputs can be of two types:
1. Active LOW: This means when the input is LOW, it would affect the output
otherwise if input is HIGH then it causes no change.
2. Active HIGH: This means when input is HIGH then it can change the
output otherwise if input is LOW, it doesn't cause any change in the output.

Active LOW Asynchronous Input

Active HIGH Asynchronous Input


4. Flip Flops
Flip-flops are also the building blocks of sequential circuits. They are made
using latches. Flip-flops work on the application of a clock signal. This makes
them synchronous. A flip-flop has two inputs and two outputs. The outputs (Q
and Q') are complements of each other. It has two stable states.

Basic digital circuits like shift registers and counters are made using flip-flops.
Flip-flops can be implemented in two methods. In first method, cascade two
latches, that is master slave configuration of latches in such a way that the first
latch is enabled for every positive clock pulse and second latch is enabled for
every negative clock pulse. The combination of these two latches becomes a flip-
flop.

In second method, we can directly implement the flip-flop using edge triggered
clock pulse generator, which is edge sensitive.

We have four main types of flip-flops:


1. SR flip-flop (Set-Reset flip-flop)
2. D flip-flop (Delay/Data flip-flop)
3. T flip-flop (Toggle flip-flop)
4. JK flip-flop (Jack-Kilby flip-flop)
4.1 SR Flip Flop
An SR flip-flop is an extension of the SR latch. So let's take our SR latch.
Attach the outputs of two new NAND gates to the inputs of the SR latch.
Apply a common clock input to the new NAND gates. The other inputs to the
first and second new NAND gates are S and R, respectively. This is how we
construct an SR flip-flop.

SR Flip Flop
4. Flip Flops
4.1 SR Flip Flop
The following table shows the characteristic table of SR flip-flop: Here, Q(t) &
Q(t+1) are present state & next state respectively

Excitation table for S-R flip flop


From the above truth table, we can infer following points:
When Q retains state 'o', we have two conditions S = R = '0' and S = '0';
R='1', hence to retain state '1',S = '0' and R = 'x'
When Q changes from 0' to '1', S = '1'; R = '0'
When Q changes from '1' to '0', S = '0'; R = '1'.
When Q retains state '1', we have two conditions S = R = '0' and S = '1';
R = '0', hence to retain state '1', S='x' and R = '0'.
4. Flip Flops
4.2 D Flip Flop
A D flip-flop stands for a data or delay flip-flop. The outputs of this flip-flop
are equal to the inputs. We can make a D flip-flop using both SR and JK flip-
flops. The construction is similar. Only one input is given to the flip-flop. The
other input is the invert of the input given. We achieve the inversion using a
NOT gate. Now, it is a data or delay flip-flop depending on whether the SR/JK
flip-flop requires positive or negative edge triggering, respectively.

D Flip Flop

Characteristic Table
4. Flip Flops
4.2 D Flip Flop
From the above table next state equation can be written as:
Q(n+1)= D
From the truth table, we can see that,
When Q retains it state from '0' to '0' or changes from '1' to '0', the value of D
is '0'.
When Q retains it state from '1' to '1' or changes from '0' to '1', the value of D
is '1'.

4.3 T Flip Flop


The T in T flip-flop stands for toggle. This implies that the output will change
from the previous value with a change in the input. We can construct a T flip-flop
using a JK flip-flop
4. Flip Flops
4.4 JK Flip Flop
JK Flip Flop is similar to RS flip flop with the feedback which enables only one
of its input terminals. It eliminates the invalid condition which arises in the RS
flip flop and put the input terminal either to set or reset condition one at a time.

JK Flip Flop

Therefore, the simplified expression for next state Qt+1t+1 is:


Q(t+1)=JQ(t)’+K’Q(t)
4. Flip Flops
4.4 JK Flip Flop
Excitation table for J-K flip flop:
From the truth table,
When Q retains state '0', J = K = 0 and J = 0 K=1 => J = '0', K = 'x'
When Q changes from '0' to '1', J = K = 1 and J = 1 , K = 0 =>J=1, K = 'x'
When Q changes from '1' to 'o', J = K = 1 and J = 0 K = 1 =>J=’x’, K = '1'
When Q retains state '1', J = K = 0 and J = 1, K = 0 =>J=x K = '0'

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