Shi et al.

Nanoscale Research Letters (2020) 15:104

https://doi.org/10.1186/s11671-020-03333-w

NANO EXPRESS Open Access

A 180 nm Self-biased Bandgap Reference

with High PSRR Enhancement
Yue Shi1, Shilei Li2, Jianwen Cao2, Zekun Zhou2* and Weiwei Ling1

Abstract
In this paper, an improved self-biased bandgap reference (BGR) with high power supply rejection ratio (PSRR) is presented.
An operational amplifier constructing feedback loop is multiplexed with the generation of positive temperature coefficient
(TC) voltage for lower power consumption, where an offset voltage is adopted to achieve proportional to absolute
temperature (PTAT) voltage. With the temperature-independent reference generation, two feedback loops are realized at the
same time for PSRR enhancement, which form a local negative feedback loop (LNFL) and a global self-biased loop (GSBL).
The proposed BGR is implemented in a 180 nm BCD technology, whose results show that the generated reference voltage
is 2.506 V, and the TC is 25 ppm/°C in the temperature range of −55 to 125 °C. The line sensitivity (LS) is 0.08 ‰/V. Without
any filter capacitor, the PSRR is 76 dB at low frequencies, over 46 dB up to 1 MHz.
Keywords: Global self-biased loop, Local negative feedback loop, High power supply rejection ratio

Introduction compensation (LSRC) [4], and so on. Another disadvan-

Voltage reference is one of the core modules in electronic tage of the conventional BGR circuit is that it is greatly
systems, which is widely used in medical electronics, affected by the external environment and the output
power managements, wireless environmental sensors, and voltage is unstable, which is the focus of this article.
communication circuits. With the improvement of Power supply rejection ratio (PSRR) is an important
technology, the area of chip continues to shrink, and the parameter to measure the noise immunity of a voltage
anti-interference ability continues to increase, and the reference. Conventional solutions to improve PSRR are
requirements for structural optimization and noise im- at the cost of chip area and power consumption [5],
munity of voltage reference are increasing dramatically, such as additional amplifiers, long channel transistors,
especially in nanoscale applications [1]. cascode structures [6], additional gain stage [7], and so
Conventional bandgap reference (BGR) circuits require on. Active attenuator and impedance adapting compen-
additional circuit blocks to provide bias current for the sation were adopted in [8] to improve the PSRR at low
entire circuit, which greatly increases the circuit area and high frequencies, respectively. Yue et al. [9] used
and power consumption. At the same time, the gener- cascode current mirrors to enhance PSRR. Body bias
ated bias current is greatly affected by temperature, and negative feedback techniques were utilized in [10]
which affects the temperature coefficient (TC) of the for high PSRR.
reference voltage. Lots of high-order compensated tech- In order to overcome the above-mentioned issues, an
niques for improved TC have been reported, such as improved self-biased BGR with high PSRR is proposed
piecewise curvature compensation [2], exponential in this brief. Two feedback loops are realized at the same
curvature compensation [3], leakage-based square root time for PSRR enhancement, which form a local negative
feedback loop (LNFL) and a global self-biased loop
* Correspondence: [email protected] (GSBL). Meanwhile, a self-bias current source (SBCS)
2
State Key Laboratory of Electronic Thin Films and Integrated Devices, for the whole BGR is achieved. At steady state, the pro-
University of Electronic Science and Technology of China, Chengdu 610054,
Sichuan, China
posed BGR is self-powered through the GSBL without
Full list of author information is available at the end of the article additional bias current modules and chip area. The
© The Author(s). 2020 Open Access This article is licensed under a Creative Commons Attribution 4.0 International License,
which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give
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Shi et al. Nanoscale Research Letters (2020) 15:104 Page 2 of 10

presented technique separates the supply voltage from help of an amplifier to improve the performance. Com-
the output reference voltage through a current amplifier bined with the current amplifier on the top of Fig. 1, a
embedded in GSBL, which can effectively improve the GSBL is realized for further PSRR improvement. The de-
PSRR. In addition, in order to prevent the output voltage tail implementation of the proposed BGR is shown in
from instability, a LNFL is designed at the output volt- Fig. 2.
age terminal to keep the output voltage stable. What is
more, the temperature-stable reference voltage is gener- Start-up Circuit
ated with LNFL and GSBL in a multiplexing way. With The start-up circuit is shown in the left part of Fig. 2. At
these methods, a self-biased BGR with high PSRR en- the beginning of the start-up stage, output voltage VREF
hancement is implemented with compacted structure is at low level, which keeps MN8 and MN9 off. The
and current consumption. current through MP1_1 is used to generate a start-up
current to MP5, where MP1_1 is as a large resistance
Method with quite small aspect ratio. The voltage at VREF will be
As shown in Fig. 1, the proposed BGR circuit consists of gradually charged by the start-up current. When the
a start-up circuit, a current amplifier, an operational voltage at VREF exceeds the minimum operation voltage
amplifier, and a bandgap reference core. The start-up of the bandgap core part, the bias current for the ampli-
circuit is used to get rid of the zero-degenerate point. fier will be generated. This will drive the BGR to the
The built-in offset voltage in the amplifier is set to be desired operation point. At the same time, transistors
proportional to absolute temperature (PTAT) voltage, MN8 and MN9 will be gradually on, which switches the
which can realize a PTAT current through resistor R1. supply current of MP5 to the self-biased current gener-
With the positive TC of voltage across R1 and R2, the ated in the bandgap core. After the startup is completed,
negative TC of VBE(Q5) and VBE(Q4) can be properly can- the startup current is not turned off for VREF re-
celed to achieve a temperature-stable reference voltage adjustment in the case of reference voltage falling for
at node VREF. At the same time, a LNFL formed with the some reasons [11].

Fig. 1 Equivalent architecture diagram of proposed voltage reference

Shi et al. Nanoscale Research Letters (2020) 15:104 Page 3 of 10

Fig. 2 Schematic of proposed voltage reference

SBCS Generator by K as the current source to node VREF, which can be

There are two SBCS loops in the proposed BGR, which described as
are helpful for performance enhancement [1]. The first
one is located at the tail current of the amplifier. The K ¼ k1k2 ð3Þ
PTAT current through transistor Q4 is mirrored into
Q3. However, the current through Q4 is determined by where k1 = SMN6/SMN7, k2 = SMP3/SMP2, Si is the aspect
the voltage across resistor R1, which is clamped to the ratio of transistor i. Therefore, the current, KI, is re-
input offset voltage of the amplifier. Due to the same as- injected into the amplifier and bandgap core parts,
pect ratios of MP7 and MP8, the input offset voltage of which constructs the second self-bias loop.
the amplifier can be expressed as In order to guarantee the proper operation with low
power consumption, the current, KI, should be slightly
V OS ¼ V T ln N ð1Þ larger than the minimum current requirement of ampli-
fier and bandgap core. In the proposed design, the cur-
where N is the area ratio of Q1 and Q2, and VT is the rents through MP6, MP7, and MP8 are set at the same
thermal voltage. Therefore, the current in amplifier and level, I. The current through bandgap core is 2I. There-
bandgap core parts is PTAT current, which can be given fore, the relationship, 6 ≥ K > 5, should be satisfied [12–
by 14].

I R1 ¼ V T ln N=R1 ð2Þ VREF Generator Circuit

The VREF generator circuit is shown in the right part of
The current of bandgap reference core is mirrored into Fig. 2, which consists of an amplifier and bandgap core.
the amplifier as tail current, forming the first self-biased As shown in equation (2), the PTAT offset voltage of
loop. the amplifier is multiplexed by the SBCS loops [15]. This
The second SBCS loop is made up with the current makes the current through R1, R2, and RTrimming is
amplifier. The PATA current shown in equation (2) is PTAT current, which is used as temperature compensa-
mirrored into the current amplifier by the current mir- tion of the negative TC of Q4 and Q5. The generated
ror of MP7 and MP6. Then the current, I, is amplified reference voltage, VREF, can be expressed as
Shi et al. Nanoscale Research Letters (2020) 15:104 Page 4 of 10

Fig. 3 Req calculation diagram

Fig. 4 Small-signal model for Req. a Req1,2 calculation diagram. b Req3 calculation diagram. c Req4 calculation diagram
Shi et al. Nanoscale Research Letters (2020) 15:104 Page 5 of 10

 RTrim ming
R2 þ RTrim ming AV ;PF ¼ g r o;MP8 ð5Þ
V REF ¼ 2V BE þ 1þ V T ln N ð4Þ R1 þ RTrim ming þ R2 m;Q1
R1
R1 þ RTrim ming
AV ;NF ¼ g r o;MP8 ð6Þ
With the ratio adjustment of (R2 + RTrim min g)/R1, a R1 þ RTrim ming þ R2 m;Q2
temperature-compensated reference voltage can be real-
ized with low-temperature drift. where gm, Q1 is the transconductance of transistor Q1,
ro, MP8 is the output resistance of transistor MP8, and
the gm of Q1 and Q2 is approximately equal. Since the
Feedback effect of the negative feedback loop is stronger than that
A LNFL is established in the amplifier and bandgap of the positive feedback loop, the loop1 behaves as a
core, which is formed by two small LNFLs. The first feedback loop, whose loop characteristic can be
one, loop1, is from the input of the amplifier to VREF, expressed as
and feedback to the input of the amplifier. The other
one, loop2, is from VREF through Bandgap core to R1
current tail of amplifier, and feedback to VREF. For T loop1 ≈ g r o;MP8 ð7Þ
R1 þ RTrim ming þ R2 m;Q1
loop1, there are positive feedback and negative feed-
back double local loops with the input of the ampli- 1
fier. The positive feedback loop is composed of Q5, p0 ≈ ð8Þ
r o;MP8 C 1
R2, R1, Q1, MP8, and MX. The negative feedback
loop consists of Q5, R2, Q2, and MX. The gain of
where p0 is the dominant pole. With regard to loop2,
the positive and negative feedback loop is derived as
the performance can be given by

Fig. 5 Small-signal model for PSRR

Shi et al. Nanoscale Research Letters (2020) 15:104 Page 6 of 10

1=g m;MP8 the whole circuit in a self-biased method with enhanced

T loop2 ≈ ð9Þ PSRR performance. The loop gain of GSBL can be given
R1 þ RTrim ming þ R2
by
g m;MP8
p1 ≈ ð10Þ
C1  
K 1=3g m;MP8 ‖1=g m;MX
where gm, MP8 is the transconductance of transistor T GSBL ≈ ð13Þ
MP8, and p1 is the dominant pole. As a result, the total R1 þ RTrim ming þ R2
loop gain of LNFL is
R1 g m;Q1 r o;MP8 þ 1=g m;MP8 where gm, MX is the transconductance of transistor MX.
1 þ s=z0
T LNFL ≈ The main effect of transistor MX is to lower the equiva-
R1 þ RTrim ming þ R2 ð1 þ s=p0 Þð1 þ s=p1 Þ
lent impedance at VREF with the convenience of loop
ð11Þ compensation. TGSBL is set to be smaller than one in the
proposed design, which can avoid oscillation.
Taken equation (2) into consideration, equation (11) can
With the help of LNFL and GSBL, the stability of gen-
be rewritten as,
erated reference voltage, VREF, can be greatly improved.
r o;MP8 ln N þ 1=g m;MP8 1 þ s=z0
T LNFL ≈
R1 þ RTrim ming þ R2 ð1 þ s=p0 Þð1 þ s=p1 Þ PSRR of Proposed Voltage Reference
ð12Þ In order to simplify the PSRR calculation of the proposed
circuit, the equivalent resistance of the part powered by
where z0 ≈ gm, MP8/[C1(1 + 1/ ln N)]. Since N = 8 in the the reference voltage, VREF, is firstly calculated. The calcu-
proposed design, it makes the zero, z0, proximately equal lation diagram of this part is shown in Fig. 3 [16].
to twice the pole, p1, which can extend the loop band- Figure 4a shows a small-signal model for the equiva-
width of LNFL by twice. lent resistance calculation of circuit branches 1, 2, where
A GSBL is formed by the current amplifier, bandgap currents I1 and I2 flow in Fig. 3, respectively. Then, the
core, and amplifier, which can provide bias current for equivalent resistance, Req1,2, can be expressed as

Fig. 6 Layout of proposed circuit

Shi et al. Nanoscale Research Letters (2020) 15:104 Page 7 of 10

3Req;4 r o;Q1
Req1;2 ≈  
3g m;Q1 r o;Q1 RT þ R1 þ r o;Q3 þ g m;Q1 R1 r o;Q1 þ 3Req;4
ð14Þ

where gm,Q1 and ro,Q1 are transconductance and output

resistance of Q1, respectively; Req4 is equivalent resist-
ance of branch with I4. Since the gate voltage of MP6
shown in Fig. 2 is determined by the drain voltage of
MP7, the power supply noise attenuation (PSNA) at
node M should be also calculated, which can be given by

V M ¼ ΔV ref
g m;Q1 R1 r o;Q2
þ   ΔV ref ≈ ΔV ref
2g m;MP7 r o;Q2 þ r o;MP8 Req4
ð15Þ

where ro,MP8 and ro,Q2 are output resistance of MP8 and

Q2, respectively; gm,MP7 is transconductance of MP7. As
claimed in equation (15), the supply noise has little in-
fluence on the source-gate voltage of MP6. This makes
MP6 act as a high impedance, ro,MP6, which separates
the noise impacts from the amplifier and bandgap core
parts.
The equivalent resistance of branch with I3 in Fig. 3
can be derived by Fig. 4b, which can be expressed as

6Req;4
Req3 ≈ h   i
g m;mx 3g m;Q1 r o;Q1 RT þ R1 þ r o;Q3 þ 3Req;4 þ g m;Q1 r o;Q1 R1

ð16Þ Fig. 7 Start-up transient characteristic of proposed voltage reference

where gm,Mx is the transconductance of Mx. The small-

Fig. 8 Temperature dependence of generated reference voltage

Shi et al. Nanoscale Research Letters (2020) 15:104 Page 8 of 10

Fig. 9 Supply dependence of generated reference voltage

signal model of equivalent resistance of branch with I4 Therefore, the total PSRR of the proposed voltage reference
in Fig. 3 is shown in Fig. 4c, which is, can be illustrated in Fig. 5. The PSRR can be given by

Req4 ≈ 1=g m;Q5 þ R1 þ RT þ 1=g m;Q4 þ R2 ð17Þ ΔV ref 6Req;4

≈    ð19Þ
ΔV CC g m;mx g m;mp3 r o;mp3 r o;mp6 3g m;Q1 r o;Q1 RT þ R1 þ r o;Q3
þ3Req;4 þ g m;Q1 r o;Q1 R1 
Therefore, the small-signal equivalent resistance of amp-
lifier and bandgap core parts in Fig. 3 is Since gmro > > 1 is generally valid, the influence of power
Req ¼ Req1;2 ‖Req3 ‖Req4 ð18Þ supply noise on the generated reference voltage is greatly
suppressed.

Fig. 10 PSRR characteristic of proposed voltage reference

Shi et al. Nanoscale Research Letters (2020) 15:104 Page 9 of 10

Table 1 Performance of reference voltage with process The improved PSRR performance is illustrated in Fig. 10,
variations which has a PSRR of 76 dB agreeing with theoretical results
Parameter results VREF (V) TC (ppm/°C) LS (‰/V) PSRR@10 Hz (dB) in equation (19) at low frequencies and above 46 dB up to 1
Minimum value 2.484 24 0.02 −71 MHz.
Typical value 2.506 25 0.08 −76 Conventional binary trimming method is suitable for
the proposed BGR, which adopts an 8-bit trimming for
Maximum value 2.522 30 0.12 −78
RTrimming. This can realize a 9 mV/LSB trimming step.
Table 1 shows the performance of trimmed voltage ref-
erence with 3 -5 V supply voltage and −55 to 125 °C
Results and Discussion temperature range under difference process corners,
The voltage reference is implemented in a 180 nm BCD which include typical, slow, and fast cases. As shown in
process, whose layout is shown in Fig. 6, occupying a Table 1, the temperature drift is within 0.6%, the LS is
0.05690 mm2 active area. below 0.12‰/V, and PSRR is above 71 dB@10 Hz.
The simulated start-up waveforms are shown in Fig. 7, Table 2 gives the characteristic summary of the pro-
which illustrates the transient procedure with the posed voltage reference and the comparison with some
power-supply-voltage establishment. When the supply previously reported voltage references. Since the proposed
voltage is small, the entire reference circuit is not fully voltage reference is aiming at high supply stability, no
operated, which means the startup branch current is high-order temperature compensation is utilized in this
very small and the reference voltage is maintained at paper. Therefore, the TC of [11–13], which mainly focus
zero. With the rising of power supply voltage, the gener- on temperature or power optimization methods, is smaller
ated reference voltage is firstly stable at approximately than that of the proposed voltage reference. The TC of
2VBE due to the abnormal operation of the amplifier part the proposed voltage reference can be further optimized
in Fig. 2. When the supply voltage increases above the with literature reported curvature-compensation methods
minimum required supply voltage of proposed BGR, the as needed. With the proposed compacted structure, LNFL
core operational amplifier starts to work, and the refer- and GSBL are realized with a temperature-independent
ence voltage is quickly stabilized at the desired value. Be- reference voltage at the same time, which has the best
sides, the start-up current drops about to zero with a PSRR and LS performance in Table 2.
desired reference voltage, while the proposed SBCS tak-
ing the place of current supply with the GSBL. The
power consumption of start-up circuit accounts for a Conclusion
small part of that of the chip. A compacted self-biased BGR with high PSRR is pre-
The temperature characteristics of the generated refer- sented in this paper. The PTAT voltage is implemented
ence voltage, VREF, are shown in Fig. 8. The voltage vari- by an operational amplifier with asymmetrical input off-
ation of VREF in the range of −55 °C ~ 125 °C is 11.3 mV, set voltage, and the negative temperature voltage is
where a TC of 25 ppm/°C is achieved. superimposed to generate a reference output voltage. At
Figure 9 demonstrates the line sensitivity (LS) of the the same time, two feedback loops, LNFL and GSBL, are
reference output voltage. The proposed BGR can be suc- realized with the same parts for temperature stability,
cessfully established over 3 V supply voltage, and VREF which reduces the structural complexity. This leads to
variation is 0.2 mV within 3 -5 V supply voltage. This self-sufficiency of supply current and power supply sen-
means a good LS of 0.08‰/V is realized. sitivity improvement with high PSRR.

Table 2 Performance summary and comparison

This work [17] [18] [19] [20]
Process (nm) 180 350 180 180 180
Minimum supply voltage (V) 3 2 1.4 0.9 0.8
Power (W) 45 μ 66 μ 34p 85n 79n
Temperature range (°C) −55-125 −40-125 0-100 −40-125 10-100
VREF (V) 2.506 1.141 1.250 0.412 0.328
TC (ppm/°C) 25 1.01 23 33.7 33.8
PSRR@10 Hz (dB) −76 −61 −42.2 −61 −55
LS (‰/V) 0.08 2 2.5 0.6 2.1
Shi et al. Nanoscale Research Letters (2020) 15:104 Page 10 of 10

Abbreviations exploiting the zero-temperature-coefficient point. IEEE Journal of Solid-State

BGR: Bandgap reference; PSRR: Power supply rejection ratio; TC: Temperature Circuits, 2017, 52(3): 623-33. DOI: https://doi.org/10.1109/JSSC.2016.2627544.
coefficient; PTAT: Proportional to absolute temperature; LNFL: Local negative 9. H. Yue, X. Sun, J. Liu, et al. 16.8/15.2 ppm/°C 81 nW high PSRR dual-output
feedback loop voltage reference for portable biomedical application. Electronics, 2019, 8(2).
DOI: https://doi.org/10.3390/electronics8020213.
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Not applicable. voltage reference with negative feedback. IET Circuits Devices & Systems
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Yue Shi proposed the novel structure and was a major contributor in writing with an inherent curvature-compensation property. IEEE Transactions on
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contributor in writing the manuscript. Jianwen Cao improved the design of TCSI.2014.2340553
the circuit. Other authors offered comments and revised the manuscript. All 12. Ji Y, Lee J, Kim B, Park H, Sim J (2019) A 192-pW voltage reference
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This work was supported by the National Science Foundation of China under 13. Chen H, Lee C, Jheng S, Chen W, Lee B (2017) A sub-1 ppm/°C precision
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Competing Interests
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16. Zhou Z, Cao J, Wang Y et al (2019) A nanoscale low-power resistorless
Author details
1 voltage reference with high PSRR. Nanoscale Res Lett 14:33. https://doi.org/
College of Communication Engineering (College of Microelectronics),
10.1186/s11671-019-2864-7
Chengdu University of Information Technology, Chengdu 610225, China.
2 17. Zhou Z et al (2019) A resistorless high-precision compensated CMOS
State Key Laboratory of Electronic Thin Films and Integrated Devices,
bandgap voltage reference. IEEE Transactions on Circuits and Systems I:
University of Electronic Science and Technology of China, Chengdu 610054,
Regular Papers 66(1):428–437. https://doi.org/10.1109/TCSI.2018.2857821
Sichuan, China.
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scalable output voltage for low-power IoT systems. IEEE J. Solid-State
Received: 14 February 2020 Accepted: 24 April 2020
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