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Siddaganga Institute of Technology, Tumakuru - 572 103: Usn 1 S I 3RCS01

This document outlines the examination structure for the Third Semester B.E. Computer Science & Engineering at Siddaganga Institute of Technology, covering topics in Computer Organization. It includes various units with questions on processor-memory connections, addressing modes, datapath organization, multiplication algorithms, and memory types. Students are required to answer five questions, selecting one from each unit, within a three-hour time frame.

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6 views2 pages

Siddaganga Institute of Technology, Tumakuru - 572 103: Usn 1 S I 3RCS01

This document outlines the examination structure for the Third Semester B.E. Computer Science & Engineering at Siddaganga Institute of Technology, covering topics in Computer Organization. It includes various units with questions on processor-memory connections, addressing modes, datapath organization, multiplication algorithms, and memory types. Students are required to answer five questions, selecting one from each unit, within a three-hour time frame.

Uploaded by

kushal2005bs
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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USN 1 S I 3RCS01

Siddaganga Institute of Technology, Tumakuru – 572 103


(An Autonomous Institution affiliated to VTU, Belagavi, Approved by AICTE, New Delhi)

Third Semester B.E. Computer Science & Engineering Examinations Dec. 2019
Computer Organization
Time: 3 Hours Max. Marks: 100
Note : Answer any five questions choosing one full question from each unit.

Unit - I
01 a) Explain with a neat diagram, the connection between the processor and the computer memory. 6
b) Represent the decimal values 5, -2, -10, 26, -19, 51 as signed, 7 bit numbers in the following
binary formats:
i) sign-and-magnitude ii) 1’s complement iii) 2’s complement 6
c) Write a program segment for the task C ← [A] + [B] and explain in detail the execution of this
program with a neat diagram. 8
OR
02 a) Briefly explain Big-endian and Little-endian assignments for storing word data in memory. 6
b) Convert the following pairs of decimal numbers to 5-bit, signed, 2’s complement binary
numbers and add them. State whether or not overflow occurs in each case:
i) -14 and 11 ii) -10 and -13 6
c) Write a program segment for adding n numbers using a loop, and explain in detail the execution
of this program with a neat diagram. 8

Unit - II
03 a) What is an addressing mode? Explain any four addressing modes with an example for each. 10
b) Explain single bus organization of the datapath inside a processor with a neat diagram. 10
OR
04 a) Write an assembly program that reads a line of characters and display it. 6
b) What is stack frame? Explain with a neat diagram. 6
c) With a neat diagram and with an example, discuss the connection and control signals for register
MDR to fetch a word from memory. 8

Unit - III
05 a) Explain three-bus organization of the datapath with a neat diagram for the control sequence for
the instruction ADD R4, R5, R6 10
b) With a neat diagram, explain 4-bit carry-lookahead adder and justify how it can speed up the
generation of carry signals. 10
OR
06 a) Explain with a neat diagram, a hardwired control unit. 8
b) Explain binary addition-subtraction logic network with a neat diagram. 6
c) Write control sequence for execution of instruction, MOVE (R1), R2 using single-bus
organization. 6

-1- Please Turn Over


-2- 3RCS01
Unit – IV
07 a) Perform multiplication for -13 and +9 using Booth’s algorithm and Bit-pair recoding algorithm. 8
b) Write IEEE standard formats for representing floating-point numbers. 6
c) Perform 11 x 13 using sequential circuit binary multiplication method. 6
OR
08 a) Explain with a neat diagram, the circuit arrangement for sequential circuit binary multiplier. 6
b) Illustrate the steps for carry-save addition for the operands 45 and 63. Draw the schematic
representation for the same. 8
c) Perform division of 810 by 510 using non-restoring division technique. 6

Unit – V
09 a) With a neat diagram, explain static RAM cell and CMOS memory cell. 10
b) Explain Direct-mapped, Associative-mapped and Set-associative-mapped cache memory with
illustration. 10
OR
10 a) With a neat diagram, explain the functioning of 2M x 8 dynamic memory chip. 10
b) Describe the following:
i) ROM ii) PROM iii) EPROM iv) EEPROM v) Flash memory 10
________

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