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Lab Manual 8

Lab 6 focuses on designing a 4-bit up/down counter and a 32-byte memory using ISE IP cores. Students will utilize ModelSim/ISE IDE to synthesize their designs and verify outputs through testbenches. A lab report detailing the design process and results is required for submission before the next lab session.

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20 views2 pages

Lab Manual 8

Lab 6 focuses on designing a 4-bit up/down counter and a 32-byte memory using ISE IP cores. Students will utilize ModelSim/ISE IDE to synthesize their designs and verify outputs through testbenches. A lab report detailing the design process and results is required for submission before the next lab session.

Uploaded by

satwat
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab 6: Counter and Memory with IP Cores FPGA Lab Manual

Lab 6: Implementation of Counter and Memory


using ISE IP Cores

1 Objectives
The objectives of this lab are:

• Design the RTL of a 4-bit up/down counter using ISE IP cores.

• Design the RTL of a 32-byte memory using block RAM and distributed RAM using
IP cores.

• Synthesize the code of both Block RAM and Distributed RAM.

2 Background
ModelSim / ISE IDE will be used in this lab along with prior learning of digital de-
sign concepts including decoder implementation. The knowledge of using IP cores and
understanding their syntax is essential for this lab.

3 Pre-Lab
8.3.1 Reading and Preparation
1. Read the Xilinx ISE tutorial available online.

2. Ensure that lecture notes and other reference materials provided by the instructor
are available during the lab session.

3. Review the syntax and usage of IP core-based Verilog coding.

4 Equipment
• Computer or Laptop

• ModelSim / ISE IDE Software

5 Procedure
Description: Design behavioral-level Verilog code of a 4-bit up/down counter and 32-
byte memory using IP cores.

i. Design the RTL of a 4-bit up/down counter using ISE IP cores.

ii. Design the RTL of 32-byte memory using Block RAM and Distributed RAM via
IP cores.

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Lab 6: Counter and Memory with IP Cores FPGA Lab Manual

iii. Synthesize both Block RAM and Distributed RAM, and comment on the synthesis
report (Check whether the 20 RAM blocks available in Spartan-3E are utilized or
not).

iv. Design the testbench to verify the outputs from (i) and (ii).

v. Investigate how many Block RAMs can be instantiated using a single RAM block
in Spartan-3E.

vi. Show the output results to the instructor.

Note: Block diagram and discussion must be handwritten in the lab report. The block
diagram should include complete details about intermediate signals, instance names, and
their connections. The discussion must comprehensively explain the observed output
waveforms.

6 Lab Report
A typeset (hand-written and printed) group lab report is required. It must be submitted
by 12 PM one day before the next lab session.

7 Results
Simulation or hardware results must be shown to the instructor for evaluation.

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