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Assignment7

CS224 Assignment 7 requires students to implement efficient long chain addition in Verilog and demonstrate it using FPGA. Students must create three different datapaths, compare their performance, and demonstrate the first implementation in FPGA. The assignment emphasizes correctness, design quality, and modularity, with specific submission requirements including a report, Verilog code, and a testbench.

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5 views

Assignment7

CS224 Assignment 7 requires students to implement efficient long chain addition in Verilog and demonstrate it using FPGA. Students must create three different datapaths, compare their performance, and demonstrate the first implementation in FPGA. The assignment emphasizes correctness, design quality, and modularity, with specific submission requirements including a report, Verilog code, and a testbench.

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feciitg
Copyright
© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
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CS224: Assignment 7

Weightage: 10%

Date of Demonstration: 10th April 2025 (2PM-5PM) in H/W Lab.

Problem Statement: Efficient Implementations of long chain addition in Verilog and demonstration
using FPGA.

Consider a long chain addition:

X = a + b + c + d + e + f + g + h;

All inputs are 4 bits. Calculate the output width according to the computation requirements.

1. Implement an iterative datapath that uses only one adder to calculate the output.
2. Create an iterative datapath that uses four adders to calculate the output.
3. Create a pipelined datapath of the design with initiation interval is one and throughput is one
per clock cycle.

Use a full ripple carry adder as adder module. Write a modular code.

For Simulation based implementation

1. Use a stream of 10 set of inputs and compare the performance of those three different
implementations.
2. Compare the area, latency, clock period, throughput of these three designs.
3. For RTL simulation, you can read all inputs at the same clock.

In FPGA:

1. Show the demo only for the first implementation in FPGA. For FPGA demo, read one input at a
time. Use the data valid signal to control the reading inputs from ports. Similarly, use out valid
signal to display the output

Guidelines:

• All the member of the group needs to be present at the time of Demonstration of the assignment.
All the absent members will be awarded 0 marks for the assignment. Please show your ID card at
the time of demonstration.
• The grading will be based on (a) Correctness, (b) Quality of design, (c) Cleanliness/modular design,
(f) Use of proper Comment/Naming of the design components and (g) Questionnaire and
explanation and (h) correctness of your Verilog implementation.
• The Verilog implementation will also be checked during evaluation.

Submission:

1. You need to submit following items in a zip folder. For each group, one of the members must
submit the report. One submission per group. We will share the marks in teams against your
submission each Assignment.
2. A PDF file containing (i) clear diagram of the design (ii) Logic behind the circuit obtained. The
report must be available during Lab evaluation.
3. Verilog code of your design
4. Testbench file

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