EE244 Prof. Dr.

Şenol Mutlu

LAB6: UP/DOWN BCD COUNTING THE NUMBER OF PUSHES ON

BUTTONS AND ITS FPGA IMPLEMENTATION

The purpose of this lab is to design a parallel loadable, 2-digit up/down BCD counter.
Counting is done by pressing and releasing a push-button switch. By pressing and
releasing one of the three push-button switches, the counter can be parallel loaded, up-
counted or down-counted. The content of the counter is displayed on two 7-segment LED
displays. This counter is implemented on the FPGA board. Overall schematic for the
system is shown below.

System overview of Lab 6

FPGA Implementation of the Up/Down Counter

The purpose of this laboratory assignment is to design, synthesize and implement a BCD
counter. In this assignment you are supposed to show that you can do up-counting, down-
counting and also parallel loading. You are going to use 8 slide switches available on the
FPGA kit to enter an 8 bit data for parallel loading. You will use 3 push-button switches,
to do parallel load and then stop, to count up and to count down. The content of your
counter should be displayed on the two digits of the seven-segment display of the Nexys3
board. The details are given below.

Reading the Switch

The FPGA is connected to five push buttons (BTNL, BTNR, BTNU, BTND and BTNS) on
the Nexys3 board. Each push button applies a high level to its FPGA pin through a resistor
when pressed and a resistor pulls the pin to a low level when the pushbutton is released.
You will use the outputs of three of these switches as parallel load, up-count and down-
count commands. If you press and release BTNL, it should load the 8-bit data presented

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by the slide switches to the counter. After loading, it should not count automatically. If you
press and release BTNU once, your system should count up once. If you press and
release BTND once, your system should count down once. If you keep pressing BTNU or
BTND, your counter should not do any counting. Counting is executed once you release
the button.

You should condition the output of the push-button switches before you use them as inputs
to your system since pressing these buttons once actually generates many glitches (many
negative and positive levels and edges). You can use a shift-register to detect if the button
is pressed and then generate a clean input signal.

In order to use the push buttons as inputs, they must be debounced so that a single push
of the button results in a clean signal. One way to debounce a switch signal is to shift the
bouncing signal down to a shift register. Then, the outputs of all the flip-flops can be
ANDed to generate a clean signal as shown in the figure below. Assume that the bounce
interval of a switch has been experimentally determined to be about 10 ms. That is the
output of the switch is stabilized 10 ms after acting on the switch. If we sample the switch
value every 100 Hz, and record the last four or more switch values in a shift register and
AND these four or more recent switch results, bouncing on the mechanical switch will be
filtered out and the AND gate will give us a clean signal with one edge for every press of
the switch. The fixed frequency of the global clock that the FPGA uses, which is generated
by the Nexys3 board, is 100 MHz. We should design a clock divider circuit using an N-bit
counter that will divide the 100 MHz clock into a clock rate suitable for switch debouncing
(approximately to 100 Hz by dividing it by 220 times). Note that an n-bit counter divides the
frequency of a clock signal by 2n times. Design a switch debouncing circuit in VHDL using
a 4-bit shift register and an AND gate. The output of this circuit should control your counter.

A switch debouncing circuit example

Also eight slide switches are available on the FPGA board. When closed (ON), each switch
pulls the connected pin of the FPGA to ground through a resistor. The pin is pulled high
through a resistor when the switch is open (OFF). You will use eight of these switches as
the 8 bit input to be parallel loaded to your counter. The format of the 8-bit input should be
in BCD. You do not need to implement debouncer circuits for them.

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8-bit Up-Counter
Your counter should count up and down in two-digit BCD format. It should count from 00
(0000-0000) to 99 (1001-1001) as a push-button is pressed and released. You can
achieve this by implementing a BCD up/down counter. Alternatively, you can design a 7
or 8 bit binary up/down counter. Then, connect a binary to BCD converter to its outputs.
In this case, you can enter input from slide switches in the binary format. Also, you should
not worry about binary values exceeding 99. A behavioral VHDL code for an up-counting
single digit BCD counter is given below. You can modify this code to realize the desired
BCD counter in this lab.

A behavioral VHDL code for an up-counting 8-bit binary counter is given below. You can
modify this code to realize the desired counting function.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity my_count8 is
port( D: in std_logic_vector(7 downto 0);
Q: out std_logic_vector(7 downto 0);
CLK, clk_enable, RESET : in std_logic );
end count4;

ARCHITECTURE behavioral OF my_count8 IS

SIGNAL count : std_logic_vector (7 downto 0);
BEGIN

my_counter: PROCESS(clk, reset)

BEGIN

IF (reset = '0') THEN

count <= (others => '0');
--This assigns ‘0’ to all bits of count signal. “Others” means other values of count
--This is a generic usage since signal assignment becomes independent of the
--vector size of count. i.e. you do not need to change this line if count becomes 16-bit wide
elsif(clock'event and clock='1') then
if clock_enable='1' then
count <= count + “00000001”;
else count <= count;
end if;
end if;
END PROCESS my_counter;
Q <= count; -- assign count signal to output
END behavioral;

Writing the Counter Content to the LED Display

As done before in Lab 5, the contents of the counter are displayed on the four-digit-seven-
segment LED display on the FPGA board using Digit0 and Digit1. In order to do that, a
BCD-to-7-segment decoding is necessary. After adding the decimal point bit, 8 bits are
required to show each digit. We want to display two digits. Thus, your design should have
16 bit output. The first 8 bit (least significant digit) is connected to Digit0. The second 8 bit

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(most significant digit) is connected to Digit1. The entity of your design should have two
sets of 8-bit output ports. These outputs are connected to the seven-segment display
driver, nexys3_sseg_driver.vhd, given and explained in Lab 5.

Overall Design
As explained above your design accepts 8-bit input, named pdata, one clock signal named
board_clk, three control signals named pload, upcount and downcount and generate 8-bit
lowdig output and 8-bit highdig output. Then, these outputs will be inputs to the design
given in the nexys3_sseg_driver.vhd file using structural vhdl style. This design will
generate the SSEG_CA(7 downto 0) and SSEG_AN(3 downto 0) outputs using the clock
signal. Your VHDL code for this design should have the following structure. You should
complete the architecture. Your VHDL code can use structural and/or dataflow and/or
behavioral style VHDL.

-- Synthesizable 2-Digit, parallel loadable up/down BCD Count by pressing push-button switches
-- EE244 class Bogazici University
-- Implemented on Xilinx Spartan VI FPGA chip

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
USE ieee.std_logic_arith.all ;
USE ieee.std_logic_unsigned.all;

entity ee240_bcdcounter is
port (
pdata: in std_logic_vector(7 downto 0);
pload: in std_logic;
upcount: in std_logic;
downcount: in std_logic;
board_clk: in std_logic;
SSEG_CA: out std_logic_vector(7 downto 0);
SSEG_AN: out std_logic_vector(3 downto 0));
end;

architecture arch_BCD_counter of ee240_bcdcounter is

-- pdata(7) comes from slide SW-7 (slide Switch)

-- pdata(6) comes from slide SW-6 (slide Switch)
-- pdata(5) comes from slide SW-5 (slide Switch)
-- pdata(4) comes from slide SW-4 (slide Switch)
-- pdata(3) comes from slide SW-3 (slide Switch)
-- pdata(2) comes from slide SW-2 (slide Switch)
-- pdata(1) comes from slide SW-1 (slide Switch)
-- pdata(0) comes from slide SW-0 (slide Switch)

-- pload comes from BTNL (Push-Button Switch)

-- upcount comes from BTNU (Push-Button Switch)
-- downcount comes from BTND (Push-Button Switch)

-- board_clk comes from the 100 MHz board clock connected to V10

--lowdig(0) is displayed on Digit0 Segment CA

--lowdig(1) is displayed on Digit0 Segment CB

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--lowdig(2) is displayed on Digit0 Segment CC

--lowdig(3) is displayed on Digit0 Segment CD
--lowdig(4) is displayed on Digit0 Segment CE
--lowdig(5) is displayed on Digit0 Segment CF
--lowdig(6) is displayed on Digit0 Segment CG
--lowdig(7) is displayed on Digit0 Segment DP, which is always logic 1

--highdig(0) is displayed on Digit1 Segment CA

--highdig(1) is displayed on Digit1 Segment CB
--highdig(2) is displayed on Digit1 Segment CC
--highdig(3) is displayed on Digit1 Segment CD
--highdig(4) is displayed on Digit1 Segment CE
--highdig(5) is displayed on Digit1 Segment CF
--highdig(6) is displayed on Digit1 Segment CG
--highdig(7) is displayed on Digit1 Segment DP, which is always logic 1

-- lowdig(7 downto 0), highdig(7 downto 0) will be input to the design

-- given in the nexys3_sseg_driver.vhd file using structural vhdl style. This design will generate
-- the SSEG_CA(7 downto 0) and SSEG_AN(3 downto 0) outputs using the clock signal.

end arch_BCD_counter;

Pin Assignment
After successfully completing the design, compilation, ISim simulations and synthesis, you
should show that your design work on the FPGA board. By looking at the manual of the
Nexys3 Board, we can find which FPGA pins are connected to which components. The
following is a list of pin connection we want for this lab and their meanings.

pdata(7) -> T5 Slide SW-7 (Slide Switch)-> T5

pdata(6) -> V8 Slide SW-6 (Slide Switch)-> V8
pdata(5) -> U8 Slide SW-5 (Slide Switch)-> U8
pdata(4) -> N8 Slide SW-4 (Slide Switch)-> N8
pdata(3) -> M8 Slide SW-3 (Slide Switch)-> M8
pdata(2) -> V9 Slide SW-2 (Slide Switch)-> V9
pdata(1) -> T9 Slide SW-1 (Slide Switch)-> T9
pdata(0) -> T10 Slide SW-0 (Slide Switch)-> T10

pload -> C4 BTNL (Push-Button Switch)-> C4

upcount -> A8 BTNU (Push-Button Switch)-> A8
downcount -> C9 BTND (Push-Button Switch)-> C9

board_clk -> V10 100 MHz board clock -> V10

SSEG_CA<0> -> T17

SSEG_CA<1> -> T18
SSEG_CA<2> -> U17
SSEG_CA<3> -> U18
SSEG_CA<4> -> M14
SSEG_CA<5> -> N14
SSEG_CA<6> -> L14
SSEG_CA<7> -> M13

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SSEG_AN<0> -> N16

SSEG_AN<1> -> N15
SSEG_AN<2> -> P18
SSEG_AN<3> -> P17

The .ucf file should be like this.

#
# Pin assignments for the Nexys3 Board.
#
net pdata<7> loc=T5; # Slide SW-7 (Slide Switch)
net pdata<6> loc=V8; # Slide SW-6 (Slide Switch)
net pdata<5> loc=U8; # Slide SW-5 (Slide Switch)
net pdata<4> loc=N8; # Slide SW-4 (Slide Switch)
net pdata<3> loc=M8; # Slide SW-3 (Slide Switch)
net pdata<2> loc=V9; # Slide SW-2 (Slide Switch)
net pdata<1> loc=T9; # Slide SW-1 (Slide Switch)
net pdata<0> loc=T10; # Slide SW-0 (Slide Switch)

net pload loc=C4; # BTNL (Push-Button Switch)

net upcount loc=A8; # BTNU (Push-Button Switch)
net downcount loc=C9; # BTND (Push-Button Switch)

net board_clk loc=V10; # 100 MHz board clock

Net SSEG_CA<0> LOC=T17 | IOSTANDARD=LVCMOS33; # Connected to CA

Net SSEG_CA<1> LOC=T18 | IOSTANDARD=LVCMOS33; # Connected to CB
Net SSEG_CA<2> LOC=U17 | IOSTANDARD=LVCMOS33; # Connected to CC
Net SSEG_CA<3> LOC=U18 | IOSTANDARD=LVCMOS33; # Connected to CD
Net SSEG_CA<4> LOC=M14 | IOSTANDARD=LVCMOS33; # Connected to CE
Net SSEG_CA<5> LOC=N14 | IOSTANDARD=LVCMOS33; # Connected to CF
Net SSEG_CA<6> LOC=L14 | IOSTANDARD=LVCMOS33; # Connected to CG
Net SSEG_CA<7> LOC=M13 | IOSTANDARD=LVCMOS33; # Connected to DP

Net SSEG_AN<0> LOC=N16 | IOSTANDARD=LVCMOS33; # Connected to AN0

Net SSEG_AN<1> LOC=N15 | IOSTANDARD=LVCMOS33; # Connected to AN1
Net SSEG_AN<2> LOC=P18 | IOSTANDARD=LVCMOS33; # Connected to AN2
Net SSEG_AN<3> LOC=P17 | IOSTANDARD=LVCMOS33; # Connected to AN3

Preparation (Prelab)
For Frequency Divider and Debouncer Circuit
• Write a VHDL code for these components.
• Run ISim and verify that they function as expected by running test sequences.

For parallel loadable 2-digit up/down BCD counter

• Write a VHDL code for this component.
• Run ISim and verify that it functions as expected by running a few test sequences.

For the BCD-to7-Segment Conversion

• Use the BCD-to_seven_segment code used before.

For the Overall Design

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• Combine the design components under ee240_bcdcounter architecture and run ISim
on it and verify that it functions as expected by running a few test sequences.

In Lab
• Use Xilinx ISE to synthesize the design based on Xilinx Spartan VI family. Use
either the given ucf file or enter pins manually to make pin assignment.
• Generate the bit file and upload it to your FPGA.
• On the hardware show that your design works.
• See if the LEDs show what you expect every time you apply your data using Slide
and push-button switches.

References
[1] "Nexys 3 Manual." (accessed 18 March 2021).