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Exp 9

The document details Experiment-9 on Asynchronous Counters, including the design and implementation of various types of counters using Verilog code. It covers a negative edge triggered JK flip-flop, a modulo 16 asynchronous counter, a BCD counter, and a down counter, along with their respective constraints files. Additionally, it provides a brief overview of how a ripple counter operates, highlighting its counting mechanism and potential timing issues.

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8 views7 pages

Exp 9

The document details Experiment-9 on Asynchronous Counters, including the design and implementation of various types of counters using Verilog code. It covers a negative edge triggered JK flip-flop, a modulo 16 asynchronous counter, a BCD counter, and a down counter, along with their respective constraints files. Additionally, it provides a brief overview of how a ripple counter operates, highlighting its counting mechanism and potential timing issues.

Uploaded by

michelfarday66
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment-9: Asynchronous Counters

Group Member Details:


Chandra Sekhar,23ec01021

Roshan Raghavendra ,23ec01008

Part 1: Negative edge triggered JK flip-flop with Clear and Preset


Verilog code for JK Flip-flop:

DigitalElectronicCircuitsLaboratory(EC2P004) 1
Experiment-9: Asynchronous Counters

constraints file for JK Flip-flop:

Part 2: Modulo 16 Asynchronous Counter Using JK


flip-flops

Verilog code for modulo 16 Asynchronous Counter:

DigitalElectronicCircuitsLaboratory(EC2P004) 2
Experiment-9: Asynchronous Counters

constraints file:

DigitalElectronicCircuitsLaboratory(EC2P004) 3
Experiment-9: Asynchronous Counters

Part 3: BCD Counter


Verilog code for BCD Counter:

constraints file:

DigitalElectronicCircuitsLaboratory(EC2P004) 4
Experiment-9: Asynchronous Counters

Part 4: Down Counter

Verilog code for Down Counter:

constraints file:

DigitalElectronicCircuitsLaboratory(EC2P004) 5
Experiment-9: Asynchronous Counters

Bonus-1
Verilog code for :

constraints file:

DigitalElectronicCircuitsLaboratory(EC2P004) 6
Experiment-9: Asynchronous Counters

Brief description of ripple counter:


An asynchronous modulo-16 counter is a specific type of digital counter that counts modulo-
16, meaning it counts from 0 to 15 (or 0000 to 1111 in binary) and then resets back to 0.
Here's a brief overview of how an asynchronous modulo-16 counter works: The counter
consists of four flip-flops connected in cascade, each
representing one bit of the counter. Since we are counting modulo-16, we need four flip-flops
to represent the 16 possible states.

Unlike synchronous counters where all flip-flops are clocked simultaneously, in an


asynchronous counter, each flip-flop's clock input is driven by the output of the
previous flip-flop. This means that the clock signal ripples through the flip-flops, hence the
name "ripple counter".

As the clock signal propagates through the flip-flops, the counter increments its
count by one on each clock edge. The binary count represented by the outputs of the flip-flops
follows a natural sequence from 0000 to 1111, which corresponds to decimal 0 to 15.
When the count reaches 15 (1111 in binary), the next clock pulse will cause the
counter to reset back to 0 (0000 in binary), completing one full counting cycle. This is the
modulo-16 operation, where the counter resets after reaching the maximum
count of 15.As with any asynchronous counter, there is a propagation delay associated with
the transition of the clock signal through the flip-flops. This delay may cause timing issues,
especially at higher clock frequencies, and can affect the maximum achievable counting
speed.

DigitalElectronicCircuitsLaboratory(EC2P004) 7

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