p-n junction: A p-n junction is formed when a p-type and an n-type semiconductor are

brought into intimate contact. The p-n junction, in addition to being a device that is used in
many applications, is the basic building block for other semiconductor devices.
Basic fabrication steps:
Most modern p-n junctions are fabricated using "planar technology." This technology includes
oxidation, lithography, ion implanation, and metallization.
Oxidation
In the fabrication of a p-n junction (Fig. l), the SiO, film is used to define the junction area.
There are two SiO growth methods, dry and wet oxidation, depending on whether dry oxygen
or water vapor is used. Dry oxidation is usually used to form thin oxides in a device structure
because of its good Si-SiO, interface characteristics, whereas wet oxidation is used for thicker
layers because of its higher growth rate. Figure la shows a section of a bare Si wafer ready for
oxidation. After the oxidation process, a SiO, layer is formed all over the wafer surface. For
simplicity, Fig. lb shows only the upper surface of an oxidized wafer.
Lithography
Photolithography is used to define the geometry of the p-n junction. After the formation of SiO,
the wafer is coated with an ultraviolet (UV)-light sensitive material called a photoresist,
which is spun on the wafer surface by a high-speed spinner. After spinner (Fig. lc), the wafer is
baked at about 80-100°C to drive the solvent out of the resist and to harden the resist for
improved adhesion. Figure Id shows the next step, which is to expose the wafer through a
patterned mask using an UV-light source. The exposed region of the photoresist-coated wafer

Fig. 1 (a) A bare n-type Si wafer. (b) An oxidized Si wafer by dry or wet oxidation. (c) Application of
resist. (d) Resist exposure through the mask.
undergoes a chemical reaction depending on the type of resist. The area exposed to light
become polymerized and difficult to remove in an etchant." The polymerized region remains
when the wafer is placed in a developer, whereas the unexposed region (under the opaque
area) dissolves and washes away. Figure 2a shows the wafer after the development. The wafer
is again baked to 120"-180°C for 20 minutes to enhance the adhesion and improve the
resistance to the subsequent etching process. Then, an etch using buffered hydrofluoric acid
(HF) removes the unprotected SiO, surface (Fig. 2b). Last, the resist is stripped away by a
chemical solution or an oxygen plasma system. Figure 2c shows the final result of a region
without oxide (a window) after the lithography process. The wafer is now ready for forming
the p-n junction by a diffusion or ion-implantation process.
Diffusion and Ion Implantation
In the diffusion method, the semiconductor surface not protected by the oxide is exposed to a
source with a high concentration of opposite-type impurity, The impurity moves into the
semiconductor crystal by solid-state diffusion. In the ion-implantation method, the intended
impurity is introduced into the semiconductor by accelerating the impurity ions to a high-
energy level and then implanting the ions in the semiconductor. The SiO, layer serves as
barrier to impurity diffusion or ion implantation. After the diffusion or implantation process,
the p-n junction is formed as shown in Fig. 2d. Due to lateral diffusion of impurities or lateral
straggle of implanted ions, the width of the p region is slightly wider than the window
opening.
Metallization
After diffusion or ion-implantation process, a metallization process is used to form ohmic
contacts and interconnections (Fig. 2e). Metal films can be formed by physical vapor
deposition and chemical vapor deposition. The lithography process is again used to define the
front contact which is shown in Fig. 2f. A similar metallization step is done on the back
contact without using a lithography process. With the completion of the metallization, the p-n
junctions become functional.
BJT: The bipolar junction transistor is a three-layer semiconductor device consisting of either
two n- and one p-type layers of material or two p- and one n-type layers of material. The
former is called an npn transistor, while the latter is called a pnp transistor. Both are shown
in Fig. 3 with the proper dc biasing. The terminals have been indicated by the capital letters E
for emitter, C for collector, and B for base. The term bipolar reflects the fact that holes and
electrons participate in the injection process into the oppositely polarized material.

(a) (b)
Fig. 3 Types of transistors: (a) pnp; (b) npn.

Transistor construction
The emitter layer is heavily doped, the base lightly doped, and the collector only lightly doped.
The outer layers have widths much greater than the sandwiched p- or n-type material. For the
transistors shown in Fig. 3 the ratio of the total width to that of the center layer is
0.150/0.001=150:1. The doping of the sandwiched layer is also considerably less than that of
the outer layers (typically, 10:1 or less). This lower doping level decreases the conductivity
(increases the resistance) of this material by limiting the number of “free” carriers.
Transistor operation
The basic operation of the transistor will now be described using the pnp transistor. The
operation of the npn transistor is exactly the same if the roles played by the electron and hole
are interchanged. In Fig. 3.3 the pnp transistor has been drawn without the base-to-collector
bias. The depletion region has been reduced in width due to the applied bias, resulting in a

heavy flow of majority carriers from the p- to the n-type material. Let us now remove the
base-to-emitter bias of the pnp transistor as shown in Fig. 3.4. The flow of majority carriers is
zero, resulting in only a minority-carrier flow, as indicated in Fig. 3.4. In summary, therefore:
One p-n junction of a transistor is reverse biased, while the other is forward biased.
In Fig. 3.5 both biasing potentials have been applied to a pnp transistor, with the resulting
majority- and minority-carrier flow indicated. Note in Fig. 3.5 the widths of the depletion
regions, indicating clearly which junction is forward-biased and which is reverse-biased. As
indicated in Fig. 3.5, a large number of majority carriers will diffuse across the forward-
biased p-njunction into the n-type material. The question then is whether these carriers will
contribute directly to the base current IBor pass directly into the p-type material. Since the
sandwiched n-type material is very thin and has a low conductivity, a very small number of
these carriers will take this path of high resistance to the base terminal. The magnitude of the
base current is typically on the order of microamperes as compared to milliamperes for the
emitter and collector currents. The larger number of these majority carriers will diffuse
across the reverse-biased junction into the p-type material connected to the collector terminal
as indicated in Fig. 3.5. The reason for the relative ease with which the majority carriers can
cross the reverse-biased junction is easily understood if we consider that for the reverse-
biased diode the injected majority carriers will appear as minority carriers in the n-type
material. In other words, there has been an injectionof minority carriers into the n-type base
region material. Combining this with the fact that all the minority carriers in the depletion
region will cross the reverse-biased junction of a diode accounts for the flow indicated in Fig.
3.5. Applying Kirchhoff’s current law to the transistor of Fig. 3.5 as if it were a single node, we
obtain

and find that the emitter current is the sum of the collector and base currents. The collector
current, however, is comprised of two components—the majority and minority carriers as
indicated in Fig. 3.5. The minority-current component is called the leakage current and is
given the symbol ICO (IC current with emitter terminal Open). The collector current, therefore,
is determined in total by Eq. (3.2).

Common-emitter configuration
The most frequently encountered transistor configuration appears in Fig. 3.13 for the pnp and
npn transistors. It is called the common-emitter configuration since the emitter is common or
reference to both the input and output terminals (in this case common to both the base and
collector terminals). Two sets of characteristics are necessary to describe fully the behavior of
the common-emitter configuration: one for the input or base-emitter circuit and one for the
output or collector-emitter circuit. Both are shown in Fig. 3.14.
The emitter, collector, and base currents are shown in their actual conventional current
direction. The current relations are
IE = IC + IB (i)
and IC= αIE (ii)
For the common-emitter configuration the output characteristics are a plot of the output
current (IC) versus output voltage (VCE) for a range of values of input current (IB). The input
characteristics are a plot of the input current (IB) versus the input voltage (VBE) for a range of
values of output voltage (VCE).
The active region for the common-emitter configuration is that portion of the upper-right
quadrant that has the greatest linearity, that is, that region in which the curves for IB are
nearly straight and equally spaced. In Fig. 3.14a this region exists to the right of the vertical
dashed line at VCEsat and above the curve for IB equal to zero. The region to the left of VCEsat is
called the saturation region. In the active region of a common-emitter amplifier the collector-
base junction is reverse-biased, while the base-emitter junction is forward-biased.
Note on the collector characteristics of Fig. 3.14 that IC is not equal to zero when IB is zero.
We have IC = αIE + ICBO
Or, IC = α(IC+IB) + ICBO
Or, IC(1- α) = α(IB + ICBO)
Or, = +
( ) ( )

Chapter-3

Crystal growth technology:

The two most important semiconductors for discrete devices and integrated circuits are
silicon and gallium arsenide. In this chapter we describe the common techniques for growing
single crystals of these two semiconductors. The basic process flow from starting materials to
polished wafers is shown in Fig. 1. The starting materials, silicon dioxide for a silicon wafer
and gallium and arsenic for a gallium arsenide wafer, are chemically processed to form a
high-purity polycrystalline semiconductor from which single crystals are grown. The single-
crystal ingots are shaped to define the diameter of the material and sawed into wafers. These
wafers are etched and polished to provide smooth, specular surfaces on which devices will be
made.
A technology closely related to crystal growth involves the growth of single-crystal
semiconductor layers on a single-crystal semiconductor substrate. This is called epitaxy, from
the Greek words epi (meaning "on") and taxis (meaning "arrangement"). The epitaxial layer
and the substrate materials may be the same, giving rise to homoepitaxial.
SILICON CRYSTAL GROWTH FROM THE MELT
The basic technique for silicon crystal growth from the melt, which is material in liquid form,
is the Czochralski technique. A substantial percentage (> 90%) of the silicon crystals for the
semiconductor industry is prepared by the Czochralski technique, and virtually all the silicon
used for fabricating integrated circuits is prepared by this technique.
Starting Material
The starting material for silicon is a relatively pure form of sand (SiO,) called quartzite. This is
placed in a furnace with various forms of carbon (coal, coke, and wood chips). Although a
number of reactions take place in the furnace, the overall reaction is
( ) + ( )→ ( ) + ( ) + ( ), (1)
This process produces metallurgical-grade silicon with a purity of about 98%. Next, the silicon
is pulverized and treated with hydrogen chloride (HCI) to form trichlorosilane (SiHC13):
°
( )+ 3 ( ) ⎯⎯ ( )+ ( ). (2)
The trichlorosilane is a liquid at room temperature (boiling point 32OC); Fractional
distillation of the liquid removes the unwanted impurities. The purified SiHCI, is then used in a
hydrogen reduction reaction to prepare the electronic-grade silicon (EGS):
( )+ ( )→ ( ) + 3 ( ). (3)
This reaction takes place in a reactor containing a resistance-heated silicon rod, which serves
as the nucleation point for the deposition of silicon. The EGS, a polycrystalline material of high
purity, is the raw material used to prepare device-quality, single-crystal silicon. Pure EGS
generally has impurity concentrations in the parts-per-billion range.