What Is A Multiprocessor?

A multiprocessor is a computer with numerous processors in one unit. At various levels of

solving a problem, the processors of a multiprocessor system may be able to interact and
cooperate. The processors communicate with one another by passing messages or by sharing a
common memory.

Two or more CPUs make up a multiprocessor system. It’s a system that connects two or more
CPUs with memory and I/O equipment. The term “processor” can refer to either a central
processing unit (CPU) or an input-output processor in a multiprocessor (IOP). A system with a
single CPU and one or more lOPs, on the other hand, is usually not considered a multiprocessor
unless the IOP has computational capabilities comparable to a CPU. A multiprocessor system, as
most people understand it, consists of numerous CPUs, with one or more lOPs thrown in for
good measure. Multiprocessors are categorized as MIMD (multiple instruction streams, multiple
data stream) systems, as previously stated.

Characteristics of Multiprocessor
The following are the important characteristics of multiprocessors.

1. Parallel Processing: This requires the use of many processors at the same time. These
processors are designed to do a particular task using a single architecture. Processors are
generally identical, and they operate together to create the effect that the users are the only
individuals who are using the system. In reality, several others are trying to use the system in the
first place.

2. Distributed Computing: In addition to parallel computing, this distributed processing requires the
use of a processor network. Each processor in this network can be thought of as a standalone
computer with the ability to solve problems. These processors are diverse, and each one is
typically assigned to a separate job.

3. Supercomputing: This entails using the quickest machines to address large, computationally
difficult issues. Supercomputers used to be vector computers, but nowadays, most people
accept vector or parallel computing.
4. Pipelining: Besides supercomputing, this is a method that divides a task into multiple subtasks
that must be completed in a specified order. Each subtask is aided by the functional units. The
devices are connected serially, and they all work at the same time.

5. Vector Computing: This is a method that divides a task into multiple subtasks that must be
completed in a specified order. Each subtask is aided by the functional units. The devices are
connected serially, and they all work at the same time.

6. Systolic: Pipelining is similar, but the units are not organized linearly. Systolic steps are often tiny
and numerous, and they are conducted in lockstep. This is more commonly used in specialized
hardware like image or signal processors.

Interconnection Structures for Multiprocessor

Interconnection structure can decide the overall system’s performance in a multi-processor
environment. The processors must be able to share a set of main memory modules & I/O
devices in a multiprocessor system. This sharing capability can be provided through
interconnection structures. The interconnection structures that are commonly used can be given
as follows:
1. Time shared / Common Bus
2. Cross bar Switch
3. Multiport Memory
4. Multistage Switching Network
5. Hypercube System

1. Time-shared (common bus)

In any multiprocessor system, the time-shared common bus interconnection structures provide a

common communication path by connecting all the functional units like I/O processor,

processor, memory unit, etc. The figure below displays a multiprocessor system with a common

communication path (single bus).

 A single bus multiprocessor system

The processor needs the common bus to communicate with a functional unit to transfer data. To
do so, the processor first checks if the bus is available or not. The processor can only use the
common bus if it is free. The processor puts the destination unit address on the common bus, and
the destination unit identifies it. A command is issued to tell the receiver unit what work is to be
done to communicate with a functional unit. The other functional units at that time will be either
busy in internal operations or will sit free, waiting to get the common bus.
We can resolve memory access conflict with methods such as First-In-Out (FIFO) queues, static
& fixed priorities, and daisy chains can be used.

2. Crossbar switch
Crossbar Switch system contains of a number of cross points that are kept at intersections
among memory module and processor buses paths. In each cross point, the small square
represents a switch which obtains the path from a processor to a memory module. Each
switch point has control logic to set up the transfer path among a memory and processor. It
calculates the address which is placed in the bus to obtain whether its specific module is
being addressed. In addition, it eliminates multiple requests for access to the same memory
module on a predetermined priority basis.
Functional design of a crossbar switch connected to one memory module is shown in figure.
The circuit contains multiplexers which choose the data, address, and control from one CPU
for communication with the memory module. Arbitration logic established priority levels to
select one CPU when two or more CPUs attempt to access the same memory. The
multiplexers can be handled by the binary code which is produced by a priority encoder
within the arbitration logic.

A crossbar switch system permits simultaneous transfers from all memory modules because
there is a separate path associated with each module. Thus, the hardware needed to implement
the switch may become quite large and complex.
3. Multiport Memory
Multiport Memory System employs separate buses between each memory module and each
CPU. A processor bus comprises the address, data and control lines necessary to communicate
with memory. Each memory module connects each processor bus. At any given time, the
memory module should have internal control logic to obtain which port can have access to
memory.
Memory module can be said to have four ports and each port accommodates one of the buses.
Assigning fixed priorities to each memory port resolve the memory access conflicts. The
priority is established for memory access associated with each processor by the physical port
position that its bus occupies in each module. Therefore CPU 1 can have priority over CPU 2,
CPU 2 can have priority over CPU 3 and CPU 4 can have the lowest priority.

4. Multistage Switching Network

The 2×2 crossbar switch is used in the multistage network. It has 2 inputs (A & B) and 2
outputs (0 & 1). To establish the connection between the input & output terminals, the control
inputs CA & CB are associated.
 2 * 2 Crossbar Switch

 The input is connected to 0 output if the control input is 0 & the input is connected to 1
output if the control input is 1. This switch can arbitrate between conflicting requests. Only
1 will be connected if both A & B require the same output terminal, the other will be
blocked/ rejected.
 We can construct a multistage network using 2×2 switches, in order to control the
communication between a number of sources & destinations. Creating a binary tree of
cross-bar switches accomplishes the connections to connect the input to one of the 8
possible destinations.
 1 to 8 way switch using 2*2 Switch

 In the above diagram, PA & PB are 2 processors, and they are connected to 8 memory
modules in a binary way from 000(0) to 111(7) through switches. Three levels are there
from a source to a destination. To choose output in a level, one bit is assigned to each of
the 3 levels. There are 3 bits in the destination number: 1st bit determines the output of the
switch in 1st level, 2nd bit in 2nd level & 3rd bit in the 3rd level.
 Example: If the source is: PB & the destination is memory module 011 (as in the figure): A
path is formed from PB to 0 output in 1st level, output 1 in 2nd level & output 1 in 3rd
level.
 Usually, the processor acts as the source and the memory unit acts as a destination in a
tightly coupled system. The destination is a memory module. But, processing units act as
both, the source and the destination in a loosely coupled system.
 Many patterns can be made using 2×2 switches such as Omega networks, Butterfly
Network, etc.

5. Hypercube System
Hypercube (or Binary n-cube multiprocessor)
Structure represents a loosely coupled system made up of N=2n processors interconnected in
an n-dimensional binary cube. Each processor makes a node of the cube. Therefore, it is
customary to refer to each node as containing a processor; in effect it has not only a CPU but
also local memory and I/O interface. Each processor has direct communication paths to n other
neighbor processors. These paths correspond to the cube edges. There are 2 distinct n-bit
binary addresses which can be assigned to the processors. Each processor address differs from
that of each of its n neighbors by exactly one bit position.
 Hypercube structure for n= 1, 2 and 3.
 A one cube structure contains n = 1 and 2n = 2.
 It has two processors interconnected by a single path.
 A two-cube structure contains n=2 and 2n=4.
 It has four nodes interconnected as a cube.
 An n-cube structure contains 2n nodes with a processor residing in each node.
Each node is assigned a binary address in such a manner, that the addresses of two neighbors
differ in exactly one bit position. For example, the three neighbors of the node with address
100 are 000, 110, and 101 in a three-cube structure. Each of these binary numbers differs from
address 100 by one bit value.

Routing messages through an n-cube structure may take from one to n links from a source node
to a destination node.

Inter Processor Communication and Synchronization

Inter Process Communication
Inter process communication (IPC) allows different programs or processes running on a
computer to share information with each other. IPC allows processes to communicate by using
different techniques like sharing memory, sending messages, or using files. It ensures that
processes can work together without interfering with each other. Cooperating processes require
an Inter Process Communication (IPC) mechanism that will allow them to exchange data and
information.
The two fundamental models of Inter Process Communication are:
 Shared Memory
 Message Passing
Figure 1 below shows a basic structure of communication between processes via the shared
memory method and via the message passing method.
An operating system can implement both methods of communication. First, we will discuss the
shared memory methods of communication and then message passing. Communication
between processes using shared memory requires processes to share some variable, and it
completely depends on how the programmer will implement it. One way of communication
using shared memory can be imagined like this: Suppose process1 and process2 are executing
simultaneously, and they share some resources or use some information from another process.
Process1 generates information about certain computations or resources being used and keeps
it as a record in shared memory. When process2 needs to use the shared information, it will
check in the record stored in shared memory and take note of the information generated by
process1 and act accordingly. Processes can use shared memory for extracting information as a
record from another process as well as for delivering any specific information to other
processes.
Figure 1 below shows a basic structure of communication between processes via the shared
memory method and via the message passing method.
Synchronization in Inter Processor Communication
Synchronization is an essential part of inter process communication. It refers to a case where the
data used to communicate between processors is control information. It is either given by the
inter process control mechanism or handled by the communicating processes.
It is required to maintain the correct sequence of processes and to make sure equal access to
shared writable data.
Multiprocessor systems have various mechanisms for the synchronization of resources. Below
are some methods to provide synchronization are as follows −
1. Mutual Exclusion
2. Semaphore
3. Barrier
4. Spinlock
Mutual Exclusion
Mutual Exclusion requires that only a single process thread can enter the critical section one at a
time. This also helps synchronize and prevents the race condition by creating a stable state.
Semaphore
Semaphore is a type of variable that generally controls the access to the shared resources by
several processes. Further, Semaphore is divided into two types as follows:
Binary Semaphore
A binary semaphore is limited to zero or one. It could be used to control access to one resource.
In particular, it can be used to force the same release of an important category in the user code.
Counting Semaphore
Counting semaphore may take any integer value. It could be used to control access to resources
having many instances.
Barrier
A barrier (as evident by its name) does not allow an individual process to proceed unless all the
processes do not reach it. Many parallel languages use it, and collective routines impose barriers.
Spinlock
As evident by its name, a spinlock is a type of lock that prevents processes from operating any
function unless it is available. The processes which are trying to acquire the spinlock wait in a
loop while checking if the lock is available or not. This is also known as busy waiting because
the process is not doing any helpful operation even though it is active.