A HIGHRESOLUTION,STICTIONLESS,

CMOS COMPATIBLE SO1 ACCELEROMETER

WITH A LOW NOISE,LOW POWER, 0.25w CMOS INTERFACE
Babak Vukili Amini, Siavash Pourkamali, and Farrokh Ayazi
School of Electrical and Computer Engineering
Georgia Institute of Technology, Atlanta, GA 30332-0250
Email: [email protected]; Tel: (404) 385-2400; Fax: (404) 894-4700

ABSTRACT axis with respect to its frame (X=Y-Z) in response to an

external acceleration (aaJ. The proof mass is suspended
The implementation and characterization of a high by four tethers that act as mechanical springs and the
sensitivity silicon-on-insulator (Sol) capacitive surrounding air imposes damping (0) on the structure.
microaccelerometer with sub-25pg resolution is presented.
The in-plane accelerometers were fabricated on 40ym thick aexr
SO1 substrates using a two-mask, dry-release low
temperature process comprising of three plasma etching
steps. The fabricated devices were interfaced with a high
resolution, low noise and low power switched-capacitor
integrated circuit (IC) fabricated in a 2.5V 0.25pm N-well
CMOS process. The measured sensitivity is 0.2pF/g and
the output noise floor is ZOpg/dHz. The total power
consumption is 3mW.
I. INTRODUCTION
Silicon-on-insulator wafers have become the substrate of
choice for many high-performance MEMS devices such as Figure I . Simplified schematic of a differential MEMS
multi-axis optical micromirrors [I]. Low cost, small accelerometer.
footprint accelerometers with high sensitivity, high
The dynamic behavior of the sensor is interpreted by the
resolution and low power are needed in a number of
Newton's second law of motion:
applications including microgravity surveys, geophysical
sensing, robotics, vibration analysis, GPS-augmented
navigation, and spacecraft guidance/stahilization [2]. The
use of thick SO1 substrates in implementing lateral The effective spring constant (Ked of the accelerometer is
capacitive accelerometers has the advantage of increased expressed by:
mass compared to the polysilicon surface micromachined
devices, which results in reduced Brownian noise floor for Kef = KmechoHid - Ke/ectrrcoI m1 ('1
these devices. However, bulk silicon accelerometers are The mechanical and electrical stiffness of the structure are
typically limited by the electronic noise floor, which can be given by:
improved by increasing the sensitivity (AC/g) of the
micromachined device. This usually requires an increase in
the capacitive area and a reduction in the stiffness of the
device, which in turn increases the possibility of stiction.
In this paper, we present the implementation of 40pm-thick
high sensitivity silicon capacitive accelerometers on low-
resistivity SO1 substrates using a backside dry release where E, is the Young's modulus of silicon in the sense
process that eliminates stiction along with the need for direction; h, w and I are the height, width and length of the
perforating the proof mass. A solid proof mass with no tethers, respectively; Cs is the half of the rest capacitance in
perforations results in a smaller footprint for the sensor and between the proof mass fingers and the sense electrodes
an improved mechanical design. The fabricated with an initial gap spacing of d; the applied voltage to sense
accelerometers were interfaced using a low noise and low capacitors is 0.5Vdd.The accelerometers are designed such
power switched-capacitor readout IC implemented in 2.5V that K ~ l e c , , j ~ ~ i ~ Q Y mThe
s r h oBrownian
n j ~ ~ / . noise equivalent
0.25pm CMOS. The interface IC consumes 3mW of power. acceleration (BNEA) is expressed by:
11. ACCELEROMETER
DESIGN
The simplified schematic of a differential MEMS
accelerometer is shown in Fig. 1. The accelerometer
consists of a proof mass (w
that moves along the sense The air-damping coefficient D is formulated as [6,7]:

0-7803-8265-X/04/$17.00 02004 IEEE. 512

 The wafer is flipped and the top layer is patterned all the
way through the thickness of the device layer,. leaving
behind the suspended structure (capacitive gaps=2pm).
where n is the total number of the sense electrodes and pef The devices were fabricated in low resistivity (<O.OlR.cm)
is the effective viscosity of air. We have considered that the SO1 wafers. Since accelerometers are released from the
length of the electrodes (lJ is larger than the height of the backside, no perforation in the proof mass is needed,
electrodes (hJ. The circuit noise equivalent acceleration resulting in a higher mass value and better mechanical
(CNEA) will depend on the capacitive resolution of the noise specification compared to the perforated shucture
interface IC and the sensitivity of the accelerometer: with same dimensions that are fabricated without backside
etching. Figure 3 shows the SEM of a fabricated 401m
Gc(min) thick accelerometer and Fig. 4 is the close-up view of the
CNEA = -
S electrode and tether area.

m+
where Sis the sensitivity of the differential accelerometer:
-Buried
Oxide
Backside silicon etching
Finally, the total noise equivalent acceleration (TNEA) of
the accelerometer is expressed as: '

TNEA = J B N E A ~+ C N E A ~ [g] (9)

Bachide buried oxide etching

In a lateral SO1 accelerometer, capacitive gaps are created

using the Deep Reactive Ion Etching (DRIE) process. Device patterning and release
Since the maximum achievable aspect ratio (AR) in DRIE
is typically limited to 25-30:1, increasing the thickness of Figure 2. Sensorfabrication processflow on SOI.
the SO1 will deteriorate the sensitivity of the device. In ow
design, we chose a 40bm thick SO1 substrate to reduce the
Brownian noise floor of our accelerometers to less than
I!~gi(Hz)~-'and make the CNEA the resolution-limiting
mechanism. In order to improve the sensitivity and hence
reduce the CNEA, the number of sense fingers must be
increased and the effective stiffness must he reduced. This
will in turn increase the susceptibility of the device to
stiction during the release step. Therefore, processing
techniques that reduce this susceptibility while maintaining
high-sensitivity in a minimum area are of interest.
Table 1 shows the specifications of the MEMS SO1 Figure 3. SEA4 of the fabricated devices with backside
accelerometers with a solid proof mass. etching; no stiction has been observed.
Table 1. Sensor Specifications
I Proof mass dimensions I 4mmx3mmx40~m I
Proof mass

Capacitive gap 2 p
Quality factor 0.3
Resonance frequency 1.5Mz

Figure 4. SEMof the sense electrodes and tether area

It should be mentioned that, our attempt to release high
sensitivity SO1 accelerometers with very compliant
perforated proof mass from the front-side using liquid HF
resulted in severe stiction between the proof mass and the
handle silicon layer. Figure 5 illustrates stiction in a front-

573
side wet-released device, which could not be avoided even
by critical point drying after the wet release. In contrast, the
backside dryreleased devices do not suffer from stiction at
all and have solid proof mass with no perforations.
. .
I Stuck electrode I .
.........
.........
..
.....................
.
!.ne
.
. . .. . . . . . . . . . . . . . . . . . . . . . . . . .
kW

.......................................

Figure 5. SEMshowing stiction in devices with no backside

etching.
IV. THEACCELEROMETER
INTERFACE
CIRCUIT
The schematic diagram of the accelerometer interface IC is
shown in Fig. 6. A fully- differential programmable-gain
switched-capacitor (SC) charge amplifier was designed to
sense the capacitance changes due to the external
acceleration. The interface IC was fabricated in a 0.25pm
CMOS process operating from a single 2.SV supply and
was wire-bonded to the accelerometer chip. A low power
consumption of 3mW including on-chip multiphase clock
generator for data sampling circuit bas been achieved. The
effective die area is about lmm2 including amplification
and reference capacitance banks. In order to reduce the
CNEA and improve the dynamic range, low frequency
noise and offset reduction techniques, i.e., correlated
double sampling (CDS) and optimized transistor sizing
were deployed. Moreover, the filly differential input- Figure 8. Fully differential IN3folded-cascode OTA.
output scheme would reduce the background common
mode noise signals. The input stage of the OTA is designed with optimized-
dimension PMOS transistors to decrease the inherent
.............. ,-__...._______...._______ flicker noise and thermal noise of the amplifier. Long
CMOS switches are used to reduce the clock feedthrough
and appropriate delayed clocks and their complements are
generated to reduce charge injection of switches. The chip
microphotograph is shown in Fig. 9.

I MEMS-IC hterfacr I SC Amplifier

I......-------J-....------......-------!

Figure 6. CDS-compensated SC charge amplifer.

As shown in Fig. 7 , a spot noise of -80dBm was measured
at lkHz with lOHz resolution bandwidth (RBW), which
shows a lOdB suppression of the l/f noise compared to the
circuit without CDS. Gain and reference capacitor
multiplexers have been used to provide the ability of 2mm
interfacing accelerometers with different sensitivities and Figure 9. Chip photograph.

574
V. TESTRESULTS VI. CONCLUSION
The fabricated SO1 accelerometers were wirebonded to the A new SO1 accelerometer fabrication process suitable for
interface IC and tested under static and dynamic high sensitivity devices has been introduced. The process
accelerations. Figure IO shows the static response of the flow is very simple compared to some other mixed-mode
system to acceleration in the k l g range (applied using a fabrication technologies that use regular silicon substrates.
dividing head) for the maximum amplifier gain of 0.5Vig. The devices were interfaced with a sampled data front-end
IC. The test results indicate that discrete-time analog signal
processing is still one of the best candidates for high
precision instmmentation systems. The designed circuit
was able to reduce the low frequency noise by IOdB, which
would be difficult to achieve in a continuous version.
ACKNOWLEDGEMENTS
The authors would like to thank National Semiconductor
Corporations for their generous support and Mohammad
I) I
-1 4.75 4.5 4.25 0 0.25 0.5 0.75 1
Zaman for his contributions.
Acceleration (g)
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Figure 1 1 . Dynamic output response of the SOI

accelerometer to a 5OHz, lgpeak sinusoidal acceleration.
The measured characteristics of the readout interface IC
with the SO1 accelerometer are summarized in Table 2.
Table 2. Measured MEMS+IC specificafions