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16

SUB-MICRO-GRAVITY CAPACITIVE SO1 MICROACCELEROMETERS

B. Vakili Amini, R. Abdolvand, and F. Ayazi
Integrated MEMS laboratory
Georgia Institute of Technology, Atlanta, GA 30332-0250
Email: [email protected] Tel: (404) 385-6693 Fax: (404) 385-6650

ABSTRACT the interface architecture results in a generic front-end with

significant reduction in the electronic die size. The front-end
The implementation and preliminary characterization of
IC i s implemented in the 2.5V 0.25 m 2P5M N-well
a new in-plane capacitive microaccelerometer with &-
CMOS process from National Semiconductor. Correlated
micro-gravity resolution (<200ng/.\IHz) and very high double sampling scheme (CDS) is used for strong
sensitivity ( 15pFig) is presented. The accelerometers are suppressiori of the low-frequency flicker noise and offset.
fabricated in thick ( 100 m) silicon-on-insulator (SOI)
substrates using a 2-mask fully-dry-release process that
provides large seismic mass ( 10milli-g), reduced
capacitive gaps, and reduced in-plane stiffness. The
fabricated devices were interfaced to a high resolution
switched-capacitor CMOS IC that eliminates the need for
area-consuming reference capacitors. The measured
sensitivity is 83mVimg (17pFig) and the output noise floor
is -9 1dBm/Wz at 1OHz (corresponding to an acceleration
resolution of 170ng/dHz). The IC consumes 6mW power
I.I’
‘
and measures 0.65mm2 core area.
Keywords: MEMS, Capacitive SO1 Accelerometers, Fig 1. Schematic diagram of the fully differential
capacitive SO1 accelerometer with extra seismic mass
CMOS Interface IC, Nano-Gravity Measurement
OPERATING MECHANISM AND DESIGN
INTRODUCTION
Sensor target specifications are listed in Table 1. The
Sub-micro-gravity accelerometers are used for accelerometers have been designed to achieve the goal
measurement of very small vibratory disturbances on objectives for open loop operation in air.
platforms installed on earth, space shuttles, and space
Table 1. Target sensor requirements
stations as well as geophysical sensing and earthquake
detection. However, the available systems are bulky,
complex and expensive, and consunie a lot of power [I].
100d3
We had previously presented 40 m thick SO1
accelerometers with 20 g/dHz resolution and sensitivity in
uality factor
the order of 0.2pFig [Z]. In this work, through innovation in
SO1 thickness
process and IC design, the resolution and sensitivity of the
dry-relcased SO1 accelerometers were each improved by Proof mass size I5 ~ x 7 ”
lOOx to achieve, for the first time, deep sub-micro-g overall sensor size 1 7mmx7mm
resolution in a small footprint (<0.5cm2). The figure-of- Mass I 1Omillinam
merit, defined as the ratio of the device sensitivity to its The Brownian noise equivalent acceleration is
mechanical noise floor, is improved by increasing the solid expressed as
seismic mass through saving some part of the handle layer
attached to the proof mass (as shown in Fig. 1). Also,
capacitive gap sizes are reduced through deposition of a
layer o f doped LPCVD poly silicon, which relaxes the
trench etching process and allows for higher aspect ratios. where is the Boltzmann constant, is the absolute
Moreovcr, the sense capacitance is split into four identical temperature, w is the accelerometer s natural angular
sub-capacitances in a fully symmetric and differential frequency (first flexural mode), and is the mechanical
manner (two increasing and two decreasing). Hence, the quality factor, lncreasing the mass and reducing the air
referencc capacitor is absorbed in the sense capacitance of damping improves this mechanical noise floor. However,
the accelerometer without compromising the sensitivity of reducing the damping increases the possibility of resonance
the device or increasing area (Fig, 1). The proof mass is tied (high- ) and sensitivity to higher order modes, which is not
to a constant voltage source at all times and is never desirable. Another limiting factor is the circuit noise
switched. By eliminating the need for reference capacitors, equivalent acceleration C that depends on the
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capacitive resolution of the interface IC (ACM,~)and the

capacitive sensitivity of the accelerometer (SI:

The design objective is to minimize the Brownian noise

equivalent acceleration (BNEA) and to maximize the static
sensitivity (S, while satisfying process simplicity and size
limitations. The proposed fabrication process enables
increase of the seismic mass (to suppress the B M A ) and
reduction of gap sizes (to increase S and reduce Q),
independently. BNEA is a function o f capacitive gap size Capacltlve Cap Sir8 [micro-meter)

and reduces for larger gaps (Equation 1). Deposited Fig. 4. Quality factor versus capacitive gap size
polysilicon changes the tethers’ thickness as well, which
ACCELEROMETER FABRICATION
causes the mechanical compliance and therefore . the
sensitivity to start increasing for thinner poly layers. As Figure 5 illustrates the 2-mask fabrication process flow.
demonstrated in Fig. 2 and Fig. 3, a capacitive gap size in It begins with growing a thick thermal silicon oxide on a
between 4 to Xpm satisfies the BNEA and S requirements for low resistivity thick,SOI wafer, The oxide layer is patterned
the target accelerometer. However, the Q should be on the both sides of the wafer to form the DRIE mask (Fig.
examined to guarantee the accelerometers are in over- 5.a). This will prevent further lithography step after the
damped region (Fig. 4). Since the seismic mass is really device layer is etched to define the accelerometer structure.
large (10’s of milligram) and the accelerometer is very Trenches are etched on the front side. A layer of LPCVD
compliant, the device is vulnerable to damage caused by polysilicon is deposited and doped uniformly to reduce the
mechanical shock. Hence, proper shock stops and deflection capacitive gap size (Fig. 5.b). A blanket etch step removes
limiters should be devised to protect the accelerometer and the polysilicon at the bottom of trenches and provides
avoid non-linear effects caused by momentum of the off- isolation between bonding pads and fingers. The handle
plane center of mass, ANSYSB simulation predicts the first layer is then etched down to the buffer oxide (BOX) from
mode shape (in-plane flexural) to occur at 180Hz. and the backside. A portion of handle layer on the backside of the
next mode shape (out-of-plane motion) to occur at 13OOHz, accelerometer proof mass will remain intact to add
which is well above the in-plane motion. substantial amount of mass.

0 351

Oxide growlh and panemlna,Top srde ORIE

I -
L P C W pol~silicond e p ~ r l t l o n

Capacmve Gap 5121 (micrometer)

Fig. 2. BNEA versus capacitive gap IT71Top side poly b l a n k e t etch, Backside

ORIE, ICP Oxide eteh release

Fig. 5. Fabrication process flow

At the end, the BOX is dry etched in an ICP and the device
is released (Fig. 5.c). This fully-dry process is key to the
high-yield fabrication of extremely compliant structures
with small gaps without experiencing stiction problems. The
SEM picture of a 7mmx7mm microaccelerometer in 120pm
thick SO1 substrate is shown in Fig. 6. The backside of this
device, showing extra seismic mass, is illustrated in Fig. 7.
The proof mass is solid with no perforation that maximizes
Capacluve Gap Size (micrometer)
the sensitivity and minimizes the mechanical noise floor per
Fig. 3. Static sensitivity versus capacitive gap size unit area.

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1NTERFACE CIRCUIT AND TEST RESULTS

The schematic diagram of the accelerometer interface
IC is shown in Fig. IO. The proposed switched-capacitor
(SC) charge amplifier eliminates the need for reference
capacitors and has virtually zero input offset voltage [3].
Previously reported SC charge amplifiers for capacitive
sensors required on-chip reference capacitors to set the
input common mode voltage [4-61. In this architecture, the
reference capacitor is absorbed in the sense capacitance of
the accelerometer without compromising the sensitivity of
the device or increasing area.
~ ~ ~

Fig. 6. SEM picture ofthe accelerometer from top side

Fig. 10. Schematic diagram of the interface circuit

Pig. 7. SEM picture of the backside with extra inasses The interface 1C was fabricated in a 0.25pm CMOS process
operating from a single 2.5V supply and was wire-bonded
4 close up view of the tether and sense electrodes is to the accelerometer chip. A low power consumption of
provided in Fig. 8. While the mask opening size betwcen 6mW has been achieved. The effective die area is about
readout fingers is 9 pm,the gap has been reduced to 5pm by 0.65mm2. In order to reduce the CNEA and improve the
deposition of Zpm polysilicon on the sidewalls (Fig. 9). dynamic range, low frequency noise and offset reduction
techniques, i.e., correlated double sampling (CDS) and
optimized transistor sizing were deployed. Moreover, the
fully differential input-output scheme would reduce the
background common mode noise signals. The measured
sensitivity is &3mV/mg and the interface IC output noise
floor is -9ldBmiHz at IOHz, corresponding to an
acceleration resohtion of 17OngidHz (Fig.,1 1).

.. .
. . : <&.e H i
.
..................................................
. .
. . .
...................................... . . :............
. . . .
..... . . ... . .. ..... . . ...
Fig. 8. Close-up, of the tether and electrodes (top view)
showing no residual stress

Fig. 11. IC output noise spectrum

Dynamic response of the accelerometer to an external
acceleration of 16mg (peak) in a 0.46Hz bandwidth is
shown in Fig.12. Due to extremely high sensitivity of the
accelerometer, the device picks up any external vibration of
Fig. 9. Gap sizc reduction by polysilicon deposition the test setup (and hence the noisy response of Fig. 12).

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Table 2. MEMS + Interface circuit specifications

Top-side proof mass 7mmx5mmx120i.tm

Extra seismic mass 5mmx3mmx40Oum
Proof mass I ~mi~li-eram I
Sensitivity I7pFlg
Brownian noise floor lOOnano-g/dHz
f.?,,,( I "-flexural) 180Hz
Fig. 12. Accelerometer's response to a l6mg (peak) 2""mode (out-of-plane) 1300Hz
460mHz acceleration Gap size 5P
The static response of the accelerometer is provided in Fig.
13. The IC output saturates with less than 30mg (<2* from Gain 83mVimilli-g
earth surface). The measured specifications are summarized Output noise floor -91dBm @IOHz
in Table 2.
Min. detectable Accl. 170nano-g @ 1 OHz
Sensitiv ityCurve Capacitive resolution 2aFidHz @ 1OHz
Gain=83mV/milli-g I Power supply GND-2.5V
l
Power dissipation 6mW
Sampling frequency 200kHz
Die core area 0.6 5mm2

REFERENCES
Input Aceeleratlon (mg]
[I] Space Acceleration Measurement System (SAMs),
Fig. 13. Static response of the accelerometer; Measured httu:/lmicroaravity.arc.nasa.govlMSD/MSD/MSDhtmls/samsff,html
sensitivity is 83mVimilli-g (=17pF/g) [2] B Vakili Amini, S . Pourkamali, and F. Ayazi "A high
resolution, stictionless, CMOS-compatible SO1 accelerometer
CONCLUSION with a low-noise, low-power, 0.25pm CMOS interface,"
MEMS 2004, pp. 272-275.
The implementation and characterization of a novel in-
plane capacitive microaccelerometer with sub-micro-gravity [3] B. Vakili Amini, S. Pourkamali, M. Zaman, and F. Ayazi, "A
resolution and high sensitivity was presented. The process new input switching scheme for a capacitive micro-g
accelerometer," Symposiun7 on VLSI Circuils 2004, p p . 3 10-
flow i s stictionlcss and very simple compared to some other
313
microaccelerometer fabrication technologies that use regular
silicon substrates with multi-mask sets [7] [SI. It is a fully- [4J B. Vakili Amini, and F. Ayazi, "A 2.5V 14-bit Sigma-Delta
dry-release process and provides the maximum sensitivity CMOS-SO1 capacitive accelerometer," IEEE J. Solid-Side
and minimum mechanical noise floor per unit area. The Circuits, pp, 2467- 2476, Dec. 2004.
accelerometers were interfaced with a generic sampled data [5] W. Jiangfeng, , G. K. Fedder, and L. R. Carley, "A low-noise
front-end IC that has the versatility of interfacing capacitive low-offset capacitive sensing amplifier for a 50-pg/\iHz
microaccelerometers with different rest capacitors. Proper monolithic CMOS MEMS accelerometer," IEEE J SoMSrare
mechanical design keeps the accelerometers in over-damped Circuits, pp. 722-730, May 2004.
region in air that avoids unpredicted resonant response in [6] H. Kulah, C. Junseok, N.Yazdi, and K. Najafi, "A multi-step
the accelerometers. The measured sensitivity is 83mVimg electromechanical Sigma-Delta converter for micro-g
(1 7pFig). The IC measures power consumption of 6mW and capacitive accelerometers,"ISSCC 2003, p p . 202-203.
core area of 0.6Smmz.
[7] P. Monajemi,and F. Ayazi, "Thick single crystal Silicon
ACKNOWLEDGEMENTS MEMS with high aspect ratio vertical air-gaps," SPIE 2005
Micromachining/Mic~ofabr;carion Process Technology,
This work was supported by NASA. The authors would pp.138-147.
like to thank National Semiconductor Corporations for their
generous support of IC fabrication. [ 8 ] J. Chae, H. Kulah, and K. Najafi., "An in-plane high-
sensitivity; low-noise micro-g silicon accelerometer," MEMS
2003, pp. 466-469.

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