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LabAssignment_1

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2 views5 pages

LabAssignment_1

Uploaded by

Ram karan verma
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Advance Analog and mixed signal Design Lab Assignment1 MELZG625 (S2_23)

Instruction

1. One needs to use LTspice to verify the design.


2. All assignments need to be uploaded on portal for evaluation
3. The marks are mentioned against each question
4. For submission one should enter the bits id and then take the screen shot and paste it on
the assignment document as shown

.include p35_cmos_models_tt.inc
Question1 [3]

One of the structures that can be used for the design of a comparator is depicted in Figure 2 It
consists of an input differential stage loaded by cross-coupled transistors. Due to the positive
feedback provided by the loading transistors, the comparator transfer characteristic exhibits
hysteresis as shown in Figure.
Given the values of some specifications (slew rate, gain-bandwidth product, input common-mode
voltage, input-referred noise, power dissipation), the sizes of transistors composing the input stage
can be determined in the same way as in the case of an amplifier

1st design a Differential amplifier in 0.35µm technology for the given specification
as per the figure 1
VDD = -VSS= 2.5V , SR ≥ 10 V/µs at CL = 5 pF, f-3 dB ≥ 100 kHz (CL = 5 pF), a small-signal differential
voltage gain of 100 V/V, -1.5 V ≤ ICMR ≤ 2V, and Pdiss =1 mW. Use the model parameters of 0.35µm.
a. Show the frequency response
b. The transient response c. The slew rate
Advance Analog and mixed signal Design Lab Assignment1 MELZG625 (S2_23)

Current-Mirror Load Differential Amplifier Design Procedure


(1) Choose I5 to satisfy the slew rate knowing CL or the power dissipation, Pdiss. (2) Check to see if
Rout will satisfy the frequency response and if not, change I5 or modify the circuit (choose a

different topology). ω-3dB= 1/(Rout.CL)


(3) Design W3/L3 (W4/L4) to satisfy the upper ICMR. . VIC (max) = VDD - VSG3 + VTN1 (4) Design
W1/L1 (W2/L2 ) to satisfy the small-signal differential voltage gain, Av. = gm1Rout

(5) Design W5/L5 to satisfy the lower ICMR VDS(sat) = VIC(min) - VSS - VGS1

(6) Iterate where necessary

Advance Analog and mixed signal Design Lab Assignment1 MELZG625 (S2_23)
(a) Comparator circuit with hysteresis; (b) comparator characteristics in the non-inverting
configuration.

The difference between the positive and negative trigger points is the hysteresis band, which is given
by VHB = Vtrig+ − Vtrig−
Assuming that the transistors T1 and T2 are matched, that is, W1/L1 = W2/L2, we obtain

For a
symmetrical structure, it is required that Vtrig+ = −Vtrig− . Hence, W3/L3 = W4/L4 and W5/L5 = W6/L6.
Given the values of IB, 2K′ (W1/L1) and the specification Vtrig+ , the ratio x = (W5/L5)/(W3/L3) can be
determined by solving the next equation, which is derived from Equation 1 and can be written as

where |∆| = Vtrig+ √( 2K′(W1/L1)/IB). Solving above Equation gives


Advance Analog and mixed signal Design Lab Assignment1 MELZG625 (S2_23)

where |∆| < √ 2 and ∆ ≠ 1. To choose between the plus and minus sign in the valid expression of x,
we note that the condition x > 1 should be realized in order for the comparator to operate with a
positive feedback. [5]

Show the following parameters

a. DC performance of the comparator


b. The outputs of the circuit with hysteresis
c. The outputs of the circuit with hysteresis
d. Transient response of the comparator
e. The gain of the comparator

Output Buffer [2]

The final component in our comparator design is the output buffer or post-amplifier. The main
purpose of the output buffer is to convert the output of the decision circuit into a logic signal. The
output buffer should accept a differential input signal and not have slew-rate limitations. For a
simple design for the output buffer, we can use the self-biased diff-amp
Advance Analog and mixed signal Design Lab Assignment1 MELZG625 (S2_23)

Show the following parameters at the final single output

a. DC performance of the comparator


b. The outputs of the circuit with hysteresis
c. The outputs of the circuit without hysteresis
d. Transient response of the comparator
e. The gain of the comparator

Note: One can take help of the comparator circuit developed and uploaded.

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