RM0438

Reference manual
STM32L552xx and STM32L562xx advanced Arm®-based
32-bit MCUs

Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32L552xx and STM32L562xx microcontrollers memory and peripherals.
STM32L552xx and STM32L562xx belong to the STM32L5x2 line of microcontrollers with
different memory sizes, packages and peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
corresponding datasheets.
For information on the Arm® Cortex®-M33 core, refer to the Cortex®-M33 Technical
Reference manual.

Related documents
• Cortex®-M33 Technical Reference Manual available at http://infocenter.arm.com
• STM32L552xx and STM32L562xx datasheets

December 2020 RM0438 Rev 7 1/2194

www.st.com 1
Contents RM0438

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.2 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
1.3 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
1.4 Availability of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.1.1 Fast C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.1.2 Slow C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.1.3 S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.1.4 DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.1.5 SDMMC controller DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.1.6 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.2 TrustZone® security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.2.1 Default TrustZone security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.2.2 TrustZone peripheral classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.3.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 88
2.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.4.1 SRAM2 parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
2.4.2 SRAM2 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
2.4.3 SRAM2 Read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.4.4 SRAM2 Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.5 Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4 System security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2 Key security features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.3 Secure install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

2/2194 RM0438 Rev 7

RM0438 Contents

4.4 Secure boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.2 Unique boot entry and BOOT_LOCK . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.3 Immutable root of trust in system Flash memory . . . . . . . . . . . . . . . . . 104
4.5 Secure update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.6 Resource isolation using TrustZone® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.6.2 TrustZone® security architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.6.3 Armv8-M security extension of Cortex®-M33 . . . . . . . . . . . . . . . . . . . . 105
4.6.4 Memory and peripheral allocation using IDAU/SAU . . . . . . . . . . . . . . 106
4.6.5 Memory and peripheral allocation using GTZC . . . . . . . . . . . . . . . . . . 108
4.6.6 Managing security in TrustZone®-aware peripherals . . . . . . . . . . . . . . 111
4.6.7 Activating TrustZone® security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.6.8 De-activating TrustZone® security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.7 Other resource isolations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
4.7.1 Temporal isolation using secure hide protection (HDP) . . . . . . . . . . . . 119
4.8 Secure execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.8.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.8.3 Embedded Flash memory write protection . . . . . . . . . . . . . . . . . . . . . 121
4.8.4 Tamper detection and response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.9 Secure storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.9.2 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.10 Crypto engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.10.2 Crypto engines features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.10.3 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . . 125
4.11 Product Lifecycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.11.2 Lifecycle management with readout protection (RDP) . . . . . . . . . . . . 127
4.11.3 Recommended option byte settings . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.12 Access controlled debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
4.12.2 Debug protection with readout protection (RDP) . . . . . . . . . . . . . . . . . 128
4.13 Software intellectual property protection and collaborative development 129

RM0438 Rev 7 3/2194

53
Contents RM0438

4.13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

4.13.2 Software intellectual property protection with
readout protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.13.3 Software intellectual property protection with OTFDEC . . . . . . . . . . . 130
4.13.4 Other software intellectual property protections . . . . . . . . . . . . . . . . . 132

5 Global TrustZone® controller (GTZC) . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.1 GTZC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2 GTZC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2.1 GTZC TrustZone system architecture . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3 GTZC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.1 GTZC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.3.2 Illegal access definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.3.3 TrustZone security controller (TZSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3.4 Memory protection controller - block based (MPCBB) . . . . . . . . . . . . . 137
5.3.5 TrustZone illegal access controller (TZIC) . . . . . . . . . . . . . . . . . . . . . . 138
5.3.6 Power-on/reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.3.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.4 GTZC events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.5 GTZC_TZSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.5.1 GTZC_TZSC control register (GTZC_TZSC_CR) . . . . . . . . . . . . . . . . 139
5.5.2 GTZC_TZSC secure configuration register 1
(GTZC_TZSC_SECCFGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.5.3 GTZC_TZSC secure configuration register 2
(GTZC_TZSC_SECCFGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.5.4 GTZC_TZSC privilege configuration register 1
(GTZC_TZSC_PRIVCFGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.5.5 GTZC_TZSC privilege configuration register 2
(GTZC_TZSC_PRIVCFGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.5.6 GTZC_TZSC external memory x non-secure watermark register 1
(GTZC_TZSC_MPCWMxANSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.5.7 GTZC_TZSC external memory x non-secure watermark register 2
(GTZC_TZSC_MPCWMxBNSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.5.8 GTZC_TZSC register map and reset values . . . . . . . . . . . . . . . . . . . . 151
5.6 GTZC_MPCBB registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.6.1 GTZC_MPCBBx control register (GTZC_MPCBBx_CR) (x = 1 to 2) . 153
5.6.2 GTZC_MPCBB1 lock register 1(GTZC_MPCBB1_LCKVTR1) . . . . . . 154
5.6.3 GTZC_MPCBB2 lock register 1
(GTZC_MPCBB2_LCKVTR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

4/2194 RM0438 Rev 7

RM0438 Contents

5.6.4 GTZC_MPCBBx vector register y

(GTZC_MPCBBx_VCTRy) (x = 1 to 2) . . . . . . . . . . . . . . . . . . . . . . . . 155
5.6.5 GTZC_MPCBB1 register map and reset values . . . . . . . . . . . . . . . . . 156
5.6.6 GTZC_MPCBB2 register map and reset values . . . . . . . . . . . . . . . . . 156
5.7 GTZC_TZIC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.7.1 GTZC_TZIC interrupt enable register 1 (GTZC_TZIC_IER1) . . . . . . . 157
5.7.2 GTZC_TZIC interrupt enable register 2 (GTZC_TZIC_IER2) . . . . . . . 160
5.7.3 GTZC_TZIC interrupt enable register 3 (GTZC_TZIC_IER3) . . . . . . . 162
5.7.4 GTZC_TZIC status register 1 (GTZC_TZIC_SR1) . . . . . . . . . . . . . . . 163
5.7.5 GTZC_TZIC status register 2 (GTZC_TZIC_SR2) . . . . . . . . . . . . . . . 166
5.7.6 GTZC_TZIC status register 3 (GTZC_TZIC_SR3) . . . . . . . . . . . . . . . 168
5.7.7 GTZC_TZIC flag clear register 1 (GTZC_TZIC_FCR1) . . . . . . . . . . . . 169
5.7.8 GTZC_TZIC flag clear register 2 (GTZC_TZIC_FCR2) . . . . . . . . . . . . 172
5.7.9 GTZC_TZIC flag clear register 3 (GTZC_TZIC_FCR3) . . . . . . . . . . . . 174
5.7.10 GTZC_TZIC register map and reset values . . . . . . . . . . . . . . . . . . . . . 175

6 Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.2 FLASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
6.3 Flash memory functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.1 Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.2 Error code correction (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.3 Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.4 Low-voltage read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.5 Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.6 Flash main memory erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.7 Flash main memory programming sequences . . . . . . . . . . . . . . . . . . . 187
6.3.8 Flash errors flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
6.3.9 Read-while-write (RWW) available only in dual-bank mode
(DBANK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.4 Flash memory option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.4.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.4.2 Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.5 Flash TrustZone security and privilege protections . . . . . . . . . . . . . . . . 195
6.5.1 TrustZone security protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.5.2 Secure watermark-based area protection . . . . . . . . . . . . . . . . . . . . . . 197
6.5.3 Secure hide protection (HDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

RM0438 Rev 7 5/2194

53
Contents RM0438

6.5.4 Secure block-based area (SECBB) protection . . . . . . . . . . . . . . . . . . 198

6.5.5 Forcing boot from a secure memory address . . . . . . . . . . . . . . . . . . . 199
6.5.6 Flash security attribute state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.5.7 Flash registers privileged and unprivileged modes . . . . . . . . . . . . . . . 200
6.6 Secure system memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.6.2 RSS allocates resource to bootloader . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.6.3 RSSLIB functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.7 FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.7.1 Write protection (WRP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.7.2 Readout protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.8 FLASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.9 FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.9.1 Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . 215
6.9.2 Flash power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . 216
6.9.3 Flash non-secure key register (FLASH_NSKEYR) . . . . . . . . . . . . . . . 217
6.9.4 Flash secure key register (FLASH_SECKEYR) . . . . . . . . . . . . . . . . . 217
6.9.5 Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . 218
6.9.6 Flash low voltage key register (FLASH_LVEKEYR) . . . . . . . . . . . . . . 218
6.9.7 Flash status register (FLASH_NSSR) . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.9.8 Flash status register (FLASH_SECSR) . . . . . . . . . . . . . . . . . . . . . . . . 220
6.9.9 Flash non-secure control register (FLASH_NSCR) . . . . . . . . . . . . . . . 222
6.9.10 Flash secure control register (FLASH_SECCR) . . . . . . . . . . . . . . . . . 224
6.9.11 Flash ECC register (FLASH_ECCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.9.12 Flash option register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.9.13 Flash non-secure boot address 0 register (FLASH_NSBOOTADD0R) 229
6.9.14 Flash non-secure boot address 1 register (FLASH_NSBOOTADD1R) 230
6.9.15 Flash secure boot address 0 register (FLASH_SECBOOTADD0R) . . 230
6.9.16 Flash bank 1 secure watermak1 register (FLASH_SECWM1R1) . . . . 231
6.9.17 Flash secure watermak1 register 2 (FLASH_SECWM1R2) . . . . . . . . 232
6.9.18 Flash WPR1 area A address register (FLASH_WRP1AR) . . . . . . . . . 233
6.9.19 Flash WPR1 area B address register (FLASH_WRP1BR) . . . . . . . . . 234
6.9.20 Flash secure watermak2 register (FLASH_SECWM2R1) . . . . . . . . . . 235
6.9.21 Flash secure watermak2 register 2 (FLASH_SECWM2R2) . . . . . . . . 236
6.9.22 Flash WPR2 area A address register (FLASH_WRP2AR) . . . . . . . . . 237
6.9.23 Flash WPR2 area B address register (FLASH_WRP2BR) . . . . . . . . . 238

6/2194 RM0438 Rev 7

RM0438 Contents

6.9.24 FLASH secure block based bank 1 register (FLASH_SECBB1Rx)

(where x=1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.9.25 FLASH secure block based bank 2 register (FLASH_SECBB2Rx)
(where x=1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
6.9.26 FLASH secure HDP control register (FLASH_SECHDPCR) . . . . . . . . 240
6.9.27 FLASH privilege configuration register (FLASH_PRIVCFGR) . . . . . . . 240
6.9.28 FLASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 241

7 Instruction cache (ICACHE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.2 ICACHE main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.3 ICACHE implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.4 ICACHE functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
7.4.1 ICACHE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.4.2 ICACHE reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
7.4.3 ICACHE TAG memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
7.4.4 Direct mapped ICACHE (1-way cache) . . . . . . . . . . . . . . . . . . . . . . . . 248
7.4.5 ICACHE enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.6 Cacheable and non-cacheable traffic . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.7 Address remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
7.4.8 Cacheable accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
7.4.9 Dual master cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.4.10 ICACHE security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.4.11 ICACHE maintenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.4.12 ICACHE performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.4.13 ICACHE Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.5 ICACHE low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
7.6 ICACHE error management and interrupts . . . . . . . . . . . . . . . . . . . . . . 255
7.7 ICACHE registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
7.7.1 ICACHE control register (ICACHE_CR) . . . . . . . . . . . . . . . . . . . . . . . 256
7.7.2 ICACHE status register (ICACHE_SR) . . . . . . . . . . . . . . . . . . . . . . . . 257
7.7.3 ICACHE interrupt enable register (ICACHE_IER) . . . . . . . . . . . . . . . . 257
7.7.4 ICACHE flag clear register (ICACHE_FCR) . . . . . . . . . . . . . . . . . . . . 258
7.7.5 ICACHE hit monitor register (ICACHE_HMONR) . . . . . . . . . . . . . . . . 259
7.7.6 ICACHE miss monitor register (ICACHE_MMONR) . . . . . . . . . . . . . . 259
7.7.7 ICACHE region x configuration register (ICACHE_CRRx) . . . . . . . . . 259
7.7.8 ICACHE register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

RM0438 Rev 7 7/2194

53
Contents RM0438

8 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

8.1 Power supplies and supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
8.1.1 Independent analog peripherals supply . . . . . . . . . . . . . . . . . . . . . . . . 267
8.1.2 Independent I/O supply rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
8.1.3 Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . 267
8.1.4 Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
8.2 System supply voltage regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.2.1 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
8.2.2 Embedded SMPS step down converter . . . . . . . . . . . . . . . . . . . . . . . . 270
8.2.3 SMPS step down converter power supply scheme . . . . . . . . . . . . . . . 271
8.2.4 SMPS step down converter versus low-power mode . . . . . . . . . . . . . 272
8.2.5 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 273
8.2.6 VDD12 domain and external SMPS . . . . . . . . . . . . . . . . . . . . . . . . . . 274
8.3 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
8.3.1 Power-on reset (POR) / power-down reset (PDR) /
brown-out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
8.3.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 277
8.3.3 Peripheral voltage monitoring (PVM) . . . . . . . . . . . . . . . . . . . . . . . . . . 278
8.3.4 Upper voltage threshold monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
8.3.5 Temperature threshold monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.4 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.4.1 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.4.2 Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
8.4.3 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
8.4.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
8.4.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8.4.6 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
8.4.7 Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
8.4.8 Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
8.4.9 Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
8.4.10 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
8.4.11 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
8.4.12 Auto-wakeup from a low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . 300
8.5 PWR TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
8.5.1 PWR Privileged and Unprivileged modes . . . . . . . . . . . . . . . . . . . . . . 302
8.6 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

8/2194 RM0438 Rev 7

RM0438 Contents

8.6.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 303

8.6.2 Power control register 2 (PWR_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 304
8.6.3 Power control register 3 (PWR_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . 305
8.6.4 Power control register 4 (PWR_CR4) . . . . . . . . . . . . . . . . . . . . . . . . . 307
8.6.5 Power status register 1 (PWR_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 308
8.6.6 Power status register 2 (PWR_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 310
8.6.7 Power status clear register (PWR_SCR) . . . . . . . . . . . . . . . . . . . . . . . 311
8.6.8 Power Port A pull-up control register (PWR_PUCRA) . . . . . . . . . . . . . 312
8.6.9 Power Port A pull-down control register (PWR_PDCRA) . . . . . . . . . . 312
8.6.10 Power Port B pull-up control register (PWR_PUCRB) . . . . . . . . . . . . . 313
8.6.11 Power Port B pull-down control register (PWR_PDCRB) . . . . . . . . . . 314
8.6.12 Power Port C pull-up control register (PWR_PUCRC) . . . . . . . . . . . . 314
8.6.13 Power Port C pull-down control register (PWR_PDCRC) . . . . . . . . . . 315
8.6.14 Power Port D pull-up control register (PWR_PUCRD) . . . . . . . . . . . . 315
8.6.15 Power Port D pull-down control register (PWR_PDCRD) . . . . . . . . . . 316
8.6.16 Power Port E pull-up control register (PWR_PUCRE) . . . . . . . . . . . . . 317
8.6.17 Power Port E pull-down control register (PWR_PDCRE) . . . . . . . . . . 317
8.6.18 Power Port F pull-up control register (PWR_PUCRF) . . . . . . . . . . . . . 318
8.6.19 Power Port F pull-down control register (PWR_PDCRF) . . . . . . . . . . 318
8.6.20 Power Port G pull-up control register (PWR_PUCRG) . . . . . . . . . . . . 319
8.6.21 Power Port G pull-down control register (PWR_PDCRG) . . . . . . . . . . 320
8.6.22 Power Port H pull-up control register (PWR_PUCRH) . . . . . . . . . . . . 320
8.6.23 Power Port H pull-down control register (PWR_PDCRH) . . . . . . . . . . 321
8.6.24 Power secure configuration register (PWR_SECCFGR) . . . . . . . . . . . 321
8.6.25 Power privilege configuration register (PWR_PRIVCFGR) . . . . . . . . . 323
8.6.26 PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 324

9 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

9.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
9.1.1 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
9.1.2 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
9.1.3 Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
9.2 RCC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
9.3 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
9.3.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
9.3.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
9.3.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

RM0438 Rev 7 9/2194

53
Contents RM0438

9.3.4 HSI48 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

9.3.5 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
9.3.6 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
9.3.7 LSE system clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
9.3.8 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
9.3.9 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
9.3.10 Clock source frequency versus voltage scaling . . . . . . . . . . . . . . . . . . 339
9.3.11 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
9.3.12 Clock security system on LSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
9.3.13 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
9.3.14 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
9.3.15 Timer clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
9.3.16 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
9.3.17 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
9.3.18 Internal/external clock measurement with TIM15/TIM16/TIM17 . . . . . 341
9.3.19 Peripheral clock enable registers
(RCC_AHBxENR, RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . 344
9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
9.5 RCC TrustZone® security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
9.6 RCC Privileged and Unprivileged mode . . . . . . . . . . . . . . . . . . . . . . . . . 347
9.7 RCC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
9.8 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
9.8.1 RCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 349
9.8.2 RCC internal clock sources calibration register (RCC_ICSCR) . . . . . . 352
9.8.3 RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 353
9.8.4 RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 356
9.8.5 RCC PLLSAI1 configuration register (RCC_PLLSAI1CFGR) . . . . . . . 359
9.8.6 RCC PLLSAI2 configuration register (RCC_PLLSAI2CFGR) . . . . . . . 362
9.8.7 RCC clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . 364
9.8.8 RCC clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . 365
9.8.9 RCC clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . 367
9.8.10 RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 368
9.8.11 RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 369
9.8.12 RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 371
9.8.13 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1) . . . . . . . . 372
9.8.14 RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2) . . . . . . . . 374
9.8.15 RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 375

10/2194 RM0438 Rev 7

RM0438 Contents

9.8.16 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR) . . . . . 377

9.8.17 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 378
9.8.18 RCC AHB3 peripheral clock enable register(RCC_AHB3ENR) . . . . . . 380
9.8.19 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1) . . . 381
9.8.20 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2) . . . 383
9.8.21 RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 385
9.8.22 RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
9.8.23 RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
9.8.24 RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
9.8.25 RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 1 (RCC_APB1SMENR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
9.8.26 RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 2 (RCC_APB1SMENR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
9.8.27 RCC APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
9.8.28 RCC peripherals independent clock configuration register 1
(RCC_CCIPR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
9.8.29 RCC Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 399
9.8.30 RCC control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . 402
9.8.31 RCC clock recovery RC register (RCC_CRRCR) . . . . . . . . . . . . . . . . 404
9.8.32 RCC peripherals independent clock configuration register 2
(RCC_CCIPR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
9.8.33 OCTOSPI delay configuration register (RCC_DLYCFGR) . . . . . . . . . 406
9.8.34 RCC secure configuration register (RCC_SECCFGR) . . . . . . . . . . . . 407
9.8.35 RCC secure status register (RCC_SECSR) . . . . . . . . . . . . . . . . . . . . 409
9.8.36 RCC AHB1 security status register (RCC_AHB1SECSR) . . . . . . . . . . 411
9.8.37 RCC AHB2 security status register (RCC_AHB2SECSR) . . . . . . . . . . 412
9.8.38 RCC AHB3 security status register (RCC_AHB3SECSR) . . . . . . . . . . 414
9.8.39 RCC APB1 security status register 1 (RCC_APB1SECSR1) . . . . . . . 415
9.8.40 RCC APB1 security status register 2 (RCC_APB1SECSR2) . . . . . . . 418
9.8.41 RCC APB2 security status register (RCC_APB2SECSR) . . . . . . . . . . 419
9.8.42 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421

10 Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
10.2 CRS main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

RM0438 Rev 7 11/2194

53
Contents RM0438

10.3 CRS implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

10.4 CRS functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
10.4.1 CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
10.4.2 Synchronization input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
10.4.3 Frequency error measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
10.4.4 Frequency error evaluation and automatic trimming . . . . . . . . . . . . . . 431
10.4.5 CRS initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
10.5 CRS low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.6 CRS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
10.7 CRS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
10.7.1 CRS control register (CRS_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
10.7.2 CRS configuration register (CRS_CFGR) . . . . . . . . . . . . . . . . . . . . . . 434
10.7.3 CRS interrupt and status register (CRS_ISR) . . . . . . . . . . . . . . . . . . . 435
10.7.4 CRS interrupt flag clear register (CRS_ICR) . . . . . . . . . . . . . . . . . . . . 437
10.7.5 CRS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

11 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
11.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
11.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
11.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
11.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 442
11.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
11.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
11.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
11.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
11.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
11.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
11.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
11.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
11.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
11.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
11.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 447
11.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 447
11.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
11.4 TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448

12/2194 RM0438 Rev 7

RM0438 Contents

11.5 Privileged and Unprivileged modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449

11.6 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
11.6.1 GPIO port mode register (GPIOx_MODER)
(x =A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
11.6.2 GPIO port output type register (GPIOx_OTYPER)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
11.6.3 GPIO port output speed register (GPIOx_OSPEEDR)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
11.6.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
11.6.5 GPIO port input data register (GPIOx_IDR)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
11.6.6 GPIO port output data register (GPIOx_ODR)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
11.6.7 GPIO port bit set/reset register (GPIOx_BSRR)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
11.6.8 GPIO port configuration lock register (GPIOx_LCKR)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
11.6.9 GPIO alternate function low register (GPIOx_AFRL)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
11.6.10 GPIO alternate function high register (GPIOx_AFRH)
(x = A to H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
11.6.11 GPIO port bit reset register (GPIOx_BRR) (x = A to H) . . . . . . . . . . . . 456
11.6.12 GPIO secure configuration register (GPIOx_SECCFGR) (x = A to H) . 456
11.6.13 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

12 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 459

12.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
12.2 SYSCFG TrustZone security and privilege . . . . . . . . . . . . . . . . . . . . . . . 459
12.3 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
12.3.1 SYSCFG secure configuration register (SYSCFG_SECCFGR) . . . . . 461
12.3.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 461
12.3.3 FPU interrupt mask register (SYSCFG_FPUIMR) . . . . . . . . . . . . . . . . 463
12.3.4 SYSCFG CPU non-secure lock register (SYSCFG_ CNSLCKR) . . . . 464
12.3.5 SYSCFG CPU secure lock register (SYSCFG _CSLOCKR) . . . . . . . . 464
12.3.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 465
12.3.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR) . . . . 466
12.3.8 SYSCFG SRAM2 key register (SYSCFG_SKR) . . . . . . . . . . . . . . . . . 467
12.3.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR) . . . . . . 468
12.3.10 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2) . . . 468

RM0438 Rev 7 13/2194

53
Contents RM0438

12.3.11 SYSCFG RSS command register (SYSCFG_RSSCMDR) . . . . . . . . . 469

12.3.12 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470

13 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
13.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
13.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
13.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to
timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15) . . . . . . . . . . . . . . . . 473
13.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC
(ADC1/ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
13.3.3 From ADC1/ADC2 to timer (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . 474
13.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC
(DAC1/DAC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
13.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16/LPTIM1)
and EXTI to DFSDM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
13.3.6 From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . . . . . . 476
13.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer
(TIM2/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
13.3.8 From RTC, COMP1, COMP2 to low-power timer
(LPTIM1/LPTIM2/LPTIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
13.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators
(COMP1/COMP2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
13.3.10 From ADC (ADC1) to ADC (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
13.3.11 From USB to timer (TIM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
13.3.12 From internal analog source to ADC (ADC1/ADC2) and OPAMP
(OPAMP1/OPAM2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
13.3.13 From comparators (COMP1/COMP2) to timers
(TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . . . 478
13.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17) . . . . 479
13.3.15 From timers (TIM16/TIM17) to IRTIM . . . . . . . . . . . . . . . . . . . . . . . . . 479
13.3.16 From ADC (ADC1/ADC2) to DFSDM . . . . . . . . . . . . . . . . . . . . . . . . . . 480

14 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 481

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
14.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
14.3 DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
14.3.1 DMA1 and DMA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
14.3.2 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482

14/2194 RM0438 Rev 7

RM0438 Contents

14.4 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

14.4.1 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
14.4.2 DMA pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
14.4.3 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
14.4.4 DMA arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
14.4.5 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
14.4.6 DMA data width, alignment and endianness . . . . . . . . . . . . . . . . . . . . 491
14.4.7 DMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
14.5 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
14.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
14.6.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 493
14.6.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 497
14.6.3 DMA channel x configuration register (DMA_CCRx) . . . . . . . . . . . . . . 498
14.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx) . 503
14.6.5 DMA channel x peripheral address register (DMA_CPARx) . . . . . . . . 504
14.6.6 DMA channel x memory 0 address register (DMA_CM0ARx) . . . . . . . 504
14.6.7 DMA channel x memory 1 address register (DMA_CM1ARx) . . . . . . . 505
14.6.8 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

15 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . 509

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
15.2 DMAMUX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
15.3 DMAMUX implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
15.3.1 DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
15.3.2 DMAMUX mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
15.4 DMAMUX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
15.4.1 DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
15.4.2 DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
15.4.3 DMAMUX channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
15.4.4 DMAMUX secure/non-secure channels . . . . . . . . . . . . . . . . . . . . . . . . 516
15.4.5 DMAMUX privileged / unprivileged channels . . . . . . . . . . . . . . . . . . . . 516
15.4.6 DMAMUX request line multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
15.4.7 DMAMUX request generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
15.5 DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
15.6 DMAMUX registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

RM0438 Rev 7 15/2194

53
Contents RM0438

15.6.1 DMAMUX request line multiplexer channel x configuration register

(DMAMUX_CxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
15.6.2 DMAMUX request line multiplexer interrupt channel status register
(DMAMUX_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
15.6.3 DMAMUX request line multiplexer interrupt channel clear flag register
(DMAMUX_CCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
15.6.4 DMAMUX request generator channel x configuration register
(DMAMUX_RGxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524
15.6.5 DMAMUX request generator interrupt status register
(DMAMUX_RGSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
15.6.6 DMAMUX request generator interrupt clear flag register
(DMAMUX_RGCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
15.6.7 DMAMUX register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

16 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 529

16.1 NVIC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
16.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
16.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

17 Extended interrupts and event controller (EXTI) . . . . . . . . . . . . . . . . 534

17.1 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
17.2 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
17.2.1 EXTI connections between peripherals and CPU . . . . . . . . . . . . . . . . 536
17.2.2 EXTI interrupt/event mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
17.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
17.3.1 EXTI configurable event input wakeup . . . . . . . . . . . . . . . . . . . . . . . . 538
17.3.2 EXTI direct event input wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
17.3.3 EXTI mux selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
17.4 EXTI functional behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
17.5 EXTI event protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
17.5.1 EXTI security protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
17.5.2 EXTI privilege protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
17.6 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
17.6.1 EXTI rising trigger selection register (EXTI_RTSR1) . . . . . . . . . . . . . . 544
17.6.2 EXTI falling trigger selection register (EXTI_FTSR1) . . . . . . . . . . . . . 545
17.6.3 EXTI software interrupt event register (EXTI_SWIER1) . . . . . . . . . . . 546
17.6.4 EXTI rising edge pending register (EXTI_RPR1) . . . . . . . . . . . . . . . . 547
17.6.5 EXTI falling edge pending register (EXTI_FPR1) . . . . . . . . . . . . . . . . 548

16/2194 RM0438 Rev 7

RM0438 Contents

17.6.6 EXTI security configuration register (EXTI_SECCFGR1) . . . . . . . . . . 549

17.6.7 EXTI privilege configuration register (EXTI_PRIVCFGR1) . . . . . . . . . 550
17.6.8 EXTI rising trigger selection register (EXTI_RTSR2) . . . . . . . . . . . . . . 550
17.6.9 EXTI falling trigger selection register (EXTI_FTSR2) . . . . . . . . . . . . . 551
17.6.10 EXTI software interrupt event register (EXTI_SWIER2) . . . . . . . . . . . 552
17.6.11 EXTI rising edge pending register (EXTI_RPR2) . . . . . . . . . . . . . . . . 552
17.6.12 EXTI falling edge pending register (EXTI_FPR2) . . . . . . . . . . . . . . . . 553
17.6.13 EXTI security enable register (EXTI_SECCFGR2) . . . . . . . . . . . . . . . 554
17.6.14 EXTI privilege enable register (EXTI_PRIVCFGR2) . . . . . . . . . . . . . . 554
17.6.15 EXTI external interrupt selection register (EXTI_EXTICRn) . . . . . . . . 555
17.6.16 EXTI lock register (EXTI_LOCKR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
17.6.17 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1) . . . . . . . 558
17.6.18 EXTI CPU wakeup with event mask register (EXTI_EMR1) . . . . . . . . 559
17.6.19 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2) . . . . . . . 560
17.6.20 EXTI CPU wakeup with event mask register (EXTI_EMR2) . . . . . . . . 560
17.6.21 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

18 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 564

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
18.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
18.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
18.3.1 CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
18.3.2 CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
18.3.3 CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
18.4 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
18.4.1 CRC data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
18.4.2 CRC independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . 567
18.4.3 CRC control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
18.4.4 CRC initial value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
18.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
18.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

19 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . 571

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
19.2 FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
19.3 FMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

RM0438 Rev 7 17/2194

53
Contents RM0438

19.4 AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

19.4.1 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 573
19.5 External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574
19.5.1 NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
19.5.2 NAND Flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 576
19.6 NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577
19.6.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
19.6.2 Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 580
19.6.3 General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581
19.6.4 NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 582
19.6.5 Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
19.6.6 NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
19.7 NAND Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
19.7.1 External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
19.7.2 NAND Flash supported memories and transactions . . . . . . . . . . . . . . 617
19.7.3 Timing diagrams for NAND Flash memory . . . . . . . . . . . . . . . . . . . . . 617
19.7.4 NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
19.7.5 NAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
19.7.6 Computation of the error correction code (ECC)
in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620
19.7.7 NAND Flash controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
19.7.8 FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

20 Octo-SPI interface (OCTOSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
20.2 OCTOSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
20.3 OCTOSPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
20.4 OCTOSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
20.4.1 OCTOSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
20.4.2 OCTOSPI interface to memory modes . . . . . . . . . . . . . . . . . . . . . . . . 632
20.4.3 OCTOSPI Regular-command protocol . . . . . . . . . . . . . . . . . . . . . . . . 632
20.4.4 OCTOSPI Regular-command protocol signal interface . . . . . . . . . . . . 636
20.4.5 HyperBus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
20.4.6 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
20.4.7 OCTOSPI operating modes introduction . . . . . . . . . . . . . . . . . . . . . . . 644
20.4.8 OCTOSPI Indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
20.4.9 OCTOSPI Automatic status-polling mode . . . . . . . . . . . . . . . . . . . . . . 646

18/2194 RM0438 Rev 7

RM0438 Contents

20.4.10 OCTOSPI Memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647

20.4.11 OCTOSPI configuration introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 647
20.4.12 OCTOSPI system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
20.4.13 OCTOSPI device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
20.4.14 OCTOSPI Regular-command mode configuration . . . . . . . . . . . . . . . . 649
20.4.15 OCTOSPI HyperBus protocol configuration . . . . . . . . . . . . . . . . . . . . . 652
20.4.16 OCTOSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
20.4.17 OCTOSPI BUSY and ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
20.4.18 OCTOSPI reconfiguration or deactivation . . . . . . . . . . . . . . . . . . . . . . 654
20.4.19 NCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
20.5 Address alignment and data number . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
20.6 OCTOSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
20.7 OCTOSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
20.7.1 OCTOSPI control register (OCTOSPI_CR) . . . . . . . . . . . . . . . . . . . . . 657
20.7.2 OCTOSPI device configuration register 1 (OCTOSPI_DCR1) . . . . . . 660
20.7.3 OCTOSPI device configuration register 2 (OCTOSPI_DCR2) . . . . . . 661
20.7.4 OCTOSPI device configuration register 3 (OCTOSPI_DCR3) . . . . . . 662
20.7.5 OCTOSPI device configuration register 4 (OCTOSPI_DCR4) . . . . . . 663
20.7.6 OCTOSPI status register (OCTOSPI_SR) . . . . . . . . . . . . . . . . . . . . . . 663
20.7.7 OCTOSPI flag clear register (OCTOSPI_FCR) . . . . . . . . . . . . . . . . . . 664
20.7.8 OCTOSPI data length register (OCTOSPI_DLR) . . . . . . . . . . . . . . . . 665
20.7.9 OCTOSPI address register (OCTOSPI_AR) . . . . . . . . . . . . . . . . . . . . 666
20.7.10 OCTOSPI data register (OCTOSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 666
20.7.11 OCTOSPI polling status mask register (OCTOSPI_PSMKR) . . . . . . . 667
20.7.12 OCTOSPI polling status match register (OCTOSPI_PSMAR) . . . . . . . 667
20.7.13 OCTOSPI polling interval register (OCTOSPI_PIR) . . . . . . . . . . . . . . 668
20.7.14 OCTOSPI communication configuration register (OCTOSPI_CCR) . . 668
20.7.15 OCTOSPI timing configuration register (OCTOSPI_TCR) . . . . . . . . . . 670
20.7.16 OCTOSPI instruction register (OCTOSPI_IR) . . . . . . . . . . . . . . . . . . . 671
20.7.17 OCTOSPI alternate bytes register (OCTOSPI_ABR) . . . . . . . . . . . . . 672
20.7.18 OCTOSPI low-power timeout register (OCTOSPI_LPTR) . . . . . . . . . . 672
20.7.19 OCTOSPI wrap communication configuration register
(OCTOSPI_WPCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
20.7.20 OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR) . . 675
20.7.21 OCTOSPI wrap instruction register (OCTOSPI_WPIR) . . . . . . . . . . . . 676
20.7.22 OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR) . . . . . . 676

RM0438 Rev 7 19/2194

53
Contents RM0438

20.7.23 OCTOSPI write communication configuration register

(OCTOSPI_WCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
20.7.24 OCTOSPI write timing configuration register (OCTOSPI_WTCR) . . . . 679
20.7.25 OCTOSPI write instruction register (OCTOSPI_WIR) . . . . . . . . . . . . . 679
20.7.26 OCTOSPI write alternate bytes register (OCTOSPI_WABR) . . . . . . . 680
20.7.27 OCTOSPI HyperBus latency configuration register
(OCTOSPI_HLCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
20.7.28 OCTOSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681

21 Analog-to-digital converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 684

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
21.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
21.3 ADC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
21.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
21.4.1 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
21.4.2 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
21.4.3 ADC clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
21.4.4 ADC1/2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
21.4.5 Slave AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
21.4.7 Single-ended and differential input channels . . . . . . . . . . . . . . . . . . . . 693
21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT) . . . . . . . . . . . . . . . 694
21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . . 697
21.4.10 Constraints when writing the ADC control bits . . . . . . . . . . . . . . . . . . . 698
21.4.11 Channel selection (SQRx, JSQRx) . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2) . . . . . 700
21.4.13 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
21.4.14 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 701
21.4.15 Starting conversions (ADSTART, JADSTART) . . . . . . . . . . . . . . . . . . . 702
21.4.16 ADC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP) . . . . . . . . . . . . . . 703
21.4.18 Conversion on external trigger and trigger polarity
(EXTSEL, EXTEN, JEXTSEL, JEXTEN) . . . . . . . . . . . . . . . . . . . . . . . 705
21.4.19 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN) . . . . . . . . . . . . 709
21.4.21 Queue of context for injected conversions . . . . . . . . . . . . . . . . . . . . . . 710
21.4.22 Programmable resolution (RES) - Fast conversion mode . . . . . . . . . . 718

20/2194 RM0438 Rev 7

RM0438 Contents

21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP) . . 719
21.4.24 End of conversion sequence (EOS, JEOS) . . . . . . . . . . . . . . . . . . . . . 719
21.4.25 Timing diagrams example (single/continuous modes,
hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
21.4.26 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
21.4.27 Managing conversions using the DFSDM . . . . . . . . . . . . . . . . . . . . . . 727
21.4.28 Dynamic low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,
AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) . . . . . 733
21.4.30 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
21.4.31 Dual ADC modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
21.4.32 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
21.4.33 VBAT supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
21.4.34 Monitoring the internal voltage reference . . . . . . . . . . . . . . . . . . . . . . 759
21.5 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760
21.6 ADC registers (for each ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
21.6.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 762
21.6.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 764
21.6.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
21.6.4 ADC configuration register (ADC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 769
21.6.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 773
21.6.6 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 775
21.6.7 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 776
21.6.8 ADC watchdog threshold register 1 (ADC_TR1) . . . . . . . . . . . . . . . . . 777
21.6.9 ADC watchdog threshold register 2 (ADC_TR2) . . . . . . . . . . . . . . . . . 777
21.6.10 ADC watchdog threshold register 3 (ADC_TR3) . . . . . . . . . . . . . . . . . 778
21.6.11 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 779
21.6.12 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 780
21.6.13 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 781
21.6.14 ADC regular sequence register 4 (ADC_SQR4) . . . . . . . . . . . . . . . . . 782
21.6.15 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 782
21.6.16 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 783
21.6.17 ADC offset y register (ADC_OFRy) . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
21.6.18 ADC injected channel y data register (ADC_JDRy) . . . . . . . . . . . . . . . 786
21.6.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR) . . . . 786
21.6.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR) . . . . 787
21.6.21 ADC differential mode selection register (ADC_DIFSEL) . . . . . . . . . . 787

RM0438 Rev 7 21/2194

53
Contents RM0438

21.6.22 ADC calibration factors (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . 788

21.7 ADC common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
21.7.1 ADC common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 788
21.7.2 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 790
21.7.3 ADC common regular data register for dual mode (ADC_CDR) . . . . . 793
21.8 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793

22 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
22.2 DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
22.3 DAC implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
22.4 DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
22.4.1 DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
22.4.2 DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.4.3 DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.4.4 DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
22.4.5 DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
22.4.6 DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
22.4.7 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
22.4.8 Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
22.4.9 Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
22.4.10 DAC channel modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
22.4.11 DAC channel buffer calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
22.4.12 Dual DAC channel conversion modes (if dual channels are
available) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
22.5 DAC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
22.6 DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
22.7 DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
22.7.1 DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
22.7.2 DAC software trigger register (DAC_SWTRGR) . . . . . . . . . . . . . . . . . 820
22.7.3 DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
22.7.4 DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
22.7.5 DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
22.7.6 DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

22/2194 RM0438 Rev 7

RM0438 Contents

22.7.7 DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.7.8 DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
22.7.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.7.10 Dual DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
22.7.11 Dual DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
22.7.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 825
22.7.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 826
22.7.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
22.7.15 DAC calibration control register (DAC_CCR) . . . . . . . . . . . . . . . . . . . 828
22.7.16 DAC mode control register (DAC_MCR) . . . . . . . . . . . . . . . . . . . . . . . 828
22.7.17 DAC channel1 sample and hold sample time register
(DAC_SHSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
22.7.18 DAC channel2 sample and hold sample time register
(DAC_SHSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
22.7.19 DAC sample and hold time register (DAC_SHHR) . . . . . . . . . . . . . . . 831
22.7.20 DAC sample and hold refresh time register (DAC_SHRR) . . . . . . . . . 831
22.7.21 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833

23 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . 835

23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
23.2 VREFBUF functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
23.3 VREFBUF trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
23.4 VREFBUF registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
23.4.1 VREFBUF control and status register (VREFBUF_CSR) . . . . . . . . . . 837
23.4.2 VREFBUF calibration control register (VREFBUF_CCR) . . . . . . . . . . 838
23.4.3 VREFBUF register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838

24 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
24.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
24.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
24.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
24.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

RM0438 Rev 7 23/2194

53
Contents RM0438

24.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

24.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
24.3.5 Window comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
24.3.6 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
24.3.7 Comparator output blanking function . . . . . . . . . . . . . . . . . . . . . . . . . . 843
24.3.8 COMP power and speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
24.4 COMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
24.5 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
24.6 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
24.6.1 Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 845
24.6.2 Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 847
24.6.3 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850

25 Operational amplifiers (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851

25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
25.2 OPAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
25.3 OPAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
25.3.1 OPAMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851
25.3.2 Initial configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
25.3.3 Signal routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
25.3.4 OPAMP modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
25.3.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
25.4 OPAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
25.5 OPAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
25.5.1 OPAMP1 control/status register (OPAMP1_CSR) . . . . . . . . . . . . . . . . 859
25.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR) . . 860
25.5.3 OPAMP1 offset trimming register in low-power mode
(OPAMP1_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
25.5.4 OPAMP2 control/status register (OPAMP2_CRS) . . . . . . . . . . . . . . . . 861
25.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR) . . 862
25.5.6 OPAMP2 offset trimming register in low-power mode
(OPAMP2_LPOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
25.5.7 OPAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

26 Digital filter for sigma delta modulators (DFSDM) . . . . . . . . . . . . . . . 864

26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
26.2 DFSDM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

24/2194 RM0438 Rev 7

RM0438 Contents

26.3 DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866

26.4 DFSDM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
26.4.1 DFSDM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
26.4.2 DFSDM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
26.4.3 DFSDM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
26.4.4 Serial channel transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
26.4.5 Configuring the input serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . 879
26.4.6 Parallel data inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
26.4.7 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
26.4.8 Digital filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
26.4.9 Integrator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
26.4.10 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
26.4.11 Short-circuit detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
26.4.12 Extreme detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
26.4.13 Data unit block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
26.4.14 Signed data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888
26.4.15 Launching conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
26.4.16 Continuous and fast continuous modes . . . . . . . . . . . . . . . . . . . . . . . . 889
26.4.17 Request precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
26.4.18 Power optimization in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
26.5 DFSDM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
26.6 DFSDM DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
26.7 DFSDM channel y registers (y=0..3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
26.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1) . . . . 893
26.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2) . . . . 895
26.7.3 DFSDM channel y analog watchdog and short-circuit detector register
(DFSDM_CHyAWSCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
26.7.4 DFSDM channel y watchdog filter data register
(DFSDM_CHyWDATR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
26.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR) . . . . . . 897
26.7.6 DFSDM channel y delay register (DFSDM_CHyDLYR) . . . . . . . . . . . . 898
26.8 DFSDM filter x module registers (x=0..3) . . . . . . . . . . . . . . . . . . . . . . . . 899
26.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1) . . . . . . . . . . . . 899
26.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2) . . . . . . . . . . . . 902
26.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR) . . . . . 903
26.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR) . . . . . 905

RM0438 Rev 7 25/2194

53
Contents RM0438

26.8.5 DFSDM filter x injected channel group selection register

(DFSDM_FLTxJCHGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
26.8.6 DFSDM filter x control register (DFSDM_FLTxFCR) . . . . . . . . . . . . . . 906
26.8.7 DFSDM filter x data register for injected group
(DFSDM_FLTxJDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907
26.8.8 DFSDM filter x data register for the regular channel
(DFSDM_FLTxRDATAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908
26.8.9 DFSDM filter x analog watchdog high threshold register
(DFSDM_FLTxAWHTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
26.8.10 DFSDM filter x analog watchdog low threshold register
(DFSDM_FLTxAWLTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 909
26.8.11 DFSDM filter x analog watchdog status register
(DFSDM_FLTxAWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
26.8.12 DFSDM filter x analog watchdog clear flag register
(DFSDM_FLTxAWCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
26.8.13 DFSDM filter x extremes detector maximum register
(DFSDM_FLTxEXMAX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911
26.8.14 DFSDM filter x extremes detector minimum register
(DFSDM_FLTxEXMIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912
26.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR) . . 912
26.8.16 DFSDM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913

27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921

27.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
27.2 TSC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
27.3 TSC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
27.3.1 TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
27.3.2 Surface charge transfer acquisition overview . . . . . . . . . . . . . . . . . . . 922
27.3.3 Reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
27.3.4 Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . 925
27.3.5 Spread spectrum feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
27.3.6 Max count error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
27.3.7 Sampling capacitor I/O and channel I/O mode selection . . . . . . . . . . . 927
27.3.8 Acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
27.3.9 I/O hysteresis and analog switch control . . . . . . . . . . . . . . . . . . . . . . . 928
27.4 TSC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
27.5 TSC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
27.6 TSC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930
27.6.1 TSC control register (TSC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 930

26/2194 RM0438 Rev 7

RM0438 Contents

27.6.2 TSC interrupt enable register (TSC_IER) . . . . . . . . . . . . . . . . . . . . . . 932

27.6.3 TSC interrupt clear register (TSC_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 933
27.6.4 TSC interrupt status register (TSC_ISR) . . . . . . . . . . . . . . . . . . . . . . . 934
27.6.5 TSC I/O hysteresis control register (TSC_IOHCR) . . . . . . . . . . . . . . . 934
27.6.6 TSC I/O analog switch control register (TSC_IOASCR) . . . . . . . . . . . 935
27.6.7 TSC I/O sampling control register (TSC_IOSCR) . . . . . . . . . . . . . . . . 935
27.6.8 TSC I/O channel control register (TSC_IOCCR) . . . . . . . . . . . . . . . . . 936
27.6.9 TSC I/O group control status register (TSC_IOGCSR) . . . . . . . . . . . . 936
27.6.10 TSC I/O group x counter register (TSC_IOGxCR) . . . . . . . . . . . . . . . . 937
27.6.11 TSC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938

28 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . 940

28.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
28.2 RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
28.3 RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
28.3.1 RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
28.3.2 RNG internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
28.3.3 Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
28.3.4 RNG initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
28.3.5 RNG operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 946
28.3.6 RNG clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
28.3.7 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 947
28.3.8 RNG low-power usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
28.4 RNG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 948
28.5 RNG processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
28.6 RNG entropy source validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
28.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
28.6.2 Validation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
28.6.3 Data collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
28.7 RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
28.7.1 RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
28.7.2 RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
28.7.3 RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
28.7.4 RNG health test control register (RNG_HTCR) . . . . . . . . . . . . . . . . . . 954
28.7.5 RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955

RM0438 Rev 7 27/2194

53
Contents RM0438

29 AES hardware accelerator (AES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956

29.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
29.2 AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
29.3 AES implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
29.4 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
29.4.1 AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
29.4.2 AES internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
29.4.3 AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
29.4.4 AES procedure to perform a cipher operation . . . . . . . . . . . . . . . . . . . 963
29.4.5 AES decryption round key preparation . . . . . . . . . . . . . . . . . . . . . . . . 966
29.4.6 AES ciphertext stealing and data padding . . . . . . . . . . . . . . . . . . . . . . 966
29.4.7 AES task suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
29.4.8 AES basic chaining modes (ECB, CBC) . . . . . . . . . . . . . . . . . . . . . . . 967
29.4.9 AES counter (CTR) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
29.4.10 AES Galois/counter mode (GCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
29.4.11 AES Galois message authentication code (GMAC) . . . . . . . . . . . . . . 979
29.4.12 AES counter with CBC-MAC (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . 981
29.4.13 AES data registers and data swapping . . . . . . . . . . . . . . . . . . . . . . . . 987
29.4.14 AES key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
29.4.15 AES initialization vector registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
29.4.16 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 989
29.4.17 AES error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
29.5 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
29.6 AES processing latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
29.7 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
29.7.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
29.7.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
29.7.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 996
29.7.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 997
29.7.5 AES key register 0 (AES_KEYR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
29.7.6 AES key register 1 (AES_KEYR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
29.7.7 AES key register 2 (AES_KEYR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
29.7.8 AES key register 3 (AES_KEYR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
29.7.9 AES initialization vector register 0 (AES_IVR0) . . . . . . . . . . . . . . . . . . 999
29.7.10 AES initialization vector register 1 (AES_IVR1) . . . . . . . . . . . . . . . . . 1000
29.7.11 AES initialization vector register 2 (AES_IVR2) . . . . . . . . . . . . . . . . . 1000

28/2194 RM0438 Rev 7

RM0438 Contents

29.7.12 AES initialization vector register 3 (AES_IVR3) . . . . . . . . . . . . . . . . . 1000

29.7.13 AES key register 4 (AES_KEYR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
29.7.14 AES key register 5 (AES_KEYR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
29.7.15 AES key register 6 (AES_KEYR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
29.7.16 AES key register 7 (AES_KEYR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002
29.7.17 AES suspend registers (AES_SUSPxR) . . . . . . . . . . . . . . . . . . . . . . 1002
29.7.18 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003

30 Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005

30.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
30.2 HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
30.3 HASH implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
30.4 HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
30.4.1 HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
30.4.2 HASH internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
30.4.3 About secure hash algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
30.4.4 Message data feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
30.4.5 Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
30.4.6 Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
30.4.7 HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
30.4.8 HASH suspend/resume operations . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
30.4.9 HASH DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
30.4.10 HASH error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
30.5 HASH interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
30.6 HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
30.7 HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
30.7.1 HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
30.7.2 HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . 1020
30.7.3 HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
30.7.4 HASH digest registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
30.7.5 HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . 1023
30.7.6 HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
30.7.7 HASH context swap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
30.7.8 HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026

31 On-the-fly decryption engine (OTFDEC) . . . . . . . . . . . . . . . . . . . . . . 1028

RM0438 Rev 7 29/2194

53
Contents RM0438

31.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028

31.2 OTFDEC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
31.3 OTFDEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
31.3.1 OTFDEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
31.3.2 OTFDEC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
31.3.3 OTFDEC on-the-fly decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
31.3.4 AES in counter mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
31.3.5 Flow control management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
31.3.6 OTFDEC error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
31.4 OTFDEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
31.5 OTFDEC application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
31.5.1 OTFDEC initialization process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
31.5.2 OTFDEC and power management . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
31.5.3 Encrypting for OTFDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
31.5.4 OTFDEC key CRC source code . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1036
31.6 OTFDEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
31.6.1 OTFDEC control register (OTFDEC_CR) . . . . . . . . . . . . . . . . . . . . . 1037
31.6.2 OTFDEC privileged access control configuration register
(OTFDEC_PRIVCFGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
31.6.3 OTFDEC region x configuration register (OTFDEC_RxCFGR) . . . . . 1038
31.6.4 OTFDEC region x start address register
(OTFDEC_RxSTARTADDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1039
31.6.5 OTFDEC region x end address register (OTFDEC_RxENDADDR) . 1040
31.6.6 OTFDEC region x nonce register 0 (OTFDEC_RxNONCER0) . . . . . 1041
31.6.7 OTFDEC region x nonce register 1 (OTFDEC_RxNONCER1) . . . . . 1041
31.6.8 OTFDEC region x key register 0 (OTFDEC_RxKEYR0) . . . . . . . . . . 1042
31.6.9 OTFDEC region x key register 1 (OTFDEC_RxKEYR1) . . . . . . . . . . 1042
31.6.10 OTFDEC region x key register 2 (OTFDEC_RxKEYR2) . . . . . . . . . . 1043
31.6.11 OTFDEC region x key register 3 (OTFDEC_RxKEYR3) . . . . . . . . . . 1043
31.6.12 OTFDEC interrupt status register (OTFDEC_ISR) . . . . . . . . . . . . . . 1044
31.6.13 OTFDEC interrupt clear register (OTFDEC_ICR) . . . . . . . . . . . . . . . 1045
31.6.14 OTFDEC interrupt enable register (OTFDEC_IER) . . . . . . . . . . . . . . 1046
31.6.15 OTFDEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

32 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050

32.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
32.2 PKA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050

30/2194 RM0438 Rev 7

RM0438 Contents

32.3 PKA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050

32.3.1 PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
32.3.2 PKA internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
32.3.3 PKA reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
32.3.4 PKA public key acceleration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
32.3.5 Typical applications for PKA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
32.3.6 PKA procedure to perform an operation . . . . . . . . . . . . . . . . . . . . . . 1055
32.3.7 PKA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
32.4 PKA operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
32.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
32.4.2 Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . 1057
32.4.3 Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
32.4.4 Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
32.4.5 Modular and Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . 1059
32.4.6 Modular exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
32.4.7 Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
32.4.8 Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
32.4.9 Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
32.4.10 Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
32.4.11 Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
32.4.12 Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
32.4.13 RSA CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
32.4.14 Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063
32.4.15 ECC Fp scalar multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
32.4.16 ECDSA sign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
32.4.17 ECDSA verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
32.5 Example of configurations and processing times . . . . . . . . . . . . . . . . . 1068
32.5.1 Supported elliptic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
32.5.2 Computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
32.6 PKA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
32.7 PKA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
32.7.1 PKA control register (PKA_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
32.7.2 PKA status register (PKA_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.7.3 PKA clear flag register (PKA_CLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 1074
32.7.4 PKA RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
32.7.5 PKA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075

RM0438 Rev 7 31/2194

53
Contents RM0438

33 Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . 1076

33.1 TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
33.2 TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
33.3 TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
33.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
33.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
33.3.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1091
33.3.4 External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
33.3.5 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1094
33.3.6 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1098
33.3.7 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100
33.3.8 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1101
33.3.9 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
33.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
33.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
33.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
33.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
33.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
33.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1110
33.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
33.3.17 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
33.3.18 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1119
33.3.19 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
33.3.20 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
33.3.21 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
33.3.22 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
33.3.23 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
33.3.24 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
33.3.25 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
33.3.26 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
33.3.27 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
33.3.28 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
33.3.29 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135
33.4 TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1136
33.4.1 TIMx control register 1 (TIMx_CR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1136
33.4.2 TIMx control register 2 (TIMx_CR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . 1137

32/2194 RM0438 Rev 7

RM0438 Contents

33.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 1, 8) . . . . . . . . 1140

33.4.4 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 1, 8) . . . . . . . . 1142
33.4.5 TIMx status register (TIMx_SR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . 1144
33.4.6 TIMx event generation register (TIMx_EGR)(x = 1, 8) . . . . . . . . . . . . 1146
33.4.7 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147
33.4.8 TIMx capture/compare mode register 1 [alternate]
(TIMx_CCMR1)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148
33.4.9 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
33.4.10 TIMx capture/compare mode register 2 [alternate]
(TIMx_CCMR2)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152
33.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
33.4.12 TIMx counter (TIMx_CNT)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
33.4.13 TIMx prescaler (TIMx_PSC)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . 1157
33.4.14 TIMx auto-reload register (TIMx_ARR)(x = 1, 8) . . . . . . . . . . . . . . . . 1157
33.4.15 TIMx repetition counter register (TIMx_RCR)(x = 1, 8) . . . . . . . . . . . 1158
33.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 1, 8) . . . . . . . . . 1158
33.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 1, 8) . . . . . . . . . 1159
33.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 1, 8) . . . . . . . . . 1159
33.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 1, 8) . . . . . . . . . 1160
33.4.20 TIMx break and dead-time register
(TIMx_BDTR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
33.4.21 TIMx DMA control register (TIMx_DCR)(x = 1, 8) . . . . . . . . . . . . . . . 1164
33.4.22 TIMx DMA address for full transfer
(TIMx_DMAR)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
33.4.23 TIM1 option register 1 (TIM1_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
33.4.24 TIM8 option register 1 (TIM8_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
33.4.25 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
33.4.26 TIMx capture/compare register 5 (TIMx_CCR5)(x = 1, 8) . . . . . . . . . 1168
33.4.27 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8) . . . . . . . . . 1169
33.4.28 TIM1 option register 2 (TIM1_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
33.4.29 TIM1 option register 3 (TIM1_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
33.4.30 TIM8 option register 2 (TIM8_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
33.4.31 TIM8 option register 3 (TIM8_OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
33.4.32 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
33.4.33 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178

RM0438 Rev 7 33/2194

53
Contents RM0438

34 General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . 1181

34.1 TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1181
34.2 TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . .1181
34.3 TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . .1183
34.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
34.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
34.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
34.3.4 Capture/Compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
34.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
34.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
34.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
34.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
34.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
34.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
34.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
34.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . 1210
34.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
34.3.14 Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213
34.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
34.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
34.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1216
34.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . 1217
34.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
34.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
34.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
34.4 TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
34.4.1 TIMx control register 1 (TIMx_CR1)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1227
34.4.2 TIMx control register 2 (TIMx_CR2)(x = 2 to 5) . . . . . . . . . . . . . . . . . 1228
34.4.3 TIMx slave mode control register (TIMx_SMCR)(x = 2 to 5) . . . . . . . 1230
34.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 2 to 5) . . . . . . 1233
34.4.5 TIMx status register (TIMx_SR)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . 1234
34.4.6 TIMx event generation register (TIMx_EGR)(x = 2 to 5) . . . . . . . . . . 1235
34.4.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1236
34.4.8 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1238

34/2194 RM0438 Rev 7

RM0438 Contents

34.4.9 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)

(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1240
34.4.10 TIMx capture/compare mode register 2 [alternate] (TIMx_CCMR2)
(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1241
34.4.11 TIMx capture/compare enable register
(TIMx_CCER)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1242
34.4.12 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . 1243
34.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5) . . . . . . . . . . . . . . . . 1244
34.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5) . . . . . . . . . . . . . . . . . . . . . . . 1244
34.4.15 TIMx auto-reload register (TIMx_ARR)(x = 2 to 5) . . . . . . . . . . . . . . 1245
34.4.16 TIMx capture/compare register 1 (TIMx_CCR1)(x = 2 to 5) . . . . . . . 1245
34.4.17 TIMx capture/compare register 2 (TIMx_CCR2)(x = 2 to 5) . . . . . . . 1246
34.4.18 TIMx capture/compare register 3 (TIMx_CCR3)(x = 2 to 5) . . . . . . . 1246
34.4.19 TIMx capture/compare register 4 (TIMx_CCR4)(x = 2 to 5) . . . . . . . 1247
34.4.20 TIMx DMA control register (TIMx_DCR)(x = 2 to 5) . . . . . . . . . . . . . . 1248
34.4.21 TIMx DMA address for full transfer (TIMx_DMAR)(x = 2 to 5) . . . . . . 1248
34.4.22 TIM2 option register 1 (TIM2_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1248
34.4.23 TIM3 option register 1 (TIM3_OR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
34.4.24 TIM2 option register 2 (TIM2_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
34.4.25 TIM3 option register 2 (TIM3_OR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 1250
34.4.26 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251

35 General-purpose timers (TIM15/TIM16/TIM17) . . . . . . . . . . . . . . . . . 1254

35.1 TIM15/TIM16/TIM17 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
35.2 TIM15 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
35.3 TIM16/TIM17 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
35.4 TIM15/TIM16/TIM17 functional description . . . . . . . . . . . . . . . . . . . . . 1258
35.4.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1258
35.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
35.4.3 Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
35.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
35.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
35.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
35.4.7 PWM input mode (only for TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
35.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
35.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272
35.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
35.4.11 Combined PWM mode (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . . . 1274

RM0438 Rev 7 35/2194

53
Contents RM0438

35.4.12 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . 1275

35.4.13 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1277
35.4.14 Bidirectional break inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
35.4.15 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1284
35.4.16 Retriggerable one pulse mode (TIM15 only) . . . . . . . . . . . . . . . . . . . 1286
35.4.17 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
35.4.18 Timer input XOR function (TIM15 only) . . . . . . . . . . . . . . . . . . . . . . . 1288
35.4.19 External trigger synchronization (TIM15 only) . . . . . . . . . . . . . . . . . . 1289
35.4.20 Slave mode – combined reset + trigger mode . . . . . . . . . . . . . . . . . . 1291
35.4.21 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
35.4.22 Timer synchronization (TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
35.4.23 Using timer output as trigger for other timers (TIM16/TIM17) . . . . . . 1293
35.4.24 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1293
35.5 TIM15 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1294
35.5.1 TIM15 control register 1 (TIM15_CR1) . . . . . . . . . . . . . . . . . . . . . . . 1294
35.5.2 TIM15 control register 2 (TIM15_CR2) . . . . . . . . . . . . . . . . . . . . . . . 1295
35.5.3 TIM15 slave mode control register (TIM15_SMCR) . . . . . . . . . . . . . 1297
35.5.4 TIM15 DMA/interrupt enable register (TIM15_DIER) . . . . . . . . . . . . 1298
35.5.5 TIM15 status register (TIM15_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
35.5.6 TIM15 event generation register (TIM15_EGR) . . . . . . . . . . . . . . . . 1301
35.5.7 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
35.5.8 TIM15 capture/compare mode register 1 [alternate]
(TIM15_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
35.5.9 TIM15 capture/compare enable register (TIM15_CCER) . . . . . . . . . 1306
35.5.10 TIM15 counter (TIM15_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
35.5.11 TIM15 prescaler (TIM15_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
35.5.12 TIM15 auto-reload register (TIM15_ARR) . . . . . . . . . . . . . . . . . . . . . 1309
35.5.13 TIM15 repetition counter register (TIM15_RCR) . . . . . . . . . . . . . . . . 1310
35.5.14 TIM15 capture/compare register 1 (TIM15_CCR1) . . . . . . . . . . . . . . 1310
35.5.15 TIM15 capture/compare register 2 (TIM15_CCR2) . . . . . . . . . . . . . . 1311
35.5.16 TIM15 break and dead-time register (TIM15_BDTR) . . . . . . . . . . . . 1311
35.5.17 TIM15 DMA control register (TIM15_DCR) . . . . . . . . . . . . . . . . . . . . 1314
35.5.18 TIM15 DMA address for full transfer (TIM15_DMAR) . . . . . . . . . . . . 1314
35.5.19 TIM15 option register 1 (TIM15_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1315
35.5.20 TIM15 option register 2 (TIM15_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1315
35.5.21 TIM15 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317

36/2194 RM0438 Rev 7

RM0438 Contents

35.6 TIM16/TIM17 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1320

35.6.1 TIMx control register 1 (TIMx_CR1)(x = 16 to 17) . . . . . . . . . . . . . . . 1320
35.6.2 TIMx control register 2 (TIMx_CR2)(x = 16 to 17) . . . . . . . . . . . . . . . 1321
35.6.3 TIMx DMA/interrupt enable register (TIMx_DIER)(x = 16 to 17) . . . . 1322
35.6.4 TIMx status register (TIMx_SR)(x = 16 to 17) . . . . . . . . . . . . . . . . . . 1323
35.6.5 TIMx event generation register (TIMx_EGR)(x = 16 to 17) . . . . . . . . 1324
35.6.6 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1325
35.6.7 TIMx capture/compare mode register 1 [alternate] (TIMx_CCMR1)
(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
35.6.8 TIMx capture/compare enable register (TIMx_CCER)(x = 16 to 17) . 1328
35.6.9 TIMx counter (TIMx_CNT)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . . 1330
35.6.10 TIMx prescaler (TIMx_PSC)(x = 16 to 17) . . . . . . . . . . . . . . . . . . . . . 1331
35.6.11 TIMx auto-reload register (TIMx_ARR)(x = 16 to 17) . . . . . . . . . . . . 1331
35.6.12 TIMx repetition counter register (TIMx_RCR)(x = 16 to 17) . . . . . . . . 1332
35.6.13 TIMx capture/compare register 1 (TIMx_CCR1)(x = 16 to 17) . . . . . 1332
35.6.14 TIMx break and dead-time register (TIMx_BDTR)(x = 16 to 17) . . . . 1333
35.6.15 TIMx DMA control register (TIMx_DCR)(x = 16 to 17) . . . . . . . . . . . . 1335
35.6.16 TIMx DMA address for full transfer (TIMx_DMAR)(x = 16 to 17) . . . . 1336
35.6.17 TIM16 option register 1 (TIM16_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1336
35.6.18 TIM16 option register 2 (TIM16_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1337
35.6.19 TIM17 option register 1 (TIM17_OR1) . . . . . . . . . . . . . . . . . . . . . . . . 1338
35.6.20 TIM17 option register 2 (TIM17_OR2) . . . . . . . . . . . . . . . . . . . . . . . . 1339
35.6.21 TIM16/TIM17 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341

36 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343

36.1 TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
36.2 TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
36.3 TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
36.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1344
36.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
36.3.3 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
36.3.4 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
36.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350
36.4 TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1350
36.4.1 TIMx control register 1 (TIMx_CR1)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1350
36.4.2 TIMx control register 2 (TIMx_CR2)(x = 6 to 7) . . . . . . . . . . . . . . . . . 1352

RM0438 Rev 7 37/2194

53
Contents RM0438

36.4.3 TIMx DMA/Interrupt enable register (TIMx_DIER)(x = 6 to 7) . . . . . . 1352

36.4.4 TIMx status register (TIMx_SR)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . 1353
36.4.5 TIMx event generation register (TIMx_EGR)(x = 6 to 7) . . . . . . . . . . 1353
36.4.6 TIMx counter (TIMx_CNT)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . . 1353
36.4.7 TIMx prescaler (TIMx_PSC)(x = 6 to 7) . . . . . . . . . . . . . . . . . . . . . . . 1354
36.4.8 TIMx auto-reload register (TIMx_ARR)(x = 6 to 7) . . . . . . . . . . . . . . 1354
36.4.9 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355

37 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356

37.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
37.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1356
37.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
37.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
37.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
37.4.2 LPTIM pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
37.4.3 LPTIM trigger mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
37.4.4 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
37.4.5 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
37.4.6 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
37.4.7 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
37.4.8 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
37.4.9 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
37.4.10 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1364
37.4.11 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
37.4.12 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
37.4.13 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1366
37.4.14 Timer counter reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
37.4.15 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1367
37.4.16 Repetition Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
37.4.17 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
37.5 LPTIM low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
37.6 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
37.7 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372
37.7.1 LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . 1372
37.7.2 LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . 1373
37.7.3 LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . 1374

38/2194 RM0438 Rev 7

RM0438 Contents

37.7.4 LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . 1375

37.7.5 LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 1378
37.7.6 LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . 1379
37.7.7 LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . 1379
37.7.8 LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 1380
37.7.9 LPTIM1 option register (LPTIM1_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1380
37.7.10 LPTIM2 option register (LPTIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1381
37.7.11 LPTIM3 option register (LPTIM3_OR) . . . . . . . . . . . . . . . . . . . . . . . . 1381
37.7.12 LPTIM repetition register (LPTIM_RCR) . . . . . . . . . . . . . . . . . . . . . . 1382
37.7.13 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383

38 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1385

39 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386

39.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
39.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
39.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
39.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
39.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
39.3.3 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
39.3.4 Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
39.3.5 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
39.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1388
39.4 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
39.4.1 IWDG key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1389
39.4.2 IWDG prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . 1390
39.4.3 IWDG reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1391
39.4.4 IWDG status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392
39.4.5 IWDG window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . 1393
39.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394

40 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . 1395

40.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
40.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
40.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1395
40.3.1 WWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
40.3.2 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396

RM0438 Rev 7 39/2194

53
Contents RM0438

40.3.3 Controlling the down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396

40.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . 1396
40.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
40.4 WWDG interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398
40.5 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1398
40.5.1 WWDG control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . 1398
40.5.2 WWDG configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . 1399
40.5.3 WWDG status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . 1399
40.5.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399

41 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401

41.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
41.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
41.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
41.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1402
41.3.2 RTC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404
41.3.3 GPIOs controlled by the RTC and TAMP . . . . . . . . . . . . . . . . . . . . . . 1405
41.3.4 RTC secure protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
41.3.5 RTC privilege protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1409
41.3.6 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1410
41.3.7 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
41.3.8 Calendar ultra-low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
41.3.9 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1411
41.3.10 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1412
41.3.11 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 1413
41.3.12 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1415
41.3.13 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
41.3.14 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
41.3.15 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
41.3.16 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
41.3.17 Timestamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
41.3.18 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
41.3.19 Tamper and alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
41.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422
41.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
41.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425

40/2194 RM0438 Rev 7

RM0438 Contents

41.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1425

41.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1426
41.6.3 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . 1427
41.6.4 RTC initialization control and status register (RTC_ICSR) . . . . . . . . 1427
41.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . 1429
41.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . 1430
41.6.7 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
41.6.8 RTC privilege mode control register (RTC_PRIVCR) . . . . . . . . . . . . 1434
41.6.9 RTC secure mode control register (RTC_SMCR) . . . . . . . . . . . . . . . 1435
41.6.10 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . 1437
41.6.11 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . 1437
41.6.12 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . 1439
41.6.13 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . 1440
41.6.14 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . 1441
41.6.15 RTC timestamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 1442
41.6.16 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . 1442
41.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . 1444
41.6.18 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . 1445
41.6.19 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . 1446
41.6.20 RTC status register (RTC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
41.6.21 RTC non-secure masked interrupt status register (RTC_MISR) . . . . 1448
41.6.22 RTC secure masked interrupt status register (RTC_SMISR) . . . . . . 1449
41.6.23 RTC status clear register (RTC_SCR) . . . . . . . . . . . . . . . . . . . . . . . . 1450
41.6.24 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451

42 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . 1453

42.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
42.2 TAMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
42.3 TAMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454
42.3.1 TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454
42.3.2 TAMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
42.3.3 TAMP register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
42.3.4 TAMP secure protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
42.3.5 TAMP privilege protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
42.3.6 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1457
42.4 TAMP low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
42.5 TAMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462

RM0438 Rev 7 41/2194

53
Contents RM0438

42.6 TAMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462

42.6.1 TAMP control register 1 (TAMP_CR1) . . . . . . . . . . . . . . . . . . . . . . . . 1462
42.6.2 TAMP control register 2 (TAMP_CR2) . . . . . . . . . . . . . . . . . . . . . . . . 1464
42.6.3 TAMP control register 3 (TAMP_CR3) . . . . . . . . . . . . . . . . . . . . . . . . 1467
42.6.4 TAMP filter control register (TAMP_FLTCR) . . . . . . . . . . . . . . . . . . . 1468
42.6.5 TAMP active tamper control register 1 (TAMP_ATCR1) . . . . . . . . . . 1469
42.6.6 TAMP active tamper seed register (TAMP_ATSEEDR) . . . . . . . . . . . 1472
42.6.7 TAMP active tamper output register (TAMP_ATOR) . . . . . . . . . . . . . 1472
42.6.8 TAMP active tamper control register 2 (TAMP_ATCR2) . . . . . . . . . . 1473
42.6.9 TAMP secure mode register (TAMP_SMCR) . . . . . . . . . . . . . . . . . . . 1476
42.6.10 TAMP privilege mode control register (TAMP_PRIVCR) . . . . . . . . . . 1477
42.6.11 TAMP interrupt enable register (TAMP_IER) . . . . . . . . . . . . . . . . . . . 1478
42.6.12 TAMP status register (TAMP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
42.6.13 TAMP non-secure masked interrupt status register (TAMP_MISR) . . 1481
42.6.14 TAMP secure masked interrupt status register (TAMP_SMISR) . . . . 1482
42.6.15 TAMP status clear register (TAMP_SCR) . . . . . . . . . . . . . . . . . . . . . 1483
42.6.16 TAMP monotonic counter register (TAMP_COUNTR) . . . . . . . . . . . . 1485
42.6.17 TAMP configuration register (TAMP_CFGR) . . . . . . . . . . . . . . . . . . . 1485
42.6.18 TAMP backup x register (TAMP_BKPxR) . . . . . . . . . . . . . . . . . . . . . 1486
42.6.19 TAMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487

43 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . 1489

43.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
43.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
43.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
43.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
43.4.1 I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
43.4.2 I2C pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
43.4.3 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
43.4.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
43.4.5 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
43.4.6 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
43.4.7 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
43.4.8 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
43.4.9 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
43.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . 1522
43.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523

42/2194 RM0438 Rev 7

RM0438 Contents

43.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526

43.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . 1528
43.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
43.4.15 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . 1536
43.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
43.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
43.4.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
43.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
43.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
43.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
43.7.1 I2C control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1541
43.7.2 I2C control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1544
43.7.3 I2C own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . 1546
43.7.4 I2C own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . 1547
43.7.5 I2C timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
43.7.6 I2C timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . 1549
43.7.7 I2C interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . 1550
43.7.8 I2C interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . 1552
43.7.9 I2C PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1553
43.7.10 I2C receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . 1554
43.7.11 I2C transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 1554
43.7.12 I2C hardware configuration register (I2C_HWCFGR) . . . . . . . . . . . . 1554
43.7.13 I2C version register (I2C_VERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1555
43.7.14 I2C identification register (I2C_IPIDR) . . . . . . . . . . . . . . . . . . . . . . . . 1555
43.7.15 I2C size identification register (I2C_SIDR) . . . . . . . . . . . . . . . . . . . . 1556
43.7.16 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557

44 Universal synchronous/asynchronous receiver

transmitter (USART/UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
44.1 USART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1559
44.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1560
44.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
44.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
44.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
44.5.1 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
44.5.2 USART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1563

RM0438 Rev 7 43/2194

53
Contents RM0438

44.5.3 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1564

44.5.4 USART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
44.5.5 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1566
44.5.6 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
44.5.7 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
44.5.8 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1578
44.5.9 USART Auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1580
44.5.10 USART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 1582
44.5.11 USART Modbus communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
44.5.12 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
44.5.13 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1586
44.5.14 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1588
44.5.15 USART single-wire Half-duplex communication . . . . . . . . . . . . . . . . 1592
44.5.16 USART receiver timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1592
44.5.17 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
44.5.18 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
44.5.19 Continuous communication using USART and DMA . . . . . . . . . . . . . 1600
44.5.20 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1602
44.5.21 USART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
44.6 USART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
44.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
44.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
44.8.1 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 1610
44.8.2 USART control register 1 [alternate] (USART_CR1) . . . . . . . . . . . . . 1614
44.8.3 USART control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . 1617
44.8.4 USART control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . 1621
44.8.5 USART baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . 1626
44.8.6 USART guard time and prescaler register (USART_GTPR) . . . . . . . 1626
44.8.7 USART receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . 1627
44.8.8 USART request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . 1628
44.8.9 USART interrupt and status register [alternate] (USART_ISR) . . . . . 1629
44.8.10 USART interrupt and status register [alternate] (USART_ISR) . . . . . 1635
44.8.11 USART interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . 1640
44.8.12 USART receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . 1642
44.8.13 USART transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . 1642
44.8.14 USART prescaler register (USART_PRESC) . . . . . . . . . . . . . . . . . . 1643
44.8.15 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644

44/2194 RM0438 Rev 7

RM0438 Contents

45 Low-power universal asynchronous receiver

transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
45.1 LPUART introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1646
45.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
45.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
45.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
45.4.1 LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
45.4.2 LPUART signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
45.4.3 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
45.4.4 LPUART FIFOs and thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
45.4.5 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
45.4.6 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
45.4.7 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1659
45.4.8 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . 1660
45.4.9 LPUART multiprocessor communication . . . . . . . . . . . . . . . . . . . . . . 1661
45.4.10 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
45.4.11 LPUART single-wire Half-duplex communication . . . . . . . . . . . . . . . 1664
45.4.12 Continuous communication using DMA and LPUART . . . . . . . . . . . . 1664
45.4.13 RS232 Hardware flow control and RS485 Driver Enable . . . . . . . . . 1667
45.4.14 LPUART low-power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 1669
45.5 LPUART in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672
45.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
45.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1674
45.7.1 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 1674
45.7.2 LPUART control register 1 [alternate] (LPUART_CR1) . . . . . . . . . . . 1677
45.7.3 LPUART control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . 1680
45.7.4 LPUART control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . 1682
45.7.5 LPUART baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . 1685
45.7.6 LPUART request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . 1686
45.7.7 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 1686
45.7.8 LPUART interrupt and status register [alternate] (LPUART_ISR) . . . 1691
45.7.9 LPUART interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . 1694
45.7.10 LPUART receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . 1695
45.7.11 LPUART transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . 1695
45.7.12 LPUART prescaler register (LPUART_PRESC) . . . . . . . . . . . . . . . . 1696
45.7.13 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697

RM0438 Rev 7 45/2194

53
Contents RM0438

46 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699

46.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
46.2 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
46.3 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1699
46.4 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
46.4.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
46.4.2 Communications between one master and one slave . . . . . . . . . . . . 1701
46.4.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1703
46.4.4 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
46.4.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1705
46.4.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
46.4.7 Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1708
46.4.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1709
46.4.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1709
46.4.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719
46.4.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1720
46.4.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
46.4.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
46.4.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
46.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
46.6 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
46.6.1 SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1725
46.6.2 SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1727
46.6.3 SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1729
46.6.4 SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1730
46.6.5 SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1731
46.6.6 SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1731
46.6.7 SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1731
46.6.8 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733

47 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734

47.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
47.2 SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1734
47.3 SAI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
47.4 SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
47.4.1 SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735

46/2194 RM0438 Rev 7

RM0438 Contents

47.4.2 SAI pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737

47.4.3 Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
47.4.4 SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1738
47.4.5 Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
47.4.6 Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
47.4.7 Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
47.4.8 SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
47.4.9 Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
47.4.10 PDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
47.4.11 AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
47.4.12 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
47.4.13 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1763
47.4.14 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
47.4.15 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
47.4.16 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1770
47.5 SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
47.6 SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1773
47.6.1 SAI global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . 1773
47.6.2 SAI configuration register 1 (SAI_ACR1) . . . . . . . . . . . . . . . . . . . . . . 1773
47.6.3 SAI configuration register 1 (SAI_BCR1) . . . . . . . . . . . . . . . . . . . . . . 1776
47.6.4 SAI configuration register 2 (SAI_ACR2) . . . . . . . . . . . . . . . . . . . . . . 1779
47.6.5 SAI configuration register 2 (SAI_BCR2) . . . . . . . . . . . . . . . . . . . . . . 1781
47.6.6 SAI frame configuration register (SAI_AFRCR) . . . . . . . . . . . . . . . . . 1783
47.6.7 SAI frame configuration register (SAI_BFRCR) . . . . . . . . . . . . . . . . . 1784
47.6.8 SAI slot register (SAI_ASLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785
47.6.9 SAI slot register (SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1786
47.6.10 SAI interrupt mask register (SAI_AIM) . . . . . . . . . . . . . . . . . . . . . . . . 1787
47.6.11 SAI interrupt mask register (SAI_BIM) . . . . . . . . . . . . . . . . . . . . . . . . 1789
47.6.12 SAI status register (SAI_ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1790
47.6.13 SAI status register (SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792
47.6.14 SAI clear flag register (SAI_ACLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 1794
47.6.15 SAI clear flag register (SAI_BCLRFR) . . . . . . . . . . . . . . . . . . . . . . . . 1795
47.6.16 SAI data register (SAI_ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1796
47.6.17 SAI data register (SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1797
47.6.18 SAI PDM control register (SAI_PDMCR) . . . . . . . . . . . . . . . . . . . . . . 1797
47.6.19 SAI PDM delay register (SAI_PDMDLY) . . . . . . . . . . . . . . . . . . . . . . 1798
47.6.20 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801

RM0438 Rev 7 47/2194

53
Contents RM0438

48 Secure digital input/output MultiMediaCard interface (SDMMC) . . 1803

48.1 SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803
48.2 SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1803
48.3 SDMMC operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805
48.4 SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
48.4.1 SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
48.4.2 SDMMC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807
48.4.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807
48.4.4 SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1809
48.4.5 SDMMC AHB slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
48.4.6 SDMMC AHB master interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
48.4.7 AHB and SDMMC_CK clock relation . . . . . . . . . . . . . . . . . . . . . . . . . 1833
48.5 Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
48.5.1 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
48.5.2 CMD12 send timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
48.5.3 Sleep (CMD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1845
48.5.4 Interrupt mode (Wait-IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
48.5.5 Boot operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1847
48.5.6 Response R1b handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
48.5.7 Reset and card cycle power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1851
48.6 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
48.7 Ultra-high-speed phase I (UHS-I) voltage switch . . . . . . . . . . . . . . . . . 1853
48.8 SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
48.9 SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1858
48.9.1 SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 1858
48.9.2 SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 1859
48.9.3 SDMMC argument register (SDMMC_ARGR) . . . . . . . . . . . . . . . . . . 1861
48.9.4 SDMMC command register (SDMMC_CMDR) . . . . . . . . . . . . . . . . . 1861
48.9.5 SDMMC command response register (SDMMC_RESPCMDR) . . . . 1863
48.9.6 SDMMC response x register (SDMMC_RESPxR) . . . . . . . . . . . . . . 1864
48.9.7 SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . 1864
48.9.8 SDMMC data length register (SDMMC_DLENR) . . . . . . . . . . . . . . . 1865
48.9.9 SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 1866
48.9.10 SDMMC data counter register (SDMMC_DCNTR) . . . . . . . . . . . . . . 1867
48.9.11 SDMMC status register (SDMMC_STAR) . . . . . . . . . . . . . . . . . . . . . 1868
48.9.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 1871

48/2194 RM0438 Rev 7

RM0438 Contents

48.9.13 SDMMC mask register (SDMMC_MASKR) . . . . . . . . . . . . . . . . . . . . 1873

48.9.14 SDMMC acknowledgment timer register (SDMMC_ACKTIMER) . . . 1876
48.9.15 SDMMC data FIFO registers x (SDMMC_FIFORx) . . . . . . . . . . . . . . 1876
48.9.16 SDMMC DMA control register (SDMMC_IDMACTRLR) . . . . . . . . . . 1877
48.9.17 SDMMC IDMA buffer size register (SDMMC_IDMABSIZER) . . . . . . 1878
48.9.18 SDMMC IDMA buffer 0 base address register
(SDMMC_IDMABASE0R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1878
48.9.19 SDMMC IDMA buffer 1 base address register
(SDMMC_IDMABASE1R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1879
48.9.20 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1880

49 FD controller area network (FDCAN) . . . . . . . . . . . . . . . . . . . . . . . . . 1883

49.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
49.2 FDCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1885
49.3 FDCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886
49.3.1 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1887
49.3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888
49.3.3 Message RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
49.3.4 FIFO acknowledge handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1905
49.3.5 FDCAN Rx FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
49.3.6 FDCAN Tx buffer element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
49.3.7 FDCAN Tx event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910
49.3.8 FDCAN Standard message ID Filter element . . . . . . . . . . . . . . . . . . 1911
49.3.9 FDCAN Extended message ID filter element . . . . . . . . . . . . . . . . . . 1912
49.4 FDCAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1913
49.4.1 FDCAN core release register (FDCAN_CREL) . . . . . . . . . . . . . . . . . 1913
49.4.2 FDCAN endian register (FDCAN_ENDN) . . . . . . . . . . . . . . . . . . . . . 1913
49.4.3 FDCAN data bit timing and prescaler register (FDCAN_DBTP) . . . . 1914
49.4.4 FDCAN test register (FDCAN_TEST) . . . . . . . . . . . . . . . . . . . . . . . . 1915
49.4.5 FDCAN RAM watchdog register (FDCAN_RWD) . . . . . . . . . . . . . . . 1915
49.4.6 FDCAN CC control register (FDCAN_CCCR) . . . . . . . . . . . . . . . . . . 1916
49.4.7 FDCAN nominal bit timing and prescaler register (FDCAN_NBTP) . 1918
49.4.8 FDCAN timestamp counter configuration register (FDCAN_TSCC) . 1919
49.4.9 FDCAN timestamp counter value register (FDCAN_TSCV) . . . . . . . 1920
49.4.10 FDCAN timeout counter configuration register (FDCAN_TOCC) . . . 1921
49.4.11 FDCAN timeout counter value register (FDCAN_TOCV) . . . . . . . . . 1921
49.4.12 FDCAN error counter register (FDCAN_ECR) . . . . . . . . . . . . . . . . . 1922

RM0438 Rev 7 49/2194

53
Contents RM0438

49.4.13 FDCAN protocol status register (FDCAN_PSR) . . . . . . . . . . . . . . . . 1922

49.4.14 FDCAN transmitter delay compensation register (FDCAN_TDCR) . . 1925
49.4.15 FDCAN interrupt register (FDCAN_IR) . . . . . . . . . . . . . . . . . . . . . . . 1925
49.4.16 FDCAN interrupt enable register (FDCAN_IE) . . . . . . . . . . . . . . . . . 1928
49.4.17 FDCAN interrupt line select register (FDCAN_ILS) . . . . . . . . . . . . . . 1930
49.4.18 FDCAN interrupt line enable register (FDCAN_ILE) . . . . . . . . . . . . . 1931
49.4.19 FDCAN global filter configuration register (FDCAN_RXGFC) . . . . . . 1931
49.4.20 FDCAN extended ID and mask register (FDCAN_XIDAM) . . . . . . . . 1933
49.4.21 FDCAN high-priority message status register (FDCAN_HPMS) . . . . 1933
49.4.22 FDCAN Rx FIFO 0 status register (FDCAN_RXF0S) . . . . . . . . . . . . 1934
49.4.23 CAN Rx FIFO 0 acknowledge register (FDCAN_RXF0A) . . . . . . . . . 1935
49.4.24 FDCAN Rx FIFO 1 status register (FDCAN_RXF1S) . . . . . . . . . . . . 1935
49.4.25 FDCAN Rx FIFO 1 acknowledge register (FDCAN_RXF1A) . . . . . . 1936
49.4.26 FDCAN Tx buffer configuration register (FDCAN_TXBC) . . . . . . . . . 1936
49.4.27 FDCAN Tx FIFO/queue status register (FDCAN_TXFQS) . . . . . . . . 1937
49.4.28 FDCAN Tx buffer request pending register (FDCAN_TXBRP) . . . . . 1938
49.4.29 FDCAN Tx buffer add request register (FDCAN_TXBAR) . . . . . . . . . 1939
49.4.30 FDCAN Tx buffer cancellation request register (FDCAN_TXBCR) . . 1939
49.4.31 FDCAN Tx buffer transmission occurred register (FDCAN_TXBTO) 1940
49.4.32 FDCAN Tx buffer cancellation finished register (FDCAN_TXBCF) . . 1940
49.4.33 FDCAN Tx buffer transmission interrupt enable register
(FDCAN_TXBTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1941
49.4.34 FDCAN Tx buffer cancellation finished interrupt enable register
(FDCAN_ TXBCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1941
49.4.35 FDCAN Tx event FIFO status register (FDCAN_TXEFS) . . . . . . . . . 1942
49.4.36 FDCAN Tx event FIFO acknowledge register (FDCAN_TXEFA) . . . 1942
49.4.37 FDCAN CFG clock divider register (FDCAN_CKDIV) . . . . . . . . . . . . 1943
49.4.38 FDCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944

50 Universal serial bus full-speed device interface (USB) . . . . . . . . . . 1948

50.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
50.2 USB main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
50.3 USB implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1948
50.4 USB functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
50.4.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1950
50.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1951
50.5.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . 1951

50/2194 RM0438 Rev 7

RM0438 Contents

50.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1952

50.5.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1957
50.5.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1959
50.5.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
50.6 USB and USB SRAM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963
50.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1963
50.6.2 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1976
50.6.3 USB register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1979

51 USB Type-C™ / USB Power Delivery interface (UCPD) . . . . . . . . . . 1981

51.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
51.2 UCPD main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
51.3 UCPD implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1981
51.4 UCPD functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982
51.4.1 UCPD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
51.4.2 UCPD reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
51.4.3 Physical layer protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
51.4.4 UCPD BMC transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
51.4.5 UCPD BMC receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
51.4.6 UCPD Type-C pull-ups (Rp) and pull-downs (Rd) . . . . . . . . . . . . . . . 1995
51.4.7 UCPD Type-C voltage monitoring and de-bouncing . . . . . . . . . . . . . 1995
51.4.8 UCPD fast role swap (FRS) signaling and detection . . . . . . . . . . . . . 1995
51.4.9 UCPD DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
51.4.10 Wakeup from Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
51.4.11 UCPD programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996
51.5 UCPD low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
51.6 UCPD interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
51.7 UCPD registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2002
51.7.1 UCPD configuration register 1 (UCPD_CFGR1) . . . . . . . . . . . . . . . . 2002
51.7.2 UCPD configuration register 2 (UCPD_CFGR2) . . . . . . . . . . . . . . . . 2004
51.7.3 UCPD configuration register 3 (UCPD_CFGR3) . . . . . . . . . . . . . . . . 2004
51.7.4 UCPD control register (UCPD_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2005
51.7.5 UCPD interrupt mask register (UCPD_IMR) . . . . . . . . . . . . . . . . . . . 2007
51.7.6 UCPD status register (UCPD_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 2009
51.7.7 UCPD interrupt clear register (UCPD_ICR) . . . . . . . . . . . . . . . . . . . . 2012
51.7.8 UCPD Tx ordered set type register (UCPD_TX_ORDSETR) . . . . . . 2013

RM0438 Rev 7 51/2194

53
Contents RM0438

51.7.9 UCPD Tx payload size register (UCPD_TX_PAYSZR) . . . . . . . . . . . 2013

51.7.10 UCPD Tx data register (UCPD_TXDR) . . . . . . . . . . . . . . . . . . . . . . . 2014
51.7.11 UCPD Rx ordered set register (UCPD_RX_ORDSETR) . . . . . . . . . . 2014
51.7.12 UCPD Rx payload size register (UCPD_RX_PAYSZR) . . . . . . . . . . . 2015
51.7.13 UCPD receive data register (UCPD_RXDR) . . . . . . . . . . . . . . . . . . . 2016
51.7.14 UCPD Rx ordered set extension register 1
(UCPD_RX_ORDEXTR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2016
51.7.15 UCPD Rx ordered set extension register 2
(UCPD_RX_ORDEXTR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017
51.7.16 UCPD register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017

52 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020

52.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2020
52.2 DBG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
52.2.1 DBG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
52.2.2 DBG pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
52.2.3 DBG reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
52.2.4 DBG power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
52.2.5 Debug and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
52.2.6 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
52.2.7 Serial-wire and JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . 2024
52.2.8 JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
52.2.9 Serial-wire debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2027
52.2.10 Debug port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
52.2.11 Debug port register map and reset values . . . . . . . . . . . . . . . . . . . . . 2036
52.3 Access ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2037
52.3.1 Access port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2037
52.3.2 Access port register map and reset values . . . . . . . . . . . . . . . . . . . . 2042
52.4 ROM tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
52.4.1 MCU ROM table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046
52.4.2 MCU ROM table register map and reset values . . . . . . . . . . . . . . . . 2051
52.4.3 Processor ROM table registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2052
52.4.4 Processor ROM table register map and reset values . . . . . . . . . . . . 2057
52.5 Data watchpoint and trace unit (DWT) . . . . . . . . . . . . . . . . . . . . . . . . . 2058
52.5.1 DWT registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2059
52.5.2 DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 2074
52.6 Instrumentation trace macrocell (ITM) . . . . . . . . . . . . . . . . . . . . . . . . . 2076

52/2194 RM0438 Rev 7

RM0438 Contents

52.6.1 ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2077

52.6.2 ITM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 2086
52.7 Breakpoint unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2087
52.7.1 BPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2088
52.7.2 BPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
52.8 Embedded Trace Macrocell™ (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . 2096
52.8.1 ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2097
52.8.2 ETM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 2123
52.9 Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2127
52.9.1 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2128
52.9.2 TPIU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . 2139
52.10 Cross-trigger interface (CTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
52.10.1 CTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2142
52.10.2 CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154
52.11 Microcontroller debug unit (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . 2156
52.11.1 DBGMCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2157
52.11.2 DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . 2162
52.12 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2163

53 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2164

53.1 Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2165
53.2 Flash size data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2166
53.3 Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2167

54 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168

RM0438 Rev 7 53/2194

53
List of tables RM0438

List of tables

Table 1. Example of memory map security attribution versus SAU regions configuration . . . . . . . . 82
Table 2. Securable peripherals by TZSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 3. TrustZone-aware peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 5. SRAM2 organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 6. Boot modes when TrustZone is disabled (TZEN=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 7. Boot modes when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 8. Boot space versus RDP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 9. Configuring security attributes with IDAU and SAU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 10. MPCWMx instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 11. MPCBBx instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 12. DMA channel usage (security) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 13. DMA channel usage (privilege) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 14. Secure Alternate function between peripherals and allocated I/Os . . . . . . . . . . . . . . . . . 116
Table 15. Summary of the I/Os that cannot be connected to a non-secure peripheral when secure 116
Table 16. Summary of the I/Os that can be secured and connected to a non-secure peripheral. . . 117
Table 17. Internal tampers in TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 18. Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 19. Accelerated cryptographic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 20. Main product lifecycle transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 21. Typical product lifecycle phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 22. Debug protection with RDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 23. Software intellectual property protection with RDP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 24. MPCWMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 25. MPCBBx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 26. GTZC_TZSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 27. GTZC_MPCBB1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 28. GTZC_MPCBB2 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 29. GTZC_TZIC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 30. Flash module - 512 KB dual bank organization (64 bits read width). . . . . . . . . . . . . . . . . 179
Table 31. Flash module - 512 KB single bank organization (128 bits read width) . . . . . . . . . . . . . . 179
Table 32. Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . 181
Table 33. User option byte organization mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 34. Default secure option bytes after TZEN activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 35. Secure watermark-based area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 36. Secure, HDP protections summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 37. Flash security state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 38. User accesses via bootloader or JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 39. Non-secure peripherals, IRQn and IOs for bootloader execution . . . . . . . . . . . . . . . . . . . 202
Table 40. WRP protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 41. Flash memory readout protection status (TZEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 42. Access status versus protection level and execution modes when TZEN=0 . . . . . . . . . . 207
Table 43. Flash memory readout protection status (TZEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 44. Access status versus protection level and execution modes when TZEN=1 . . . . . . . . . . 209
Table 45. Flash access versus RDP level when TrustZone is active (TZEN=1) . . . . . . . . . . . . . . . 212
Table 46. Flash access versus RDP level when TrustZone is disabled (TZEN=0) . . . . . . . . . . . . . 212
Table 47. Flash mass erase versus RDP level when TrustZone is active (TZEN = 1) . . . . . . . . . . . 213

54/2194 RM0438 Rev 7

RM0438 List of tables

Table 48. Flash system memory, RSS and OTP accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 49. Flash registers access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 50. Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 51. Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 52. ICACHE features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 53. TAG memory dimensioning parameters
for n-way set associative operating mode (default) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 54. TAG memory dimensioning parameters
for direct mapped cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Table 55. ICACHE cacheability for AHB transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 56. Configurations of product memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 57. ICACHE remap region size, base address and remap address . . . . . . . . . . . . . . . . . . . . 251
Table 58. ICACHE interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 59. ICACHE register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Table 60. SMPS modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 61. SMPS step down converter operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Table 62. SMPS step down converter versus low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Table 63. PVM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 64. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Table 65. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 66. Low-power run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Table 67. Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Table 68. Low-power sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Table 69. Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 70. Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Table 71. Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Table 72. Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Table 73. Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
Table 74. PWR Security configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 75. PWR register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Table 76. RCC input/output signals connected to package pins or balls . . . . . . . . . . . . . . . . . . . . . 329
Table 77. Clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Table 78. RCC security configuration summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
Table 79. Interrupt sources and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 80. RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Table 81. CRS features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Table 82. Effect of low-power modes on CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Table 83. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Table 84. CRS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
Table 85. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
Table 86. GPIO secured bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Table 87. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Table 88. TrustZone security and privilege register accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Table 89. BOOSTEN and ANASWVDD set/reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Table 90. SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Table 91. STM32L552xx and STM32L562xx peripherals interconnect matrix . . . . . . . . . . . . . . . . 472
Table 92. DMA1 and DMA2 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Table 93. DMA internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
Table 94. Programmable data width and endian behavior (when PINC = MINC = 1) . . . . . . . . . . . 491
Table 95. DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
Table 96. DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
Table 97. DMAMUX instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

RM0438 Rev 7 55/2194

63
List of tables RM0438

Table 98. DMAMUX: assignment of multiplexer inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . 511

Table 99. DMAMUX: assignment of trigger inputs to resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Table 100. DMAMUX: assignment of synchronization inputs to resources . . . . . . . . . . . . . . . . . . . . 513
Table 101. DMAMUX signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Table 102. DMAMUX interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Table 103. DMAMUX register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Table 104. STM32L552xx and STM32L562xx vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
Table 105. EXTI pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Table 106. EVG pin overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 107. EXTI line connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Table 108. EXTI event input configurations and register control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
Table 109. Masking functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Table 110. Register protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Table 111. EXTI register map sections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Table 112. Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 561
Table 113. CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Table 114. CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Table 115. NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Table 116. NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Table 117. NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Table 118. NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
Table 119. Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Table 120. Non-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
Table 121. 16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Table 122. Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Table 123. 16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579
Table 124. NOR Flash/PSRAM: example of supported memories
and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580
Table 125. FMC_BCRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Table 126. FMC_BTRx bitfields (mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Table 127. FMC_BCRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Table 128. FMC_BTRx bitfields (mode A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Table 129. FMC_BWTRx bitfields (mode A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
Table 130. FMC_BCRx bitfields (mode 2/B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Table 131. FMC_BTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Table 132. FMC_BWTRx bitfields (mode 2/B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
Table 133. FMC_BCRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Table 134. FMC_BTRx bitfields (mode C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Table 135. FMC_BWTRx bitfields (mode C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Table 136. FMC_BCRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Table 137. FMC_BTRx bitfields (mode D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Table 138. FMC_BWTRx bitfields (mode D). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
Table 139. FMC_BCRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Table 140. FMC_BTRx bitfields (Muxed mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
Table 141. FMC_BCRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 602
Table 142. FMC_BTRx bitfields (Synchronous multiplexed read mode) . . . . . . . . . . . . . . . . . . . . . . 603
Table 143. FMC_BCRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 604
Table 144. FMC_BTRx bitfields (Synchronous multiplexed write mode) . . . . . . . . . . . . . . . . . . . . . . 605
Table 145. Programmable NAND Flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Table 146. 8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Table 147. 16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616
Table 148. Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

56/2194 RM0438 Rev 7

RM0438 List of tables

Table 149. ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626

Table 150. FMC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
Table 151. OCTOSPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Table 152. Command/address phase description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Table 153. Address alignment cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Table 154. OCTOSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
Table 155. OCTOSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Table 156. ADC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Table 157. ADC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Table 158. ADC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Table 159. Configuring the trigger polarity for regular external triggers . . . . . . . . . . . . . . . . . . . . . . . 705
Table 160. Configuring the trigger polarity for injected external triggers . . . . . . . . . . . . . . . . . . . . . . 705
Table 161. ADC1/2 - External triggers for regular channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Table 162. ADC1/2 - External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Table 163. TSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Table 164. Offset computation versus data resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Table 165. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Table 166. Analog watchdog 1 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Table 167. Analog watchdog 2 and 3 comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Table 168. Maximum output results versus N and M (gray cells indicate truncation). . . . . . . . . . . . . 738
Table 169. Oversampler operating modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Table 170. ADC interrupts per each ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761
Table 171. DELAY bits versus ADC resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Table 172. ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Table 173. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794
Table 174. ADC register map and reset values (master and slave ADC
common registers) offset = 0x300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Table 175. DAC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
Table 176. DAC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
Table 177. DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803
Table 178. Sample and refresh timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
Table 179. Channel output modes summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Table 180. Effect of low-power modes on DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
Table 181. DAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
Table 182. DAC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
Table 183. VREF buffer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Table 184. VREFBUF trimming data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Table 185. VREFBUF register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
Table 186. COMP1 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Table 187. COMP1 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Table 188. COMP2 input plus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Table 189. COMP2 input minus assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
Table 190. Comparator behavior in the low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
Table 191. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
Table 192. COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
Table 193. Operational amplifier possible connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
Table 194. Operating modes and calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
Table 195. Effect of low-power modes on the OPAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
Table 196. OPAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
Table 197. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Table 198. DFSDM external pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

RM0438 Rev 7 57/2194

63
List of tables RM0438

Table 199. DFSDM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868

Table 200. DFSDM triggers connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
Table 201. DFSDM break connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
Table 202. Filter maximum output resolution (peak data values from filter output)
for some FOSR values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Table 203. Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data) . . . . 884
Table 204. DFSDM interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
Table 205. DFSDM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
Table 206. Acquisition sequence summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Table 207. Spread spectrum deviation versus AHB clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . 926
Table 208. I/O state depending on its mode and IODEF bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Table 209. Effect of low-power modes on TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Table 210. Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
Table 211. TSC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
Table 212. RNG internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Table 213. RNG interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Table 214. RNG configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Table 215. RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Table 216. AES internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Table 217. CTR mode initialization vector definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Table 218. GCM last block definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Table 219. GCM mode IVI bitfield initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Table 220. Initialization of AES_IVRx registers in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Table 221. Key endianness in AES_KEYRx registers (128- or 256-bit key length) . . . . . . . . . . . . . . 989
Table 222. AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
Table 223. Processing latency for ECB, CBC and CTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
Table 224. Processing latency for GCM and CCM (in clock cycles). . . . . . . . . . . . . . . . . . . . . . . . . . 992
Table 225. AES register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Table 226. HASH internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Table 227. Hash processor outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
Table 228. HASH interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
Table 229. Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
Table 230. HASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
Table 231. OTFDEC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Table 232. OTFDEC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033
Table 233. OTFDEC register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047
Table 234. Internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Table 235. PKA integer arithmetic functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Table 236. PKA prime field (Fp) elliptic curve functions list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Table 237. Montgomery parameter computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Table 238. Modular addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Table 239. Modular subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Table 240. Montgomery multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Table 241. Modular exponentiation (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Table 242. Modular exponentiation (fast mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
Table 243. Modular inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Table 244. Modular reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Table 245. Arithmetic addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
Table 246. Arithmetic subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Table 247. Arithmetic multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062
Table 248. Arithmetic comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1062

58/2194 RM0438 Rev 7

RM0438 List of tables

Table 249. CRT exponentiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1063

Table 250. Point on elliptic curve Fp check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Table 251. ECC Fp scalar multiplication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Table 252. ECC Fp scalar multiplication (Fast Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065
Table 253. ECDSA sign - Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Table 254. ECDSA sign - Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1066
Table 255. Extended ECDSA sign (extra outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Table 256. ECDSA verification (inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Table 257. ECDSA verification (outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Table 258. Family of supported curves for ECC operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
Table 259. Modular exponentiation computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Table 260. ECC scalar multiplication computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Table 261. ECDSA signature average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
Table 262. ECDSA verification average computation times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Table 263. Point on elliptic curve Fp check average computation times . . . . . . . . . . . . . . . . . . . . . 1071
Table 264. Montgomery parameters average computation times. . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Table 265. PKA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
Table 266. PKA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1075
Table 267. Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
Table 268. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Table 269. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Table 270. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142
Table 271. Output control bits for complementary OCx and OCxN channels with break feature . . . 1156
Table 272. TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1176
Table 273. TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
Table 274. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1215
Table 275. TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
Table 276. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1243
Table 277. TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
Table 278. Break protection disarming conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
Table 279. TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
Table 280. Output control bits for complementary OCx and OCxN channels with break feature
(TIM15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308
Table 281. TIM15 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317
Table 282. Output control bits for complementary OCx and OCxN channels with break feature
(TIM16/17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1330
Table 283. TIM16/TIM17 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1341
Table 284. TIMx register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
Table 285. STM32L552xx and STM32L562xx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
Table 286. LPTIM input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
Table 287. LPTIM internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
Table 288. LPTIM1 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1358
Table 289. LPTIM2 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
Table 290. LPTIM3 external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1359
Table 291. Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1361
Table 292. Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1368
Table 293. Effect of low-power modes on the LPTIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Table 294. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1371
Table 295. LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
Table 296. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394
Table 297. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
Table 298. RTC input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404

RM0438 Rev 7 59/2194

63
List of tables RM0438

Table 299. RTC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1404

Table 300. RTC interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Table 301. RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1405
Table 302. RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1407
Table 303. Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422
Table 304. RTC pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422
Table 305. Non-secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
Table 306. Secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1424
Table 307. RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1451
Table 308. TAMP input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
Table 309. TAMP internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
Table 310. TAMP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
Table 311. Minimum ATPER value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1460
Table 312. Effect of low-power modes on TAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
Table 313. TAMP pins functionality over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
Table 314. Non-secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
Table 315. Secure interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462
Table 316. TAMP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
Table 317. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Table 318. I2C input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
Table 319. I2C internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
Table 320. Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
Table 321. I2C-SMBus specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . 1497
Table 322. I2C configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
Table 323. I2C-SMBus specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
Table 324. Examples of timing settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
Table 325. Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
Table 326. Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
Table 327. SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
Table 328. SMBus with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527
Table 329. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Table 330. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . 1528
Table 331. Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Table 332. Effect of low-power modes on the I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1539
Table 333. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
Table 334. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1557
Table 335. STM32L552xx and STM32L562xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
Table 336. USART / LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1561
Table 337. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
Table 338. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1579
Table 339. Tolerance of the USART receiver when BRR[3:0] is different from 0000 . . . . . . . . . . . . 1580
Table 340. USART frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1585
Table 341. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
Table 342. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
Table 343. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644
Table 344. STM32L552xx and STM32L562xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
Table 345. USART / LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
Table 346. Error calculation for programmed baud rates at lpuart_ker_ck_pres = 32,768 KHz. . . . 1659
Table 347. Error calculation for programmed baud rates at fCK = 100 MHz . . . . . . . . . . . . . . . . . . 1660
Table 348. Tolerance of the LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1661

60/2194 RM0438 Rev 7

RM0438 List of tables

Table 350. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672

Table 351. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1673
Table 352. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1697
Table 353. STM32L552xx and STM32L562xx SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . 1700
Table 354. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724
Table 355. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1733
Table 356. STM32L5 Series SAI features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1735
Table 357. SAI internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
Table 358. SAI input/output pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1737
Table 359. External synchronization selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1739
Table 360. MCLK_x activation conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1745
Table 361. Clock generator programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1748
Table 362. TDM settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755
Table 363. Allowed TDM frame configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1757
Table 364. SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
Table 365. Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
Table 366. Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762
Table 367. SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1771
Table 368. SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1801
Table 369. SDMMC operation modes SD & SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805
Table 370. SDMMC operation modes e•MMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
Table 371. SDMMC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807
Table 372. SDMMC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1807
Table 373. SDMMC Command and data phase selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
Table 374. Command token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1814
Table 375. Short response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Table 376. Short response without CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Table 377. Long response with CRC token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1815
Table 378. Specific Commands overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1816
Table 379. Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
Table 380. Command path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1817
Table 381. Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
Table 382. Data path status flags and clear bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825
Table 383. Data path error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1827
Table 384. Data FIFO access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1828
Table 385. Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1829
Table 386. Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1830
Table 387. AHB and SDMMC_CK clock frequency relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833
Table 388. SDIO special operation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1834
Table 389. 4-bit mode Start, interrupt, and CRC-status Signaling detection . . . . . . . . . . . . . . . . . . 1838
Table 390. CMD12 use cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
Table 391. SDMMC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1856
Table 392. Response type and SDMMC_RESPxR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1864
Table 393. SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1880
Table 394. CAN subsystem I/O signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883
Table 395. DLC coding in FDCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1891
Table 396. Possible configurations for Frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1903
Table 397. Rx FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Table 398. Rx FIFO element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1906
Table 399. Tx buffer and FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Table 400. Tx buffer element description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1908
Table 401. Tx event FIFO element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910

RM0438 Rev 7 61/2194

63
List of tables RM0438

Table 402. Tx event FIFO element description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1910

Table 403. Standard Message ID Filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Table 404. Standard Message ID Filter element Field description . . . . . . . . . . . . . . . . . . . . . . . . . . 1911
Table 405. Extended Message ID Filter element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
Table 406. Extended Message ID Filter element field description . . . . . . . . . . . . . . . . . . . . . . . . . . 1912
Table 407. FDCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1944
Table 408. STM32L552xx and STM32L562xx USB implementation . . . . . . . . . . . . . . . . . . . . . . . . 1948
Table 409. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1958
Table 410. Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1958
Table 411. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1960
Table 412. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1961
Table 413. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
Table 414. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
Table 415. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1974
Table 416. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1975
Table 417. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1978
Table 418. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1979
Table 419. UCPD implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1982
Table 420. UCPD signals on pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
Table 421. UCPD internal signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
Table 422. 4b5b Symbol Encoding Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1985
Table 423. Ordered sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
Table 424. Validation of ordered sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
Table 425. Data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988
Table 426. Coding for ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx . . . . . . . 1997
Table 427. Type-C sequence (source: 3A); cable/sink connected (Rd on CC1; Ra on CC2) . . . . . 1998
Table 428. Effect of low power modes on the UCPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000
Table 429. UCPD interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2001
Table 430. UCPD register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2017
Table 431. JTAG/Serial-wire debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
Table 432. Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
Table 433. Single Wire Trace port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2022
Table 434. Authentication signal states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023
Table 435. JTAG-DP data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2026
Table 436. Packet request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
Table 437. ACK response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
Table 438. Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2028
Table 439. Debug port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2036
Table 440. Access port register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2042
Table 441. MCU ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2043
Table 442. Processor ROM table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2044
Table 443. MCU ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2051
Table 444. CPU ROM table register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2057
Table 445. DWT register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2074
Table 446. CPU1 ITM register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2086
Table 447. CPU1 BPU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2095
Table 448. ETM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2123
Table 449. CPU1 TPIU register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2139
Table 450. CTI inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
Table 451. CTI outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141
Table 452. CTI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2154
Table 453. DBGMCU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2162

62/2194 RM0438 Rev 7

RM0438 List of tables

Table 454. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2168

RM0438 Rev 7 63/2194

63
List of figures RM0438

List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Figure 2. Memory map based on IDAU mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 3. Secure/non-secure partitioning using TrustZone® technology . . . . . . . . . . . . . . . . . . . . . 105
Figure 4. Sharing memory map between CPU in secure and non-secure state . . . . . . . . . . . . . . . 107
Figure 5. Secure world transition and memory partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 6. Global TrustZone® framework and TrustZone® awareness . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 7. Flash memory TrustZone® protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 8. Flash memory secure hide protection (HDP) area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 9. Key management principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 10. Device lifecycle security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 11. RDP level transition scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Figure 12. Collaborative development principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 13. External Flash memory protection using SFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure 14. GTZC in Armv8-M subsystem block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Figure 15. GTZC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 16. RDP level transition scheme when TrustZone is disabled (TZEN=0l) . . . . . . . . . . . . . . . 211
Figure 17. RDP level transition scheme when TrustZone is enabled (TZEN=1) . . . . . . . . . . . . . . . . 211
Figure 18. ICACHE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 19. ICACHE TAG and data memories functional view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 20. ICACHE remapping address mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 21. STM32L552xx and STM32L562xx power supply overview . . . . . . . . . . . . . . . . . . . . . . . 264
Figure 22. STM32L552xxxP and STM32L562xxxP power supply overview . . . . . . . . . . . . . . . . . . . 265
Figure 23. STM32L552xxxQ and STM32L562xxxQ power supply overview . . . . . . . . . . . . . . . . . . . 266
Figure 24. SMPS step down converter power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Figure 25. Internal main regulator overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Figure 26. Brown-out reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Figure 27. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Figure 28. Low-power modes possible transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Figure 29. Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Figure 30. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 31. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 32. Frequency measurement with TIM15 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 33. Frequency measurement with TIM16 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 34. Frequency measurement with TIM17 in capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 343
Figure 35. CRS block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Figure 36. CRS counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Figure 37. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 38. Basic structure of a 5-Volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 39. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Figure 40. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 41. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 42. High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
Figure 43. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Figure 44. DMAMUX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Figure 45. Synchronization mode of the DMAMUX request line multiplexer channel . . . . . . . . . . . . 518
Figure 46. Event generation of the DMA request line multiplexer channel . . . . . . . . . . . . . . . . . . . . 518
Figure 47. EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
Figure 48. Configurable event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

64/2194 RM0438 Rev 7

RM0438 List of figures

Figure 49. Direct event trigger logic CPU wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

Figure 50. EXTI mux GPIO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
Figure 51. CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Figure 52. FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Figure 53. FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
Figure 54. Mode 1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
Figure 55. Mode 1 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
Figure 56. Mode A read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
Figure 57. Mode A write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
Figure 58. Mode 2 and mode B read access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Figure 59. Mode 2 write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Figure 60. Mode B write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Figure 61. Mode C read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Figure 62. Mode C write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
Figure 63. Mode D read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
Figure 64. Mode D write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Figure 65. Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595
Figure 66. Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Figure 67. Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
Figure 68. Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
Figure 69. Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
Figure 70. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 602
Figure 71. Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 604
Figure 72. NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 618
Figure 73. Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Figure 74. OCTOSPI block diagram in octal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 75. OCTOSPI block diagram in quad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
Figure 76. OCTOSPI block diagram in dual-quad configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Figure 77. SDR read command in octal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Figure 78. DTR read in Octal-SPI mode with DQS (Macronix mode) example . . . . . . . . . . . . . . . . . 636
Figure 79. SDR write command in Octo-SPI mode example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 80. DTR write in Octal-SPI mode (Macronix mode) example . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 81. Example of HyperBus read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 82. HyperBus write operation with initial latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 83. HyperBus read operation with additional latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
Figure 84. HyperBus write operation with additional latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 85. HyperBus write operation with no latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 86. HyperBus read operation page crossing with latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 87. NCS when CKMODE = 0 (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Figure 88. NCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 89. NCS when CKMODE = 1 in DTR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 90. NCS when CKMODE = 1 with an abort (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . 655
Figure 91. ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
Figure 92. ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Figure 93. ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691
Figure 94. ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Figure 95. ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
Figure 96. Updating the ADC calibration factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 97. Mixing single-ended and differential channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
Figure 98. Enabling / disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698
Figure 99. Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
Figure 100. Stopping ongoing regular conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

RM0438 Rev 7 65/2194

75
List of figures RM0438

Figure 101. Stopping ongoing regular and injected conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

Figure 102. Triggers sharing between ADC master and ADC slave . . . . . . . . . . . . . . . . . . . . . . . . . . 706
Figure 103. Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Figure 104. Example of JSQR queue of context (sequence change) . . . . . . . . . . . . . . . . . . . . . . . . . 712
Figure 105. Example of JSQR queue of context (trigger change) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Figure 106. Example of JSQR queue of context with overflow before conversion . . . . . . . . . . . . . . . 713
Figure 107. Example of JSQR queue of context with overflow during conversion . . . . . . . . . . . . . . . 713
Figure 108. Example of JSQR queue of context with empty queue (case JQM=0). . . . . . . . . . . . . . . 714
Figure 109. Example of JSQR queue of context with empty queue (case JQM=1). . . . . . . . . . . . . . . 715
Figure 110. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion. . . . . . . . . . . . . . . . . . . . . . . 715
Figure 111. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 112. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).
Case when JADSTP occurs outside an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . 716
Figure 113. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1) . . . . . . . . . . . . . . . . . . 717
Figure 114. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0). . . . . . . . . . . . . . . . . . . . 717
Figure 115. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1). . . . . . . . . . . . . . . . . . . . 718
Figure 116. Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 117. Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 118. Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 119. Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 120. Right alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 121. Right alignment (offset enabled, signed value). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 122. Left alignment (offset disabled, unsigned value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 123. Left alignment (offset enabled, signed value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725
Figure 124. Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 125. AUTODLY=1, regular conversion in continuous mode, software trigger . . . . . . . . . . . . . 729
Figure 126. AUTODLY=1, regular HW conversions interrupted by injected conversions
(DISCEN=0; JDISCEN=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730
Figure 127. AUTODLY=1, regular HW conversions interrupted by injected conversions . . . . . . . . . . . . .
(DISCEN=1, JDISCEN=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 128. AUTODLY=1, regular continuous conversions interrupted by injected conversions . . . . 732
Figure 129. AUTODLY=1 in auto- injected mode (JAUTO=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
Figure 130. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 131. ADCy_AWDx_OUT signal generation (on all regular channels). . . . . . . . . . . . . . . . . . . . 735
Figure 132. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software) . . . . . . . . . . 736
Figure 133. ADCy_AWDx_OUT signal generation (on a single regular channel) . . . . . . . . . . . . . . . . 736
Figure 134. ADCy_AWDx_OUT signal generation (on all injected channels) . . . . . . . . . . . . . . . . . . . 736
Figure 135. 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 136. Numerical example with 5-bit shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 137. Triggered regular oversampling mode (TROVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Figure 138. Regular oversampling modes (4x ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 139. Regular and injected oversampling modes used simultaneously . . . . . . . . . . . . . . . . . . . 741
Figure 140. Triggered regular oversampling with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 141. Oversampling in auto-injected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 142. Dual ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Figure 143. Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 745
Figure 144. Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 747
Figure 145. Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 748
Figure 146. Interleaved mode on 1 channel in single conversion mode: dual ADC mode. . . . . . . . . . 749

66/2194 RM0438 Rev 7

RM0438 List of figures

Figure 147. Interleaved conversion with injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

Figure 148. Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Figure 149. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 751
Figure 150. Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Figure 151. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Figure 152. Interleaved single channel CH0 with injected sequence CH11, CH12 . . . . . . . . . . . . . . . 753
Figure 153. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Figure 154. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
Figure 155. DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 754
Figure 156. DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 755
Figure 157. DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Figure 158. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757
Figure 159. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758
Figure 160. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
Figure 161. Dual-channel DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Figure 162. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Figure 163. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
Figure 164. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 802
Figure 165. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805
Figure 166. DAC conversion (SW trigger enabled) with LFSR wave generation . . . . . . . . . . . . . . . . 805
Figure 167. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
Figure 168. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 806
Figure 169. DAC Sample and hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809
Figure 170. Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Figure 171. Window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
Figure 172. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Figure 173. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Figure 174. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853
Figure 175. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854
Figure 176. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used . . . . . . . . . . . . 855
Figure 177. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
Figure 178. Single DFSDM block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Figure 179. Input channel pins redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Figure 180. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
Figure 181. Clock absence timing diagram for SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
Figure 182. Clock absence timing diagram for Manchester coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
Figure 183. First conversion for Manchester coding (Manchester synchronization) . . . . . . . . . . . . . . 877
Figure 184. DFSDM_CHyDATINR registers operation modes and assignment . . . . . . . . . . . . . . . . . 881
Figure 185. Example: Sinc3 filter response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
Figure 186. TSC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
Figure 187. Surface charge transfer analog I/O group structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
Figure 188. Sampling capacitor voltage variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
Figure 189. Charge transfer acquisition sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
Figure 190. Spread spectrum variation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Figure 191. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
Figure 192. NIST SP800-90B entropy source model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
Figure 193. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Figure 194. AES block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
Figure 195. ECB encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

RM0438 Rev 7 67/2194

75
List of figures RM0438

Figure 196. CBC encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 960

Figure 197. CTR encryption and decryption principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
Figure 198. GCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Figure 199. GMAC authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Figure 200. CCM encryption and authentication principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
Figure 201. Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
Figure 202. ECB encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Figure 203. ECB decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
Figure 204. CBC encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Figure 205. CBC decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
Figure 206. ECB/CBC encryption (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
Figure 207. ECB/CBC decryption (Mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
Figure 208. Message construction in CTR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Figure 209. CTR encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Figure 210. CTR decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Figure 211. Message construction in GCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Figure 212. GCM authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Figure 213. Message construction in GMAC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Figure 214. GMAC authentication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Figure 215. Message construction in CCM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Figure 216. CCM mode authenticated encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Figure 217. 128-bit block construction with respect to data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Figure 218. DMA transfer of a 128-bit data block during input phase . . . . . . . . . . . . . . . . . . . . . . . . . 990
Figure 219. DMA transfer of a 128-bit data block during output phase . . . . . . . . . . . . . . . . . . . . . . . . 990
Figure 220. HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
Figure 221. Message data swapping feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Figure 222. HASH suspend/resume mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Figure 223. OTFDEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
Figure 224. Typical OTFDEC use in a SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
Figure 225. AES CTR decryption flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Figure 226. OTFDEC flow control overview (dual burst read request) . . . . . . . . . . . . . . . . . . . . . . . 1032
Figure 227. PKA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
Figure 228. Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Figure 229. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1079
Figure 230. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1079
Figure 231. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Figure 232. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Figure 233. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 234. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
Figure 235. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . 1083
Figure 236. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . 1083
Figure 237. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 238. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
Figure 239. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Figure 240. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
Figure 241. Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . 1087
Figure 242. Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . 1088
Figure 243. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089
Figure 244. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1089
Figure 245. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
Figure 246. Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . 1090
Figure 247. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1091

68/2194 RM0438 Rev 7

RM0438 List of figures

Figure 248. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1092
Figure 249. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Figure 250. TIM1 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Figure 251. TIM8 ETR input circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
Figure 252. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1094
Figure 253. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
Figure 254. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
Figure 255. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
Figure 256. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
Figure 257. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1098
Figure 258. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
Figure 259. Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . 1099
Figure 260. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . 1100
Figure 261. Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . 1100
Figure 262. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
Figure 263. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1104
Figure 264. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1105
Figure 265. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1106
Figure 266. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1108
Figure 267. Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
Figure 268. 3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . 1110
Figure 269. Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
Figure 270. Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . 1111
Figure 271. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1112
Figure 272. Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
Figure 273. Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . 1116
Figure 274. PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . 1117
Figure 275. PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
Figure 276. Output redirection (BRK2 request not represented) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Figure 277. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
Figure 278. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
Figure 279. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
Figure 280. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Figure 281. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . 1125
Figure 282. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . 1126
Figure 283. Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Figure 284. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1129
Figure 285. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1130
Figure 286. Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
Figure 287. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Figure 288. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Figure 289. General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
Figure 290. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1184
Figure 291. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1184
Figure 292. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
Figure 293. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Figure 294. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
Figure 295. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
Figure 296. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . 1187
Figure 297. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . 1188
Figure 298. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189
Figure 299. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189

RM0438 Rev 7 69/2194

75
List of figures RM0438

Figure 300. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190

Figure 301. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Figure 302. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1191
Figure 303. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . 1192
Figure 304. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193
Figure 305. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . 1193
Figure 306. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Figure 307. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . 1194
Figure 308. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . 1195
Figure 309. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1196
Figure 310. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Figure 311. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Figure 312. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
Figure 313. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Figure 314. Capture/Compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . 1200
Figure 315. Capture/Compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
Figure 316. Output stage of Capture/Compare channel (channel 1) . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Figure 317. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Figure 318. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
Figure 319. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Figure 320. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Figure 321. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . 1208
Figure 322. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
Figure 323. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
Figure 324. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
Figure 325. Retriggerable one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
Figure 326. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . 1215
Figure 327. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . 1216
Figure 328. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1217
Figure 329. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
Figure 330. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219
Figure 331. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . 1220
Figure 332. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1220
Figure 333. Master/slave connection example with 1 channel only timers . . . . . . . . . . . . . . . . . . . . 1221
Figure 334. Gating TIM2 with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
Figure 335. Gating TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
Figure 336. Triggering TIM2 with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
Figure 337. Triggering TIM2 with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Figure 338. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
Figure 339. TIM15 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
Figure 340. TIM16/TIM17 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Figure 341. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1259
Figure 342. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1259
Figure 343. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
Figure 344. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
Figure 345. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Figure 346. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1262
Figure 347. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Figure 348. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1263

70/2194 RM0438 Rev 7

RM0438 List of figures

Figure 349. Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . 1265
Figure 350. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1266
Figure 351. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
Figure 352. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
Figure 353. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . 1268
Figure 354. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
Figure 355. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . 1269
Figure 356. Output stage of capture/compare channel (channel 2 for TIM15) . . . . . . . . . . . . . . . . . 1269
Figure 357. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
Figure 358. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1273
Figure 359. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1274
Figure 360. Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1275
Figure 361. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1276
Figure 362. Dead-time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . 1276
Figure 363. Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . 1277
Figure 364. Break circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1279
Figure 365. Output behavior in response to a break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
Figure 366. Output redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1283
Figure 367. Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1285
Figure 368. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1286
Figure 369. Measuring time interval between edges on 2 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
Figure 370. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289
Figure 371. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290
Figure 372. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1291
Figure 373. Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1343
Figure 374. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . 1345
Figure 375. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . 1345
Figure 376. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1346
Figure 377. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
Figure 378. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1347
Figure 379. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Figure 380. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1348
Figure 381. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1349
Figure 382. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . 1350
Figure 383. Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1357
Figure 384. Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
Figure 385. LPTIM output waveform, single counting mode configuration
when repetition register content is different than zero (with PRELOAD = 1) . . . . . . . . . 1362
Figure 386. LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
Figure 387. LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . 1363
Figure 388. Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
Figure 389. Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1369
Figure 390. Continuous counting mode when repetition register LPTIM_RCR
different from zero (with PRELOAD = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1370
Figure 391. IRTIM internal hardware connections with TIM16 and TIM17 . . . . . . . . . . . . . . . . . . 1385
Figure 392. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
Figure 393. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1396
Figure 394. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
Figure 395. RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403

RM0438 Rev 7 71/2194

75
List of figures RM0438

Figure 396. TAMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1454

Figure 397. Backup registers secure protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1456
Figure 398. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
Figure 399. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1493
Figure 400. Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
Figure 401. I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1498
Figure 402. Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1499
Figure 403. Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1500
Figure 404. Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1503
Figure 405. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1505
Figure 406. Transfer sequence flowchart for I2C slave transmitter,
NOSTRETCH= 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
Figure 407. Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Figure 408. Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . 1508
Figure 409. Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . 1509
Figure 410. Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1509
Figure 411. Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Figure 412. Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
Figure 413. 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
Figure 414. 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1514
Figure 415. Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . 1515
Figure 416. Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . 1516
Figure 417. Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1517
Figure 418. Transfer sequence flowchart for I2C master receiver for N≤255 bytes . . . . . . . . . . . . . 1519
Figure 419. Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . 1520
Figure 420. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
Figure 421. Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1525
Figure 422. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . 1529
Figure 423. Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . 1530
Figure 424. Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . 1531
Figure 425. Bus transfer diagrams for SMBus slave receiver (SBC=1). . . . . . . . . . . . . . . . . . . . . . . 1532
Figure 426. Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 1533
Figure 427. Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
Figure 428. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1562
Figure 429. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1565
Figure 430. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1567
Figure 431. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
Figure 432. Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1571
Figure 433. usart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1574
Figure 434. Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
Figure 435. Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1576
Figure 436. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1583
Figure 437. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1584
Figure 438. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1587
Figure 439. Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1588
Figure 440. USART example of synchronous master transmission. . . . . . . . . . . . . . . . . . . . . . . . . . 1589
Figure 441. USART data clock timing diagram in synchronous master mode
(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1589
Figure 442. USART data clock timing diagram in synchronous master mode
(M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1590
Figure 443. USART data clock timing diagram in synchronous slave mode

72/2194 RM0438 Rev 7

RM0438 List of figures

(M bits = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1591

Figure 444. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1593
Figure 445. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1595
Figure 446. IrDA SIR ENDEC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
Figure 447. IrDA data modulation (3/16) - Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1599
Figure 448. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1601
Figure 449. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
Figure 450. Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
Figure 451. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
Figure 452. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
Figure 453. Wakeup event verified (wakeup event = address match, FIFO disabled) . . . . . . . . . . . 1607
Figure 454. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
Figure 455. LPUART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Figure 456. LPUART word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
Figure 457. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Figure 458. TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
Figure 459. lpuart_ker_ck clock divider block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1658
Figure 460. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
Figure 461. Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1663
Figure 462. Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1665
Figure 463. Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1666
Figure 464. Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
Figure 465. RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1667
Figure 466. RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1668
Figure 467. Wakeup event verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
Figure 468. Wakeup event not verified (wakeup event = address match,
FIFO disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1671
Figure 469. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1700
Figure 470. Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1701
Figure 471. Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1702
Figure 472. Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1703
Figure 473. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1704
Figure 474. Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1705
Figure 475. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1706
Figure 476. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1707
Figure 477. Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1708
Figure 478. Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712
Figure 479. Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715
Figure 480. Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1716
Figure 481. Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1717
Figure 482. Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1718
Figure 483. NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1721
Figure 484. TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722
Figure 485. SAI functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1736
Figure 486. Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1740
Figure 487. FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 1742
Figure 488. FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1743
Figure 489. Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 1744
Figure 490. First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1744

RM0438 Rev 7 73/2194

75
List of figures RM0438

Figure 491. Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1746

Figure 492. PDM typical connection and timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1750
Figure 493. Detailed PDM interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1751
Figure 494. Start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752
Figure 495. SAI_ADR format in TDM, 32-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1753
Figure 496. SAI_ADR format in TDM, 16-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1754
Figure 497. SAI_ADR format in TDM, 8-bit slot width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1755
Figure 498. AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1758
Figure 499. Example of typical AC’97 configuration on devices featuring at least
2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1759
Figure 500. SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1760
Figure 501. SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1761
Figure 502. Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 1765
Figure 503. Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 1766
Figure 504. Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1767
Figure 505. Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
Figure 506. FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1768
Figure 507. SDMMC “no response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Figure 508. SDMMC (multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Figure 509. SDMMC (multiple) block write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1804
Figure 510. SDMMC (sequential) stream read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805
Figure 511. SDMMC (sequential) stream write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1805
Figure 512. SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1806
Figure 513. SDMMC Command and data phase relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1808
Figure 514. Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1810
Figure 515. Command/response path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1811
Figure 516. Command path state machine (CPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812
Figure 517. Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1818
Figure 518. DDR mode data packet clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1819
Figure 519. DDR mode CRC status / boot acknowledgment clocking. . . . . . . . . . . . . . . . . . . . . . . . 1819
Figure 520. Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820
Figure 521. CLKMUX unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1831
Figure 522. Asynchronous interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
Figure 523. Synchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1835
Figure 524. Synchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1836
Figure 525. Asynchronous interrupt period data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837
Figure 526. Asynchronous interrupt period data write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1837
Figure 527. Clock stop with SDMMC_CK for DS, HS, SDR12, SDR25. . . . . . . . . . . . . . . . . . . . . . . 1840
Figure 528. Clock stop with SDMMC_CK for DDR50, SDR50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1840
Figure 529. Read Wait with SDMMC_CK < 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1841
Figure 530. Read Wait with SDMMC_CK > 50 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1842
Figure 531. CMD12 stream timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1844
Figure 532. CMD5 Sleep Awake procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1846
Figure 533. Normal boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1848
Figure 534. Alternative boot mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1849
Figure 535. Command response R1b busy signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1850
Figure 536. SDMMC state control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1851
Figure 537. Card cycle power / power up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1852
Figure 538. CMD11 signal voltage switch sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1853
Figure 539. Voltage switch transceiver typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1855
Figure 540. CAN subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1884
Figure 541. FDCAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1886

74/2194 RM0438 Rev 7

RM0438 List of figures

Figure 542. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1888

Figure 543. Transceiver delay measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893
Figure 544. Pin control in Bus monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1894
Figure 545. Pin control in Loop Back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1896
Figure 546. Message RAM configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1897
Figure 547. Standard Message ID filter path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1900
Figure 548. Extended Message ID filter path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1901
Figure 549. USB peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1949
Figure 550. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . 1953
Figure 551. UCPD block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1983
Figure 552. Clock division and timing elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1984
Figure 553. K-code transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1987
Figure 554. Transmit order for various sizes of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1988
Figure 555. Packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Figure 556. Line format of Hard Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1989
Figure 557. Line format of Cable Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1990
Figure 558. BIST test data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
Figure 559. BIST Carrier Mode 2 frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1991
Figure 560. UCPD BMC transmitter architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1992
Figure 561. UCPD BMC receiver architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1993
Figure 562. Block diagram of debug support infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2021
Figure 563. JTAG TAP state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2025
Figure 564. CoreSight topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2045
Figure 565. Trace port interface unit (TPIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2128
Figure 566. Embedded cross trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2141

RM0438 Rev 7 75/2194

75
Documentation conventions RM0438

1 Documentation conventions

1.1 General information

The STM32L552xx and STM32L562xx devices have an Arm®(a) Cortex®-M33 core.

1.2 List of abbreviations for registers

The following abbreviations(b) are used in register descriptions:

read/write (rw) Software can read and write to this bit.

read-only (r) Software can only read this bit.
write-only (w) Software can only write to this bit. Reading this bit returns the reset value.
read/clear write0 (rc_w0) Software can read as well as clear this bit by writing 0. Writing 1 has no
effect on the bit value.
read/clear write1 (rc_w1) Software can read as well as clear this bit by writing 1. Writing 0 has no
effect on the bit value.
read/clear write (rc_w) Software can read as well as clear this bit by writing to the register. The
value written to this bit is not important.
read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to 0.
Writing this bit has no effect on the bit value.
read/set by read (rs_r) Software can read this bit. Reading this bit automatically sets it to 1.
Writing this bit has no effect on the bit value.
read/set (rs) Software can read as well as set this bit. Writing 0 has no effect on the bit
value.
read/write once (rwo) Software can only write once to this bit and can also read it at any time.
Only a reset can return the bit to its reset value.
toggle (t) The software can toggle this bit by writing 1. Writing 0 has no effect.
read-only write trigger (rt_w1) Software can read this bit. Writing 1 triggers an event but has no effect on
the bit value.
Reserved (Res.) Reserved bit, must be kept at reset value.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
b. This is an exhaustive list of all abbreviations applicable to STMicroelectronics microcontrollers, some of
them may not be used in the current document.

76/2194 RM0438 Rev 7

RM0438 Documentation conventions

1.3 Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
• Word: data of 32-bit length.
• Half-word: data of 16-bit length.
• Byte: data of 8-bit length.
• IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
• ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
• Option bytes: product configuration bits stored in the Flash memory.
• OBL: option byte loader.
• AHB: advanced high-performance bus.
• APB: advanced peripheral bus.
• RAZ: read-as-zero.
• WI: writes ignored.
• RAZ/WI: read-as-zero, writes ignored.

1.4 Availability of peripherals

For availability of peripherals and their number across all sales types, refer to the particular
device datasheet.

RM0438 Rev 7 77/2194

77
Memory and bus architecture RM0438

2 Memory and bus architecture

The STM32L552xx and STM32L562xx devices are ultra-low-power microcontrollers

(STM32L5 Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core.
They operate at frequencies up to 110 MHz.
The Cortex®-M33 processor delivers a high computational performance with low-power
consumption and an advanced response to interrupts. it features:
• Arm® TrustZone® technology, using the Armv8-M main extension supporting secure
and non-secure states
• Memory protection units (MPUs), supporting 8 regions for secure world and 8 regions
for non-secure world.
• Configurable security attribution unit (SAU) supporting up to 8 memory regions
• Floating-point arithmetic functionality with support for single precision arithmetic
The Cortex®-M33 processor supports the following bus interfaces:
• System AHB bus: the system AHB (S-AHB) bus interface is used for any instruction
fetch and data access to the memory-mapped SRAM, peripherals, external RAM and
external devices, or Vendor_SYS regions of the Armv8-M memory map.
• Code AHB bus: the Code AHB (C-AHB) bus interface is used for any instruction fetch
and data access to the code region of the Armv8-M memory map.

2.1 System architecture

The main system consists of 32-bit multilayer AHB bus matrix that interconnects:
• Up to six masters:
– Fast C-bus, connecting Cortex®-M33 with TrustZone and FPU core C-bus to the
internal memories through the ART (instruction cache)
– Slow C-bus, connecting Cortex®-M33 with TrustZone and FPU core C-bus to the
external memories through the ART (instruction cache)
– Cortex®-M33 with TrustZone and FPU core S-bus
– DMA1
– DMA2
– SDMMC1 bus
• Up to seven slaves:
– Internal Flash memory on the fast C-bus
– Internal SRAM1 (192 Kbytes)
– Internal SRAM2 (64 Kbytes)
– AHB1 peripherals including AHB to APB bridges and APB peripherals (connected
to APB1 and APB2)
– AHB2 peripherals
– Flexible static memory controller (FSMC)
– OCTOSPI1 memory controller

78/2194 RM0438 Rev 7

RM0438 Memory and bus architecture

The bus matrix provides access from a master to a slave, enabling concurrent access and
efficient operation even when several high-speed peripherals work simultaneously. This
architecture is shown in Figure 1:

Figure 1. System architecture

CORTEX®-M33
with TrustZone mainline DMA1 DMA2 SDMMC1 Legend
and FPU Bus multiplexer Master Interface
C-bus

Slave Interface
S-bus

MPCBBx: Memory protection controller block-based

8 KB ART (I cache) MPCWMx: Memory protection controller Watermark
Fast-bus
Slow-bus

FLASH
512 KB

MPCBB1 SRAM1

MPCBB2 SRAM2

AHB1
peripherals

AHB2
OTFDEC peripherals

MPCWM1 OctoSPI1

MPCWM2 FSMC
MPCWM3
BusMatrix-S

When remapped by ICACHE MSv49345V2

2.1.1 Fast C-bus

This bus connects the C-bus of the Cortex®-M33 core to the BusMatrix via the instruction
cache. This bus is used for instruction fetch and data access to the internal memories
mapped in code region. The target of this bus are the internal Flash and internal SRAMs.

2.1.2 Slow C-bus

This bus connects the C-bus of the Cortex®-M33 core to the BusMatrix via the instruction
cache. This bus is used for instruction fetch and data access to the external memories
mapped in code region. The target of this bus are the external memories (FSMC and
OCTOSPI).

2.1.3 S-bus
This bus connects the system bus of the Cortex®-M33 core to the BusMatrix. This bus is
used by the core to access data located in a peripheral or SRAM area. The targets of this
bus are the internal SRAMs, the AHB1 peripherals including the APB1 and APB2

RM0438 Rev 7 79/2194

86
Memory and bus architecture RM0438

peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the
FSMC.
The SRAM2 is also accessible on this bus to allow continuous mapping with SRAM1.

2.1.4 DMA-bus
This bus connects the AHB master interface of the DMA to the BusMatrix.The targets of this
bus are the SRAM1 and SRAM2, the AHB1 peripherals including the APB1 and APB2
peripherals, the AHB2 peripherals and the external memories through the OCTOSPI or the
FSMC.

2.1.5 SDMMC controller DMA bus

This bus connects the SDMMC1 DMA master interface to the BusMatrix. This bus is used
only by the SDMMC1 DMA to load/store data from/to memory. The targets of this bus are
data memories: internal SRAMs (SRAM1, SRAM2), internal Flash memory or external
memories through FSMC or OCTOSPI.

2.1.6 BusMatrix
The BusMatrix manages the access arbitration between masters. The arbitration uses a
Round Robin algorithm. The BusMatrix is composed of up to six masters (CPU AHB,
system bus, Fast C-bus, Slow C-bus, DMA1, DMA2, SDMMC1) and up to seven slaves
(FLASH, SRAM1, SRAM2, AHB1 (including APB1 and APB2), AHB2, OCTOSTPI1 and
FSMC).

AHB/APB bridges
The two AHB/APB bridges provide full synchronous connections between the AHB and the
two APB buses, allowing flexible selection of the peripheral frequency.
Refer to Section 2.3.2: Memory map and register boundary addresses on page 88 for the
address mapping of the peripherals connected to this bridge.
After each device reset, all peripheral clocks are disabled (except for the SRAM1/2 and
Flash memory interface). Before using a peripheral the user has to enable its clock in the
RCC_AHBxENR and the RCC_APBxENR registers.
Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into
a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.

2.2 TrustZone® security architecture

The security architecture is based on Arm® TrustZone® with the Armv8-M Main Extension.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
When the TrustZone is enabled, the SAU (security attribution unit) and IDAU
(implementation defined attribution unit) define the memory access permissions based on
secure or non-secure state of the processor.
• SAU: Up to eight SAU configurable regions are available for security attribution.
• IDAU: It provides a first memory partition between non-secure and non-secure-callable
regions. The IDAU memory map partition is not configurable and fixed by hardware

80/2194 RM0438 Rev 7

RM0438 Memory and bus architecture

implementation (refer to Figure 2). It is then combined with the results from the SAU
security attribution and the most secure level between the two is selected.
Based on IDAU security attribution, the Flash, system SRAMs and peripherals memory
space is aliased twice for secure and non-secure state. However, the external memories
space is not aliased.
Table 1 shows an example of typical eight SAU regions mapping based on IDAU regions.
The user can split and choose the secure, non-secure or NSC regions for external
memories as needed.

RM0438 Rev 7 81/2194

86
Memory and bus architecture RM0438

Table 1. Example of memory map security attribution versus SAU regions configuration(1)
SAU security
Region IDAU security Final security
Address range attribution typical
description attribution attribution
configuration

Code - external 0x0000_0000 Secure or non- Secure or non-

Non-secure
memories 0x07FF_FFFF secure or NSC secure or NSC

0x0800_0000
Non-secure Non-secure Non-secure
Code - Flash and 0x0BFF_FFFF
SRAM 0x0C00_0000
NSC Secure or NSC Secure or NSC
0x0FFF_FFFF
0x1000_0000
Non-secure Non-secure Non-secure
Code - external 0x17FF_FFFF
memories 0x1800_0000
Non-secure Non-secure Non-secure
0x1FFF_FFFF
0x2000_0000
Non-secure Non-secure Non-secure
0x2FFF_FFFFF
SRAM
0x3000_0000
NSC Secure or NSC Secure or NSC
0x3FFF_FFFFF
0x4000_0000
Non-secure Non-secure Non-secure
0x4FFF_FFFFF
Peripherals
0x5000_0000
NSC Secure or NSC Secure or NSC
0x5FFF_FFFFF
0x6000_0000 Secure or non- Secure or non-
External memories Non-secure
0xDFFF_FFFF secure or NSC secure or NSC
1. Different colors highlights the different configurations
Pink: Non-secure
Green: NSC (non-secure callable)
Lighter green: Secure or non-secure or NSC

82/2194 RM0438 Rev 7

RM0438 Memory and bus architecture

2.2.1 Default TrustZone security state

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR, the
default system security state is:
• CPU:
– Cortex-M33 is in secure state after reset. The boot address must be in secure
address (i.e. belonging to the secure part of the memory map).
• Memory map:
– SAU: is fully secure after reset. Consequently, the memory map is fully secure. Up
to 8 SAU configurable regions are available for security attribution.
• Flash:
– Flash secure regions are defined by watermark user options.
– Flash interface blocks (i.e. pages) are all Non-Secure after reset (but the
watermark configuration supersedes the block-based one in case of overlap).
• SRAMs:
– All SRAMs are secure after reset. MPCBB (memory protection block based
controller) is configured as fully secure.
• External memories:
– FSMC, OCTOSPI banks are secure after reset. MPCWM (memory protection
watermark based controller) is secure
• All peripherals (except GPIOs) are non secure after reset. For TrustZone-aware
peripherals, their secure configuration registers are secure.
Note: Refer to Table 2 and Table 3 for a list of Securable and TrustZone-aware peripherals.
• All GPIO are secure after reset.
• Interrupts:
– NVIC: All interrupts are secure after reset. NVIC is banked for secure and non-
secure state.
– TZIC: All illegal access interrupts are disabled after reset.

2.2.2 TrustZone peripheral classification

When the TrustZone security is active, a peripheral can be either Securable or TrustZone-
aware type as defined below:
• Securable: a peripheral is protected by an AHB/APB firewall gate that is controlled from
TZSC controller to define security properties.
• TrustZone-aware: a peripheral connected directly to AHB or APB bus and
implementing a specific TrustZone behavior such as a subset of registers being
secure. TrustZone-aware AHB masters always drive HNONSEC signal according to
their security mode (as CM33 core and DMA).
Refer to Section 5.2.1: GTZC TrustZone system architecture
Table 2 and Table 3 summarize the list of Securable and TrustZone aware peripherals within
the system.

RM0438 Rev 7 83/2194

86
Memory and bus architecture RM0438

Table 2. Securable peripherals by TZSC

Bus Peripheral

OCTOSPI1 registers
AHB3
FMC registers
SDMMC1
PKA
RNG
AHB 2
HASH
AES
ADC
ICACHE registers
AHB1 TSC
CRC
DFSDM1
SAI2
SAI1
TIM17
TIM16
TIM15
APB2
USART1
TIM8
SPI1
TIM1
COMP
VREFBUF

84/2194 RM0438 Rev 7

RM0438 Memory and bus architecture

Table 2. Securable peripherals by TZSC (continued)

Bus Peripheral

UCPD1
USB FS
FDCAN1
LPTIM3
LPTIM2
I2C4
LPUART1
LPTIM1
OPAMP
DAC1/DAC2
CRS
I2C3
I2C2
I2C1
APB1
UART5
UART4
USART3
USART2
SPI3
SPI2
IWDG
WWDG
TIM7
TIM6
TIM5
TIM4
TIM3
TIM2

RM0438 Rev 7 85/2194

86
Memory and bus architecture RM0438

Table 3. TrustZone-aware peripherals

Bus Peripheral

GPIOH
GPIOG
GPIOF
GPIOE
AHB2 GPIOD
GPIOC
GPIOB
GPIOA
OTFDEC1(1)
GTZC
EXTIT
Flash memory
AHB1 RCC
DMAMUX1
DMA2
DMA1
APB2 SYSCFG
PWR
APB1 RTC
TAMP
1. Always secure when TZEN = 1.

86/2194 RM0438 Rev 7

RM0438

2.3 Memory organization

2.3.1 Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.

RM0438 Rev 7 87/2194

87
 RM0438

2.3.2 Memory map and register boundary addresses

Figure 2. Memory map based on IDAU mapping

0x6000 0000
Reserved
0x5402 2000
AHB3
0x5402 0000
Reserved
0x520C 8000
AHB2
0x5202 0000
0xFFFF FFFF Reserved
Cortex M33 0x5003 3000
Non-secure AHB1
0x5002 0000
0xE000 0000 Reserved
0x5001 6800
0xA000 0000 APB2
0x5001 0000
Reserved
OCTOSPI1 bank 0x5000 E000
Non-secure APB1
0x9000 0000 0x5000 0000

FMC bank 3
Non-secure
0x5000 0000
0x8000 0000 Reserved
0x4402 2000
0x7000 0000 AHB3
0x4402 0000
FMC bank 1 Reserved
0x420C 8400
Non-secure AHB2
0x6000 0000 0x4202 0000
Reserved
0x4003 3400
AHB1
0x4002 0000
Peripherals Reserved
0x4001 6800
Non-secure callable APB2
0x5000 0000 0x4001 0000
Reserved
0x4000 E000
APB1
0x4000 0000
Peripherals
Non-secure
0x4000 0000 0x1000 0000
Reserved
0x0FF8 27FF
RSS
SRAM2 0x0FF8 0000
Reserved
Non-secure callable 0x0E04 0000
SRAM2
0x3003 0000 0x0E03 0000
SRAM1 SRAM1
0x0E00 0000
Non-secure callable Reserved
0x3000 0000 0x0C08 0000
FLASH
SRAM 2 0x0C00 0000
Non-secure
0x2003 0000
SRAM 1 0x0C00 0000
Non-secure Reserved
0x0BFB 0000
0x2000 0000 OTP
0x0BFA 0000
Code Reserved
Non-secure 0x0BF9 7FFF
System memory
0x1000 0000 0x0BF9 0000
Code Reserved
0x0A04 0000
Non-secure callable SRAM2
0x0C00 0000 0x0A03 0000
SRAM1
Code 0x0A00 0000
Non-secure Reserved
0x0000 0000 0x0808 0000
FLASH
0x0800 0000
External memories remap
Non-secure 0x0000 0000

Non-secure callable
MSv49340V3

88/2194 RM0438 Rev 7

RM0438

All the memory map areas that are not allocated to memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
refer to the following table.
The following table gives the boundary addresses of the peripherals available in the
devices.

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses
Non-secure boundary Size Peripheral register
Bus Secure boundary address Peripheral
address (bytes) map

0x5402 1400 - 0x5FFF FFFF 0x4402 1400 - 0x4FFF FFFF 129 MB Reserved -
OCTOSPI1 Section 20.7.28:
0x5402 1000 - 0x5402 13FF 0x4402 1000 - 0x4402 13FF 1 KB
registers OCTOSPI register map
AHB3

0x5402 0400 - 0x5402 0FFF 0x4402 0400 - 0x4402 0FFF 3 KB Reserved -

FMC Section 19.7.8: FMC
0x5402 0000 - 0x5402 03FF 0x4402 0000 - 0x4402 03FF 1 KB
registers register map
0x520C 8400 - 0x5401 FFFF 0x420C 8400 - 0x4401 FFFF 32 MB Reserved -
Section 48.9.20:
0x520C 8000 - 0x520C 83FF 0x420C 8000 - 0x420C 83FF 1 KB SDMMC1
SDMMC register map
0x520C 5400 - 0x520C 7FFF 0x420C 5400 - 0x420C 7FFF 11 KB Reserved -
Section 31.6.15:
0x520C 5000 - 0x520C 53FF 0x420C 5000 - 0x420C 53FF 1 KB OTFDEC1
OTFDEC register map
0x520C 4000 - 0x520C 4FFF 0x420C 4000 - 0x420C 4FFF 4 KB Reserved -
Section 32.7.5: PKA
0x520C 2000 - 0x520C 3FFF 0x420C 2000 - 0x420C 3FFF 8 KB PKA
register map
0x520C 0C00 - 0x520C 1FFF 0x420C 0C00 - 0x420C 1FFF 5 KB Reserved -
Section 28.7.5: RNG
0x520C 0800 - 0x520C 0BFF 0x420C 0800 - 0x420C 0BFF 1 KB RNG
register map
Section 30.7.8: HASH
AHB2

0x520C 0400 - 0x520C 07FF 0x420C 0400 - 0x420C 07FF 1 KB HASH

register map
Section 29.7.18: AES
0x520C 0000 - 0x520C 03FF 0x420C 0000 - 0x420C 03FF 1 KB AES
register map
0x5202 8400 - 0x520B FFFF 0x4202 8400 - 0x420B FFFF 609 KB Reserved -
Section 21.8: ADC
0x5202 8000 - 0x5202 83FF 0x4202 8000 - 0x4202 83FF 1 KB ADC register map on
page 793
0x5202 2000 - 0x5202 7FFF 0x4202 2000 - 0x4202 7FFF 24 KB Reserved -
Section 11.6.13: GPIO
0x5202 1C00 - 0x5202 1FFF 0x4202 1C00 - 0x4202 1FFF 1 KB GPIOH
register map
Section 11.6.13: GPIO
0x5202 1800 - 0x5202 1BFF 0x4202 1800 - 0x4202 1BFF 1 KB GPIOG
register map
Section 11.6.13: GPIO
0x5202 1400 - 0x5202 17FF 0x4202 1400 - 0x4202 17FF 1 KB GPIOF
register map

RM0438 Rev 7 89/2194

100
 RM0438

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses (continued)
Non-secure boundary Size Peripheral register
Bus Secure boundary address Peripheral
address (bytes) map

Section 11.6.13: GPIO

0x5202 1000 - 0x5202 13FF 0x4202 1000 - 0x4202 13FF 1 KB GPIOE
register map
Section 11.6.13: GPIO
AHB2 (continued)

0x5202 0C00 - 0x5202 0FFF 0x4202 0C00 - 0x4202 0FFF 1 KB GPIOD

register map
Section 11.6.13: GPIO
0x5202 0800 - 0x5202 0BFF 0x4202 0800 - 0x4202 0BFF 1 KB GPIOC
register map
Section 11.6.13: GPIO
0x5202 0400 - 0x5202 07FF 0x4202 0400 - 0x4202 07FF 1 KB GPIOB
register map
Section 11.6.13: GPIO
0x5202 0000 - 0x5202 03FF 0x4202 0000 - 0x4202 03FF 1 KB GPIOA
register map
0x5003 4000 - 0x5201 FFFF 0x4003 3400 - 0x4201 FFFF 32 MB Reserved -
Section 5.6.5:
GTZC_MPCBB1
register map and reset
values
Section 5.6.6:
GTZC_MPCBB2
register map and reset
0x5003 2400 - 0x5003 33FF 0x4003 2400 - 0x4003 33FF 4 KB GTZC
values
Section 5.7.10:
GTZC_TZIC register
map and reset values
Section 5.5.8:
GTZC_TZSC register
map and reset values
0x5003 0800 - 0x5003 23FF 0x4003 0800 - 0x4003 23FF 7 KB Reserved -
AHB1

Section 7.7.8: ICACHE

0x5003 0400 - 0x5003 07FF 0x4003 0400 - 0x4003 07FF 1 KB ICache
register map
0x5002 F800 - 0x5003 03FF 0x4002 F800 - 0x4003 03FF 3 KB Reserved -
Section 17.6.21: EXTI
0x5002 F400 - 0x5002 F7FF 0x4002 F400 - 0x4002 F7FF 1 KB EXTI
register map
0x5002 4400 - 0x5002 F3FF 0x4002 4400 - 0x4002 F3FF 43 KB Reserved -
Section 27.6.11: TSC
0x5002 4000 - 0x5002 43FF 0x4002 4000 - 0x4002 43FF 1 KB TSC
register map
0x5002 3400 - 0x5002 3FFF 0x4002 3400 - 0x4002 3FFF 3 KB Reserved -
Section 18.4.6: CRC
0x5002 3000 - 0x5002 33FF 0x4002 3000 - 0x4002 33FF 1 KB CRC
register map
0x5002 2400 - 0x5002 2FFF 0x4002 2400 - 0x4002 2FFF 3 KB Reserved -
Section 6.9.28: FLASH
Flash
0x5002 2000 - 0x5002 23FF 0x4002 2000 - 0x4002 23FF 1 KB register map and reset
registers
values

90/2194 RM0438 Rev 7

RM0438

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses (continued)
Non-secure boundary Size Peripheral register
Bus Secure boundary address Peripheral
address (bytes) map

0x5002 1400 - 0x5002 1FFF 0x4002 1400 - 0x4002 1FFF 3 KB Reserved -

Section 9.8.42: RCC
0X5002 1000 - 0x5002 13FF 0X4002 1000 - 0x4002 13FF 1 KB RCC
register map
AHB1 (continued)

0x5002 0C00 - 0x5002 0FFF 0x4002 0C00 - 0x4002 0FFF 1 KB Reserved -

Section 15.6.7:
0x5002 0800 - 0x5002 0BFF 0x4002 0800 - 0x4002 0BFF 1 KB DMAMUX1
DMAMUX register map
Section 14.6.8: DMA
0x5002 0400 - 0x5002 07FF 0x4002 0400 - 0x4002 07FF 1 KB DMA2
register map
Section 14.6.8: DMA
0x5002 0000 - 0x5002 03FF 0x4002 0000 - 0x4002 03FF 1 KB DMA1
register map
0x5001 6800 - 0x5001 FFFF 0x4001 6800 - 0x4001 FFFF 38 KB Reserved -
Section 26.8.16:
0x5001 6000 - 0x5001 67FF 0x4001 6000 - 0x4001 67FF 2 KB DFSDM1
DFSDM register map
0x5001 5C00 - 0x5001 5FFF 0x4001 5C00 - 0x4001 5FFF 1 KB Reserved -
Section 47.6.20: SAI
0x5001 5800 - 0x5001 5BFF 0x4001 5800 - 0x4001 5BFF 1 KB SAI2
register map
Section 47.6.20: SAI
0x5001 5400 - 0x5001 57FF 0x4001 5400 - 0x4001 57FF 1 KB SAI1
register map
0x5001 4C00 - 0x5001 53FF 0x4001 4C00 - 0x4001 53FF 2 KB Reserved -
Section 35.6.21:
0x5001 4800 - 0x5001 4BFF 0x4001 4800 - 0x4001 4BFF 1 KB TIM17 TIM16/TIM17 register
map
APB2

Section 35.6.21:
0x5001 4400 - 0x5001 47FF 0x4001 4400 - 0x4001 47FF 1 KB TIM16 TIM16/TIM17 register
map
Section 35.5.21: TIM15
0x5001 4000 - 0x5001 43FF 0x4001 4000 - 0x4001 43FF 1 KB TIM15
register map
0x5001 3C00 - 0x5001 3FFF 0x4001 3C00 - 0x4001 3FFF 1 KB Reserved -
Section 44.8.15:
0x5001 3800 - 0x5001 3BFF 0x4001 3800 - 0x4001 3BFF 1 KB USART1
USART register map
Section 33.4.33: TIM8
0x5001 3400 - 0x5001 37FF 0x4001 3400 - 0x4001 37FF 1 KB TIM8
register map
Section 46.6.8: SPI
0x5001 3000 - 0x5001 33FF 0x4001 3000 - 0x4001 33FF 1 KB SPI1
register map
Section 33.4.32: TIM1
0x5001 2C00 - 0x5001 2FFF 0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
register map

RM0438 Rev 7 91/2194

100
 RM0438

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses (continued)
Non-secure boundary Size Peripheral register
Bus Secure boundary address Peripheral
address (bytes) map

0x5001 0400 - 0x5001 2BFF 0x4001 0400 - 0x4001 2BFF 10 KB Reserved -

APB2 (continued)

Section 24.6.3: COMP

0x5001 0200 - 0x5001 03FF 0x4001 0200 - 0x4001 03FF 1 KB COMP
register map
Section 23.4.3:
0x5001 0100 - 0x5001 01FF 0x4001 0100 - 0x4001 01FF 1 KB VREFBUF
VREFBUF register map
Section 12.3.12:
0x5001 0000 - 0x5001 002F 0x4001 0000 - 0x4001 002F 1 KB SYSCFG
SYSCFG register map
0x5000 E000 - 0x5000 FFFF 0x4000 E000 - 0x4000 FFFF 8 KB Reserved -
Section 51.7.16: UCPD
0x5000 DC00 - 0x5000 DFFF 0x4000 DC00 - 0x4000 DFFF 1 KB UCPD1
register map
Section 50.6.3: USB
0x5000 D800 - 0x5000 DBFF 0x4000 D800 - 0x4000 DBFF 1 KB USB SRAM
register map
Section 50.6.3: USB
0x5000 D400 - 0x5000 D7FF 0x4000 D400 - 0x4000 D7FF 1 KB USB FS
register map
0x5000 B000 - 0x5000 D3FF 0x4000 B000 - 0x4000 D3FF 9 KB Reserved -
FDCAN Section 49.4.38:
0x5000 AC00 - 0x5000 AFFF 0x4000 AC00 - 0x4000 AFFF 1 KB
RAM FDCAN register map
0x5000 A800 - 0x5000 ABFF 0x4000 A800 - 0x4000 ABFF 1 KB Reserved -
Section 49.4.38:
0x5000 A400 - 0x5000 A7FF 0x4000 A400 - 0x4000 A7FF 1 KB FDCAN1
FDCAN register map
APB1

0x5000 9C00 - 0x5000 A3FF 0x4000 9C00 - 0x4000 A3FF 2 KB Reserved -

Section 37.7.13: LPTIM
0x5000 9800 - 0x5000 9BFF 0x4000 9800 - 0x4000 9BFF 1 KB LPTIM3
register map
Section 37.7.13: LPTIM
0x5000 9400 - 0x5000 97FF 0x4000 9400 - 0x4000 97FF 1 KB LPTIM2
register map
0x5000 8800 - 0x5000 93FF 0x4000 8800 - 0x4000 93FF 3 KB Reserved -
Section 43.7.16: I2C
0x5000 8400 - 0x5000 87FF 0x4000 8400 - 0x4000 87FF 1 KB I2C4
register map
0x5000 8000 - 0x5000 83FF 0x4000 8000 - 0x4000 83FF 1 KB LPUART1 -
Section 37.7.13: LPTIM
0x5000 7C00 - 0x5000 7FFF 0x4000 7C00 - 0x4000 7FFF 1 KB LPTIM1
register map
Section 25.5: OPAMP
0x5000 7800 - 0x5000 7BFF 0x4000 7800 - 0x4000 7BFF 1 KB OPAMP
registers

92/2194 RM0438 Rev 7

RM0438

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses (continued)
Non-secure boundary Size Peripheral register
Bus Secure boundary address Peripheral
address (bytes) map

Section 22.7.21: DAC

0x5000 7400 - 0x5000 77FF 0x4000 7400 - 0x4000 77FF 1 KB DAC
register map
Section 8.6.26: PWR
0x5000 7000 - 0x5000 73FF 0x4000 7000 - 0x4000 73FF 1 KB PWR register map and reset
values
0x5000 6400 - 0x5000 6FFF 0x4000 6400 - 0x4000 6FFF 3 KB Reserved -
Section 10.7.5: CRS
0x5000 6000 - 0x5000 63FF 0x4000 6000 - 0x4000 63FF 1 KB CRS
register map
Section 43.7.16: I2C
0x5000 5C00 - 0x5000 5FFF 0x4000 5C00 - 0x4000 5FFF 1 KB I2C3
register map
Section 43.7.16: I2C
0x5000 5800 - 0x5000 5BFF 0x4000 5800 - 0x4000 5BFF 1 KB I2C2
register map
Section 43.7.16: I2C
0x5000 5400 - 0x5000 57FF 0x4000 5400 - 0x4000 57FF 1 KB I2C1
register map
Section 44.8.15:
0x5000 5000 - 0x5000 53FF 0x4000 5000 - 0x4000 53FF 1 KB UART5
USART register map
Section 44.8.15:
0x5000 4C00 - 0x5000 4FFF 0x4000 4C00 - 0x4000 4FFF 1 KB UART4
APB1 (continued)

USART register map

Section 44.8.15:
0x5000 4800 - 0x5000 4BFF 0x4000 4800 - 0x4000 4BFF 1 KB USART3
USART register map
Section 44.8.15:
0x5000 4400 - 0x5000 47FF 0x4000 4400 - 0x4000 47FF 1 KB USART2
USART register map
0x5000 4000 - 0x5000 43FF 0x4000 4000 - 0x4000 43FF 1 KB Reserved -
Section 46.6.8: SPI
0x5000 3C00 - 0x5000 3FFF 0x4000 3C00 - 0x4000 3FFF 1 KB SPI3
register map
Section 46.6.8: SPI
0x5000 3800 - 0x5000 3BFF 0x4000 3800 - 0x4000 3BFF 1 KB SPI2
register map
Section 42.6.19: TAMP
0x5000 3400 - 0x5000 37FF 0x4000 3400 - 0x4000 37FF 1 KB TAMP
register map
Section 39.4.6: IWDG
0x5000 3000 - 0x5000 33FF 0x4000 3000 - 0x4000 33FF 1 KB IWDG
register map
Section 40.5.4: WWDG
0x5000 2C00 - 0x5000 2FFF 0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
register map
Section 41.6.24: RTC
0x5000 2800 - 0x5000 2BFF 0x4000 2800 - 0x4000 2BFF 1 KB RTC
register map
0x5000 1800 - 0x5000 27FF 0x4000 1800 - 0x4000 27FF 4 KB Reserved -
Section 36.4.9: TIMx
0x5000 1400 - 0x5000 17FF 0x4000 1400 - 0x4000 17FF 1 KB TIM7
register map

RM0438 Rev 7 93/2194

100
 RM0438

Table 4. STM32L552xx and STM32L562xx memory map and peripheral register boundary
addresses (continued)
Non-secure boundary Size Peripheral register
Bus Secure boundary address Peripheral
address (bytes) map

Section 36.4.9: TIMx

0x5000 1000 - 0x5000 13FF 0x4000 1000 - 0x4000 13FF 1 KB TIM6
register map
Section 34.4.26: TIMx
APB1 (continued)

0x5000 0C00 - 0x5000 0FFF 0x4000 0C00 - 0x4000 0FFF 1 KB TIM5

register map
Section 34.4.26: TIMx
0x5000 0800 - 0x5000 0BFF 0x4000 0800 - 0x4000 0BFF 1 KB TIM4
register map
Section 34.4.26: TIMx
0x5000 0400 - 0x5000 07FF 0x4000 0400 - 0x4000 07FF 1 KB TIM3
register map
Section 34.4.26: TIMx
0x5000 0000 - 0x5000 03FF 0x4000 0000 - 0x4000 03FF 1 KB TIM2
register map

2.4 Embedded SRAM

The STM32L552xx and STM32L562xx devices feature up to 256 Kbytes SRAM:
• 192 Kbytes SRAM1
• 64 Kbytes SRAM2
These SRAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). These
memories can be addressed at maximum system clock frequency without wait state and
thus by both CPU and DMA.
The CPU can access the SRAM1 and SRAM2 through the system bus or through the C-bus
depending on the selected address.
Either 64 Kbytes or upper 4 Kbytes of SRAM2 can be retained in Standby mode.
When the TrustZone security is enabled, all SRAMs are secure after reset. The SRAM can
be programmed as non-secure with a block granularity, using MPCBB (memory protection
controller block configuration based) in GTZC controller. The granularity of SRAM
secure/non-secure block-based is a page of 256 bytes.

2.4.1 SRAM2 parity check

The user can enable the SRAM2 parity check using the option bit SRAM2_PE in the OPTR
user option register (refer to Section 6.4.1: Option bytes description).
The data bus width is 36 bits because 4 bits are available for parity check (1 bit per byte) in
order to increase memory robustness, as required for instance by Class B or SIL safety
standards.
The parity bits are computed and stored when writing into the SRAM2. Then, they are
automatically checked when reading. If one bit fails, an NMI is generated. The same error
can also be linked to the BRK_IN Break input of TIM1/TIM8/TIM15/TIM16/TIM17 with the
SPL control bit in the SYSCFG configuration register 2 (SYSCFG_CFGR2). The SRAM2
Parity Error flag (SPF) is available in the SYSCFG configuration register 2
(SYSCFG_CFGR2).

94/2194 RM0438 Rev 7

RM0438

Note: When enabling the RAM parity check, it is advised to initialize by software the whole RAM
memory at the beginning of the code, to avoid getting parity errors when reading non-
initialized locations.

2.4.2 SRAM2 Write protection

The SRAM2 can be write protected with a page granularity of 1 Kbyte.

Table 5. SRAM2 organization

Page number Start address End address

Page 0 0x2003 0000 0x2003 03FF

Page 1 0x2003 0400 0x2003 07FF
Page 2 0x2003 0800 0x2003 0BFF
Page 3 0x2003 0C00 0x2003 0FFF
Page 4 0x2003 1000 0x2003 13FF
Page 5 0x2003 1400 0x2003 17FF
Page 6 0x2003 1800 0x2003 1BFF
Page 7 0x2003 1C00 0x2003 1FFF
Page 8 0x2003 2000 0x2003 23FF
Page 9 0x2003 2400 0x2003 27FF
Page 10 0x2003 2800 0x2003 2BFF
Page 11 0x2003 2C00 0x2003 2FFF
Page 12 0x2003 3000 0x2003 33FF
Page 13 0x2003 3400 0x2003 37FF
Page 14 0x2003 3800 0x2003 3BFF
Page 15 0x2003 3C00 0x2003 3FFF
Page 16 0x2003 4000 0x2003 43FF
Page 17 0x2003 4400 0x2003 47FF
Page 18 0x2003 4800 0x2003 4BFF
Page 19 0x2003 4C00 0x2003 4FFF
Page 20 0x2003 5000 0x2003 53FF
Page 21 0x2003 5400 0x2003 57FF
Page 22 0x2003 5800 0x2003 5BFF
Page 23 0x2003 5C00 0x2003 5FFF
Page 24 0x2003 6000 0x2003 63FF
Page 25 0x2003 6400 0x2003 67FF
Page 26 0x2003 6800 0x2003 6BFF
Page 27 0x2003 6C00 0x2003 6FFF
Page 28 0x2003 7000 0x2003 73FF

RM0438 Rev 7 95/2194

100
 RM0438

Table 5. SRAM2 organization (continued)

Page number Start address End address

Page 29 0x2003 7400 0x2003 77FF

Page 30 0x2003 7800 0x2003 7BFF
Page 31 0x2003 7C00 0x2003 7FFF
Page 32 0x2003 8000 0x2003 83FF
Page 33 0x2003 8400 0x2003 87FF
Page 34 0x2003 8800 0x2003 8BFF
Page 35 0x2003 8C00 0x2003 8FFF
Page 36 0x2003 9000 0x2003 93FF
Page 37 0x2003 9400 0x2003 97FF
Page 38 0x2003 9800 0x2003 9BFF
Page 39 0x2003 9C00 0x2003 9FFF
Page 40 0x2003 A000 0x2003 A3FF
Page 41 0x2003 A400 0x2003 A7FF
Page 42 0x2003 A800 0x2003 ABFF
Page 43 0x2003 AC00 0x2003 AFFF
Page 44 0x2003 B000 0x2003 B3FF
Page 45 0x2003 B400 0x2003 B7FF
Page 46 0x2003 B800 0x2003 BBFF
Page 47 0x2003 BC00 0x2003 BFFF
Page 48 0x2003 C000 0x2003 C3FF
Page 49 0x2003 C400 0x2003 C7FF
Page 50 0x2003 C800 0x2003 CBFF
Page 51 0x2003 CC00 0x2003 CFFF
Page 52 0x2003 D000 0x2003 D3FF
Page 53 0x2003 D400 0x2003 D7FF
Page 54 0x2003 D800 0x2003 DBFF
Page 55 0x2003 DC00 0x2003 DFFF
Page 56 0x2003 E000 0x2003 E3FF
Page 57 0x2003 E400 0x2003 E7FF
Page 58 0x2003 E800 0x2003 EBFF
Page 59 0x2003 EC00 0x2003 EFFF
Page 60 0x2003 F000 0x2003 F3FF
Page 61 0x2003 F400 0x2003 F7FF
Page 62 0x2003 F800 0x2003 FBFF
Page 63 0x2003 FC00 0x2003 FFFF

96/2194 RM0438 Rev 7

RM0438

The write protection can be enabled in SYSCFG SRAM2 write protection register
(SYSCFG_SWPR) in the SYSCFG block. This is a register with write ‘1’ once mechanism,
which means that writing ‘1’ on a bit will setup the write protection for that page of SRAM
and it can be removed/cleared by a system reset only.

2.4.3 SRAM2 Read protection

The SRAM2 is protected with the Read protection (RDP). Refer to Section 6.7.2: Readout
protection (RDP) for more details.

2.4.4 SRAM2 Erase

The SRAM2 can be erased with a system reset using the option bit SRAM2_RST in the
OPTR user option register (refer to Section 6.4.1: Option bytes description).
The SRAM2 erase can also be requested by software by setting the bit SRAM2ER in the
SYSCFG SRAM2 control and status register (SYSCFG_SCSR).
The SRAM2 is also erased by a Backup domain reset.

2.5 Flash memory overview

The Flash memory is composed of two distinct physical areas:
• The main Flash memory block. It contains the application program and user data if
necessary.
• The information block. It is composed of three parts:
– Option bytes for hardware and memory protection user configuration.
– System memory that contains the ST proprietary code.
– OTP (one-time programmable) area
The Flash interface implements instruction access and data access based on the AHB
protocol. It also implements the logic necessary to carry out the Flash memory operations
(program/erase) controlled through the Flash registers plus security access control
features.Refer to Section 6: Embedded Flash memory (FLASH) for more details.

RM0438 Rev 7 97/2194

100
Boot configuration RM0438

3 Boot configuration

At startup, a BOOT0 pin, nBOOT0 and NSBOOTADDx[24:0] / SECBOOTADD0[24:0] option

bytes are used to select the boot memory address which includes:
• Boot from any address in user Flash
• Boot from system memory bootloader
• Boot from any address in embedded SRAM
• Boot from Root Security service (RSS)
The BOOT0 value may come from the PH3-BOOT0 pin or from an option bit depending on
the value of a user option bit to free the GPIO pad if needed.
Refer to Table 6 and Table 7 for boot modes when TrustZone is disabled and enabled
respectively.

Table 6. Boot modes when TrustZone is disabled (TZEN=0)

nBOOT0 nSWBOOT0
BOOT0 Boot address option- ST programmed
FLASH_ FLASH_ Boot area
pin PH3 bytes selection default value
OPTR[27] OPTR[26]

Boot address defined by

- 0 1 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
System bootloader:
- 1 1 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]
Boot address defined by
1 - 0 NSBOOTADD0[24:0] user option bytes Flash: 0x0800 0000
NSBOOTADD0[24:0]
Boot address defined by
System bootloader:
0 - 0 NSBOOTADD1[24:0] user option bytes
0x0BF9 0000
NSBOOTADD1[24:0]

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address.
A unique boot entry option can be selected by setting the BOOT_LOCK option bit. All other
boot options are ignored.

98/2194 RM0438 Rev 7

RM0438 Boot configuration

Table 7. Boot modes when TrustZone is enabled (TZEN=1)

ST
nBOOT0 BOOT0 nSWBOOT0 Boot address
BOOT_ RSS programme
FLASH_ pin FLASH_ option-bytes Boot area
LOCK command d default
OPTR[27] PH3 OPTR[26] selection
value

Secure boot address

defined by user option
SECBOOTADD Flash:
- 0 1 0 bytes
0[24:0] 0x0C00 0000
SECBOOTADD0
[24:0]
RSS:
- 1 1 0 N/A RSS: 0x0FF8 0000
0x0FF8 0000
Secure boot address
0
defined by user option
SECBOOTADD Flash:
1 - 0 0 bytes
0[24:0] 0x0C00 0000
SECBOOTADD0
[24:0]
RSS: RSS: RSS:
0 - 0 0 N/A
0x0FF8 0000 0x0FF8 0000
RSS: RSS: RSS:
- - - ≠0 N/A
0x0FF8 0000 0x0FF8 0000
Secure boot address
defined by user option
SECBOOTADD Flash:
1 - - - - bytes
0[24:0] 0x0C00 0000
SECBOOTADD0
[24:0]

The boot address option bytes enables the possibility to program any boot memory address.
However, the allowed address space depends on Flash read protection RDP level.
If the programmed boot memory address is out of the allowed memory mapped area when
RDP level is 0.5 or more, the default boot fetch address is forced to:
• 0x0800 0000 (when TZEN = 0)
• RSS (when TZEN = 1)
Refer to the Table 8.
Table 8. Boot space versus RDP protection
RDP TZEN = 1 TZEN = 0

0 Any boot address Any boot address

0.5 N/A
Boot address only in:
1 Any boot address
RSS: 0x0FF80000
or secure Flash: 0x0C000000 - Boot address only in Flash 0x0800 0000 -
0x0C07 FFFF 0x0807 FFFF
2
Otherwise the boot address is forced to RSS Otherwise the forced boot address is:
0x0800 0000(1)

RM0438 Rev 7 99/2194

100
Boot configuration RM0438

1. In RDP level 2, the boot is done from the address programmed in NSBOOTADD0 or NSBOOTADD1
depending on the boot configuration before setting the RDP level 2 and if the programmed address is
within the user Flash memory.
If the programmed NSBOOTADD0 or NSBOOTADD1 is not a valid address, the boot if forced at 0x800
0000.

The BOOT0 value (either coming from the pin or the option bit) is latched upon reset
release. It is up to the user to set nBOOT0 or BOOT0 values to select the required boot
mode.
The BOOT0 pin or user option bit (depending on the nSWBOOT0 bit value in the
FLASH_OPTR register) is also re-sampled when exiting from Standby mode. Consequently,
they must be kept in the required Boot mode configuration in Standby mode.After startup
delay, the selection of the boot area is done before releasing the processor reset.
PH3/BOOT0 GPIO is configured in:
• Input mode during the complete reset phase if the option bit nSWBOOT0 is set into the
FLASH_OPTR register and then switches automatically in analog mode after reset is
released (BOOT0 pin).
• Input mode from the reset phase to the completion of the option byte loading if the bit
nSWBOOT0 is cleared into the FLASH_OPTR register (BOOT0 value coming from the
option bit). It switches then automatically to the analog mode even if the reset phase is
not complete.

Embedded bootloader and RSS

The bootloader is located in the system memory. It is used to reprogram the Flash memory
by using USART, I2C, SPI, FDCAN or USB FS in device mode through the DFU (device
firmware upgrade). It is programmed by ST during production. Refer to AN2606, STM32
microcontroller system memory boot mode.
The root secure services (RSS) are embedded in a Flash memory area named secure
information block, programmed during ST production.
The RSS enables for example the secure firmware installation (SFI) thanks to the RSS
extension firmware (RSSe SFI).
This feature allows the customers to protect the confidentiality of the firmware to be
provisioned into the STM32 device when the production is subcontracted to a third party.
The RSS is available on all devices, after enabling the TrustZone through the TZEN option
bit. Refer to AN5428, STM32L5 Series microcontroller system memory RSS services.

100/2194 RM0438 Rev 7

RM0438 System security

4 System security

4.1 Introduction
The STM32L552xx and STM32L562xx have been designed with a comprehensive set of
security features, some of which being based on standard Arm TrustZone® technology.
These security features should simplify the process of evaluating IoT devices against
security standards. They also significantly reduce the cost and complexity of software
development for OEMs and third party developers by facilitating the re-use, improving the
interoperability, and minimizing the API fragmentation.
This section explains the different security features available on the STM32L552xx and
STM32L562xx devices.

RM0438 Rev 7 101/2194

132
System security RM0438

4.2 Key security features

• Resource isolation using Armv8-M mainline security extension of Cortex®-M33,
extended to securable I/Os, memories and peripherals
• Secure firmware installation (SFI) with device unique cryptographic key pair
– Leveraging the on-chip immutable bootloader that supports the download of
image through USART, USB, I2C, SPI, FDCAN and JTAG
• Enabled for secure boot thanks to unique boot entry feature and hide protect area
(HDP) mechanism.
• Secure storage, featuring:
– Non-volatile on-chip secure storage, protected with secure & HDP areas
– Battery-powered volatile secure storage, automatically erased in case of tamper
– Write-only key registers in AES engine
– STM32L552xx and STM32L562xx Unique ID (96 bits)
• General purpose cryptographic acceleration (AES and PKA only in STM32L562xx)
– AES 256-bit engine, supporting ECB, CBC, CTR, GCM and CCM chaining modes
– HASH processor, supporting MD5/SHA-1 checksums and SHA-2 secure hash
– Public key accelerator (PKA) for RSA/DH (up to 3136 bits) and ECC (up to 640
bits)
– True random number generator (RNG), NIST SP800-90B pre-certified
• On-the-fly decryption of encrypted image stored on external Flash memory connected
through OCTOSPI (STM32L562xx only)
– Almost-zero latency with standard NOR Flash memories
– Can be used to encrypt the image using device unique secret keys
– Automatic key erase in case of tamper
• Flexible lifecycle scheme with readout protection (RDP), including support for product
decommissioning (auto-erase)
– Debug protection, depending on the readout protection level
• Protected firmware distribution scheme, using TrustZone®, on-the-fly decryption and
RDP level 0.5
• Active tamper and protection against temperature, voltage and frequency attacks
– 3 active inputs, 1 active output tamper pin available in all power modes

4.3 Secure install

Secure firmware install (SFI) is an immutable secure service embedded by
STMicroelectronics in STM32L552xx and STM32L562xx devices. It allows secure and
counted installation of OEM firmware in untrusted production environment (such as OEM
contract manufacturer).
The confidentiality of the installed images written either in internal Flash memory or
encrypted in external Flash memory is also protected, using AES.

102/2194 RM0438 Rev 7

RM0438 System security

The SFI native service leverages the following hardware security features:
• Secure boot (see Section 4.4)
• Resource isolation using TrustZone® (see Section 4.6)
• Temporal isolation using hide protection (see Section 4.7.1)
• Secure execution (see Section 4.8)
• Secure storage, with associated cryptographic engines (see Section 4.9 and
Section 4.10)
Further information can be found in application note AN4992 - Overview secure firmware
install (SFI) available on www.st.com.

4.4 Secure boot

4.4.1 Introduction
Secure boot is an immutable code that is always executed after a system reset. As a root of
trust, this code checks the STM32L552xx and STM32L562xx static protections and
activates available STM32L552xx and STM32L562xx runtime protections, reducing the risk
that invalid or malicious code runs on the platform. As root of trust, secure boot also checks
integrity and authenticity of the next level firmware before executing it.
The actual functions of secure boot depend on availability of TrustZone® features, and the
firmware stored in the device. However it would typically initializes secure storage, and
install on-the-fly decryption keys in OTFDEC to be able to use encrypted firmware stored in
external Flash memory.
The STM32L552xx and STM32L562xx Trusted Firmware-M (TFM) application, supported
by the STM32 ecosystem, provides a root of trust solution including secure boot functions.
For more information, refer to user manual UM2671 - Getting started with STM32CubeL5
TFM application available from www.st.com.
In the STM32L552xx and STM32L562xx devices, the secure boot takes benefit of hardware
security features such as:
• Resource isolation using TrustZone® (see Section 4.6)
• Temporal isolation using hide protection (see Section 4.7.1)
• Secure execution (see Section 4.8)
• Secure install and update (see Section 4.3 and Section 4.5)
• Secure storage, with associated cryptographic engines if available (see Section 4.9
and Section 4.10)
This section describes the features specifically designed for secure boot.

4.4.2 Unique boot entry and BOOT_LOCK

When TrustZone® is activated (TZEN=1) and BOOT_LOCK secure option bit is cleared the
application selects a boot entry point located either in system Flash memory (see
Section 4.4.3) or in secure user Flash memory, at the address defined by SECBOOTADD0
option bytes.
When TrustZone® is activated (TZEN=1) and BOOT_LOCK secure option bit is set the
device unique boot entry is the secure address defined by SECBOOTADD0 option bytes.
These option bytes cannot be modified by the application anymore.

RM0438 Rev 7 103/2194

132
System security RM0438

Note: As long as it is cleared, the BOOT_LOCK option byte can be set without any constraint. But
once set the BOOT_LOCK option bit cannot be cleared.
For more information on STM32L552xx and STM32L562xx boot mechanisms, refer to
Section 3: Boot configuration.

4.4.3 Immutable root of trust in system Flash memory

The first usage of the immutable root of trust code stored in STM32L552xx and
STM32L562xx system Flash memory is to perform secure firmware install (SFI), allowing
secure and counted installation of OEM firmware in untrusted production environment (such
as OEM contract manufacturer). See Section 4.4.2 for more details.
STMicroelectronics immutable code also includes secure runtime services that can be
called at runtime when secure application sets the SYSCFG_RSSCMDR register to a non-
null value before triggering a system reset. This runtime feature is deactivated when
BOOT_LOCK secure option bit is set.

4.5 Secure update

Secure firmware update is a secure service that runs after a secure boot. Its actual functions
depend on availability of TrustZone® features, and the firmware stored in the device.
The STM32L552xx and STM32L562xx Trusted Firmware-M (TFM) application, supported
by the STM32 ecosystem, allows the update of the microcontroller built-in program with new
firmware versions, adding new features and correcting potential issues. The update process
is performed in a secure way to prevent unauthorized updates and access to confidential
on-device data.
A firmware update can be done either on a single firmware image including both secure and
non-secure parts, or on the secure (respectively non-secure) part of the firmware image,
independently.
In the STM32L552xx and STM32L562xx devices, the secure update application leverages
the same hardware security as the firmware install described in Section 4.3.
For more information, refer to user manual UM2671 - Getting started with STM32CubeL5
TFM application available on www.st.com.

4.6 Resource isolation using TrustZone®

4.6.1 Introduction
In the STM32L552xx and STM32L562xx devices, the hardware and software resources can
be partitioned so that they exist either in the secure world or in the non-secure world, as
shown on Figure 3.
Note: The initial partitioning of the platform is under the responsibility of the secure firmware
executed after reset of the device.
Thanks to this resource isolation technology, the secure world can be used to protect critical
code against intentional or unintentional tampering from the more exposed code running in
the non-secure world.

104/2194 RM0438 Rev 7

RM0438 System security

Note: Typically secure code is small and rarely modified, while non-secure code is more exposed,
and prone to firmware updates.

Figure 3. Secure/non-secure partitioning using TrustZone® technology

Init

Non-secure world Secure world

Applications Application RoT

Privileged system Root of trust

services services

Peripherals and I/Os

Memory (internal, external)

Non- secure world CPU time
Secure world MSv64438V1

4.6.2 TrustZone® security architecture

Armv8-M TrustZone® technology is a comprehensive hardware architecture that proposes
to developers a comprehensive, holistic protection across the entire processor and system.
In this device TrustZone® hardware features include:
• The Armv8-M mainline security extension of Cortex®-M33, enabling a new processor
secure state, with its associated secure interrupts
• The dynamic allocation of memory and peripherals to TrustZone® using eight security
attribution unit (SAU) regions of Cortex®-M33
• A global TrustZone® framework (GTZC), extending TrustZone® protection against
transactions coming from other masters in the system than the Cortex®-M33.
• TrustZone®-aware embedded Flash memory and peripherals
Note: TrustZone® security is activated by the TZEN option bit in the FLASH_OPTR register
Each of the elements above are described in the following subsections.

4.6.3 Armv8-M security extension of Cortex®-M33

The Arm security extension of the Cortex®-M33 is an evolution, not a revolution. It is using
the programmer’s model you find in earlier Cortex® M subfamilies like Cortex®-M4. Indeed,
Armv8-M is architecturally similar to Armv7-M, using the same 32-bit architecture, the same
memory mapped resources protected with an MPU, and it also uses the Nested Vectored
Interrupt Controller (NVIC).

RM0438 Rev 7 105/2194

132
System security RM0438

Armv8-M TrustZone® implementation in STM32L552xx and STM32L562xx is composed of

the following features:
• A new processor state, with almost no additional code/cycle overhead as opposed to
Armv8-A TrustZone® that uses a dedicated exception routine for triggering a
secure/non-secure world change
• Two memory map views of a shared 4 Gbytes address space
• A low interrupt latency for both secure and non-secure domains. It also includes a new
interrupt configuration for security grouping and priority setting.
• Separated exception vector tables for the secure and non-secure exceptions
• Micro-coded context preservation
• Banking of specific registers across secure/non-secure states, including stack pointers
with stack-limit checkers
• Banking of following Cortex®-M33 programmable components (two separate units for
secure and non-secure):
– SysTick timer
– MPU configuration registers (eight MPU regions in secure, eight in non-secure)
– Some of the system control block (SCB) registers
• New system exception (SecureFault) for handling of security violations
• Configurable debug support, as defined in Section 4.12: Access controlled debug
For more information please refer to Cortex®-M33 programming manual (PM0264).

4.6.4 Memory and peripheral allocation using IDAU/SAU

Security attributes
As illustrated on Figure 4, Armv8-M non-secure memory view is similar to Armv7-M (that
can be found in Cortex® M4), with the difference that secure memory is hidden. The secure
memory view shows Flash memory, SRAM and peripherals that are only accessible while
the Cortex® processor executes in Secure state.
Note: Figure 4 shows the 32-bit address space viewed after SAU has been configured by the
secure code.

106/2194 RM0438 Rev 7

RM0438 System security

Figure 4. Sharing memory map between CPU in secure and non-secure state
Non-secure Secure Non-secure Secure
memory view memory view memory view memory view
0xFFFF FFFF
System region MPU-NS*
0xF000 0000
hidden SCB-NS*
System control and debug
SysTick-NS*
0xE000 0000
DEBUG
External peripherals
hidden SAU
0xA000 0000
MPU-NS MPU-S
External memories
SCB-NS SCB-S
0x6000 0000
Periph-NS NVIC
hidden Periph-S SysTick-NS SysTick-S
0x4000 0000
SRAM-NS ITM / DWT / FBP
hidden SRAM-S
0x2000 0000
Flash-NS
hidden Flash-S
0x0000 0000 (*) Aliased addresses
MSv64440V1

®
The Cortex processor state (and associated rights) depends on the security attribute
assigned to the memory region where it is executing. More specifically:
• A processor in a non-secure state only executes from non-secure (NS) program
memory, while a processor in a secure state only executes from secure (S) program
memory.
• While running in secure state the processor can access data from both S and NS
memories. Running in non-secure state the CPU is limited to non-secure memories.
In order to manage transitions to secure world, developers must create non-secure callable
(NSC) regions that contain valid entry points to the secure libraries. The first instruction in
these entry points must be the new secure gate (SG) instruction, used by non-secure
code to call a secure function. It is illustrated on Figure 5.

Figure 5. Secure world transition and memory partitioning

Non-secure memory Secure memory

Non-secure
callable

call
Secure call / branch
return entry point
Non-secure
application Secure
library

return

MSv64441V1

RM0438 Rev 7 107/2194

132
System security RM0438

Programming security attributes

In Cortex®-M33 the static implementation defined attribution unit (IDAU) works in
conjunction with the programmable security attribution unit (SAU) to assign a specific
security attribute (S, NS or NSC) to a specific address, as shown on Table 9.

Table 9. Configuring security attributes with IDAU and SAU

IDAU security attribution SAU security attribution(1) Final security attribution

Secure Secure
Non-secure Secure-NSC Secure-NSC
Non-secure Non-secure
Secure Secure
Secure-NSC
Non-secure Secure-NSC
1. Defined regions are aligned to 32-byte boundaries.

The SAU can only be configured by the Cortex®-M33 in the secure privileged state. When
TrustZone® is enabled, the SAU defaults all addresses as secure (S). A secure boot
application can then program SAU to create NSC or NS regions, as shown in Table 9.
The SAU/IDAU settings are applicable to only the Cortex®-M33. The other masters like
DMA are not affected by those policies.
For more information on memory security attribution using IDAU/SAU on STM32L552xx and
STM32L562xx, please refer to AN5347 on STMicroelectronics website.

4.6.5 Memory and peripheral allocation using GTZC

Global Trustzone® framework architecture
On top of Armv8-M TrustZone® security extension in Cortex®-M33, the STM32L552xx and
STM32L562xx devices come with complementary security features that reinforce in a
flexible way the isolation between the secure and the non-secure worlds. Unlike the
SAU/IDAU, the GTZC can protect legacy memories and peripherals against non-secure
transactions coming from other masters than the Cortex-M33..

108/2194 RM0438 Rev 7

RM0438 System security

Figure 6. Global TrustZone® framework and TrustZone® awareness

Device boundary

Other bus CPU DMA

master
Config SAU+IDAU

MPU

Flash memory

SRAM

External
OTFDEC
Flash memory

External
SRAM

Peripheral Peripheral Peripheral Peripheral

I/O I/O

Global TrustZone® framework

TrustZone®-aware peripherals
MSv64450V1

Securing peripherals with TZSC

When the TrustZone® security is active, a peripheral is either securable through global
TrustZone® controller (GTZC) or is natively TrustZone®-aware, as shown in Figure 6. More
specifically:
• A securable peripheral or memory is protected by an AHB/APB firewall gate that is
controlled by the TrustZone® security controller (TZSC)
• A TrustZone®-aware peripheral or memory is connected directly to AHB or APB
interconnect, implementing a specific TrustZone® behavior such as a subset of secure
registers or a secure memory area.
When a securable peripheral is made secure-only with GTZC, if this peripheral is master on
the interconnect it automatically issues secure transactions. SDMMC is an example of
securable master. TrustZone®-aware AHB masters like Cortex®-M33 or DMAs drive secure
signal in the AHB interconnect according to their security mode, independently to the GTZC.
Note: Like with TrustZone® a peripheral can be made privileged-only with TZSC. In this case, if
this peripheral is master on the interconnect, it automatically issues privileged transactions

RM0438 Rev 7 109/2194

132
System security RM0438

Securing memories with TZSC and MPCBB

The TZSC block in GTZC provides the capability to manage the security for all securable
external memories (including SRAM devices), programming the MPCWM instances as
defined in Table 10.

Table 10. MPCWMx instances

on-the-fly
Number of Default
Memory MPC instance Type of filtering decryption
regions security (1)

OCTOSPI MPCWM1 2 yes

Non secure region
FMC_NOR bank MPCWM2 2 Secure(2) no
(watermarks)
FMC_NAND bank MPCWM3 1 no
1. Using OTDEC peripheral.
2. Assuming TrustZone® is activated on the device, non-secure otherwise.

The MPCBB instances in GTZC provide the capability to configure the security of
embedded SRAM blocks, as defined in Table 11.

Table 11. MPCBBx instances

Memory size Block size Number Default
Memory MPC instance Type of filtering
(kBytes) (Bytes) of blocks security

SRAM1 MPCBB1 Block based, 192 768

managing security 256(1) secure(2)
SRAM2 MPCBB2 and privilege 64 256

1. Blocks are grouped in superblocks of 32 consecutive blocks, to manage configuration locking.

2. Assuming TrustZone® is activated on the device, non-secure otherwise.

Applying GTZC configurations

The TZSC and MPCBB blocks can be used in one of the following ways:
• Statically programmed during secure boot, locked and not changed afterwards.
• Dynamically re-programmed using specific application code or real-time kernel.
When dynamic option is selected and the configuration is not locked:
• MPCBB secure blocks or MPCWM non-secure regions size can be changed by secure
software.
• Secure (respectively privilege) state of each peripheral can be changed writing to
GTZC_TZSC_SECCFRGx (respectively GTZC_TZSC_PRIVCFGRx) registers.

Securing peripherals with TZSC

The TZSC block in GTZC provides the capability to manage the security and the privilege
for all securable peripherals. The list of those peripherals can be found in Section 5: Global
TrustZone® controller (GTZC).
Note: When TrustZone® is deactivated, resource isolation hardware GTZC can still be used to
isolate peripherals to privileged code only.

110/2194 RM0438 Rev 7

RM0438 System security

When TrustZone® is activated, peripherals are set as non-secure and non-privilege after
reset.

TrustZone®-aware peripheral list

STM32L552xx and STM32L562xx devices include the following TrustZone®-aware
peripherals. The way illegal accesses to those peripherals are monitored through TZIC
registers is described in Section 5: Global TrustZone® controller (GTZC).
• GPIOA to GPIOH
• MPCBB1 (SRAM1) and MPCBB2 (SRAM2)
• TZIC and TZSC (GTZC blocks)
• OTFDEC, writable only in secure if TZEN=1
• EXTI
• Flash memory
• RCC and PWR
• DMA1, DMA2 and DMAMUX
• SYSCFG registers
• RTC and TAMP
For more details please refer to Section 4.6.6: Managing security in TrustZone®-aware
peripherals.

TrustZone® illegal access controller (TZIC)

The TZIC block in GTZC gathers all illegal access events originated from sources either
protected by GTZC or TrustZone®-aware, generating one global secure interrupt towards
the NVIC.
TZIC is available only when the system is TrustZone® enabled (TZEN = 1). All accesses to
TZIC registers must be secured.
For each illegal event source, a status flag and a clear bit exist. Each illegal event can be
masked, not generating an interrupt toward the NVIC.
Note: By default all events are masked.

4.6.6 Managing security in TrustZone®-aware peripherals

This section gives more details on the way security is implemented in the TrustZone®-aware
peripherals listed on Section 4.6.5.

RM0438 Rev 7 111/2194

132
System security RM0438

Embedded Flash
When the TrustZone® security is enabled through option bytes (TZEN = 1), the whole Flash
memory is secure after reset and the following protections, shown on Figure 7, are available
to the application:
• Non-volatile user secure areas, defined with non-volatile secure user option bytes
– Watermark-based secure only area (x2 in dual bank configuration)
– Secure hide protection (HDP) area, stickily hidden after boot (x2 in dual bank
configuration)
• Volatile user secure pages, defined with volatile secure registers (lost after reset)
– Any page set as non-secure (example: outside watermark-based secure only
area), can be set as secure on-the-fly using the block-based configuration
registers
Note: All areas aligned on Flash memory page granularity.
Flash memory area can be configured as secure while they are tagged as non-secure in
Cortex®-M33 IDAU/SAU. In this case non-secure accesses by the CPU to the Flash
memory is denied.
Erase or program operation can be performed in secure or non-secure mode with
associated configuration bits.

Figure 7. Flash memory TrustZone® protections

TrustZone® disabled TrustZone® enabled

Non-secure pages
Secure pages
Non-secure pages
Secure pages
User Flash memory
Non-secure pages

Flash memory-S (*)

Flash memory-S(*)
(HDP)
Boot
Boot

Bootloader Bootloader-NS
Read-only system
Boot
Flash memory
Hidden RSS(*) (HDP)
Boot

(*): non-volatile security configuration

MSv64451V1

®
As shown above, when TrustZone is activated (TZEN=1) the application code can use the
HDP area that is part of the Flash watermark-based secure area. Indeed, when application
sets HDPxACCDIS bit, data read, write and instruction fetch on this hide protection area are
denied until next system reset. For example, the software code in the secure Flash hide
protected area can be executed only once, with any further access to this area denied until
next system reset. Additionally, any Flash memory page belonging to an active HDP area
cannot be erased anymore.

112/2194 RM0438 Rev 7

RM0438 System security

When TrustZone® is disabled (TZEN=0) the volatile/non-volatile secure areas features are
deactivated and all secure registers are RAZ/WI.
See Section 6: Embedded Flash memory (FLASH) for details.

On-the-fly encryption/decryption (OTFDEC)

When the TrustZone® security is activated (TZEN=1) the OTFDEC peripheral can only be
initialized by secure applications. Each of the four encrypted regions, once the configuration
is confirmed, can be write-locked until next power-on-reset.
Note: Any application (secure or non-secure) can verify the initialization context of each OTFDEC
region (including CRC of the keys), by reading the peripheral registers.
Key registers in OTFDEC are write-only.
See Section 4.10.3 for more details on this cryptographic engine.

DMA and DMAMUX

When a DMA channel is defined as secure (SECM = 1 in DMA_CCRx registers), the source
and destination transfers can be independently set as secure or non-secure by a secure
application using SSEC and DSEC bits in DMA_CCRx registers. Table 13 summarizes
these security options available in each DMA channel.
Note: Secure (resp. non-secure) DMA channel and associated DMAMUX is programmed by a
secure (resp. secure or non-secure) application.
This feature is not available when TrustZone® is disabled.

Table 12. DMA channel usage (security) (1)

Secure DMA channel (SECM = 1) Non-secure DMA channel (SECM = 0)

Secure source Non-secure source Secure source Non-secure source

Secure destination OK OK(2) Transfer blocked

(3)
Non-secure destination OK OK(4) Transfer blocked OK
1. When a transfer is blocked, the transfer completes but the corresponding writes are ignored, and reads return zeros. Also
an illegal access event to TZIC is automatically triggered by the memory/peripheral used as source or destination.
2. If the source is a memory the transfer is only possible if SSEC = 0, otherwise the transfer is blocked.
3. If the destination is a memory the transfer is only possible if DSEC = 0, otherwise the transfer is blocked.
4. If the transfer is memory-to-memory, the transfer is only possible if SSEC = 0 and DSEC = 0, otherwise the transfer is
blocked.

Similarly, when a DMA channel is defined as privileged (PRIV = 1 in DMA_CCRx register),

special rules apply when accessing privileged/unprivileged source or destination. Those
rules are summarized on Table 13.
Note: A privileged (resp. unprivileged) DMA channel and associated DMAMUX is programmed by
a privileged (resp. privileged or unprivileged) application.

RM0438 Rev 7 113/2194

132
System security RM0438

Table 13. DMA channel usage (privilege) (1)

Privileged DMA channel (PRIV=1) Non-privileged DMA channel (PRIV=0)

Privileged Non-privileged Privileged Non-privileged

source source source source

Privileged destination OK OK Transfer blocked

Non-privileged destination OK OK Transfer blocked OK
1. When a transfer is blocked, the transfer completes but the corresponding writes are ignored, and reads return zeros.

Note: When a DMA transfer error occurs during a DMA read or write access, the faulty channel x
is automatically disabled, and TEIFx bit is set in DMA_ISR register.
See Section 14: Direct memory access controller (DMA) and Section 15: DMA request
multiplexer (DMAMUX) for details.

Power control (PWR)

When the TrustZone® security is activated (TZEN = 1), the selected PWR registers can be
secured through the PWR_SECCFGR register, protecting the following PWR features:
• Low-power mode setup
• Wakeup (WKUP) pins definition
• Voltage detection and monitoring
• VBAT mode setup
Other PWR configuration bits becomes secure when:
• the system clock selection is secure in RCC. In this case the voltage scaling (VOS)
configuration becomes secure.
• a GPIO is configured as secure. In this case its corresponding bit for pull-up/pull-down
configuration in Standby mode becomes secure.
• the TrustZone®-aware RTC is configured as secure. In this case the backup domain
write protection bit (DBP) becomes secure.
• the USB Type-C™ / USB power delivery interface (UCPD) is configured as secure in
TZSC. In this case UCPD bits in PWR becomes secure.
See Section 8: Power control (PWR) for details.

Secure clock and reset (RCC)

When the TrustZone® security is activated (TZEN = 1) and security is enabled in the RCC,
the bits controlling the peripheral clocks and resets becomes TrustZone®-aware:
• If the peripheral is securable the peripheral clock and reset bits become secure if the
peripheral is programmed as secure in the TZSC.
• If the peripheral is TrustZone®-aware, the peripheral clock and reset bits become
secure as soon as at least one function is configured as secured inside the peripheral.
When a peripheral is defined as secure in the RCC, the bits Enable, Reset & LPEnable
become secure, and in some case the selection of clock source as well. The RCC can also
secure the system clock, the system configuration, the system multiplex and the reset flag.
Note: Refer to Table 10 and Table 11 in Section 4.6.5 for the list of securable and TrustZone®-
aware peripherals.

114/2194 RM0438 Rev 7

RM0438 System security

See Section 9: Reset and clock control (RCC) for details.

Real time clock (RTC)

Like all TrustZone®-aware peripherals, A non-secure read/write access to a secured RTC
register is RAZ/WI. It also generates an illegal access event that triggers a secure illegal
access interrupt if the RTC illegal access event is enabled in the TZIC peripheral.
After a backup domain power-on reset, all RTC registers can be read or written in both
secure and non-secure modes. Secure boot code can then change this security setup,
making registers Alarm A, alarm B, wakeup Timer and timestamp secure or not as needed,
using RTC_SMCR register.
Note: The RTC security configuration is not affected by a system reset.
See Section 41: Real-time clock (RTC) for details.

Tamper and backup registers (TAMP)

Like all TrustZone®-aware peripherals, A non-secure read/write access to a secured TAMP
register is RAZ/WI. It also generates an illegal access event that triggers a secure illegal
access interrupt if the TAMP illegal access event is enabled in the TZIC peripheral.
After a backup domain power-on reset, all TAMP registers can be read or written in both
secure and non-secure modes. Secure boot code can change this security setup, making
some registers secure or not as needed, using TAMP_SMCR register. More specifically:
• When TAMPDPROT=0 in the TAMP_SMCR register
– Writing the TAMP registers is possible only in secure mode. Backup registers
have their own write protection (see below).
– Reading the TAMP registers (with the exception of TAMP_SMCR,
TAMP_PRIVCR and TAMP_MISR) returns zero if the access is non-secure.
Backup registers have their own read protection (see below).
• Backup registers in TAMP have three protection zones configured in
BKPRWDPROT[7:0] and BKPWDPROT[7:0] registers:
– Protection zone 1 is read non-secure, write non-secure
– Protection zone 2 is read non-secure, write secure
– Protection zone 3 is read secure, write secure
Note: The TAMP security configuration is not affected by a system reset.
See Section 42: Tamper and backup registers (TAMP) for details.

General-purpose I/Os (GPIO)

When TrustZone® security is activated (TZEN = 1), each I/O pin of GPIO port can be
individually configured as secure through the GPIOx_SECCFGR registers. Only secure
application can write to GPIOx_SECCFGR registers. After boot, each I/O pin of GPIO is set
as secure.
When an I/O pin is configured as secure, its corresponding configuration bits for alternate
function (AF), mode selection (MODE) and I/O data are RAZ/WI in case of non-secure
access.
When digital alternate function is used (input/output mode), in order to protect the data
transiting from/to the I/O managed by a secure peripheral, the STM32L552xx and

RM0438 Rev 7 115/2194

132
System security RM0438

STM32L562xx add a secure alternate function gate on the path between the peripheral and
its allocated I/Os:
• If the peripheral is secure, the I/O pin must also be secure to allow input/output of data
• If the peripheral is not secure, the connection is allowed regardless of the I/O pin state.
TrustZone®-aware logic around GPIO ports used as alternate function is summarized in
Table 14.

Table 14. Secure Alternate function between peripherals and allocated I/Os
Security configuration Alternate function logic
Comment
Peripheral Allocated I/O pin Input Output

Secure -
Secure I/O data Peripheral data
Non-secure Out of reset configuration
Secure Zero Zero
Non-secure -
Non-secure I/O data Peripheral data

When analog function with analog switch is used, the connection to the peripherals
described in Table 15 is blocked by hardware when the peripheral is non-secure and the I/O
is secure.

Table 15. Summary of the I/Os that cannot be connected to a non-secure peripheral
when secure
Peripheral Analog function(1) Output Input

ADCx (x= 1, 2) ADC12_INy (y= 1 to 16) - X

OPAMPx (x= 1, 2) OPAMPx_VINy (x= 1, 2 ; y= 1, 2) - X
COMPx (x= 1, 2) COMPx_INy (x= 1, 2 ; y = 1, 2) - X
1. To find the I/O corresponding to the signal/function on the package, refer to the product datasheet.

Finally, regarding GPIO and security, Table 16 summarizes the list of I/Os that do not have
an hardware protection linked to TrustZone®. More specifically the listed signals (input
and/or outputs) are not blocked when the I/O is set as secure and the associated peripheral
is non secure.
For example, when secure application sets PA4 as secure to be used as LPTIM2_OUT, if
the DAC peripheral is non-secure it can be programmed to output data to PA4, potentially
causing malfunction to the secure application.
Similarly, when secure application sets PA0 as secure to be used as UART4_TX, if the
TAMP peripheral is non-secure it can be programmed to capture the USART input traffic
through the TAMP_IN signal.
Hence it is important that for each case described in Table 16 secure application decides if a
potential effect on data integrity or confidentiality is critical or not. For example, if the USART
situation described above is not acceptable (data transiting on secure USART is
confidential) then the secure application should configure the TAMP peripheral as secure
even if it is not used by the secure application.

116/2194 RM0438 Rev 7

RM0438 System security

Note: How to make a peripheral secure is summarized on the last column.

Table 16. Summary of the I/Os that can be secured and connected to a non-secure
peripheral
How to set the peripheral or
Peripheral Signal (1) Output Input
function as secure

Set DAC1SEC bit in the

DAC DAC1_OUTx (x=1,2) X -
GTZC_TZSC_SECCFGR1 register
PVD PVD_IN - X -
UCPD1_CCx (x=1,2) X X Set UCPD1SEC bit in the
UCPD1
UCPD1_DBx (x=1,2) - X GTZC_TZSC_SECCFGR1 register

TSC_G1_IOy (y= 1 to 3) - X
TSC_G2_IOy (y= 1 to 4) - X
Set TSCSEC bit in the
TSC TSC_G3_IOy (y= 2 to 4) - X GTZC_TZSC_SECCFGR2 register
TSC_Gx_IOy
- X
(x=4 to 8, y=1 to 4)
TAMP_INx (x= 1 to 8) - X Set TAMPDPROT bit in the
TAMP
TAMP_OUTy (x= 1 to 8) X - TAMP_SMCR register

RTC_OUTx (x=1,2) X - Set DECPROT bit in RTC_SMCR

RTC_REFIN - X register
RTC
Set TSDPROT bit in RTC_SMCR
RTC_TS - X
register.
Set WUPxSEC bit in
PWR WKUPx (x=1 to 5) - X
PWR_SECCFGR register
Set LSESEC bit in RCC_SECCFGR
RCC LSCO X -
register
Set SEC bit in EXTI_SECCFGR
EXTI EXTIx (x=0 to 15) - X
register
1. To find the I/O corresponding to the signal/function on the package, refer to the product datasheet.

For more detailed information on the topic refer to Section 11: General-purpose I/Os
(GPIO).

Extended interrupts and event controller (EXTI)

When the TrustZone® security is activated (TZEN = 1), the EXTI is able to protect event
register bits from being modified by non-secure accesses. The protection can individually be
activated per input event via the register bits in EXTI_SECCFGR registers. At EXTI level,
the protection consists in preventing unauthorized write access to:
• the change of settings for the secure configurable events,
• the change of masking for the secure input events,
• the clearing of pending status for the secure input events.
The security configuration in registers EXTI_SECCFGR can be globally locked after reset in
EXTI_LOCKR register.

RM0438 Rev 7 117/2194

132
System security RM0438

See Section 17: Extended interrupts and event controller (EXTI) for details.

System configuration controller (SYSCFG)

Like all TrustZone®-aware peripherals, a non-secure read/write access to a secured
SYSCFG register is RAZ/WI. Such access also generates an illegal access event that
triggers a secure illegal access interrupt if the SYSCFG illegal access event is not masked
in the TZIC.
See Section 12: System configuration controller (SYSCFG) for details.

4.6.7 Activating TrustZone® security

TrustZone® is disabled by default in all STM32L552xx and STM32L562xx devices. It can be
activated by setting the TZEN option bit in FLASH_OPTR when RDP level = 0. Once TZEN
has changed from 0 to 1 the default security state after reset is always the following:
• CPU subsystem
– Cortex®-M33 exits reset in secure state, hence the boot address must point
toward a secure memory area
– All interrupt sources are secure (in NVIC)
– The memory mapped viewed by the CPU through IDAU/SAU is fully secure
• Embedded Flash memory
– Flash memory non-volatile secure areas are defined with non-volatile registers
SECWMxR (where x = 1 or 2).
– Volatile block-based security attributions of the Flash memory are non-secure.
• Embedded SRAM memories
– All SRAMs are secure, as defined in GTZC/MPCBB (see Section 4.6.5). Secure
boot code can change this security setup, making blocks secure or not as needed.
• External memories
– All memory devices connected to FSMC and OCTOSPIs are secure, as defined in
GTZC/MPCWM (see Section 4.6.5). Secure boot code can change this security
setup, making components secure or not as needed.
• All GPIOs are secure
• All DMA channels are non-secure
• Backup registers are non-secure
• About peripherals and GTZC
– Securable peripherals are non-secure and unprivileged
– TrustZone®-aware peripherals are non-secure, with their secure configuration
registers being secure.
– All illegal access interrupts in GTZC/TZIC are disabled
Note: Refer to Table 10 and Table 11 in Section 4.6.5 for the list of securable and TrustZone®-
aware peripherals.

4.6.8 De-activating TrustZone® security

Once TrustZone® is activated on the device it can only be deactivated during a RDP
regression to level 0 (example: RDP change from 1 to 0, or from 0.5 to 0).

118/2194 RM0438 Rev 7

RM0438 System security

Note: Such RDP regression triggers the erase of embedded memories (SRAM2, flash), and the
reset of all peripherals, including the on-the-fly decryption and all the crypto engines.
After the TrustZone® deactivation, most features mentioned in Section 4.6 are no more
available. More specifically:
• Non-volatile secure area of embedded Flash memory is deactivated, including the HDP
area
• NVIC only manages non-secure interrupts
• All secure registers in TrustZone®-aware peripherals are RAZ/WI.
Note: When TrustZone® is disabled GTZC can still be used to configure the privilege access to
securable peripherals.
For more information please refer to application AN5347 available at www.st.com.

4.7 Other resource isolations

These are hardware mechanisms offering an additional level of isolation on top of
TrustZone® technology.

4.7.1 Temporal isolation using secure hide protection (HDP)

The STM32L552xx and STM32L562xx embedded Flash memory allows to define one hide
protection (HDP) area per watermarked-secure area of each bank. The code executed in
HDP area, with its related data and keys, can be hidden after boot until the next system
reset. Hide protection principle is pictured on Figure 8.
The number of HDP area, and its granularity, depends on the DBANK mode:
• in single-bank mode (DBANK=0) two HDP area can be defined, with the granularity of
a 4 Kbytes page.
• in dual-bank mode (DBANK=1) one HDP area per bank can be defined, with the
granularity of a 2 Kbytes page.

RM0438 Rev 7 119/2194

132
System security RM0438

When HDPxEN and HDPxACCDIS bits are set, data read, write and instruction fetch on the
area defined by SECWMx_STRT and HDPx_PEND are denied until next device reset.

Figure 8. Flash memory secure hide protection (HDP) area

User User
applications applications

Secure Secure
Flash memory Flash memory
Secure area

applications applications
2) Jump to secure code and hide area
Secure boot
code and data Hidden
(HDP)

1) Execute after reset

MSv67370V1

Note: Bank erase aborts when it contains a write-protected area (WRP or HDP area).
HDP area can be resized by secure application if the area is not hidden and if RDP level is
different than 2.

4.8 Secure execution

4.8.1 Introduction
Through a mix of special software and hardware features, STM32L552xx and
STM32L562xx devices ensure the correct operation of their functions against abnormal
situations caused by programmer errors, software attacks through network access or local
attempt for tampering code execution.
This section describes the hardware features specifically designed for secure execution.

4.8.2 Memory protection unit (MPU)

The Cortex®-M in STM32L552xx and STM32L562xx devices includes a memory protection
unit (MPU) that can restrict the read and write accesses to memory regions (including
regions mapped to peripherals), based on one or more of the following parameters
• Cortex®-M operating mode (privileged, unprivileged)
• Data/instruction fetch
The memory map and the programming of the non-secure and secure MPUs split memory
into regions (up to eight per MPU). Secure MPU is only available when TrustZone is
activated.

120/2194 RM0438 Rev 7

RM0438 System security

4.8.3 Embedded Flash memory write protection

The embedded Flash memory write protection (WRP) prevents illegals or unwanted
write/erase to special sections of the embedded Flash memory user area (system area is
permanently write protected).
Write protected area is defined through the option bytes, writing the start and end
addresses. More specifically, in STM32L552xx and STM32L562xx:
• In single-bank mode (DBANK = 0) four write-protected areas can be defined, with the
granularity of a 4 Kbytes page.
• In dual-bank mode (DBANK = 1) two write-protected areas can be defined in each
bank, with the granularity of a 2 Kbytes page.
WRP areas can be modified through option byte changes while RDP level is less than 2.
Note: Bank erase aborts when it contains a write-protected area (WRP or HDP area)

4.8.4 Tamper detection and response

Principle
STM32L552xx and STM32L562xx devices include active protection of critical security
assets against temperature, voltage and frequency attacks. More specifically, it features:
• erasure of device secrets upon tamper detection
• improved guarantee of safe execution for the CPU and its associated security
peripherals, including:
– out-of-range voltage (example: VBAT, VDDA), temperature and clocking (LSE)
detection
– security watchdog IWDG clocked by the internal oscillator LSI
– possible selection of internal oscillator HSI as system clock
• power supply protection
– RTC/TAMP domain powered automatically with VDD or VBAT
See Section 42: Tamper and backup registers (TAMP) for details.

Tamper detection sources

The device features three active tamper inputs (TAMP_IN1,2,3) associated to one active
output tamper pin (TAMP_OUT2), available in all power modes (including VBAT mode).
The device also has a number of internal tamper sources, as described in Table 17.
Note: Timestamps are automatically generated when a tamper event occurs.

Table 17. Internal tampers in TAMP

Tamper input NOER bit Tamper source

itamp1 TAMP_CR3[0] VDD upper voltage threshold monitoring

itamp2 TAMP_CR3[1] Temperature monitoring
itamp3 TAMP_CR3[2] LSE monitoring
itamp4 - not used
itamp5 TAMP_CR3[4] RTC calendar overflow (rtc_calovf)

RM0438 Rev 7 121/2194

132
System security RM0438

Table 17. Internal tampers in TAMP (continued)

Tamper input NOER bit Tamper source

itamp6 - not used

itamp7 - not applicable
itamp8 TAMP_CR3[7] Monotonic counter overflow (generated internally)

Response to tampers
Each source of tamper in the device can be configured to trigger the following events:
• Generate an interrupt, capable of waking up the device from Stop and Standby modes
(see TAMPxMSK bits in TAMP_CR2 register)
• Generate a hardware trigger for the low-power timers
• Erase of device secrets if corresponding TAMPxNOER bit is cleared in TAMP_CR2
register (for tamper pins) or TAMP_CR3 register (for internal tamper). These erasable
secrets are:
– Symmetric keys stored in backup registers (x32), in AES, HASH and in OTFDEC
(encrypted Flash memory regions are read as zero)
– Asymmetric keys stored in PKA SRAM
– Other secrets stored in SRAM2 and CPU instruction cache memory
Note: Device secrets erase are also triggered by setting the BKERASE bit in the TAMP_CR2
register, or by performing an RDP regression as defined in Section 4.11.2: Lifecycle
management with readout protection (RDP).
Device secrets are not reset by system reset or when the device wakes up from Standby
mode.

Tamper detection and low power modes

The effect of low power modes on tamper detection are summarized on Table 18.

Table 18. Effect of low-power modes on TAMP

Mode Description

No effect on tamper detection features.

Sleep
TAMP interrupts cause the device to exit the Sleep mode.
No effect on tamper detection features, except for level detection with filtering and active
Stop tamper modes which remain active only when the clock source is LSE or LSI.
Tamper events cause the device to exit the Stop mode.
No effect on tamper detection features, except for level detection with filtering and active
Standby tamper modes which remain active only when the clock source is LSE or LSI.Tamper
events cause the device to exit the Standby mode.
No effect on tamper detection features, except for level detection with filtering and active
Shutdown tamper modes which remain active only when the clock source is LSE. Tamper events
cause the device to exit the Shutdown mode.

122/2194 RM0438 Rev 7

RM0438 System security

4.9 Secure storage

4.9.1 Introduction
A critical feature of any security system is how root keys are stored, protected, and
provisioned. Such keys are typically used for loading a boot image, or handling of critical
user data.
Figure 9 shows how key management service application can use the AES engine for
example to compute external image decryption keys. Embedded non-volatile key can be
stored in the secure HDP area (see Section 4.7.1), while volatile key storage consists in the
battery-powered, tamper-protected SRAM or registers in TrustZone®-aware TAMP
peripheral.
Details on tamper protection is found in Section 4.8.4, while TrustZone® features of TAMP is
briefly described in Section 4.6.6.

Figure 9. Key management principle

Embedded
key
non-volatile storage
AES
(secure or non-secure)
Embedded
volatile storage key
(tamper resistant)
key

OTFDEC

key Secure software transfer of keys (write only)

MSv64453V1

4.9.2 Unique ID
The STM32L552xx and STM32L562xx store a 96-bit ID that is unique to each device. It is
stored at the address 0x0BFA 0590.
Application services can use this unique identity key to identify the product in the cloud
network, or make it difficult for counterfeit devices or clones to inject untrusted data into the
network.

4.10 Crypto engines

4.10.1 Introduction
STM32L552xx and STM32L562xx devices implement state-of-the-art cryptographic
algorithms featuring key sizes and computing protection as recommended by national
security agencies such as NIST for the U.S.A, BSI for Germany or ANSSI for France. Those
algorithms are used to support privacy, authentication, integrity, entropy and identity
attestation.

RM0438 Rev 7 123/2194

132
System security RM0438

The crypto engines embedded in STM32 reduces weaknesses on the implementation of

critical cryptographic functions, preventing for example the use of weak cryptographic
algorithms and key sizes. They also enable lower processing times and lower power
consumption when performing cryptographic operations, offloading those computations
from Cortex®-M33. This is especially true for asymmetric cryptography.
For product certification purpose, ST can provides certified device information on how these
security functions are implemented and validated.
For more information on crypto engine processing times, refer to their respective sections in
the reference manual.

4.10.2 Crypto engines features

Table 19 lists the accelerated cryptographic operations available in the STM32L552xx and
STM32L562xx devices.
Note: Additional operations can be added using firmware.
Public key accelerator can accelerate asymmetric crypto operations (like key pair
generation, ECC scalar multiplication, point on curve check). See Section 32: Public key
accelerator (PKA) for details.

Table 19. Accelerated cryptographic operations

Algo- Key lengths
Operations Specification Modes
rithm (in bit)

Get entropy RNG NIST SP800-90B(1) N/A N/A

FIPS PUB 197
Encryption, decryption 128, 256 ECB, CBC, CTR
NIST SP800-38A

Authenticated encryption or NIST SP800-38C

AES 128, 256 GCM, CCM
decryption NIST SP800-38D
Cipher-based message
NIST SP800-38D 128, 256 GMAC
authentication code
MD5 IETF RFC 1321 Digest 128-bit
Checksum
SHA-1 n/a Digest 160-bit
FIPS PUB 180-4
Cryptographic hash SHA-2 SHA-224, SHA-256

Keyed-hashing for message FIPS PUB 198-1 short, long

HMAC -
authentication IETF RFC 2104 (>64 bytes)

Encryption/decryption IETF RFC 8017

RSA up to 3136 RSAES-OAEP
key-pair generation NIST SP800-56B

124/2194 RM0438 Rev 7

RM0438 System security

Table 19. Accelerated cryptographic operations (continued)

Algo- Key lengths
Operations Specification Modes
rithm (in bit)

IETF RFC 8017

RSA up to 3136 PKCS1-v1_5, PSS
FIPS PUB 186-4
Signature with hashing
ANSI X9.62 Nist: P-256, P-384,
Signature verification
ECDSA IETF RFC 7027 P-521,...
FIPS PUB 186-4 Brainpool:
P256r1/t1,
up to 640
P384r1/t1,
P512r1/t1,...
Key agreement ECDH ANSI X9.42
SEC2: secp256k1
OSCCA SM2
1. Certifiable using STMicroelectronics reviewed documents.

4.10.3 On-the-fly decryption engine (OTFDEC)

OTFDEC TrustZone®-aware peripheral proposes on-the-fly decryption of encrypted images
stored on external Flash memory, connected through OCTOSPI peripheral. This decryption
process introduces almost no additional cycle overhead when standard NOR Flash memory
is used. OTFDEC can also be used to encrypt Flash memory images on the device, for
example to encrypt with a device unique secret key.
When a tamper event is confirmed in TAMP peripheral, all OTFDEC keys are erased and
encrypted regions read as zero until OTFDEC is properly initialized again.
Typical usage of OTFDEC can be found in Section 4.13.3: Software intellectual property
protection with OTFDEC. For more details on the programming of the peripheral please
refer to Section 31: On-the-fly decryption engine (OTFDEC).

4.11 Product Lifecycle

4.11.1 Introduction
A typical IoT device lifecycle is summarized in Figure 10. For each step, STM32L552xx and
STM32L562xx devices propose secure lifecycle management mechanisms embedded in
the hardware.

RM0438 Rev 7 125/2194

132
System security RM0438

Figure 10. Device lifecycle security

Vendor states
User states
Virgin device

Device manufacturing

STM32 personalized device

Development platform Vendor manufacturing

Use
r pr
ovis
ioni
ng
Platform
tio n
tiza
duc
Pro
Deployed product

Fie
Decommissioning ld
ret
urn

Decommissioned product Return material for analysis

MSv64454V1

More details on the various phases and associated transitions, found either at the vendor or
end user premises, are summarized on Table 20.

Table 20. Main product lifecycle transitions

Transitions Description

STMicroelectronics creates new STM32 devices, always checking for manufacturing

Device manufacturing defects. During this process STM32 is provisioned with ROM firmware, secure firmware
install (SFI) unique key pair, and a public ID.
One (or more) vendor is responsible for the platform assembly, initialization, and
provisioning before delivery to the end user. This end user can use the final product
Vendor manufacturing
(“productization” transition) or he/she can use the platform for software development
(“user provisioning” transition).
The end user gets a product ready for use. All security functions of the platform are
Productization enabled, the debugging/testing features are restricted/disabled, and unique boot entry to
immutable code is enforced.
Platform vendor prepares an individual platform for development, not to be connected to
User provisioning
a production cloud network.
Those are one way transitions, with devices kept in user premises or returned to the
Field return or
manufacturer. In both cases all data including user data are destroyed, therefore the
decommissioning device loses the ability to operate securely (e.g. connecting to a managed IoT network).

The features described hereafter contribute to securing the device lifecycle.

126/2194 RM0438 Rev 7

RM0438 System security

4.11.2 Lifecycle management with readout protection (RDP)

The readout protection mechanism (full hardware feature) controls the access to the
STM32L552xx and STM32L562xx debug, test and provisioned secrets, as summarized on
Table 21. The supported transitions, summarized on Figure 11, can be requested (when
available) through the debug interface or via the system bootloader.

Table 21. Typical product lifecycle phases

RDP protection level Debug Comments

Level Secure(1) and Boot address must target a secure area when TrustZone® is enabled
Device is open
0 non-secure (secure SRAM, secure Flash memory, RSS in system Flash memory).
Boot address must target a secure area when TrustZone® is enabled
Device is partially (secure user or system Flash memory). boot on SRAM is not
Level Non-secure
(2) closed (closed- permitted.
0.5 only
secure) Access to non-secure Flash memory is allowed when debug is
connected.
Boot address must target the secure user Flash memory.
Non-secure
Level Device memories Accesses to non-secure Flash memory, encrypted Flash memory(3),
only
1 are protected SRAM2 and backup registers are not allowed when debug is
(conditioned)
connected.

Level None Boot address must target the user Flash memory (secure if TZEN=1).
Device is closed
2 (JTAG fuse) Option bytes are read-only, hence RDP level 2 cannot be changed.
1. Debug is not available when executing RSS code.
2. Only applicable when TrustZone® security is activated in the product.
3. External Flash memory area decrypted on-the-fly with OTFDEC peripheral.

Figure 11. RDP level transition scheme

TrustZone® disabled TrustZone® enabled

Full Flash
memory erase +
secret erase
RDP1
RDP1
Non-secure
Full Flash
Flash memory
memory erase +
erase +
secret erase
secret erase

RDP2 RDP0 RDP0.5

RDP2 RDP0

MSv64463V1

As shown on Figure 11, the user Flash memory is automatically erased, either partially or in
totality, during a RDP regression. During the transition from RDP1 to RDP0.5 only non-
secure embedded Flash memory is erased, keeping functional for example the secure boot
and the secure firmware update. In all regressions OTP area in Flash memory is kept, and
device secrets are erased, hence no secrets shall be stored in OTP as they are revealed
after a regression to RDP0. Those secrets, erased as response to tamper, are defined in
Section 4.8.4: Tamper detection and response.
Note: Enabling TrustZone® using option byte TZEN is only possible when RDP level is 0.

RM0438 Rev 7 127/2194

132
System security RM0438

For more details on RDP please refer to Section 6: Embedded Flash memory (FLASH).

4.11.3 Recommended option byte settings

Most of the time, the user threat model focuses mainly on software attacks, in this case, it
may be sufficient to keep the RDP level 1 as device protection.
For a more aggressive threat model, where user may fear physical attacks on the STM32
device, it is recommended to optimize the level of security by setting the RDP level 2. The
recommended settings are detailed below:
If TrustZone® is disabled (TZEN=0) it is recommended to set the following option bytes:
• RDP = level 2
• Non-secure boot address option bytes set in user Flash memory
If TrustZone® is enabled (TZEN=1) it is recommended to set the following option bytes:
• RDP = level 2
• Boot_lock = 1
• Secure boot address option bytes set in user Flash memory

4.12 Access controlled debug

4.12.1 Introduction
The device restricts access to embedded debug features, in order to guarantee the
confidentiality of customer assets against unauthorized usage of debug & trace features.

4.12.2 Debug protection with readout protection (RDP)

As described in Section 4.11.2 the hardware readout protection (RDP) mechanism
automatically controls the accesses to the device debug and tests. The protection of these
debug features are defined in Table 22

Table 22. Debug protection with RDP

RDP protection level Debug features protection

Level 0 Device is open Any debug(1)

Level 0.5(2) Device is partially closed Secure debug is no more available
Non-secure debug can no longer debug code &
data stored in embedded Flash memory, encrypted
Level 1 Device memories are protected
external Flash memory(3), SRAM2 and backup
registers
Level 2 Device is closed JTAG is physically deactivated
1. Including ST engineering test modes, used for field returns.
2. Only applicable when TrustZone® security is activated in the product.
3. External Flash memory area decrypted on-the-fly with OTFDEC peripheral.

128/2194 RM0438 Rev 7

RM0438 System security

4.13 Software intellectual property protection and collaborative

development

4.13.1 Introduction
Thanks to software intellectual property protection and collaborative model the
STM32L552xx and STM32L562xx devices allow to integrate and implement with third-party
libraries innovative solutions.
Collaborative development is summarized on Figure 12. Starting from a personalized device
sold by STMicroelectronics, a vendor A can integrate a portion of hardware and software on
a platform A, that can then be used by a vendor B that will do the same before deploying a
final product to the end users.
Note: Each platform vendor can provision individual platforms for development, not to be
connected to a production cloud network (“Development Platform X”).

Figure 12. Collaborative development principle

Vendor states
User states

STM32 personalized
device

Vendor A manufacturing Platform part

Development platform B
Use ed
r pro rat
visio eg
ning Int
Platform A

Development platform B Vendor B manufacturing Platform part

Use ed
r pro rat
visio eg
ning Int
Platform B
atio n
uctiz
Prod
Deployed product

Decommissioning

Decommissioned product

MSv64455V1

The features described hereafter contribute to securing the software intellectual property
within such a collaborative development.

4.13.2 Software intellectual property protection with

readout protection (RDP)
As described in Section 4.11.2 the hardware readout protection (RDP) mechanism
automatically controls the accesses to secrets provisioned in the device. The protection of
these secrets are defined in Table 23.

RM0438 Rev 7 129/2194

132
System security RM0438

Table 23. Software intellectual property protection with RDP

RDP protection level Secrets protection

Level 0 Device is open No special protections.

All peripherals and memories mapped as secure during
Level 0.5(1) Device is partially closed
secure boot cannot be dumped, debugged or traced
Data and code stored in embedded Flash memory,
Device memories are
Level 1 encrypted external Flash memory(2), SRAM2 and
protected
backup registers are no more accessible via debugger.
All data and code stored in the device or encrypted in
Level 2 Device is closed external Flash memory cannot be dumped clear-text,
debugged or traced.
1. Only applicable when TrustZone® security is activated in the product.
2. External Flash memory area decrypted on-the-fly with OTFDEC peripheral.

4.13.3 Software intellectual property protection with OTFDEC

As described in Section 4.10.3 the OTFDEC peripheral associated with the OCTOSPI is
able to decrypt on-the-fly encrypted images stored in external SPI Flash memory devices.
Thanks to this feature STM32L562xx devices allow the installation of intellectual properties:
• over the air, with the image already encrypted with a key provisioned in the device, or
• through a provisioning host located in a trusted or an non-trusted environment/facility.
Figure 13 illustrates this last case with the provisioning, in a non-trusted environment, of
software intellectual properties both in embedded Flash memory and in external SPI Flash
memory (encrypted).
Note: Since OTFDEC is using AES in counter mode (CTR) to achieve the lowest possible latency,
each time the content of one encrypted region is changed the corresponding cryptographic
context (key or initialization vector) must be changed. This constraint makes OTFDEC
suitable to decrypt read-only data or code, stored in external NOR Flash memory.

130/2194 RM0438 Rev 7

RM0438 System security

Figure 13. External Flash memory protection using SFI

Provisioning
STM32
SRAM2
Secure Flash
JTAG 3
bootloader
part II
Option
bytes Octo-
2 Flash
USART OTF SPI
memory
DEC
SPI 4 5 6
ROM
Secure
I2C
bootloader
Host FDCAN part I SRAM
1
1 USB

1 ... 6 See details in section “Provisioning” below the figure.

Secure boot
STM32
Application
Octo-
Flash 1 OTF Flash
SPI
Secure boot memory
DEC
2
tamper

1 ... 2 See details in section “Secure boot” below the figure.

MSv65211V2

Provisioning
Assuming the device is virgin, the first step is to provision both Flash memories, as detailed
below:
1. User creates an SFI image, composed of:
– Encrypted internal firmware and data (including external Flash memory drivers)
– Encrypted external firmware and data AES key (up to 4)
– Encrypted external firmware and data image
2. The secure bootloader stored in system memory loads the second part of the secure-
bootloader in SRAM2 through the supported communication ports (USART, SPI, I2C,
FDCAN, USB and JTAG). This second part runs in secure SRAM2 and is responsible

RM0438 Rev 7 131/2194

132
System security RM0438

for executing the SFI process, applying the SFI protocol thanks to the commands
received through the above mentioned supported communication ports.
3. Internal Flash memory is programmed with decrypted option bytes, internal firmware
and data, and external firmware and data AES key(s). Alternatively, device unique
external firmware AES keys could be used instead of such global keys.
4. OTFDEC is properly initialized with encrypted region(s) information, including the
corresponding external firmware and data AES key.
5. Running the SFI process, chunks of encrypted external firmware and data image are
decrypted in the device, then re-encrypted in OTFDEC.
6. After chunk OTFDEC re-encryption, user external Flash memory programmer is
responsible for programming those last encrypted chunks to external SPI Flash
memories through OCTOSPI peripheral.

Secure boot
After provisioning, each time the device initializes on trusted firmware, the following actions
are required:
1. Secure boot firmware executes, programming the external firmware and data AES
key(s) to OTFDEC write-only key registers, along with the other needed information.
2. Application reads or executes the encrypted external firmware and data through
OCTOSPI memory mapped mode, unless a tamper event is detected. In this case all
OTFDEC keys are erased and encrypted regions read as zero until OTFDEC is
properly initialized again.
For more information on above secure firmware install (SFI) solutions for STM32L552xx and
STM32L562xx devices please refer to AN4992 on STMicroelectronics website.

4.13.4 Other software intellectual property protections

STM32L552xx and STM32L562xx devices additional protections to software intellectual
property is:
• Invasive attacks such as physical tampering or perturbation are countered by detection
then decommissioning of the device before the detected attack succeeds.

132/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

5 Global TrustZone® controller (GTZC)

5.1 GTZC introduction

This section includes the description of the three following sub-blocks:
• TZSC: TrustZone® security controller
This sub-block defines the secure/privilege state of slave/master peripherals. It also
controls the non-secure area size for the watermark memory peripheral controller
(MPCWM). The TZSC block informs some peripherals (such as RCC or GPIOs) about
the secure status of each securable peripheral, by sharing with RCC and I/O logic.
• MPCBB: block-based memory protection controller
This sub-block controls secure states of all blocks (256-byte pages) of the associated
SRAM.
• TZIC: TrustZone illegal access controller
This sub-block gathers all illegal access events in the system and generates a secure
interrupt towards NVIC.
These sub-blocks are used to configure TrustZone system security in a product having bus
agents with programmable-security and privileged attributes (securable) such as:
• on-chip RAM with programmable secure blocks (pages)
• AHB and APB peripherals with programmable security and/or privilege access
• AHB master granted as secure and/or privilege
• off-chip memories with secure areas

5.2 GTZC main features

GTZC main features are listed below:
• 3 independent 32-bit AHB interface for TZSC, MPCBB and TZIC
• MPCBB and TZIC accessible only with secure transactions
• Secure and non-secure access supported for priv/non-priv part of TZSC
• Set of registers to define product security settings:
– Secure blocks for internal SRAM
– Non-secure regions for external memories
– Secure/privilege access mode for securable and TrustZone-aware peripherals
– Secure/privilege access mode for securable masters

5.2.1 GTZC TrustZone system architecture

The Armv8-M supports security per TrustZone-M model with isolation between:
• a secure world, where usually security sensitive applications are run and critical
resources are located; secure transactions are signaled with HNONSEC[1] = 0 on AHB
bus
• a non-secure or public world (such as usual non secure and user space) where non-
secure transactions are signaled with HNONSEC = 1 on AHB bus

RM0438 Rev 7 133/2194

176
Global TrustZone® controller (GTZC) RM0438

The TrustZone architecture is extended beyond AHB and Armv8-M with:

• AHB/APB bridge used as secure gate to block or propagate secure/non-secure and
privilege/non-privilege transaction towards APB agents
• peripheral protection controller (PPC) used as secure gate to block or propagate
secure/non-secure and privilege/non-privilege transaction towards AHB agents
• TrustZone block-based MPC firewalls used as secure gate to filter secure/non secure
access towards internal SRAMs
• Trustzone watermark MPC firewalls used as secure gate to filter secure/non secure
access towards external memories
AHB and APB peripherals can be categorized as:
• privilege: peripherals protected by AHB/APB firewall stub that is controlled from TZSC
to define privilege properties
• secure: peripherals always protected by an AHB/APB firewall stub. These peripherals
are always secure (TZIC).
• securable: peripherals protected by an AHB/APB firewall stub that is controlled from
TZSC to define security properties (optional)
• non-secure and non-privilege: peripherals connected directly to AHB/APB
interconnect without any secure gate
• TrustZone-aware: peripherals connected directly to AHB or APB bus and
implementing a specific TrustZone behavior (such as a subset of registers being
secure). TrustZone-aware AHB masters always drive HNONSEC signal according to
their security mode (such as Armv8-M core or DMA).
AHB securable masters can be configured in the TZSC to be secure/non-secure and/or
privilege/non-privilege.

Application information
The TZSC, MPCBB and TZIC sub-blocks can be used in one of the following ways:
• programmed during secure Boot only, locked and not changed afterwards
• dynamically re-programmed when using specific application code or secure kernel
(microvisor). When not locked, MPC secure blocks or region size can be changed by
secure software executing from the secure FLASH memory region or secure SRAM.
Same remark applies to the GTZC_TZSC_SECCFRGx and
GTZC_TZSC_PRIVCFGRx registers that define secure/privilege state of each
peripheral.

134/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

The Armv8-M security architecture with secure, securable and TrustZone-aware peripherals
is shown in Figure 14.

Figure 14. GTZC in Armv8-M subsystem block diagram

AHB
Armv8-M AHB
Masters...
MCU masters

Master sec/priv
Security master wrapper
AHB

AHB2/APB bridge
MPC
TZIC
Sec/priv gate BBx

Periph
sec / priv

Periph
sec / priv
AHB-PPC
TZSC stub
UART
MPCWMx

MPCBBx Crypto
Crypto
APB (AES)
GTZC (AES)
Block 1- NS NS
Block 2 - S
Block 3 - S
Block 4 - NS Securable
Timer ... peripherals
SPI NS
SPI Timer ...
Block N-1 - S
Block N - NS
External memories
Internal SRAM
Securable peripherals Securable memories
MSv48198V2

5.3 GTZC functional description

5.3.1 GTZC block diagram

Figure 15 describes the combined feature of TZSC, MPCBB and TZIC. Each sub-block is
controlled by its own AHB configuration port. The TZSC defines which peripheral is secured
and/or privileged.
The privilege configuration bit of a given peripheral can be modified by a secure-privilege
transaction when the peripheral has been configured as secure, otherwise a privileged
transaction (non-secure) is sufficient. The definition of these privilege attributes is possible
even when TZEN = 0.

RM0438 Rev 7 135/2194

176
Global TrustZone® controller (GTZC) RM0438

The secure configuration bit a given peripheral can be modified only with a secure-privilege
transaction if the peripheral has been configured as privilege, otherwise a secure
transaction (non-privileged) is sufficient.

Figure 15. GTZC block diagram

TZEN
(from option bytes)
GTZC

TZSC
Sec/NSec

AHB Priv/NPriv
SECCFGR
PRIVCFGR

TZSC_ILA_event
MPCWMR

MPCBB
AHB MPCBBVCT
MPCBB_VCTR
MPCBB_ILA_event

MPCBB_LCKVTR (to internal block based

memroy controller)

TZIC
IER
AHB SR GTZC_IRQn
TZIC_ILA_event

(to NVIC)
FCR

N x ILA_event (from peripherals)

MSv48199V2

5.3.2 Illegal access definition

Three different types of illegal access exist:
• Illegal non-secure access
Any non-secure transaction trying to write a secure resource is considered as illegal
and thus the addressed resource generates an illegal access event for illegal write
access, and a bus error for illegal fetch access. However some exceptions exist on
transactions to secure and privilege configuration registers; these later ones authorized
non-secure read access to secure registers (see GTZC_TZSC_SECCFGRx and
GTZC_TZSC_PRIVCFGRx registers).
• Illegal secure access
Any secure transaction trying to access a non-secure block in internal block-based
SRAM or watermarked external memory, is considered as illegal.
Correct settings of the TZIC allows the capture of the associated event and then
generates the GTZC_IRQn interrupt to the NVIC. This applies for read, write and
execute access.

136/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Concerning the MPCBB controller, there is an option to ignore secure data read/write
access on non-secure SRAM blocks, by setting the SRWILADIS configuration bit in the
GTZC_MPCBBx_CR register. Secure read and write data transactions are then
allowed on non-secure SRAM blocks, while secure execution access remains not
allowed.
Any secure execute transaction trying to access a non-secure peripheral register or
memory is considered as illegal and generates a bus error.
• Illegal non-privilege access
Any non-privilege transaction trying to acces a privilege resource is considered as
illegal. There is no illegal access event generated for this type of illegal access. The
addressed resource follows a silent-fail behavior, returning all zero data for read and
ignoring any write. No bus error is generated.

5.3.3 TrustZone security controller (TZSC)

This block is composed of a configurable set of registers, providing the following features:
• Control of secure and privilege state for all peripherals, done through:
– GTZC_TZSC_SECCFGRx registers to control AHB/APB firewall stubs for the
securable peripherals and/or master
– GTZC_TZSC_PRIVCFGRx registers to control AHB/APB firewall stubs for the
privileged peripherals and/or master
• For watermark memory protection controller (external memories), two independent
regions can be defined and the following fields are used to program:
– start of the first non-secure area on external memory = NSWMxSTRT1[10:0]
– length of the first non-secure area on external memory = NSWMxLGTH1[11:0]
– start of the second non-secure area on external memory = NSWMxSTRT2[10:0]
– length of the second non-secure area on external memory = NSWMxLGTH2[11:0]
Note: x represents the target external memory interface (such as FMC or OCTOSPI). The total
area considered as non-secure is the sum of the two independent ones. An overlap of one
section over the other one has no specific effect.
Table 24 describes the characteristics of the available MPCWMx.

Table 24. MPCWMx

MPC Type Number of regions Target memory interface

MPCWM1 Non secure watermark (region) 2 OCTOSPI

MPCWM2 Non secure watermark (region) 2 FMC_NOR bank
MPCWM3 Non secure watermark (region) 1 FMC_NAND bank

5.3.4 Memory protection controller - block based (MPCBB)

For block-based memory protection controller (internal SRAM), the below registers are
available:
• GTZC_MPCBBx_VCTRy to program the vector defining 32 consecutive 256-byte block
states, secure or non-secure (means y registers of 32 bits)
• GTZC_MPCBBx_LCKVTRy to program the lock of super block (32 blocks)

RM0438 Rev 7 137/2194

176
Global TrustZone® controller (GTZC) RM0438

Note: y represents the number of super-blocks (super-block = 32 blocks of SRAM_BB_size).

On the STM32L552xx and STM32L562xx devices, the SRAM size = 192 Kbytes and the
block size = 256 bytes, then super-block size = 32 * 256 = 8 Kbytes and y = 192 / 8 = 24.
It means 24 vector registers (32-bit) are needed to control the secure state of all the
256-byte blocks. Concerning the lock bit, only one 32-bit lock register is needed since a
single lock bit applies on a super-block (32 * 256 bytes).
Table 25 describes the characteristics of the available MPCBBx.

Table 25. MPCBBx

MPC Type Number of blocks Target memory interface

MPCBB1 Block based (block size = 256 bytes) 768 SRAM1

MPCBB2 Block based (block size = 256 bytes) 256 SRAM2

5.3.5 TrustZone illegal access controller (TZIC)

This block concentrates all illegal access source events. It is used only when the system is
TrustZone enabled (TZEN = 1).
TZIC allows the trace of which event trigged the NVIC GTZC_IRQn. Register masks
(GTZC_TZIC_IERx) are available to filter unwanted event. On unmasked illegal event, the
TZIC generates the GTZC_IRQn signal to NVIC that corresponds to the GTZC_IRQn
secure interrupt.
For each illegal event source, a status flag and a clear bit exist (respectively within
GTZC_TZIC_SRx and GTZC_TZIC_FCRx registers). The reset value of mask registers
(GTZC_TZIC_IERx) is such that all events are masked.

5.3.6 Power-on/reset state

The power-on and reset state of the TZSC clear all bits of GTZC_TZSC_SECCFGRx and
GTZC_TZSC_PRIVCFGRx registers to 0, which respectively means non-secure and non-
privilege. Concerning the internal SRAM, the reset values of the GTZC_MPCBBx_VCTRy
registers are set to 0xFFFF FFFF, making all blocks of the block-based SRAM memory
secure. This is valid only when TrustZone security is enabled at system level (TZEN = 1). In
the other case (legacy mode, TZEN = 0), the reset values of the GTZC_MPCBBx_VCTRy
registers are set to 0x0000 0000 so that all block-based SRAM memories are non-secure.
Same thing applies for external memories, all MPCWMx_NSWMyR registers must be set to
0xFFFF FFFF, making the whole external memory non-secure. Secure Boot code can then
program the security settings, making components secure or not as needed.

5.3.7 DMA requests

TZSC does not support any DMA interface.

5.4 GTZC events

MPCBB and TZIC are secure peripherals, thus they both systematically generate an illegal
access event when accessed by a non-secure access. The TZSC is a TrustZone-aware
peripheral, meaning that secure and non-secure registers co-exist within the peripheral. An

138/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

exception exists for the GTZC_TZSC_SECCFGR and GTZC_TZSC_PRIVCGFR: any read

access, secure or not, are supported.

5.5 GTZC_TZSC registers

All registers are accessed only by words (32-bit).

5.5.1 GTZC_TZSC control register (GTZC_TZSC_CR)

Address offset: 0x000
Reset value: 0x0000 0000
Write-secure access only.
Read accesses are authorized for any type of transactions, secure or not, privilege or not.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCK
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LCK: lock the configuration of TZSC items until next reset
This bit is unset by default and once set, it can not be reset until global TZSC reset.
0: control register not locked
1: control register locked

RM0438 Rev 7 139/2194

176
Global TrustZone® controller (GTZC) RM0438

5.5.2 GTZC_TZSC secure configuration register 1

(GTZC_TZSC_SECCFGR1)
Address offset: 0x010
Reset value: 0x0000 0000
Write-secure access only.
This register can be written only by privilege secure transaction when corresponding
TZSC_PRIVCFGR register signal is set to 1. If a given PRIV bit is not set, the equivalent
SEC bit can be written by non- privilege secure transaction.
Read accesses are authorized for any type of transactions, secure or not, privilege or not.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREFBUFSEC

LPUART1SEC
FDCAN1SEC

OPAMPSEC
LPTIM3SEC

LPTIM2SEC

LPTIM1SEC
UCPD1SEC

USBFSSEC
COMPSEC

DAC1SEC
TIM1SEC
SPI1SEC

CRSSEC
I2C4SEC

I2C3SEC
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3SEC

USART2SEC

WWDGSEC
UART5SEC

UART4SEC

IWDGSEC

TIM7SEC

TIM6SEC

TIM5SEC

TIM4SEC

TIM3SEC

TIM2SEC
SPI3SEC

SPI2SEC
I2C2SEC

I2C1SEC

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SPI1SEC: secure access mode for SPI1

0: non-secure
1: secure
Bit 30 TIM1SEC: secure access mode for TIM1
0: non-secure
1: secure
Bit 29 COMPSEC: secure access mode for COMP
0: non-secure
1: secure
Bit 28 VREFBUFSEC: secure access mode for VREFBUF
0: non-secure
1: secure
Bit 27 UCPD1SEC: secure access mode for UCPD1
0: non-secure
1: secure
Bit 26 USBFSSEC: secure access mode for USB FS
0: non-secure
1: secure
Bit 25 FDCAN1SEC: secure access mode for FDCAN1
0: non-secure
1: secure

140/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 24 LPTIM3SEC: secure access mode for LPTIM3

0: non-secure
1: secure
Bit 23 LPTIM2SEC: secure access mode for LPTIM2
0: non-secure
1: secure
Bit 22 I2C4SEC: secure access mode for I2C4
0: non-secure
1: secure
Bit 21 LPUART1SEC: secure access mode for LPUART1
0: non-secure
1: secure
Bit 20 LPTIM1SEC: secure access mode for LPTIM1
0: non-secure
1: secure
Bit 19 OPAMPSEC: secure access mode for OPAMP
0: non-secure
1: secure
Bit 18 DAC1SEC: secure access mode for DAC1
0: non-secure
1: secure
Bit 17 CRSSEC: secure access mode for CRS
0: non-secure
1: secure
Bit 16 I2C3SEC: secure access mode for I2C3
0: non-secure
1: secure
Bit 15 I2C2SEC: secure access mode for I2C2
0: non-secure
1: secure
Bit 14 I2C1SEC: secure access mode for I2C1
0: non-secure
1: secure
Bit 13 UART5SEC: secure access mode for UART5
0: non-secure
1: secure
Bit 12 UART4SEC: secure access mode for UART4
0: non-secure
1: secure
Bit 11 USART3SEC: secure access mode for USART3
0: non-secure
1: secure
Bit 10 USART2SEC: secure access mode for USART2
0: non-secure
1: secure

RM0438 Rev 7 141/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 9 SPI3SEC: secure access mode for SPI3

0: non-secure
1: secure
Bit 8 SPI2SEC: secure access mode for SPI2
0: non-secure
1: secure
Bit 7 IWDGSEC: secure access mode for IWDG
0: non-secure
1: secure
Bit 6 WWDGSEC: secure access mode for WWDG
0: non-secure
1: secure
Bit 5 TIM7SEC: secure access mode for TIM7
0: non-secure
1: secure
Bit 4 TIM6SEC: secure access mode for TIM6
0: non-secure
1: secure
Bit 3 TIM5SEC: secure access mode for TIM5
0: non-secure
1: secure
Bit 2 TIM4SEC: secure access mode for TIM4
0: non-secure
1: secure
Bit 1 TIM3SEC: secure access mode for TIM3
0: non-secure
1: secure
Bit 0 TIM2SEC: secure access mode for TIM2
0: non-secure
1: secure

142/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

5.5.3 GTZC_TZSC secure configuration register 2

(GTZC_TZSC_SECCFGR2)
Address offset: 0x014
Reset value: 0x0000 0000
Write-secure access only.
This register can be written only by privilege secure transaction when corresponding
TZSC_PRIVCFGR register signal is set to 1. If a given PRIV is not set, the equivalent SEC
bit can be written by non- privilege secure transaction.
Read accesses are authorized for any type of transactions, secure or not, privilege or not.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCTOSPI1_REGSEC

FMC_REGSEC

SDMMC1SEC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACHE_REGSEC

DFSDM1SEC

USART1SEC
TIM17SEC

TIM16SEC

TIM15SEC
HASHSEC

TIM8SEC
RNGSEC

CRCSEC

SAI2SEC

SAI1SEC
ADCSEC

TSCSEC
PKASEC

AESSEC

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 OCTOSPI1_REGSEC: secure access mode for OCTOSPI1 registers
0: non-secure
1: secure
Bit 17 FMC_REGSEC: secure access mode for FMC registers
0: non-secure
1: secure
Bit 16 SDMMC1SEC: secure access mode for SDMMC1
0: non-secure
1: secure
Bit 15 PKASEC: secure access mode for PKA
0: non-secure
1: secure
Bit 14 RNGSEC: secure access mode for RNG
0: non-secure
1: secure
Bit 13 HASHSEC: secure access mode for HASH
0: non-secure
1: secure

RM0438 Rev 7 143/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 12 AESSEC: secure access mode for AES

0: non-secure
1: secure
Bit 11 ADCSEC: secure access mode for ADC
0: non-secure
1: secure
Bit 10 ICACHE_REGSEC: secure access mode for ICACHE registers
0: non-secure
1: secure
Bit 9 TSCSEC: secure access mode for TSC
0: non-secure
1: secure
Bit 8 CRCSEC: secure access mode for CRC
0: non-secure
1: secure
Bit 7 DFSDM1SEC: secure access mode for DFSDM1
0: non-secure
1: secure
Bit 6 SAI2SEC: secure access mode for SAI2
0: non-secure
1: secure
Bit 5 SAI1SEC: secure access mode for SAI1
0: non-secure
1: secure
Bit 4 TIM17SEC: secure access mode for TIM17
0: non-secure
1: secure
Bit 3 TIM16SEC: secure access mode for TIM16
0: non-secure
1: secure
Bit 2 TIM15SEC: secure access mode for TIM15
0: non-secure
1: secure
Bit 1 USART1SEC: secure access mode for USART1
0: non-secure
1: secure
Bit 0 TIM8SEC: secure access mode for TIM8
0: non-secure
1: secure

144/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

5.5.4 GTZC_TZSC privilege configuration register 1

(GTZC_TZSC_PRIVCFGR1)
Address offset: 0x020
Reset value: 0x0000 0000
Write-privileged access only.
This register can be read or written only by secure privilege transaction when corresponding
TZSC_SECCFGR register signal is set to1. If a given SEC bit is not set, the equivalent PRIV
bit can be read/written by non-secure privileged transaction.
Read accesses are authorized for any type of transactions, secure or not, privilege or not.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREFBUFPRIV

LPUART1PRIV
FDCAN1PRIV

OPAMPPRIV
LPTIM3PRIV

LPTIM2PRIV

LPTIM1PRIV
UCPD1PRIV

USBFSPRIV
COMPPRIV

DAC1PRIV
TIM1PRIV
SPI1PRIV

I2C4PRIV

CRSPRIV

I2C3PRIV
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3PRIV

USART2PRIV

WWDGPRIV
UART5PRIV

UART4PRIV

IWDGPRIV

TIM7PRIV

TIM6PRIV

TIM5PRIV

TIM4PRIV

TIM3PRIV

TIM2PRIV
SPI3PRIV

SPI2PRIV
I2C2PRIV

I2C1PRIV

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SPI1PRIV: privilege access mode for SPI1

0: non-privilege
1: privilege
Bit 30 TIM1PRIV: privilege access mode for TIM1
0: non-privilege
1: privilege
Bit 29 COMPPRIV: privilege access mode for COMP
0: non-privilege
1: privilege
Bit 28 VREFBUFPRIV: privilege access mode for VREFBUF
0: non-privilege
1: privilege
Bit 27 UCPD1PRIV: privilege access mode for UCPD1
0: non-privilege
1: privilege
Bit 26 USBFSPRIV: privilege access mode for USB FS
0: non-privilege
1: privilege
Bit 25 FDCAN1PRIV: privilege access mode for FDCAN1
0: non-privilege
1: privilege

RM0438 Rev 7 145/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 24 LPTIM3PRIV: privilege access mode for LPTIM3

0: non-privilege
1: privilege
Bit 23 LPTIM2PRIV: privilege access mode for LPTIM2
0: non-privilege
1: privilege
Bit 22 I2C4PRIV: privilege access mode for I2C4
0: non-privilege
1: privilege
Bit 21 LPUART1PRIV: privilege access mode for LPUART1
0: non-privilege
1: privilege
Bit 20 LPTIM1PRIV: privilege access mode for LPTIM1
0: non-privilege
1: privilege
Bit 19 OPAMPPRIV: privilege access mode for OPAMP
0: non-privilege
1: privilege
Bit 18 DAC1PRIV: privilege access mode for DAC1
0: non-privilege
1: privilege
Bit 17 CRSPRIV: privilege access mode for CRS
0: non-privilege
1: privilege
Bit 16 I2C3PRIV: privilege access mode for I2C3
0: non-privilege
1: privilege
Bit 15 I2C2PRIV: privilege access mode for I2C2
0: non-privilege
1: privilege
Bit 14 I2C1PRIV: privilege access mode for I2C1
0: non-privilege
1: privilege
Bit 13 UART5PRIV: privilege access mode for UART5
0: non-privilege
1: privilege
Bit 12 UART4PRIV: privilege access mode for UART4
0: non-privilege
1: privilege
Bit 11 USART3PRIV: privilege access mode for USART3
0: non-privilege
1: privilege
Bit 10 USART2PRIV: privilege access mode for USART2
0: non-privilege
1: privilege

146/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 9 SPI3PRIV: privilege access mode for SPI3

0: non-privilege
1: privilege
Bit 8 SPI2PRIV: privilege access mode for SPI2
0: non-privilege
1: privilege
Bit 7 IWDGPRIV: privilege access mode for IWDG
0: non-privilege
1: privilege
Bit 6 WWDGPRIV: privilege access mode for WWDG
0: non-privilege
1: privilege
Bit 5 TIM7PRIV: privilege access mode for TIM7
0: non-privilege
1: privilege
Bit 4 TIM6PRIV: privilege access mode for TIM6
0: non-privilege
1: privilege
Bit 3 TIM5PRIV: privilege access mode for TIM5
0: non-privilege
1: privilege
Bit 2 TIM4PRIV: privilege access mode for TIM4
0: non-privilege
1: privilege
Bit 1 TIM3PRIV: privilege access mode for TIM3
0: non-privilege
1: privilege
Bit 0 TIM2PRIV: privilege access mode for TIM2
0: non-privilege
1: privilege

RM0438 Rev 7 147/2194

176
Global TrustZone® controller (GTZC) RM0438

5.5.5 GTZC_TZSC privilege configuration register 2

(GTZC_TZSC_PRIVCFGR2)
Address offset: 0x024
Reset value: 0x0000 0000
Write-privileged access only.
This register can be read or written only by secure privilege transaction when corresponding
TZSC_SECCFGR register signal is set to1. If a given SEC bit is not set, the equivalent PRIV
bit can be read/written by non-secure privileged transaction.
Read accesses are authorized for any type of transactions, secure or not, privilege or not.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCTOSPI1_REGPRIV

FMC_REGPRIV

SDMMC1PRIV
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACHE_REGPRIV

DFSDM1PRIV

USART1PRIV
TIM17PRIV

TIM16PRIV

TIM15PRIV
HASHPRIV

TIM8PRIV
RNGPRIV

SAI2PRIV

SAI1PRIV
CRCPRIV
ADCPRIV
PKAPRIV

AESPRIV

TSCPRIV

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 18 OCTOSPI1_REGPRIV: privilege access mode for OCTOSPI1 registers
0: non-privilege
1: privilege
Bit 17 FMC_REGPRIV: privilege access mode for FMC registers
0: non-privilege
1: privilege
Bit 16 SDMMC1PRIV: privilege access mode for SDMMC1
0: non-privilege
1: privilege
Bit 15 PKAPRIV: privilege access mode for PKA
0: non-privilege
1: privilege
Bit 14 RNGPRIV: privilege access mode for RNG
0: non-privilege
1: privilege
Bit 13 HASHPRIV: privilege access mode for HASH
0: non-privilege
1: privilege

148/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 12 AESPRIV: privilege access mode for AES

0: non-privilege
1: privilege
Bit 11 ADCPRIV: privilege access mode for ADC
0: non-privilege
1: privilege
Bit 10 ICACHE_REGPRIV: privilege access mode for ICACHE registers
0: non-privilege
1: privilege
Bit 9 TSCPRIV: privilege access mode for TSC
0: non-privilege
1: privilege
Bit 8 CRCPRIV: privilege access mode for CRC
0: non-privilege
1: privilege
Bit 7 DFSDM1PRIV: privilege access mode for DFSDM1
0: non-privilege
1: privilege
Bit 6 SAI2PRIV: privilege access mode for SAI2
0: non-privilege
1: privilege
Bit 5 SAI1PRIV: privilege access mode for SAI1
0: non-privilege
1: privilege
Bit 4 TIM17PRIV: privilege access mode for TIM17
0: non-privilege
1: privilege
Bit 3 TIM16PRIV: privilege access mode for TIM16
0: non-privilege
1: privilege
Bit 2 TIM15PRIV: privilege access mode for TIM15
0: non-privilege
1: privilege
Bit 1 USART1PRIV: privilege access mode for USART1
0: non-privilege
1: privilege
Bit 0 TIM8PRIV: privilege access mode for TIM8
0: non-privilege
1: privilege

RM0438 Rev 7 149/2194

176
Global TrustZone® controller (GTZC) RM0438

5.5.6 GTZC_TZSC external memory x non-secure watermark register 1

(GTZC_TZSC_MPCWMxANSR)
Address offset: 0x030 + 0x008 * (x-1), (x = 1 to 3)
Reset value: 0x0000 0000
The given reset value is valid when TZEN = 1. The reset value is 0x0800 0000 when
TZEN = 0.
Secure access only.
Caution: When NSWM1STRT + NSWM1LGTH is higher than the maximum size allowed for the
memory, a saturation of NSWM1LGTH is applied automatically.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. NSWM1LGTH[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. NSWM1STRT[10:0]
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 NSWM1LGTH[11:0]: length of the first non-secure area (multiple of 128 Kbytes)
Note: If programmed NSWM1LGTH + NSWM1STRT is over 2048, the value stored in the
register is truncated to (0x800 - NSWM1STRT). Any subsequent read returns this
value.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 NSWM1STRT[10:0]: offset address for the first non-secure area (multiple of 128 Kbytes)
Note: External memories which are watermark controlled start fully non-secure at reset when
TZEN = 0. When TZEN = 1, external memories start fully secure (inverted reset-value).

5.5.7 GTZC_TZSC external memory x non-secure watermark register 2

(GTZC_TZSC_MPCWMxBNSR)
Address offset: 0x034 + 0x008 * (x-1), (x = 1 to 2)
Reset value: 0x0000 0000
The given reset value is valid when TZEN = 1. The reset value is 0x0800 0000 when
TZEN = 0.
Secure access only.
Caution: When NSWM1STRT + NSWM1LGTH is higher than the maximum size allowed for the
memory, a saturation of NSWM1LGTH is applied automatically.

150/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Note: If NSWM1LGTH = 0, the region 1 is disabled and the only non-secure memory space is
defined by NSWMPxWM2.
If both NSWMPxWM1 and NSWMPxWM2 have the reset value 0x0000 0000, all the
memory space of the external memory x (FMC NOR/SRAM or OCTOSPI) is secure.
If NSWM1LGTH = 0x800 and NSWM1STRT = 0, the whole 256-Mbyte memory space is
non-secure (independent of NSWMPxWM2 value).
If NSWM1LGTH = 0x001 and NSWM1STRT = 0x7FF, only one 128-Kbyte block is defined
as non-secure (at address offset = 0x0FFE 0000, ending at 0x0FFF FFFF).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. NSWM2LGTH[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. NSWM2STRT[10:0]
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 NSWM2LGTH[11:0]: length of the second non-secure area (multiple of 128 Kbytes)
Note: If programmed NSWM2LGTH + NSWM2STRT is over 2048, the value stored in the
register is truncated to (0x800 - NSWM2STRT). Any subsequent read returns this
value.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:0 NSWM2STRT[10:0]: offset address for the second non-secure area (multiple of 128 Kbytes)
Note: External memories which are watermark controlled start fully non-secure at reset when
TZEN = 0. When TZEN = 1, external memories start fully secure (inverted reset-value).

5.5.8 GTZC_TZSC register map and reset values

Table 26. GTZC_TZSC register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCK
GTZC_TZSC_CR
0x000
Reset value 0
0x004 to
Reserved Reserved
0x00C
VREFBUFSEC

LPUART1SEC
FDCAN1SEC

USART3SEC
USART2SEC
OPAMPSEC
LPTIM3SEC
LPTIM2SEC

LPTIM1SEC
UCPD1SEC

WWDGSEC
USBFSSEC

UART5SEC
UART4SEC
COMPSEC

IWDGSEC
DAC1SEC
TIM1SEC

TIM7SEC
TIM6SEC
TIM5SEC
TIM4SEC
TIM3SEC
TIM2SEC
SPI1SEC

SPI3SEC
SPI2SEC
CRSSEC
I2C4SEC

I2C3SEC
I2C2SEC
I2C1SEC

GTZC_TZSC
0x010 _SECCFGR1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OCTOSPI1_REGSEC

ICACHE_REGSEC
FMC_REGSEC
SDMMC1SEC

DFSDM1SEC

USART1SEC
TIM17SEC
TIM16SEC
TIM15SEC
HASHSEC

TIM8SEC
RNGSEC

CRCSEC

SAI2SEC
SAI1SEC
ADCSEC

TSCSEC
PKASEC

AESSEC

GTZC_TZSC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x014 _SECCFGR2

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 to
Reserved Reserved
0x01C

RM0438 Rev 7 151/2194

176
Global TrustZone® controller (GTZC) RM0438

Table 26. GTZC_TZSC register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
VREFBUFPRIV

LPUART1PRIV
FDCAN1PRIV

USART3PRIV
USART2PRIV
OPAMPPRIV
LPTIM3PRIV
LPTIM2PRIV

LPTIM1PRIV

WWDGPRIV
UCPD1PRIV
USBFSPRIV

UART5PRIV
UART4PRIV
COMPPRIV

IWDGPRIV
DAC1PRIV
TIM1PRIV

TIM7PRIV
TIM6PRIV
TIM5PRIV
TIM4PRIV
TIM3PRIV
TIM2PRIV
SPI1PRIV

SPI3PRIV
SPI2PRIV
CRSPRIV
I2C4PRIV

I2C3PRIV
I2C2PRIV
I2C1PRIV
GTZC_TZSC
0x020 _PRIVCFGR1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OCTOSPI1_REGPRIV

ICACHE_REGPRIV
FMC_REGPRIV
SDMMC1PRIV

DFSDM1PRIV

USART1PRIV
TIM17PRIV
TIM16PRIV
TIM15PRIV
HASHPRIV
RNGPRIV

CRCPRIV

SAI2PRIV
SAI1PRIV
ADCPRIV
PKAPRIV

AESPRIV

TSCPRIV
GTZC_TZSC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x024 _PRIVCFGR2

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x028 to
Reserved Reserved
0x02C
GTZC_TZSC
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
NSWM1LGTH[11:0] NSWM1STRT[10:0]
0x030 _MPCWM1ANSR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GTZC_TZSC
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
NSWM2LGTH[11:0] NSWM2STRT[10:0]
0x034 _MPCWM1BNSR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GTZC_TZSC
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
NSWM1LGTH[11:0] NSWM1STRT[10:0]
0x038 _MPCWM2ANSR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GTZC_TZSC
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
_MPCWM2BNSR
NSWM2LGTH[11:0] Res. NSWM2STRT[10:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
GTZC_TZSC
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.

NSWM1LGTH[11:0] NSWM1STRT[10:0]
0x040 _MPCWM3ANSR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

152/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

5.6 GTZC_MPCBB registers

All registers are accessed only by words (32-bit).

5.6.1 GTZC_MPCBBx control register (GTZC_MPCBBx_CR) (x = 1 to 2)

Address offset: 0x800 + 0x400 * (x - 1)
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
INVSECSTATE
SRWILADIS

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCK
rw

Bit 31 SRWILADIS: secure read/write illegal access disable

This bit disables the detection of an illegal access when a secure read/write transaction
access a non-secure blocks of the block-based SRAM (secure fetch on non-secure block is
always considered illegal).
0: enabled, secure read/write acces not allowed on non-secure SRAM block
1: disabled, secure read/write access allowed on non-secure SRAM block
Bit 30 INVSECSTATE: default security state
This bit is used to invert the MPCBB status information (secure or non-secure) connected to
the RCC, in order to define the MPCBB clock control as secure or not.
0: default state (source clock secured if a secure area exists in the MPCBB and vice-versa)
1: invert the state, source clock remains secure even if no secure block is set in the MPCBB
Bits 29:1 Reserved, must be kept at reset value.
Bit 0 LCK: lock the control register of the MPCBB sub-block until next reset
This bit is unset by default and once set, it can not be reset until global TZSC reset.
0: control register not locked
1: control register locked

RM0438 Rev 7 153/2194

176
Global TrustZone® controller (GTZC) RM0438

5.6.2 GTZC_MPCBB1 lock register 1(GTZC_MPCBB1_LCKVTR1)

Address offset: 0x810
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LCKSB23

LCKSB22

LCKSB21

LCKSB20

LCKSB19

LCKSB18

LCKSB17

LCKSB16
Res. Res. Res. Res. Res. Res. Res. Res.

rwo rwo rwo rwo rwo rwo rwo rwo

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB15

LCKSB14

LCKSB13

LCKSB12

LCKSB10
LCKSB11

LCKSB9

LCKSB8

LCKSB7

LCKSB6

LCKSB5

LCKSB4

LCKSB3

LCKSB2

LCKSB1

LCKSB0
rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo rwo

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:0 LCKSB[23:0]: lock/unlock status of secure access mode for the super-blocks 0 to 23
0x0000 0000: security configuration unlocked for all super-blocks
....
0x0000 00FF: security configuration locked only for super-blocks 0 to 7
.....
0x0080 0001: security configuration locked for super-blocks 0 and 23

5.6.3 GTZC_MPCBB2 lock register 1

(GTZC_MPCBB2_LCKVTR1)
Address offset: 0xC10
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCKSB7

LCKSB6

LCKSB5

LCKSB4

LCKSB3

LCKSB2

LCKSB1

LCKSB0

Res. Res. Res. Res. Res. Res. Res. Res.

rwo rwo rwo rwo rwo rwo rwo rwo

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 LCKSB[7:0]: lock/unlock status of secure access mode for the super-blocks 0 to 7
0x00: security configuration unlocked for all super-blocks
....
0xFF: security configuration locked for super-blocks 0 to 7

154/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

5.6.4 GTZC_MPCBBx vector register y

(GTZC_MPCBBx_VCTRy) (x = 1 to 2)
Address offset: 0x900 + 0x04 * y, (y = 0 to 23)
Reset value: 0xFFFF FFFF
The given reset value is valid when TZEN = 1. The reset value is 0x0000 0000 when
TZEN = 0.
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B(31 + 32 * y)

B(30 + 32 * y)

B(29 + 32 * y)

B(28 + 32 * y)

B(27 + 32 * y)

B(26 + 32 * y)

B(25 + 32 * y)

B(24 + 32 * y)

B(23 + 32 * y)

B(22 + 32 * y)

B(21 + 32 * y)

B(20 + 32 * y)

B(19 + 32 * y)

B(18 + 32 * y)

B(17 + 32 * y)

B(16 + 32 * y)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
B(15 + 32 * y)

B(14 + 32 * y)

B(13 + 32 * y)

B(12 + 32 * y)

B(10 + 32 * y)
B(11 + 32 * y)

B(9 + 32 * y)

B(8 + 32 * y)

B(7 + 32 * y)

B(6 + 32 * y)

B(5 + 32 * y)

B(4 + 32 * y)

B(3 + 32 * y)

B(2 + 32 * y)

B(1 + 32 * y)

B(32 * y)
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 B[31+ 32 * y:32 * y]: define secure access mode for the super-block y
0x0000 0000: all blocks of super-block y are non-secure.
....
0x0000 00FF: only blocks 0 to 7 of super-block y are secure.
.....
0x8000 0001: only blocks 0 and 31 of super-block y are secure.
....
0xFFFF FFFF: all super-blocks are secure.

RM0438 Rev 7 155/2194

176
 7)
23)
0x810
0x800

0x80C

0xC10
0xC00
0x8FC

5.6.6
5.6.5

0xC0C

0xCFC
Offset
Offset

0x04 *y
(y =0 to
0x900 +

(y = 0 to

0xD00 +
0x814 to
0x804 to

0x004 *y

0xC14 to
0xC04 to

156/2194
_CR
_CR

_VCTRy
_VCTRy

Reserved
Reserved
Reserved
Reserved

Register
Register

_LCKVTR1
_LCKVTR1

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GTZC_MPCBB2
GTZC_MPCBB2
GTZC_MPCBB2
GTZC_MPCBB1
GTZC_MPCBB1
GTZC_MPCBB1

1
0
1
0
B(31 + 32 * y) Res. SRWILADIS 31 B(31 + 32 * y) Res. SRWILADIS 31

1
0
1
0
B(30 + 32 * y) Res. INVSECSTATE 30 B(30 + 32 * y) Res. INVSECSTATE 30

1
1
B(29 + 32 * y) Res. Res. 29 B(29 + 32 * y) Res. Res. 29

1
1
B(28 + 32 * y) Res. Res. 28 B(28 + 32 * y) Res. Res. 28

1
1
B(27 + 32 * y) Res. Res. 27 B(27 + 32 * y) Res. Res. 27

1
1
B(26 + 32 * y) Res. Res. 26 B(26 + 32 * y) Res. Res. 26

1
1
Global TrustZone® controller (GTZC)

B(25 + 32 * y) Res. Res. 25 B(25 + 32 * y) Res. Res. 25

1
1
B(24 + 32 * y) Res. Res. 24 B(24 + 32 * y) Res. Res. 24

1
1
0
B(23 + 32 * y) Res. Res. 23 B(23 + 32 * y) LCKSB23 Res. 23

1
1
B(22 + 32 * y) Res. Res. 22 B(22 + 32 * y) 0 LCKSB22 Res. 22

1
1
0
B(21 + 32 * y) Res. Res. 21 B(21 + 32 * y) LCKSB21 Res. 21

1
1
0

B(20 + 32 * y) Res. Res. 20 B(20 + 32 * y) LCKSB20 Res. 20

1
1
0

B(19 + 32 * y) Res. Res. 19 B(19 + 32 * y) LCKSB19 Res. 19

1
1
0

B(18 + 32 * y) Res. Res. 18 B(18 + 32 * y) LCKSB18 Res. 18

RM0438 Rev 7
1
1
0

B(17 + 32 * y) Res. Res. 17 B(17 + 32 * y) LCKSB17 Res. 17

1
1
0

B(16 + 32 * y) Res. Res. 16 B(16 + 32 * y) LCKSB16 Res. 16

1
1
0

B(15 + 32 * y) Res. Res. 15 B(15 + 32 * y) LCKSB15 Res. 15

Reserved
Reserved
Reserved
Reserved

1
1
0

B(14 + 32 * y) Res. Res. 14 B(14 + 32 * y) LCKSB14 Res. 14

1
1
0

B(13 + 32 * y) Res. Res. 13 B(13 + 32 * y) LCKSB13 Res. 13

GTZC_MPCBB2 register map and reset values

GTZC_MPCBB1 register map and reset values

1
1
0

B(12 + 32 * y) Res. Res. 12 B(12 + 32 * y) LCKSB12 Res. 12

1
1
0

B(11 + 32 * y) Res. Res. 11 B(11 + 32 * y) LCKSB11 Res. 11

1
1
0

B(10 + 32 * y) Res. Res. 10 B(10 + 32 * y) LCKSB10 Res. 10

1
1
0

B(9 + 32 * y) Res. Res. 9 B(9 + 32 * y) LCKSB9 Res. 9

Table 28. GTZC_MPCBB2 register map and reset values
Table 27. GTZC_MPCBB1 register map and reset values

Refer to Section 2.3 on page 87 for the register boundary addresses.

Refer to Section 2.3 on page 87 for the register boundary addresses.

1
1
0

B(8 + 32 * y) Res. Res. 8 B(8 + 32 * y) LCKSB8 Res. 8

1
1
0

0
B(7 + 32 * y) LCKSB7 Res. 7 B(7 + 32 * y) LCKSB7 Res. 7

1
1
0

0
B(6 + 32 * y) LCKSB6 Res. 6 B(6 + 32 * y) LCKSB6 Res. 6

1
1
0

0
B(5 + 32 * y) LCKSB5 Res. 5 B(5 + 32 * y) LCKSB5 Res. 5

1
1
0

0
B(4 + 32 * y) LCKSB4 Res. 4 B(4 + 32 * y) LCKSB4 Res. 4

1
1
0

0
B(3 + 32 * y) LCKSB3 Res. 3 B(3 + 32 * y) LCKSB3 Res. 3

1
1
0

0
B(2 + 32 * y) LCKSB2 Res. 2 B(2 + 32 * y) LCKSB2 Res. 2

1
1
0

0
B(1 + 32 * y) LCKSB1 Res. 1 B(1 + 32 * y) LCKSB1 Res. 1

1
1
0

0
0
0

B(32 * y) LCKSB0 LCK 0 B(32 * y) LCKSB0 LCK 0

RM0438
RM0438 Global TrustZone® controller (GTZC)

5.7 GTZC_TZIC registers

All registers are accessed only by words (32-bit).

5.7.1 GTZC_TZIC interrupt enable register 1 (GTZC_TZIC_IER1)

Address offset: 0x400
Reset value: 0x0000 0000
Secure access only.
This register is used to enable/disable generation of GTZC_IRQn interrupt towards NVIC on
illegal access event for each source.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREFBUFIE

LPUART1IE
FDCAN1IE

OPAMPIE
LPTIM3IE

LPTIM2IE

LPTIM1IE
UCPD1IE

USBFSIE
COMPIE

DAC1IE
TIM1IE
SPI1IE

I2C4IE

I2C3IE
CRSIE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3IE

USART2IE

WWDGIE
UART5IE

UART4IE

IWDGIE

TIM7IE

TIM6IE

TIM5IE

TIM4IE

TIM3IE

TIM2IE
SPI3IE

SPI2IE
I2C2IE

I2C1IE

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SPI1IE: illegal access interrupt enable for SPI1

0: disabled
1: enabled
Bit 30 TIM1IE: illegal access interrupt enable for TIM1
0: disabled
1: enabled
Bit 29 COMPIE: illegal access interrupt enable for COMP
0: disabled
1: enabled
Bit 28 VREFBUFIE: illegal access interrupt enable for VREFBUF
0: disabled
1: enabled
Bit 27 UCPD1IE: illegal access interrupt enable for UCPD1
0: disabled
1: enabled
Bit 26 USBFSIE: illegal access interrupt enable for USBFS
0: disabled
1: enabled
Bit 25 FDCAN1IE: illegal access interrupt enable for FDCAN1
0: disabled
1: enabled

RM0438 Rev 7 157/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 24 LPTIM3IE: illegal access interrupt enable for LPTIM3

0: disabled
1: enabled
Bit 23 LPTIM2IE:illegal access interrupt enable for LPTIM2
0: disabled
1: enabled
Bit 22 I2C4IE: illegal access interrupt enable for I2C4
0: disabled
1: enabled
Bit 21 LPUART1IE: illegal access interrupt enable for LPUART1
0: disabled
1: enabled
Bit 20 LPTIM1IE: illegal access interrupt enable for LPTIM1
0: disabled
1: enabled
Bit 19 OPAMPIE: illegal access interrupt enable for OPAMP
0: disabled
1: enabled
Bit 18 DAC1IE: illegal access interrupt enable for DAC1
0: disabled
1: enabled
Bit 17 CRSIE: illegal access interrupt enable for CRS
0: disabled
1: enabled
Bit 16 I2C3IE: illegal access interrupt enable for I2C3
0: disabled
1: enabled
Bit 15 I2C2IE: illegal access interrupt enable for I2C2
0: disabled
1: enabled
Bit 14 I2C1IE: illegal access interrupt enable for I2C1
0: disabled
1: enabled
Bit 13 UART5IE: illegal access interrupt enable for UART5
0: disabled
1: enabled
Bit 12 UART4IE: illegal access interrupt enable for UART4
0: disabled
1: enabled
Bit 11 USART3IE: illegal access interrupt enable for USART3
0: disabled
1: enabled
Bit 10 USART2IE: illegal access interrupt enable for USART2
0: disabled
1: enabled

158/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 9 SPI3IE: illegal access interrupt enable for SPI3

0: disabled
1: enabled
Bit 8 SPI2IE: illegal access interrupt enable for SPI2
0: disabled
1: enabled
Bit 7 IWDGIE: illegal access interrupt enable for IWDG
0: disabled
1: enabled
Bit 6 WWDGIE: illegal access interrupt enable for WWDG
0: disabled
1: enabled
Bit 5 TIM7IE: illegal access interrupt enable for TIM7
0: disabled
1: enabled
Bit 4 TIM6IE: illegal access interrupt enable for TIM6
0: disabled
1: enabled
Bit 3 TIM5IE: illegal access interrupt enable for TIM5
0: disabled
1: enabled
Bit 2 TIM4IE: illegal access interrupt enable for TIM4
0: disabled
1: enabled
Bit 1 TIM3IE: illegal access interrupt enable for TIM3
0: disabled
1: enabled
Bit 0 TIM2IE: illegal access interrupt enable for TIM2
0: disabled
1: enabled

RM0438 Rev 7 159/2194

176
Global TrustZone® controller (GTZC) RM0438

5.7.2 GTZC_TZIC interrupt enable register 2 (GTZC_TZIC_IER2)

Address offset: 0x404
Reset value: 0x0000 0000
Secure access only.
This register is used to enable interrupt of illegal access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCTOSPI1_REGIE
FLASH_REGIE

DMAMUX1IE

FMC_REGIE
OTFDEC1IE

SDMMC1IE
SYSCFGIE
FLASHIE

DMA2IE

DMA1IE

PWRIE
EXTIIE

RCCIE

RTCIE
Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACHE_REGIE

DFSDM1IE

USART1IE
TIM17IE

TIM16IE

TIM15IE
HASHIE

TIM8IE
RNGIE

CRCIE

SAI2IE

SAI1IE
ADCIE
PKAIE

AESIE

TSCIE

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 OTFDEC1IE: illegal access interrupt enable for OTFDEC
0: disabled
1: enabled
Bit 28 EXTIIE: illegal access interrupt enable for EXTI
0: disabled
1: enabled
Bit 27 FLASH_REGIE: illegal access interrupt enable for FLASH registers
0: disabled
1: enabled
Bit 26 FLASHIE: illegal access interrupt enable for FLASH
0: disabled
1: enabled
Bit 25 RCCIE: illegal access interrupt enable for RCC
0: disabled
1: enabled
Bit 24 DMAMUX1IE: illegal access interrupt enable for DMAMUX1
0: disabled
1: enabled
Bit 23 DMA2IE: illegal access interrupt enable for DMA2
0: disabled
1: enabled

160/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 22 DMA1IE: illegal access interrupt enable for DMA1

0: disabled
1: enabled
Bit 21 SYSCFGIE: illegal access interrupt enable for SYSCFG
0: disabled
1: enabled
Bit 20 PWRIE: illegal access interrupt enable for PWR
0: disabled
1: enabled
Bit 19 RTCIE: illegal access interrupt enable for RTC
0: disabled
1: enabled
Bit 18 OCTOSPI1_REGIE: illegal access interrupt enable for OCTOSPI1 registers
0: disabled
1: enabled
Bit 17 FMC_REGIE: illegal access interrupt enable for FMC registers
0: disabled
1: enabled
Bit 16 SDMMC1IE: illegal access interrupt enable for SDMMC1
0: disabled
1: enabled
Bit 15 PKAIE: illegal access interrupt enable for PKA
0: disabled
1: enabled
Bit 14 RNGIE: illegal access interrupt enable for RNG
0: disabled
1: enabled
Bit 13 HASHIE: illegal access interrupt enable for HASH
0: disabled
1: enabled
Bit 12 AESIE: illegal access interrupt enable for AES
0: disabled
1: enabled
Bit 11 ADCIE: illegal access interrupt enable for ADC
0: disabled
1: enabled
Bit 10 ICACHE_REGIE: illegal access interrupt enable for ICACHE registers
0: disabled
1: enabled
Bit 9 TSCIE: illegal access interrupt enable for TSC
0: disabled
1: enabled
Bit 8 CRCIE: illegal access interrupt enable for CRC
0: disabled
1: enabled

RM0438 Rev 7 161/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 7 DFSDM1IE: illegal access interrupt enable for DFSDM1

0: disabled
1: enabled
Bit 6 SAI2IE: illegal access interrupt enable for SAI2
0: disabled
1: enabled
Bit 5 SAI1IE: illegal access interrupt enable for SAI1
0: disabled
1: enabled
Bit 4 TIM17IE: illegal access interrupt enable for TIM17
0: disabled
1: enabled
Bit 3 TIM16IE: illegal access interrupt enable for TIM16
0: disabled
1: enabled
Bit 2 TIM15IE: illegal access interrupt enable for TIM15
0: disabled
1: enabled
Bit 1 USART1IE: illegal access interrupt enable for USART1
0: disabled
1: enabled
Bit 0 TIM8IE: illegal access interrupt enable forTIM8
0: disabled
1: enabled

5.7.3 GTZC_TZIC interrupt enable register 3 (GTZC_TZIC_IER3)

Address offset: 0x408
Reset value: 0x0000 0000
Secure access only.
This register is used to enable interrupt of illegal access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPI1_MEMIE
MPCBB2_REGIE

MPCBB1_REGIE

FMC_MEMIE
SRAM2IE

SRAM1IE

TZSCIE
TZICIE

Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

162/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 7 MPCBB2_REGIE: illegal access interrupt enable for MPCBB2 registers

0: disabled
1: enabled
Bit 6 SRAM2IE: illegal access interrupt enable for SRAM2
0: disabled
1: enabled
Bit 5 MPCBB1_REGIE: illegal access interrupt enable for MPCBB1 registers
0: disabled
1: enabled
Bit 4 SRAM1IE: illegal access interrupt enable for SRAM1
0: disabled
1: enabled
Bit 3 OCTOSPI1_MEMIE: illegal access interrupt enable for OCTOSPI1 memory interface
0: disabled
1: enabled
Bit 2 FMC_MEMIE: illegal access interrupt enable for FMC NAND and FMC NOR memories
0: disabled
1: enabled
Bit 1 TZICIE: illegal access interrupt enable for TZIC registers
0: disabled
1: enabled
Bit 0 TZSCIE: illegal access interrupt enable TZSC
0: disabled
1: enabled

5.7.4 GTZC_TZIC status register 1 (GTZC_TZIC_SR1)

Address offset: 0x410
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREFBUFF

LPUART1F
FDCAN1F

OPAMPF
LPTIM3F

LPTIM2F

LPTIM1F
UCPD1F

USBFSF
COMPF

DAC1F
TIM1F
SPI1F

I2C4F

CRSF

I2C3F

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3F

USART2F

WWDGF
UART5F

UART4F

IWDGF

TIM7F

TIM6F

TIM5F

TIM4F

TIM3F

TIM2F
SPI3F

SPI2F
I2C2F

I2C1F

r r r r r r r r r r r r r r r r

Bit 31 SPI1F: illegal access flag for SPI1

0: no illegal access event
1: an illegal access event pending

RM0438 Rev 7 163/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 30 TIM1F: illegal access flag for TIM1

0: no illegal access event
1: an illegal access event pending
Bit 29 COMPF: illegal access flag for COMP
0: no illegal access event
1: an illegal access event pending
Bit 28 VREFBUFF: illegal access flag for VREFBUF
0: no illegal access event
1: an illegal access event pending
Bit 27 UCPD1F: illegal access flag for UCPD1
0: no illegal access event
1: an illegal access event pending
Bit 26 USBFSF: illegal access flag for USB FS
0: no illegal access event
1: an illegal access event pending
Bit 25 FDCAN1F: illegal access flag for FDCAN1
0: no illegal access event
1: an illegal access event pending
Bit 24 LPTIM3F: illegal access flag for LPTIM3
0: no illegal access event
1: an illegal access event pending
Bit 23 LPTIM2F: illegal access flag for LPTIM2
0: no illegal access event
1: an illegal access event pending
Bit 22 I2C4F: illegal access flag for I2C4
0: no illegal access event
1: an illegal access event pending
Bit 21 LPUART1F: illegal access flag for LPUART1
0: no illegal access event
1: an illegal access event pending
Bit 20 LPTIM1F: illegal access flag for LPTIM1
0: no illegal access event
1: an illegal access event pending
Bit 19 OPAMPF: illegal access flag for OPAMP
0: no illegal access event
1: an illegal access event pending
Bit 18 DAC1F: illegal access flag for DAC1
0: no illegal access event
1: an illegal access event pending
Bit 17 CRSF: illegal access flag for CRS
0: no illegal access event
1: an illegal access event pending
Bit 16 I2C3F: illegal access flag for I2C3
0: no illegal access event
1: an illegal access event pending

164/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 15 I2C2F: illegal access flag for I2C2

0: no illegal access event
1: an illegal access event pending
Bit 14 I2C1F: illegal access flag for I2C1
0: no illegal access event
1: an illegal access event pending
Bit 13 UART5F: illegal access flag for UART5
0: no illegal access event
1: an illegal access event pending
Bit 12 UART4F: illegal access flag for UART4
0: no illegal access event
1: an illegal access event pending
Bit 11 USART3F: illegal access flag for USART3
0: no illegal access event
1: an illegal access event pending
Bit 10 USART2F: illegal access flag for USART2
0: no illegal access event
1: an illegal access event pending
Bit 9 SPI3F: illegal access flag for SPI3
0: no illegal access event
1: an illegal access event pending
Bit 8 SPI2F: illegal access flag for SPI2
0: no illegal access event
1: an illegal access event pending
Bit 7 IWDGF: illegal access flag for IWDG
0: no illegal access event
1: an illegal access event pending
Bit 6 WWDGF: illegal access flag for WWDG
0: no illegal access event
1: an illegal access event pending
Bit 5 TIM7F: illegal access flag for TIM7
0: no illegal access event
1: an illegal access event pending
Bit 4 TIM6F: illegal access flag for TIM6
0: no illegal access event
1: an illegal access event pending
Bit 3 TIM5F: illegal access flag for TIM5
0: no illegal access event
1: an illegal access event pending
Bit 2 TIM4F: illegal access flag for TIM4
0: no illegal access event
1: an illegal access event pending
Bit 1 TIM3F: illegal access flag for TIM3
0: no illegal access event
1: an illegal access event pending

RM0438 Rev 7 165/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 0 TIM2F: illegal access flag for TIM2

0: no illegal access event
1: an illegal access event pending

5.7.5 GTZC_TZIC status register 2 (GTZC_TZIC_SR2)

Address offset: 0x414
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCTOSPI1_REGF
FLASH_REGF

DMAMUX1F

FMC_REGF
OTFDEC1F

SDMMC1F
SYSCFGF
FLASHF

DMA2F

DMA1F

PWRF
EXTIF

RCCF

RTCF
Res. Res.

r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACHE_REGF

DFSDM1F

USART1F
TIM17F

TIM16F

TIM15F
HASHF

TIM8F
RNGF

CRCF

SAI2F

SAI1F
ADCF
PKAF

AESF

TSCF

r r r r r r r r r r r r r r r r

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 OTFDEC1F: illegal access flag for OTFDEC1
0: no illegal access event
1: an illegal access event pending
Bit 28 EXTIF: illegal access flag for EXTI
0: no illegal access event
1: an illegal access event pending
Bit 27 FLASH_REGF: illegal access flag for FLASH registers
0: no illegal access event
1: an illegal access event pending
Bit 26 FLASHF: illegal access flag for FLASH
0: no illegal access event
1: an illegal access event pending
Bit 25 RCCF: illegal access flag for RCC
0: no illegal access event
1: an illegal access event pending
Bit 24 DMAMUX1F: illegal access flag for DMAMUX1
0: no illegal access event
1: an illegal access event pending
Bit 23 DMA2F: illegal access flag for DMA2
0: no illegal access event
1: an illegal access event pending

166/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 22 DMA1F: illegal access flag for DMA1

0: no illegal access event
1: an illegal access event pending
Bit 21 SYSCFGF: illegal access flag for SYSCFG
0: no illegal access event
1: an illegal access event pending
Bit 20 PWRF: illegal access flag for PWR
0: no illegal access event
1: an illegal access event pending
Bit 19 RTCF: illegal access flag for RTC
0: no illegal access event
1: an illegal access event pending
Bit 18 OCTOSPI1_REGF: illegal access flag for OCTOSPI1 registers
0: no illegal access event
1: an illegal access event pending
Bit 17 FMC_REGF: illegal access flag for FMC registers
0: no illegal access event
1: an illegal access event pending
Bit 16 SDMMC1F: illegal access flag for SDMMC1
0: no illegal access event
1: an illegal access event pending
Bit 15 PKAF: illegal access flag for PKA
0: no illegal access event
1: an illegal access event pending
Bit 14 RNGF: illegal access flag for RNG
0: no illegal access event
1: an illegal access event pending
Bit 13 HASHF: illegal access flag for HASH
0: no illegal access event
1: an illegal access event pending
Bit 12 AESF: illegal access flag for AES
0: no illegal access event
1: an illegal access event pending
Bit 11 ADCF: illegal access flag for ADC
0: no illegal access event
1: an illegal access event pending
Bit 10 ICACHE_REGF: illegal access flag for ICACHE registers
0: no illegal access event
1: an illegal access event pending
Bit 9 TSCF: illegal access flag for TSC
0: no illegal access event
1: an illegal access event pending
Bit 8 CRCF: illegal access flag for CRC
0: no illegal access event
1: an illegal access event pending

RM0438 Rev 7 167/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 7 DFSDM1F: illegal access flag for DFSDM1

0: no illegal access event
1: an illegal access event pending
Bit 6 SAI2F: illegal access flag for SAI2
0: no illegal access event
1: an illegal access event pending
Bit 5 SAI1F: illegal access flag for SAI1
0: no illegal access event
1: an illegal access event pending
Bit 4 TIM17F: illegal access flag for TIM17
0: no illegal access event
1: an illegal access event pending
Bit 3 TIM16F: illegal access flag for TIM16
0: no illegal access event
1: an illegal access event pending
Bit 2 TIM15F: illegal access flag for TIM15
0: no illegal access event
1: an illegal access event pending
Bit 1 USART1F: illegal access flag for USART1
0: no illegal access event
1: an illegal access event pending
Bit 0 TIM8F: illegal access flag for TIM8
0: no illegal access event
1: an illegal access event pending

5.7.6 GTZC_TZIC status register 3 (GTZC_TZIC_SR3)

Address offset: 0x418
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPI1_MEMF
MPCBB2_REGF

MPCBB1_REGF

FMC_MEMF
SRAM2F

SRAM1F

TZSCF
TZICF

Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r r r r

Bits 31:8 Reserved, must be kept at reset value.

168/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 7 MPCBB2_REGF: illegal access flag for MPCBB2 registers

0: no illegal access event
1: an illegal access event pending
Bit 6 SRAM2F: illegal access flag for SRAM2
0: no illegal access event
1: an illegal access event pending
Bit 5 MPCBB1_REGF: illegal access flag for MPCBB1 registers
0: no illegal access event
1: an illegal access event pending
Bit 4 SRAM1F: illegal access flag for SRAM1
0: no illegal access event
1: an illegal access event pending
Bit 3 OCTOSPI1_MEMF: illegal access flag for OCTOSPI memory interface
0: no illegal access event
1: an illegal access event pending
Bit 2 FMC_MEMF: illegal access flag for FMC NAND and FMC NOR memory interface
0: no illegal access event
1: an illegal access event pending
Bit 1 TZICF: illegal access flag for TZIC
0: no illegal access event
1: an illegal access event pending
Bit 0 TZSCF: illegal access flag for TZSC
0: no illegal access event
1: an illegal access event pending

5.7.7 GTZC_TZIC flag clear register 1 (GTZC_TZIC_FCR1)

Address offset: 0x420
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VREFBUFFC

LPUART1FC
FDCAN1FC

OPAMPFC
LPTIM3FC

LPTIM2FC

LPTIM1FC
UCPD1FC

USBFSFC
COMPFC

DAC1FC
TIM1FC
SPI1FC

I2C4FC

CRSFC

I2C3FC

w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART3FC

USART2FC

WWDGFC
UART5FC

UART4FC

IWDGFC

TIM7FC

TIM6FC

TIM5FC

TIM4FC

TIM3FC

TIM2FC
SPI3FC

SPI2FC
I2C2FC

I2C1FC

w w w w w w w w w w w w w w w w

Bit 31 SPI1FC: clear the illegal access flag for SPI1

0: no action
1: status flag cleared

RM0438 Rev 7 169/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 30 TIM1FC: clear the illegal access flag for TIM1

0: no action
1: status flag cleared
Bit 29 COMPFC: clear the illegal access flag for COMP
0: no action
1: status flag cleared
Bit 28 VREFBUFFC: clear the illegal access flag for VREFBUF
0: no action
1: status flag cleared
Bit 27 UCPD1FC: clear the illegal access flag for UCPD1
0: no action
1: status flag cleared
Bit 26 USBFSFC: clear the illegal access flag for USB FS
0: no action
1: status flag cleared
Bit 25 FDCAN1FC: clear the illegal access flag for FDCAN1
0: no action
1: status flag cleared
Bit 24 LPTIM3FC: clear the illegal access flag for LPTIM3
0: no action
1: status flag cleared
Bit 23 LPTIM2FC: clear the illegal access flag for LPTIM2
0: no action
1: status flag cleared
Bit 22 I2C4FC: clear the illegal access flag for I2C4
0: no action
1: status flag cleared
Bit 21 LPUART1FC: clear the illegal access flag for LPUART1
0: no action
1: status flag cleared
Bit 20 LPTIM1FC: clear the illegal access flag for LPTIM1
0: no action
1: status flag cleared
Bit 19 OPAMPFC: clear the illegal access flag for OPAMP
0: no action
1: status flag cleared
Bit 18 DAC1FC: clear the illegal access flag for DAC1
0: no action
1: status flag cleared
Bit 17 CRSFC: clear the illegal access flag for CRS
0: no action
1: status flag cleared
Bit 16 I2C3FC: clear the illegal access flag for I2C3
0: no action
1: status flag cleared

170/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 15 I2C2FC: clear the illegal access flag for I2C2

0: no action
1: status flag cleared
Bit 14 I2C1FC: clear the illegal access flag for I2C1
0: no action
1: status flag cleared
Bit 13 UART5FC: clear the illegal access flag for UART5
0: no action
1: status flag cleared
Bit 12 UART4FC: clear the illegal access flag for UART4
0: no action
1: status flag cleared
Bit 11 USART3FC: clear the illegal access flag for USART3
0: no action
1: status flag cleared
Bit 10 USART2FC: clear the illegal access flag for USART2
0: no action
1: status flag cleared
Bit 9 SPI3FC: clear the illegal access flag for SPI3
0: no action
1: status flag cleared
Bit 8 SPI2FC: clear the illegal access flag for SPI2
0: no action
1: status flag cleared
Bit 7 IWDGFC: clear the illegal access flag for IWDG
0: no action
1: status flag cleared
Bit 6 WWDGFC: clear the illegal access flag for WWDG
0: no action
1: status flag cleared
Bit 5 TIM7FC: clear the illegal access flag for TIM7
0: no action
1: status flag cleared
Bit 4 TIM6FC: clear the illegal access flag for TIM6
0: no action
1: status flag cleared
Bit 3 TIM5FC: clear the illegal access flag for TIM5
0: no action
1: status flag cleared1: enable
Bit 2 TIM4FC: clear the illegal access flag for TIM4
0: no action
1: status flag cleared
Bit 1 TIM3FC: clear the illegal access flag for TIM3
0: no action
1: status flag cleared

RM0438 Rev 7 171/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 0 TIM2FC: clear the illegal access flag for TIM2

0: no action
1: status flag cleared

5.7.8 GTZC_TZIC flag clear register 2 (GTZC_TZIC_FCR2)

Address offset: 0x424
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OCTOSPI1_REGFC
FLASH_REGFC

DMAMUX1FC

FMC_REGFC
OTFDEC1FC

SDMMC1FC
SYSCFGFC
FLASHFC

DMA2FC

DMA1FC

PWRFC
EXTIFC

RCCFC

RTCFC
Res. Res.

w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ICACHE_REGFC

DFSDM1FC

USART1FC
TIM17FC

TIM16FC

TIM15FC
HASHFC

TIM8FC
RNGFC

SAI2FC

SAI1FC
CRCFC
ADCFC
PKAFC

AESFC

TSCFC

w w w w w w w w w w w w w w w w

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 OTFDEC1FC: clear the illegal access flag for OTFDEC1
0: no action
1: status flag cleared
Bit 28 EXTIFC: clear the illegal access flag for EXTI
0: no action
1: status flag cleared
Bit 27 FLASH_REGFC: clear the illegal access flag for FLASH registers
0: no action
1: status flag cleared
Bit 26 FLASHFC: clear the illegal access flag for FLASH
0: no action
1: status flag cleared
Bit 25 RCCFC: clear the illegal access flag for RCC
0: no action
1: status flag cleared
Bit 24 DMAMUX1FC: clear the illegal access flag for DMAMUX1
0: no action
1: status flag cleared

172/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bit 23 DMA2FC: clear the illegal access flag for DMA2

0: no action
1: status flag cleared
Bit 22 DMA1FC: clear the illegal access flag for DMA1
0: no action
1: status flag cleared
Bit 21 SYSCFGFC: clear the illegal access flag for SYSCFG
0: no action
1: status flag cleared
Bit 20 PWRFC: clear the illegal access flag for PWR
0: no action
1: status flag cleared
Bit 19 RTCFC: clear the illegal access flag for RTC
0: no action
1: status flag cleared
Bit 18 OCTOSPI1_REGFC: clear the illegal access flag for OCTOPSPI1 registers
0: no action
1: status flag cleared
Bit 17 FMC_REGFC: clear the illegal access flag for FMC registers
0: no action
1: status flag cleared
Bit 16 SDMMC1FC: clear the illegal access flag for SDMMC1
0: no action
1: status flag cleared
Bit 15 PKAFC: clear the illegal access flag for PKA
0: no action
1: status flag cleared
Bit 14 RNGFC: clear the illegal access flag for RNG
0: no action
1: status flag cleared
Bit 13 HASHFC: clear the illegal access flag for HASH
0: no action
1: status flag cleared
Bit 12 AESFC: clear the illegal access flag for AES
0: no action
1: status flag cleared
Bit 11 ADCFC: clear the illegal access flag for ADC
0: no action
1: status flag cleared
Bit 10 ICACHE_REGFC: clear the illegal access flag for ICACHE registers
0: no action
1: status flag cleared
Bit 9 TSCFC: clear the illegal access flag for TSC
0: no action
1: status flag cleared

RM0438 Rev 7 173/2194

176
Global TrustZone® controller (GTZC) RM0438

Bit 8 CRCFC: clear the illegal access flag for CRC

0: no action
1: status flag cleared
Bit 7 DFSDM1FC: clear the illegal access flag for DFSDM1
0: no action
1: status flag cleared
Bit 6 SAI2FC: clear the illegal access flag for SAI2
0: no action
1: status flag cleared
Bit 5 SAI1FC: clear the illegal access flag for SAI1
0: no action
1: status flag cleared
Bit 4 TIM17FC: clear the illegal access flag for TIM17
0: no action
1: status flag cleared
Bit 3 TIM16FC: clear the illegal access flag for TIM16
0: no action
1: status flag cleared
Bit 2 TIM15FC: clear the illegal access flag for TIM15
0: no action
1: status flag cleared
Bit 1 USART1FC: clear the illegal access flag for USART1
0: no action
1: status flag cleared
Bit 0 TIM8FC: clear the illegal access flag for TIM8
0: no action
1: status flag cleared

5.7.9 GTZC_TZIC flag clear register 3 (GTZC_TZIC_FCR3)

Address offset: 0x428
Reset value: 0x0000 0000
Secure access only.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OCTOSPI1_MEMFC
MPCBB2_REGFC

MPCBB1_REGFC

FMC_MEMFC
SRAM2FC

SRAM1FC

TZSCFC
TZICFC

Res. Res. Res. Res. Res. Res. Res. Res.

w w w w w w w w

174/2194 RM0438 Rev 7

RM0438 Global TrustZone® controller (GTZC)

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 MPCBB2_REGFC: clear the illegal access flag for MPCBB2 registers
0: no action
1: status flag cleared
Bit 6 SRAM2FC: clear the illegal access flag for SRAM2
0: no action
1: status flag cleared
Bit 5 MPCBB1_REGFC: clear the illegal access flag for MPCBB1 registers
0: no action
1: status flag cleared
Bit 4 SRAM1FC: clear the illegal access flag for SRAM1
0: no action
1: status flag cleared
Bit 3 OCTOSPI1_MEMFC: clear the illegal access flag for OCTOSPI memory interface
0: no action
1: status flag cleared
Bit 2 FMC_MEMFC: clear the illegal access flag for FMC NAND and FMC NOR memory interface
0: no action
1: status flag cleared
Bit 1 TZICFC: clear the illegal access flag for TZIC
0: no action
1: status flag cleared
Bit 0 TZSCFC: clear the illegal access flag for TZSC
0: no action
1: status flag cleared

5.7.10 GTZC_TZIC register map and reset values

Table 29. GTZC_TZIC register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
VREFBUFIE

LPUART1IE
FDCAN1IE

USART3IE
USART2IE
OPAMPIE
LPTIM3IE
LPTIM2IE

LPTIM1IE
UCPD1IE

WWDGIE
USBFSIE

UART5IE
UART4IE
COMPIE

IWDGIE
DAC1IE
TIM1IE

TIM7IE
TIM6IE
TIM5IE
TIM4IE
TIM3IE
TIM2IE
SPI1IE

SPI3IE
SPI2IE
I2C4IE

I2C3IE
I2C2IE
I2C1IE
CRSIE

GTZC_TZIC_IER1
0x400

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OCTOSPI1_REGIE

ICACHE_REGIE
FLASH_REGIE

DMAMUX1IE

FMC_REGIE
OTFDEC1IE

SDMMC1IE
SYSCFGIE

DFSDM1IE

USART1IE
FLASHIE

TIM17IE
TIM16IE
TIM15IE
DMA2IE
DMA1IE

HASHIE
PWRIE

TIM8IE
EXTIIE

RNGIE
RCCIE

CRCIE

SAI2IE
SAI1IE
ADCIE
RTCIE

PKAIE

AESIE

TSCIE
Res.
Res.

GTZC_TZIC_IER2
0x404

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 175/2194

176
 0x428
0x424
0x420
0x418
0x414
0x410
0x408

0x41C
0x40C
Offset

176/2194
Reserved
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GTZC_TZIC_SR3
GTZC_TZIC_SR2
GTZC_TZIC_SR1
GTZC_TZIC_IER3

GTZC_TZIC_FCR3
GTZC_TZIC_FCR2
GTZC_TZIC_FCR1

0
0
Res. Res. SPI1FC Res. Res. SPI1F Res. 31

0
0
Res. Res. TIM1FC Res. Res. TIM1F Res. 30

0
0
0
0
Res. OTFDEC1FC COMPFC Res. OTFDEC1F COMPF Res. 29

0
0
0
0
Res. EXTIFC VREFBUFFC Res. EXTIF VREFBUFF Res. 28

0
0
0
0
Res. FLASH_REGFC UCPD1FC Res. FLASH_REGF UCPD1F Res 27

0
0
0
0
Res. FLASHFC USBFSFC Res. FLASHF USBFSF Res. 26

0
0
0
0
Global TrustZone® controller (GTZC)

Res. RCCFC FDCAN1FC Res. RCCF FDCAN1F Res. 25

0
0
0
0
Res. DMAMUX1FC LPTIM3FC Res. DMAMUX1F LPTIM3F Res. 24

0
0
0
Res. DMA2FC LPTIM2FC Res. DMA2F 0 LPTIM2F Res. 23

0
0
0
0
Res. DMA1FC I2C4FC Res. DMA1F I2C4F Res. 22

0
0
0
0

Res. SYSCFGFC LPUART1FC Res. SYSCFGF LPUART1F Res. 21

0
0
0
0

Res. PWRFC LPTIM1FC Res. PWRF LPTIM1F Res. 20

0
0
0
0

Res. RTCFC OPAMPFC Res. RTCF OPAMPF Res. 19

0
0
0
0

Res. OCTOSPI1_REGFC DAC1FC Res. OCTOSPI1_REGF DAC1F Res. 18

RM0438 Rev 7
0
0
0
0

Res. FMC_REGFC CRSFC Res. FMC_REGF CRSF Res. 17

0
0
0
0

Res. SDMMC1FC I2C3FC Res. SDMMC1F I2C3F Res. 16

0
0
0
0

Res. PKAFC I2C2FC Res. PKAF I2C2F Res. 15

Reserved
Reserved

0
0
0
0

Res. RNGFC I2C1FC Res. RNGF I2C1F Res. 14

0
0
0
0

Res. HASHFC UART5FC Res. HASHF UART5F Res. 13

0
0
0
0

Res. AESFC UART4FC Res. AESF UART4F Res. 12

0
0
0
0

Res. ADCFC USART3FC Res. ADCF USART3F Res. 11

0
0
0
0

Res. ICACHE_REGFC USART2FC Res. ICACHE_REGF USART2F Res. 10

0
0
0
0

Res. TSCFC SPI3FC Res. TSCF SPI3F Res. 9

Refer to Section 2.3 on page 87 for the register boundary addresses.

0
0
0
0

Res. CRCFC SPI2FC Res. CRCF SPI2F Res. 8

0
0
0
0

0
0
0

MPCBB2_REGFC DFSDM1FC IWDGFC MPCBB2_REGF DFSDM1F IWDGF MPCBB2_REGIE 7

Table 29. GTZC_TZIC register map and reset values (continued)

0
0
0
0

0
0
0

SRAM2FC SAI2FC WWDGFC SRAM2F SAI2F WWDGF SRAM2IE 6

0
0
0
0

0
0
0

MPCBB1_REGFC SAI1FC TIM7FC MPCBB1_REGF SAI1F TIM7F MPCBB1_REGIE 5

0
0
0
0

0
0
0

SRAM1FC TIM17FC TIM6FC SRAM1F TIM17F TIM6F SRAM1IE 4

0
0
0
0

0
0
0

OCTOSPI1_MEMFC TIM16FC TIM5FC OCTOSPI1_MEMF TIM16F TIM5F OCTOSPI1_MEMIE 3

0
0
0
0

0
0
0

FMC_MEMFC TIM15FC TIM4FC FMC_MEMF TIM15F TIMIF FMC_MEMIE 2

0
0
0
0

0
0
0

TZICFC USART1FC TIM3FC TZICF USART1F TIM3F TZICIE 1

0
0
0
0

0
0
0

TZSCFC TIM8FC TIM2FC TZSCF TIM8F TIM2F TZSCIE 0

RM0438
RM0438 Embedded Flash memory (FLASH)

6 Embedded Flash memory (FLASH)

6.1 Introduction
The Flash memory interface manages accesses to the Flash memory, maximizing
throughput to the CPU, instruction cache and DMAs. It implements the Flash memory erase
and program operations as well as the read and write protection mechanisms. It also
implements the security and privilege access control features.

6.2 FLASH main features

• Up to 512 Kbytes of Flash memory with dual bank architecture supporting read-while-
write capability (RWW).
• Flash memory read operations with two data width modes supported:
– Single bank mode DBANK=0: read access of 128 bits
– Dual bank mode DBANK=1: read access of 64 bits
• Page erase, bank erase and mass erase (both banks).
• Bank swapping: the address mapping of the user Flash memory of each bank can be
swapped.
• Readout protection activated by option (RDP) byte.
• Four write protection areas (two per bank when DBANK=1 and four for full memory
when DBANK=0).
• TrustZone support:
– Two secure areas (1 per bank when DBANK=1, 2 for all memory when DBANK=0)
– Two secure HDP (hide protection) areas part of the secure areas (one per bank
when DBANK=1, two for all memory when DBANK=0).
• Error code correction ECC: 8 bits per 64-bit double-word:
– DBANK=1: 8 + 64 = 72 bits, two bits detection, one bit correction
– DBANK=0: (8+64) + (8+64) = 144 bits, two bits detection, one bit correction per
64-bit double-word.
• Option-byte loader.
• Low-power mode.
• Privileged and unprivileged support.

RM0438 Rev 7 177/2194

243
Embedded Flash memory (FLASH) RM0438

6.3 Flash memory functional description

6.3.1 Flash memory organization

The Flash memory has the following main features:
• Capacity up to 512 Kbytes, in single-bank mode (read width of 128 bits) or in dual-bank
mode (read width of 64-bits).
• Dual-bank mode when DBANK bit is set:
– 256 Kbytes organized in two banks for main memory.
– Page size of 2 Kbytes.
– 72 bits wide data read (64 bits plus 8 ECC bits).
– Bank and mass erase.
• Single-bank mode when DBANK is reset:
– 512 Kbytes organized in one single bank for main memory.
– Page size of 4 Kbytes.
– 144 bits wide data read (64 bits plus 2x 8 ECC bits).
– Mass erase.
The Flash memory is organized as follows:
• A main memory block organized depending on the dual bank configuration bit:
– When dual bank is enabled (DBANK bit set), the Flash is divided in two banks of
256 Kbytes, and each bank is organized as follows:
The main memory block containing 128 pages of 2 Kbytes
– When dual bank is disabled (DBANK bit reset), the main memory block is
organized as one single bank of 512 Kbytes as follows:
The main memory block containing 128 pages of 4 Kbytes.
• An Information block containing:
– 32 Kbytes for system memory. The area is reserved for use by STMicroelectronics
and contains the bootloader that is used to reprogram the Flash memory through
one of the following interfaces: USART1, USART2, USART3, USB (DFU), I2C1,
I2C2, I2C3, SPI1, SPI2, SPI3. It is programmed by STMicroelectronics when the
device is manufactured, and protected against spurious write/erase operations.
For further details, please refer to the application note STM32 microcontroller
system memory boot mode (AN2606) available from www.st.com.
– 10 Kbytes for root secure services (RSS).
– 512 bytes OTP (one-time programmable) bytes for user data. The OTP data
cannot be erased and can be written only once. If only one bit is at 0, the entire
double word cannot be written anymore, even with the value 0x0000 0000 0000
0000.
– 4 Kbytes of option bytes for user configuration. Unlike user Flash memory and
system memory, it is not mapped to any memory address and can be accessed
only through the Flash register interface.
The memory organization is based on a main area and an information block as shown in
Table 30: Flash module - 512 KB dual bank organization (64 bits read width) and Table 31:
Flash module - 512 KB single bank organization (128 bits read width).

178/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Table 30. Flash module - 512 KB dual bank organization (64 bits read width)
Flash area Flash memory address Size Name

0x0800 0000 - 0x0800 07FF 2 Kbytes Page 0

0x0800 0800 - 0x0800 0FFF 2 Kbytes Page 1

Bank 1 - - -
- - -
- - -
0x0803 F800 - 0x0803 FFFF 2 Kbytes Page 127
Main memory
0x08040000 - 0x0804 07FF 2 Kbytes Page 0
0x0804 0800 - 0x0804 0FFF 2 Kbytes Page 1
- - -
Bank 2
- - -
- - -
0x0807 F800 - 0x0807 FFFF 2 Kbytes Page 127

Non-secure 0x0BF9 0000 - 0x0BF9 7FFF 32 Kbytes System memory

Information block(1) 0x0BFA 0000 - 0x0BFA 01FF 512 bytes OTP area

Secure 0x0FF8 0000 - 0x0FF8 1FFF 8 Kbytes RSS

Information block 0x0FF8 2000 - 0x0FF8 27FF 2 Kbytes RSS library
1. When the TrustZone is enabled (TZEN = 1), the non-secure information block is accessible only with a
non-secure access. This means that in order to be able to access any address in this region, it should be
configured as non-secure through the SAU. This region is also accessible when booting from RSS.

Note: The secure information block is only available when TrustZone is active.

Table 31. Flash module - 512 KB single bank organization (128 bits read width)
Flash area Flash memory address Size Name

0x0800 0000 - 0x0800 0FFF 4 Kbytes Page 0

0x0800 1000 - 0x0800 1FFF 4 Kbytes Page 1
0x0800 2000 - 0x0800 2FFF 4 Kbytes Page 2
Main memory - - -
- - -
- - -
0x0807 F000 - 0x0807 FFFF 4 Kbytes Page 127

Non-Secure 0x0BF9 0000 - 0x0BF9 7FFF 32 Kbytes System memory

Information block(1) 0x0BFA 0000 - 0x0BFA 01FF 512 bytes OTP area

Secure 0x0FF9 0000 - 0x0FF9 1FFF 8 Kbytes RSS

Information block 0x0FF9 2000 - 0x0FF9 27FF 2 Kbytes RSS library
1. When the TrustZone is enabled (TZEN = 1), the non-secure information block is accessible only with a
non-secure access. This means that in order to be able to access any address in this region, it should be
configured as non-secure through the SAU. This region is also accessible when booting from RSS.

RM0438 Rev 7 179/2194

243
Embedded Flash memory (FLASH) RM0438

Note: The secure information block is only available when TrustZone is active.

6.3.2 Error code correction (ECC)

Dual bank mode (DBANK=1, 64-bits data width)
Data in Flash memory are 72-bits words: 8 bits are added per double word (64 bits). The
ECC mechanism supports:
• One error detection and correction per 64 double words
• Two errors detection
When one error is detected and corrected, the flag ECCC (ECC correction) is set in Flash
ECC register (FLASH_ECCR). If ECCCIE is set, an interrupt is generated.
When two errors are detected, a flag ECCD (ECC detection) is set in FLASH_ECCR
register. In this case, a NMI is generated.
When an ECC error is detected, the address of the failing double word and its associated
bank are saved in ADDR_ECC[17:0] and BK_ECC in the FLASH_ECCR register.
ADDR_ECC[18] and ADDR_ECC[2:0] are always cleared.
When ECCC or ECCD is set, ADDR_ECC and BK_ECC are not updated if a new ECC error
occurs. FLASH_ECCR is updated only when ECC flags are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.

When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.

Single bank mode (DBANK=0, 128-bits data width)

Data in Flash memory are 144-bits words: 8 bits are added per each double word. The ECC
mechanism supports:
• One error detection and correction
• Two errors detection per 64 double words
The user must first check the SYSF_ECC bit, and if it is set, the user must refer to the
DBANK=1 programming model (because system Flash is always on two banks). If the bit is
not set, the user must refer to the following programing model:
Each double word (bits 63:0 and bits 127:64) has ECC.
When one error is detected in 64 LSB bits (bits 63:0) and corrected, a flag ECCC (ECC
correction) is set in the FLASH_ECCR register.
When one error is detected in 64 MSB bits (bits 127:64) and corrected, a flag ECCC2
(ECC2 correction) is set in the FLASH_ECCR register.
If the ECCCIE is set, an interrupt is generated. The user has to read ECCC and ECCC2 to
see which part of the 128-bits data has been corrected (either 63:0, 127:64 or both).
When two errors are detected in 64 LSB bits, a flag ECCD (ECC detection) is set in the
FLASH_ECCR register.
When two errors are detected in 64 MSB bits (bits 127:64), a flag ECCD2 (ECC2 detection)
is set in the FLASH_ECCR register.

180/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

In this case, a NMI is generated. The user has to read ECCD and ECCD2 to see which part
of the 128-bits data has error detection (either 63:0, 127:64 or both).
When an ECC error is detected, the address of the failing the two times double word is
saved into ADDR_ECC[18:0] in FLASH_ECCR. ADDR_ECC[18:0] contains an address of a
two times double word.
The ADDR_ECC[3:0] are always cleared. BK_ECC is not used in this mode.
When ECCC/ECCC2 or ECCD/ECCD2 is/are set, if a new ECC error occurs, the
ADDR_ECC is not updated. The FLASH_ECCR is updated only if the ECC flags
(ECCC/ECCC2/ECCD/ECCD2) are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.

6.3.3 Read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the FLASH registers according to the frequency of the CPU clock
(HCLK) and the internal voltage range of the device VCORE. Refer to Section 8.2.5: Dynamic
voltage scaling management. Table 32 shows the correspondence between wait states and
CPU clock frequency.

Table 32. Number of wait states according to CPU clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
(Latency)
VCORE Range 0 VCORE Range 1 VCORE Range 2

0 WS (1 CPU cycles) ≤20 ≤20 ≤8

1 WS (2 CPU cycles) ≤40 ≤40 ≤16
2 WS (3 CPU cycles) ≤60 ≤60 ≤26
3 WS (4 CPU cycles) ≤80 ≤80 -
4 WS (5 CPU cycles) ≤100 - -
5 WS (6 CPU cycles) ≤110 - -

After reset, the CPU clock frequency is 4 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
When changing the CPU frequency, the following software sequences must be applied in
order to tune the number of wait states needed to access the Flash memory:

RM0438 Rev 7 181/2194

243
Embedded Flash memory (FLASH) RM0438

Increasing the CPU frequency:

1. Program the new number of wait states to the LATENCY bits in Section 6.9: FLASH
registers.
2. Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register.
3. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
4. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
5. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.

Decreasing the CPU frequency:

1. Modify the CPU clock source by writing the SW bits in the RCC_CFGR register.
2. If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR.
3. Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
4. Program the new number of wait states to the LATENCY bits in Section 6.9: FLASH
registers.
5. Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register.

6.3.4 Low-voltage read

When the external SMPS option is used, the Flash must be programmed in low voltage read
mode.
• Voltage scaling range must be in range 2.
• Unlock the LVEN bit by the following procedure:
– Write LVEKEY1 = 0xF4F5F6F7 in the FLASH_LVEKEYR.
– Write LVEKEY2 = 0x0A1B2C3D in the FLASH_LVEKEYR.
• Set the LVEN bit in the FLASH_ACR register.
• Check the LVEN bit is set.
• Read back the LVEN bit the FLASH_ACR register

6.3.5 Flash program and erase operations

The embedded Flash memory can be programmed using in-circuit programming or in-
application programming.
The in-circuit programming (ICP) method is used to update the entire contents of the
Flash memory, using the JTAG, SWD protocol or the bootloader to load the user application
into the microcontroller. ICP offers quick and efficient design iterations and eliminates
unnecessary package handling or socketing of devices.
In contrast to the ICP method, in-application programming (IAP) can use any
communication interface supported by the microcontroller (I/Os, USB, CAN, UART, I2C, SPI,
etc.) to download programming data into memory. IAP allows the user to re-program the

182/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Flash memory while the application is running. Nevertheless, part of the application must
have been previously programmed in the Flash memory using ICP.
The contents of the Flash memory are not guaranteed if a device reset occurs during a
Flash memory program or erase operation.
In dual bank mode, an on-going Flash memory operation does not block the CPU as long as
the CPU does not access the same Flash memory bank. Code or data fetches are possible
on one bank while a write/erase operation is performed to the other bank (refer to
Section 6.3.9: Read-while-write (RWW) available only in dual-bank mode (DBANK = 1)).
The Flash erase and programming is only possible in the voltage scaling range 0 and 1.
Note: At power-on reset or a system reset, the main regulator voltage range 2 is selected by
default. Consequently, the voltage scaling range must be programmed to range 0 or range 1
via VOS[1:0] bits in the PWR_CR1 register prior to any Flash erase and programming
operation.
On the contrary, during a program/erase operation to the Flash memory, any attempt to read
the same Flash memory bank stalls the bus. The read operation proceeds correctly once
the program/erase operation has been completed.
The MCU supports Arm® TrustZone® which defines secure and non-secure areas in Flash.
All program and erase operations can be performed in secure mode through the secure
registers or in non-secure mode through the non-secure registers. For more information,
refer to Section 6.5: Flash TrustZone security and privilege protections.

Unlocking the secure/non-secure Flash control register

After reset, write is not allowed in the secure/non-secure Flash control register
FLASH_NSCR/FLASH_SECCR to protect the Flash memory against possible unwanted
operations due, for example, to electric disturbances. The following sequence is used to
unlock this register:
1. Write KEY1 = 0x45670123 in the Flash secure key register (FLASH_SECKEYR) or
Flash non-secure key register (FLASH_NSKEYR).
2. Write KEY2 = 0xCDEF89AB in the Flash secure key register (FLASH_SECKEYR) or
Flash non-secure key register (FLASH_NSKEYR).
Any wrong sequence locks up the FLASH_NSCR/FLASH_SECCR register until the next
system reset. In the case of a wrong key sequence, a bus error is detected and a Hard Fault
interrupt is generated.
The FLASH_NSCR and FLASH_SECCR registers can be locked again by software by
setting the NSLOCK and SECLOCK bit in the FLASH_NSCR and FLASH_SECCR register
respectively.
Note: The FLASH_NSCR and FLASH_SECCR registers cannot be written when the NSBSY or
SECBSY bits are set. Any attempt to write to them with the NSBSY or SECBSY bit causes
the AHB bus to stall until the NSBSY and SECBSY bits are cleared.

RM0438 Rev 7 183/2194

243
Embedded Flash memory (FLASH) RM0438

Flash secure and non-secure busy flags

The SECBSY and NSBSY flags are both set when a secure or non-secure Flash operation
is started:
• Erase operation: setting the NSSTRT in the Flash non-secure control register
(FLASH_NSCR) or setting the SECSTRT in the Flash secure control register
(FLASH_SECCR).
• Write operation: setting the NSPG or SECPG bit in the FLASH_NSCR or
FLASH_SECCR register respectively and writing a double-word in the Flash memory.
• Option bytes programming: setting the OPTSTRT in the FLASH_NSCR.

6.3.6 Flash main memory erase sequences

The Flash memory erase operation can be performed at page level, bank level or on the
whole Flash memory (mass erase). Mass erase does not affect the information block
(system Flash, OTP and option bytes). The erase operation is either secure or non-secure.

Non-secure page erase

To erase a non-secure page, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the NSBSY bit in the
Flash status register (FLASH_NSSR).
2. Check and clear all non-secure error programming flags due to a previous
programming. If not, NSPGSERR is set.
3. In dual-bank mode (DBANK option bit is set), set the NSPER bit and select the non-
secure page to erase (NSPNB) with the associated bank (NSBKER) in the
FLASH_NSCR. In single-bank mode (DBANK option bit is reset), set the NSPER bit
and select the page to erase (NSPNB). The NSBKER bit in the FLASH_NSCR must be
kept cleared.
4. Set the NSSTRT bit in the FLASH_NSCR register.
5. Wait for the NSBSY bit to be cleared in the FLASH_NSSR register.

Secure page erase

To erase a secure page, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the SECBSY bit in the
Flash status register (FLASH_SECSR).
2. Check and clear all secure error programming flags due to a previous programming. If
not, SECPGSERR is set.
3. In dual-bank mode (DBANK option bit is set), set the SECPER bit and select the secure
page to erase (SECPNB) with the associated bank (SECBKER) in the
FLASH_SECCR. In single-bank mode (DBANK option bit is reset), set the SECPER bit
and select the page to erase (SECPNB). The SECBKER bit in the FLASH_SECCR
must be kept cleared.
4. Set the SECSTRT bit in the FLASH_SECR register.
5. Wait for the SECBSY bit to be cleared in the FLASH_SECSR register.
Note: If the page erase is part of write-protected area (by WRP), NSWRPERR or SECWRPERR is
set and the page erase request is aborted.

184/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Non-secure bank 1, bank 2 mass erase (available only in dual-bank mode

when DBANK=1)
To perform a non-secure bank mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the NSBSY bit in the
FLASH_NSSR register.
2. Check and clear all non-secure error programming flags due to a previous
programming. If not, NSPGSERR is set.
3. Set the NSMER1 bit or NSMER2 (depending on the bank) in the FLASH_NSCR
register. Both banks can be selected in the same operation, in that case it corresponds
to a mass erase.
4. Set the NSSTRT bit in the FLACH_NSCR register.
5. Wait for the NSBSY bit to be cleared in the FLASH_NSSR register.
6. The NSMER1 or NSMER2 bits can be cleared if no more non-secure bank erase is
requested.

Secure bank 1, bank 2 mass erase (available only in dual-bank mode when
DBANK=1)
To perform a secure bank mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the SECBSY bit in the
FLASH_SECSR register.
2. Check and clear all secure error programming flags due to a previous programming. If
not, SECPGSERR is set.
3. Set the SECMER1 bit or SECMER2 (depending on the bank) in the FLASH_SECCR
register. Both banks can be selected in the same operation, in that case it corresponds
to a mass erase.
4. Set the SECSTRT bit in the FLACH_SECCR register.
5. Wait for the SECBSY bit to be cleared in the FLASH_SECSR register
6. The SECMER1 or SECMER2 bit can be cleared if no more secure bank erase is
requested.

Non-secure mass erase

To perform a non-secure mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the NSBSY bit in the
FLASH_NSSR register.
2. Check and clear all non-secure error programming flags due to a previous
programming. If not, NSPGSERR is set.
3. Set the NSMER1 bit and NSMER2 bits in the FLASH_NSCR register.
4. Set the NSSTRT bit in the FLACH_NSCR register.
5. Wait for the NSBSY bit to be cleared in the FLASH_NSSR.
6. The NSMER1 and NSMER2 bit can be cleared if no more non-secure mass erase is
requested.

RM0438 Rev 7 185/2194

243
Embedded Flash memory (FLASH) RM0438

Note: When DBANK=0, if only the NSMERA or the NSMERB bit is set, NSPGSERR is set and no
erase operation is performed.
If the bank to erase or if one of the banks to erase contains a write-protected area (by
WRP), NSWRPERR is set and the mass erase request is aborted (for both banks if both are
selected).

Secure mass erase

To perform a secure mass erase, follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the SECBSY bit in the
FLASH_SECSR register.
2. Check and clear all error programming flags due to a previous programming. If not,
SECPGSERR is set.
3. Set the SECMER1 bit and SECMER2 bits in FLASH_SECCR register.
4. Set the SECTRT bit in the FLACH_SECR register.
5. Wait for the SECBSY bit to be cleared in the FLASH_SECSR.
6. The SECMER1 and SECMER2 bit can be cleared if no more secure mass erase is
requested.
Note: The internal oscillator HSI16 (16 MHz) is enabled automatically when SECSTRT bit is set,
and disabled automatically when SECSTRT bit is cleared, except if the HSI16 is previously
enabled with HSION in RCC_CR register.
When DBANK=0, if only the SECMERA or the SECMERB bit is set, SECPGSERR is set
and no erase operation is performed.
If the bank to erase or if one of the banks to erase contains a write-protected area
(by WRP), SECWRPERR is set and the mass erase request is aborted (for both banks if
both are selected).

186/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.3.7 Flash main memory programming sequences

The Flash memory is programmed 72 bits at a time (64 bits + 8 bits ECC).
Programming in a previously programmed address is not allowed except if the data to write
is full zero, and any attempt sets the NSPROGERR or SECPROGERR flag in the Flash.
It is only possible to program double word (2 x 32-bit data).
• Any attempt to write byte or half-word sets NSSIZERR or SECSIZERR flag in the
FLASH_NSSR or FLASH_SECSR register.
• Any attempt to write a double word which is not aligned with a double word address
sets NSPGAERR or SECPGAERR flag in the FLASH_NSSR or FLASH_SECSR
register.

Non-secure programming
The Flash memory programming sequence is as follows:
1. Check that no Flash main memory operation is ongoing by checking the NSBSY bit in
the FLASH_NSSR.
2. Check and clear all non-secure error programming flags due to a previous
programming. If not, NSPGSERR is set.
3. Set the NSPG bit in the FLASH_NSCR register.
4. Perform the data write operation at the desired memory non-secure address, or in the
OTP area. Only double word can be programmed.
– Write a first word in an address aligned with double word
– Write the second word in the same double-word.
5. Wait until the NSBSY bit is cleared in the FLASH_NSSR register.
6. Check that NSEOP flag is set in the FLASH_NSSR register (meaning that the
programming operation has succeed), and clear it by software.
7. Clear the NSPG bit in the FLASH_NSSR register if there no more programming
request anymore.

Secure programming
The Flash memory programming sequence is as follows:
1. Check that no Flash main memory operation is ongoing by checking the SECBSY bit in
the FLASH_SECSR.
2. Check and clear all secure error programming flags due to a previous programming. If
not, SECPGSERR is set.
3. Set the SECPG bit in the FLASH_SECCR register.
4. Perform the data write operation at the desired memory secure address. Only double
word can be programmed.
– Write a first word in an address aligned with double word
– Write the second word in the same double-word.
5. Wait until the SECBSY bit is cleared in the FLASH_SECSR register.
6. Check that SECEOP flag is set in the FLASH_SECSR register (meaning that the
programming operation has succeed), and clear it by software.
7. Clear the SECPG bit in the FLASH_SECSR register if there is no more programming
request anymore.

RM0438 Rev 7 187/2194

243
Embedded Flash memory (FLASH) RM0438

Note: When the Flash interface has received a good sequence (a double word), programming is
automatically launched and SECBSY/NSBSY bit is set. The internal oscillator HSI16
(16 MHz) is enabled automatically when SECPG/NSPG bit is set, and disabled
automatically when SECPG/NSPG bit is cleared, except if the HSI16 is previously enabled
with HSION in RCC_CR register.
If the user needs to program only one word, double word must be completed with the erase
value 0xFFFF FFFF to launch automatically the programming.
ECC is calculated from the double word to program.

6.3.8 Flash errors flags

Flash programming errors
Several kind of errors can be detected during a secure and non-secure operations. In case
of error, the Flash operation (programming or erasing) is aborted. The secure errors flags
are only set during a secure operation and non-secure flags are only set during a non-
secure access.
• SECPROGERR, NSPROGERR: secure /non-secure programming error.
It is set when the double word to program is pointing to an address:
– Not previously erased
– Already fully programmed to “0”
– Already partially programmed (contains “0” and “1”) and the new value to program
is not full zero.
– For OTP programming, the SECPROGERR, NSPROGERR flag is set when the
address is already partially programmed (contains “0” and “1”).
• SECSIZERR, NSSIZERR: secure/non-secure size programming error.
Only a double word can be programmed and only 32-bit data can be written.
SECSIZERR or NSSIZERR flag is set if a byte or a half-word is written.
• SECPGAERR, NSPGAERR: secure/non-secure alignment programming error.
It is set when the first word to be programmed is not aligned with a double word
address, or the second word doesn’t belong to the same double word address.
• SECPGSERR: Secure programming sequence error.
SECPGSERR is set if one of the following conditions occurs during a secure erase or
program operation:
– A data is written when SECPG is cleared.
– A program operation is requested during erase: SECPG is set while SECMER1 or
SECMER2 or SECPER is set.
– In the erase sequence: SECPG is set while SECSTRT is set
– If SECSTRT is set with SECMER1 and SECMER2 and SECPER are cleared.
– If secure page and mass erase are requested at the same time: SECSTRT and
SECPER are set and SECMER1 or SECMER2 is set.
– In single-bank mode (DBANK=0), if SECSTRT is set and only SECMER1 or
SECMER2 is set.
– If SECPROGERR, SECSIZERR, SECPGAERR, SECWRPERR or SECPGSERR
is already set due to a previous programming error.

188/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

• NSPGSERR: non-secure programming sequence error.

NSPGSERR is set if one of the following conditions occurs during a non-secure erase
or program operation:
– A data is written when NSPG is cleared.
– A program operation is during erase: NSPG is set while NSMER1 or NSMER2 or
NSPER is set.
– In the erase sequence: NSPG is set while NSSTRT is set.
– If NSSTRT is set with NSMER1 and NSMER2 and NSPER are cleared.
– If non-secure page and mass erase are requested at the same time: NSSTRT and
NSPER are set and NSMER1 or NSMER2 is set.
– In single-bank mode (DBANK=0), if NSSTRT is set and only NSMER1 or
NSMER2 is set.
– If NSPROGERR, NSSIZERR, NSPGAERR, NSWRPERR, NSPGSERR or
OPTWERR is already set due to a previous programming error.
– If NSSTRT is set by a secure access.
– If NSSTRT and OPTSTRT are set at the same time.
• SECWRPERR: secure write protection error.
SEWRPERR is set if one of the following conditions occurs:
– A secure program or erase on a non-secure page or a write protected area
(WRP).
– A secure bank erase or mass erase when one page or more is protected by WRP
or HDP area with access disabled.
– Refer to Table 47 to Table 49 for all the conditions of SECWRPERR flag setting.
• NSWRPERR: non-secure write protection error.
NSWRPERR is set if one of the following conditions occurs:
– A non-secure program or erase in a non-secure write protected area (WRP) or in a
secure area (Secure watermark-based, HDP, Secure block-based).
– A non-secure bank erase or mass erase when one page or more is protected by
WRP or a secure area (SECWM, HDP, SECBB).
– Refer to Table 47 to Table 49 for all the conditions of NSWRPERR flag setting.
• OPTWERR: option bytes write error.
OPTWERR is set if when user option bytes are modified with an invalid configuration. It
set when attempt:
– To program an invalid secure watermark-based area. Refer to Table 35: Secure
watermark-based area
– To set or unset TZEN option bit without being in correct RDP level (refer to Rules
for modifying specific option bytes).
– To modify DBANK option bit while the Flash is secure (watermak or block-based)
– To set SWAP_BANK option bit while DBANK is cleared.
– To modify SWAP_BANK option bit while BOOT_LOCK and TZEN are set.
– To modify SECBOOTADD0 option bit while BOOT_LOCK is set.
– To modify DB256 option bit while BOOT_LOCK and TZEN are set.
– Attempt to modify the option bytes, except the SWAP_BANK option bit ,when the
readout protection (RDP) is set to 2.

RM0438 Rev 7 189/2194

243
Embedded Flash memory (FLASH) RM0438

If an error occurs during a a secure or non-secure program or erase operation, one of the
following programming error flags is set:
– Non-secure programming error flags: NSPROGERR, NSSIZERR, NSPGAERR,
NSPGSERR, OPTWRERR or NSWRPERR is set in the FLASH_NSSR register.
– If the non-secure error interrupt enable bit NSERRIE is set in the Flash non-secure
control register (FLASH_NSCR), an interrupt is generated and the operation error
flag NSOPERR is set in the FLASH_NSSR register.
• Secure programming error flags: SECPROGERR, SECSIZERR, SECPGAERR,
SECPGSERR or SECWRPERR is set in the FLASH_SECSR register.
– If the secure error interrupt enable bit SECERRIE is set in the Flash secure control
register (FLASH_SECCR), an interrupt is generated and the operation error flag
SECOPERR is set in the FLASH_SECSR register.
Note: If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.

6.3.9 Read-while-write (RWW) available only in dual-bank mode

(DBANK = 1)
The dual-bank mode is available only when the DBANK option bit is reset, allowing read-
while-write operations. This feature permits to perform a read operation from one bank while
erase or program operation is performed to the other bank.
Note: Write-while-write operations are not allowed. As an example, It is not possible to perform an
erase operation on one bank while programming the other one.

Read from bank 1 while page erasing in bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a page erase
operation on bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the NSBSY or SECBSY
bit in the FLASH_NSSR or FLASH_SECSR register (NSBSY, SECBSY are set when
erase/program operation is on going in bank 1 or bank 2).
2. Set NSPER or SECPER bit, NSPSB or SECPSB to select the non-secure or secure
page and NSBKER or SECBER to select the bank following the security state non-
secure or secure.
3. Set the NSSTRT or SECSTRT bit in the FLASH_NSCR/FLASH_SECCR register.
4. Wait for the NSBSY or SECBSY bit to be cleared (or use the NSEOP or SECEOP
interrupt).

190/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Read from bank 1 while mass erasing bank 2 (or vice versa)
While executing a program code from bank 1, it is possible to perform a mass erase
operation on bank 2 (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the NSBSY/SECBSY
bit in the FLASH_NSSR/FLASH_SECSR register (NSBSY, SECBSY are active when
erase/program operation is on going in bank 1 or bank 2).
2. Non-secure bank erase, set the NSMER1 or NSMER2 in the FLASH_NSCR register.
For secure bank erase, set the SECMER1 or SECMER2 in the FLASH_SECCR
register.
3. Set the NSSTRT/SECSTRT bit in the FLASH_NSCR/FLASH_SECCR register.
4. Wait for the NSBSY or SECBSY bit to be cleared (or use the NSEOP or SECEOP
interrupt).

Read from bank 1 while programming bank 2 (or vice versa)

While executing a program code from bank 1, it is possible to perform a program operation
on the bank 2. (and vice versa). Follow the procedure below:
1. Check that no Flash memory operation is ongoing by checking the NSBSY/SECBSY
bit in the FLASH_NSSR/FLASH_SECSR register (NSBSY, SECBSY are active when
erase/program operation is on going in bank 1 or bank 2).
2. Set the NSPG or SECPG bit in the FLASH_NSCR/FLASHSECCR register.
3. Perform the data write operations at the desired address memory inside the main
memory block or OTP area.
4. Wait for the NSBSY or SECBSY bit to be cleared (or use the NSEOP or SECEOP
interrupt).
Note: Due to Cortex M33 unified C-Bus, user software must ensure to not stall C-Bus with multiple
consecutive writes. It is recommended to wait the NSBSY/SECBSY flag to be cleared
before programming the next double word.

RM0438 Rev 7 191/2194

243
Embedded Flash memory (FLASH) RM0438

6.4 Flash memory option bytes

6.4.1 Option bytes description

The option bytes are configured by the end user depending on the application requirements.
As a configuration example, the watchdog may be selected in hardware or software mode
(refer to Section 6.4.2: Option bytes programming).The user option bytes are accessible
through the Flash interface registers interface.
Table 33 describes the organization of all user option bytes available in the Flash interface
registers.
Table 33. User option byte organization mapping

Register map
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
IWDG_STDBY

BOR_LEV[2:0]
nRST_STDBY
PA15_PUPEN

SWAP_BANK

nRST_SHDW
SRAM2_RST

IWDG_STOP

nRST_STOP
nSWBOOT0

WWDG_SW
SRAM2_PE

IDWG_SW
nBOOT0

DB256K
DBANK

Section 6.9.12: Flash option

TZEN

RDP
Res.
Res.

Res.

Res.

Res.

register (FLASH_OPTR)

Section 6.9.13: Flash non-

Res. secure boot address 0 regis-
Res.
Res.
Res.
Res.
Res.
Res.
NSBOOTADD0[24:0]
ter (FLASH_NSBOOT-
ADD0R)
Section 6.9.14: Flash non-
secure boot address 1 regis-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
NSBOOTADD1[24:0]
ter (FLASH_NSBOOT-
BOOT_LOCK
ADD1R)

Section 6.9.15: Flash secure

Res.
Res.
Res.
Res.
Res.
Res.

SECBOOTADD0[24:0] boot address 0 register

(FLASH_SECBOOTADD0R)

Section 6.9.16: Flash bank 1

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

SECWM1_PEND[6:0] SECWM1_PSTRT[6:0] secure watermak1 register

(FLASH_SECWM1R1)
Section 6.9.17: Flash secure
HDP1EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

HDP1_PEND[6:0] watermak1 register 2

(FLASH_SECWM1R2)
Section 6.9.18: Flash WPR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WRP1A_PEND[6:0] WRP1A_PSTRT[6:0] area A address register

(FLASH_WRP1AR)
Section 6.9.19: Flash WPR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WRP1B_PEND[6:0] WRP1B_PSTRT[6:0] area B address register

(FLASH_WRP1BR)
Section 6.9.20: Flash secure
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

SECWM2_PEND[6:0] SECWM2_PSTRT[6:0] watermak2 register

(FLASH_SECWM2R1)
Section 6.9.21: Flash secure
HDP2EN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

HDP2_PEND[6:0] watermak2 register 2

(FLASH_SECWM2R2)

192/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Table 33. User option byte organization mapping (continued)

Register map
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Section 6.9.22: Flash WPR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRP2A_PEND[6:0] WRP2A_PSTRT[6:0] area A address register
(FLASH_WRP2AR)
Section 6.9.23: Flash WPR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WRP2B_PEND[6:0] WRP2B_PSTRT[6:0] area B address register
(FLASH_WRP2BR)

6.4.2 Option bytes programming

After reset, the options related bits in the FLASH_OPTR are write-protected. To run any
operation on the option bytes page, the option lock bit OPTLOCK in the Flash non-secure
control register (FLASH_NSCR) must be cleared. The following sequence is used to unlock
this register:
1. Unlock the FLASH_NSCR with the NSLOCK clearing sequence (refer to Unlocking the
secure/non-secure Flash control register).
2. Write OPTKEY1 = 0x08192A3B in the FLASH_OPTKEYR register.
3. Write OPTKEY2 = 0x4C5D6E7F in the FLASH_OPTKEYR register.
The user options can be protected against unwanted erase/program operations by setting
the OPTLOCK bit by software.
Note: If NSLOCK is set by software, OPTLOCK is automatically set too.

Option bytes modification sequence

To modify the user options value, follow the procedure below:
1. Check that no Flash memory operation is on going by checking the NSBSY bit in the
FLASH_NSSR register.
2. Clear OPTLOCK option lock bit with the clearing sequence described above.
3. Write the desired options value in the options registers.
4. Set the options start bit OPTSTRT in the Flash non-secure control register
(FLASH_NSCR).
5. Wait for the NSBSY bit to be cleared.
6. Set the OBL_LAUNCH option bit to start option bytes loading.
Note: If the OPTWERR or NSPGSERR error bit is set, the old option byte values are kept.

Option byte loading

After the NSBSY bit is cleared, all new options are updated into the Flash but they are not
applied to the system. They affect the system when they are loaded. Option bytes loading
(OBL) is performed in two cases:
– When OBL_LAUNCH bit is set in the Flash non-secure control register
(FLASH_NSCR).
– After a power reset (BOR reset or exit from Standby/Shutdown modes).
On system reset rising, internal option registers are copied into option registers. These
registers are also used to modify the option bytes. If these registers are not modified by

RM0438 Rev 7 193/2194

243
Embedded Flash memory (FLASH) RM0438

user, they reflects the options states of the system. See Section 6.4.2: Option bytes
programming for more details.
Activating dual-bank mode (switching from DBANK=0 to DBANK=1)
When switching from one Flash mode to another (for example from single to dual bank) it is
recommended to execute the code from the SRAM or use the bootloader. To avoid reading
corrupted data from the Flash when the memory organization is changed, any access
(either CPU or DMAs) to Flash memory should be avoided before reprogramming.
• If any secure Flash protection is enabled (watemark or block-based), all must be
disabled.
• Disable the instruction cache if it is enabled
• Set the DBANK option bit and clear all the WRP write protection (follow user option
modification and option bytes loader procedure).
– Once OBL is done with DBANK=0, perform a mass erase.
– Start a new programing of code in 64 bits mode with DBANK=1 memory mapping.
– Set the new secure protection if needed.
The new software is ready to be run using the bank configuration.

De-activating dual-bank mode (switching from DBANK=1 to DBANK=0)

When switching from one Flash mode to another (for example from single to dual bank) it is
recommended to execute the code from the SRAM or use the bootloader. To avoid reading
corrupted data from the Flash when the memory organization is changed, any access
(either CPU or DMAs) to Flash memory should be avoided before reprogramming.
• If any secure Flash protection is enabled (watemark or block-based), all must be
disabled.
• Disable the instruction cache if it is enabled
• Clear the DBANK option bit and all WRP write protection (follow user option
modification and option bytes loader procedure).
– Once OBL is done with DBANK=0, perform a mass erase.
– Start a new programing of code in 128 bits mode with DBANK=0 memory
mapping.
– Set the new secure protection if needed.
The new software is ready to be run using the bank configuration.

194/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Rules for modifying specific option bytes

Some of the option byte field must respect specific rules before being updated with new
values. These option bytes, as well as the associated constraints, are described below:
• TZEN option bit
– TZEN can only be set on RDP level 0.
– Deactivation of TZEN must be done at the same time as RDP regression to level 0
(from level 1 to level 0 or from level 0.5 to level 0).
• BOOT_LOCK option bit
– BOOT_LOCK can be set without any constraint.
– It is not possible to deactivate the BOOT_LOCK option bit.
• SWAP_BANK option bit
– It is not possible to set the SWAP_BANK in single-bank mode (DBANK=0).
– It can not be modified when BOOT_LOCK and TZEN option bit are set.
• SECBOOTADD0 option bytes
– It can not be modified when BOOT_LOCK option bit is set.
• DB256K option bit
– It is not possible to modify the DB256K when BOOT_LOCK and TZEN option bits
are set.
– In single-bank mode (DBANK=0).
• DBANK option bit
– It can only be modified when all secure protections are disabled (secure
watermark or block-based area).
• SECWMx_PSTRT[6:0], SECWMxPEND[6:0], HDPx_PEND[6:0], HDPxEN option bytes
– It can only be modified when HDPxACCDIS bit is cleared. When it is set, options
bytes listed in the table below are locked and can not be modified until next
system reset.If the user options modification try to modify one of the those option
bytes while HDPxACCDIS bit is set, the option bytes modification is discarded
without error flag.
If the above user options modification tries to set or modify one of the listed option bytes
without following their associated rules, the option bytes modification is discarded and the
OPTWERR error flag is set.

Rules of RDP level regression

When TrustZone is active, in case of RDP level 0.5 or level 1, the RDP regression to level 0
or level 0.5 can only be done by the debug interface or by the system bootloader.

6.5 Flash TrustZone security and privilege protections

6.5.1 TrustZone security protection

The global TrustZone system security is activated by setting the TZEN option bit in the
FLASH_OPTR register.

RM0438 Rev 7 195/2194

243
Embedded Flash memory (FLASH) RM0438

When the TrustZone is active (TZEN=1), additional security features are available:
• Secure watermark-based user options bytes defining secure, HDP areas.
• Secure or non-secure block-based areas can be configured on-the-fly after reset. This
is a volatile secure area.
• An additional RDP protection: RDP level 0.5.
• Erase or program operation can be performed in secure or non-secure mode with
associated configuration bit.
When the TrustZone is disabled (TZEN=0), the above features are deactivated and all
secure registers are RAZ/WI.
All other option bytes not listed above, can be modified without any constraints.

Activating TrustZone security

On first TrustZone activation (TZEN is modified from 0 to 1), the secure watermark-based
user options bytes are set to default secure state: All Flash is secure, no HDP area. Refer to
Table 34: Default secure option bytes after TZEN activation.

Table 34. Default secure option bytes after TZEN activation

Secure watermark option bytes values after
DBANK option bit Security attribute
OBL when TZEN is activated (from 0 to 1)

SECWM1_PSTRT = 0
SECWM1_PEND = 0x7F
0 All Flash memory is secure
SECWM2_PSTRT = 0x7F
SECWM2_PEND = 0

SECWMx_PSTRT = 0 Bank 1 is fully secure

1
SECWMx_PEND = 0x7F Bank 2 is fully secure
HDPxEN = 0
0/1 No secure HDP area
HDPx_PEND = 0

Deactivating TrustZone security

Deactivation of TZEN (from 1 to 0) is only possible when the RDP is changing to level 0
(from level 1 to level 0 or from level 0.5 to level 0).
When the TrustZone is deactivated (TZEN is modified from 1 to 0) after option bytes
loading, the following security features are deactivated:
• Watermark-based secure area
• Block-based secure area
• RDP level 0.5
• Secure interrupt
• All secure registers are RAZ/WI.

196/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.5.2 Secure watermark-based area protection

When TrustZone security is active (TZEN=1), a part of the Flash memory can be protected
against non-secure read and write access. Up to two different non-volatile secure areas can
be defined by option bytes and can be read or written by a secure access only:
• In single-bank mode, two areas can be selected with a page granularity.
• In dual-bank mode, one area per bank can be selected with a page granularity.
The secure areas are defined by a start page offset and end page offset using the
SECWMx_PSTRT and SECWMx_PEND (x=1,2 for area 1 and area 2) option bytes.These
offsets are defined in the Secure watermark registers address registers Flash bank 1 secure
watermak1 register (FLASH_SECWM1R1), Flash secure watermak2 register
(FLASH_SECWM2R1).
The SECWMx_PSTRT and SECWMx_PEND option bytes can only be modified by secure
firmware when the HDPxACCDIS bit is reset.
If the HDPxACCDIS bit is set, the SECWMx_PSTRT and SECWMx_PEND cannot be
modified until next system reset.

Table 35. Secure watermark-based area

DBANK option Secure watermark option bytes values Secure watermark protection
bit (x = 1,2) area

0/1 SECWMx_PSTRT > SECWMx_PEND No secure area

One page defined by
0/1 SECWMx_PSTRT = SECWMx_PEND SECWMx_PSTRT is secure water-
mark-based protected
The area between SECWMx_P-
0/1 SECWMx_PSTRT < SECWMx_PEND STRT and SECWMx_PEND is
secure watermark-based protected

Caution: Switching a Flash memory area from secure to non-secure does not erase its content. The
user secure software must perform the needed operation to erase the secure area before
switching an area to non-secure attribute whenever is needed. It is also recommended to
flush the instruction cache.

6.5.3 Secure hide protection (HDP)

The secure HDP area is part of the Flash watermark-based secure area. Access to the hide
protection area can be denied by setting the HDPxACCDIS bit in FLASH_SECHDPCR
register.
When the HDPxACCDIS bit is set, data read, write and instruction fetch on this hide
protection area are denied. For example, software code in the secure Flash hide protected
area can be executed only once and deny any further access to this area until next system
reset. The HDPxACCDIS bit can be only cleared by a system reset.
Up to two non-volatile secure hide protection (HDP) areas can be defined depending of the
DBANK mode:
• In single-bank mode, two HDP areas can be selected with a page granularity.
• In dual-bank mode, one HDP area per bank can be selected with a page granularity

RM0438 Rev 7 197/2194

243
Embedded Flash memory (FLASH) RM0438

The secure HDP area is enabled by the HDPxEN (x=1,2 for area 1 and area 2). When the
HDPxEN bit is reset, there is no HDP area. The HDPxEN bit can be set or reset by the
secure firmware if the HDPx_ACCDIS bit is reset.
The secure HDP area size is defined by the end page offset using the HDPx_PEND option
bytes while the start page offset is already defined by SECWMx_PSTRT option bytes.These
offsets are defined in the Secure watermark registers address registers Flash bank 1 secure
watermak1 register (FLASH_SECWM1R1), Flash secure watermak1 register 2
(FLASH_SECWM1R2), Flash secure watermak2 register (FLASH_SECWM2R1), Flash
secure watermak2 register 2 (FLASH_SECWM2R2).
The HDPxEN and HDPx_PEND option bytes can only be modified by secure firmware when
the HDPxACCDIS bit is reset.
If the HDPxACCDIS bit is set, the HDPxEN and HDPx_PEND cannot be modified until next
system reset.
If an invalid secure HDP area is defined as described in Table 36: Secure, HDP protections
summary, the OPTWERR flag error is set and option bytes modification is discarded.

Table 36. Secure, HDP protections summary

Secure, HDP,
watermark option bytes values (x = 1,2)
Protections area
HDPxEN bit Option bytes

SECWMx_PSTRT >
x No secure area.
SECWMx_PEND
SECWMx_PSTRT <= No secure HDP area.
0
SECWMx_PEND Secure area bewteen SECWMx_STRT and SECWMx_PEND
The area between SECWMx_STRT and HDPx_PEND is
SECWMx_STRT <= HDPx-
secure HDP protected.
_PEND <=
– If SECWMx_STRT=HDPx_PEND, one page defined in
1 SECWMx_PEND
HDPx_PEND is secure HDP protected.
Invalid secure area.
Others
HDP area is defined outside the secure area.

6.5.4 Secure block-based area (SECBB) protection

Any page, non-secure through secure Flash memory watermark option bytes, can be
programmed on-the-fly as secure using the block-based configuration registers.
With SECBB, it is not possible to unsecure a secure page through secure watermark option
bytes.
In dual-bank mode (DBANK=1):
• FLASH_SECBB1Rx registers are used to configure the security attribute for pages in
bank1
• FLASH_SECBB2Rx registers are used to configure the security attribute for pages in
bank2

198/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

In single-bank mode (DBANK=0):

• the FLASH_SECBB1Rx registers are used to configure the security attribute for pages
in all Flash memory.
It is possible to temporary secure a non-secure watermark page by setting corresponding
SECBB bit to 1. Setting SECBB bit to 1 on an already secure watermark page has no effect.
To modify a page block-based security attribution, it is recommended to:
• Check that no Flash operation is ongoing on the related page.
• Add ISB instruction after modifying the page security attribute SECBB1/2[i].

6.5.5 Forcing boot from a secure memory address

When TrustZone is enabled by setting the TZEN option bit, the boot space must be in
secure area. The SECBOOTADD0[24:0] option bytes are used to select the boot secure
memory address. To increase the security and establish a chain of trust, a unique boot entry
option can be selected regardless the other boot options. This is done by setting the
BOOT_LOCK option bit in the FLASH_SECBOOTADD0R register.
This bit can be set only by a secure access.
Caution: Once set, the BOOT_LOCK option bit cannot be cleared.

6.5.6 Flash security attribute state

The Flash is secure when at least one secure area is defined either by watermark-based
option bytes or block-based security registers.
It is possible to override the Flash security state using the SECINV bit in the
FLASH_SECCR register.

Table 37. Flash security state

Secure Area SECINV bit Flash security state

0 Non secure
None
1 Secure
0 Secure
Yes
1 Non secure

• A non-secure access to a a secure Flash memory area is RAZ/WI and generates an

illegal access event. An illegal access interrupt is generated if the FLASHIE illegal
access interrupt is enabled in the GTZC_TZIC_IER2 register.
• A non-secure access to a secure Flash register generates an illegal access event. An
illegal access interrupt is generated if the FLASH_REGIE illegal access interrupt is
enabled in the GTZC_TZIC_IER2 register.

RM0438 Rev 7 199/2194

243
Embedded Flash memory (FLASH) RM0438

6.5.7 Flash registers privileged and unprivileged modes

The Flash registers can be read and written by privileged and unprivileged accesses
depending on PRIV bit in FLASH_PRIVCFGR register.
• When the PRIV bit is reset, all Flash registers could be read and written by both
privileged or unprivileged access.
• When the PRIV bit is set, all Flash registers could be read and written by privileged
access only. Unprivileged access to a privileged registers is RAZ/WI.

6.6 Secure system memory

6.6.1 Introduction
Secure system memory stores RSS (root secure services) firmware that is programmed by
ST during STM32L552xx and STM32L562xx production. The RSS provides secure services
to the bootloader and the user firmware. These services are described hereafter in this
section.
The RSS services are only available after the user enables the microcontroller TrustZone®
feature thanks to TZEN bitfield set to 1 within FLASH_OPTR option byte register.
At boot time, the RSS firmware enables and jumps to bootloader; the RSS provides services
to secure user firmware at runtime.

6.6.2 RSS allocates resource to bootloader

When the microcontroller is configured in TrustZone® enabled (option byte register
FLASH_OPTR bitfield TZEN set to 1), then the microcontroller must boot on a secure
address after reset. According to boot configuration, the boot can be done either from a
secure address programmed through SECBOOT0ADDR bitfield of
FLASH_SECBOOTADD0R option byte register or from RSS. In this last case, RSS
firmware is the first firmware running after boot.
The RSS is then responsible for the microcontroller bootloader resource allocation. The
RSS allocates SRAM, system Flash memory, peripherals (USART, I2C, SPI, …), the
respective Os and IRQs to non-secure. The bootloader uses these resources to enable
communication ports as described in AN2606 – STM32 microcontroller system memory
boot mode.
Once resource allocation is done, the RSS triggers a secure to non-secure transition
jumping to the bootloader, that in turn enables all its communication ports. At this step, the
user can connect to the microcontroller either using bootloader communication ports or
debug ports (JTAG or SWD).
As a non-secure firmware, the bootloader never accesses to secure resources. However, in
RDP level 0 only, the bootloader can access the secure option bytes.
For detailed boot modes, please refer to Section 3: Boot configuration.
Table 38 sums up user accesses via bootloader communications ports or JTAG according to
RDP level value.

200/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Table 38. User accesses via bootloader or JTAG

User access via
RDP
User access description
level
Bootloader JTAG

RWX access to non-secure user Flash memory. Yes

RWX access to secure user Flash memory. No Yes (secure debug only)
0 RW access to Flash memory secure option bytes Yes Yes
RWX access SRAM1 Yes
RWX access SRAM2 No Yes (secure debug only)
RWX access to non-secure user Flash memory. Yes
RWX access to secure user Flash memory. No
0.5 RW access to Flash memory secure option bytes No
RWX access SRAM1 Yes
RWX access SRAM2 No
RWX access to non-secure user Flash memory. No
RWX access to secure user Flash memory. No
1 RW access to Flash memory secure option bytes No
RWX access SRAM1 No Yes
RWX access SRAM2 No
RWX access to non-secure user Flash memory.
RWX access to secure user Flash memory.
2 RW access to Flash memory secure option bytes No (RSS does not jump to Bootloader)
RWX access SRAM1
RWX access SRAM2

Non secure peripherals, IRQn and IOs allocated to non-secure for bootloader execution are
described within Table 39.

RM0438 Rev 7 201/2194

243
Embedded Flash memory (FLASH) RM0438

Table 39. Non-secure peripherals, IRQn and IOs for bootloader execution
HW resource type Resource description

USART1, USART2, USART3

SPI1, SPI2, SPI3
I2C1, I2C2, I2C3,
Peripherals USBFS
FDCAN1
ICACHE
IWDG
DMA1_Channel3_IRQn,
DMA1_Channel5_IRQn,
IRQn
DMA2_Channel2_IRQn,
USB_FS_IRQn
USART1 : PA10, PA9
USART2 : PA3, PA2
USART3 : PC11, PC10
SPI1 : PA4, PA5, PA6, PA7
SPI2 : PB12, PB13, PB14, PB15
IO SPI3 : PB5, PG9, PG10, PG12
I2C1: PB6, PB7
I2C2: PB10, PB11
I2C3: PC0, PC1
USB: PA11, PA12
PDCAN: PB8, PB9

For IRQn and IO bootloader detailed usage, please refer to AN2606 – STM32
microcontroller system memory boot mode.

6.6.3 RSSLIB functions

The RSS provides runtime services thanks to RSS library. As other microcontroller
peripherals features and mapping, the RSS library functions are exposed to user within the
CMSIS device header file provided by the STM32CubeL5 firmware package. Please refer to
UM2656 to get more details regarding STM32CubeL5 firmware package. RSS library
functions are named RSSLIB functions hereafter.
The user firmware calls RSSLIB functions using RSSLIB_PFUNC C defined macro, that
points to a location within non-secure system memory. Hence prior calling RSSLIB
functions, the secure user firmware must define a non-secure region above this location
within SAU of the Cortex®-M33. This non-secure region starts from
RSSLIB_SYS_FLASH_NS_PFUNC_START up to
RSSLIB_SYS_FLASH_NS_PFUNC_END. These last addresses are provided within the
CMSIS device header file. The user can set this non-secure region either by using the
CMSIS system partition header file or by implementing its own code for SAU setup. The
CMSIS system partition header file is part of the STM32CubeL5 firmware package.
Note: Some RSSLIB functions are tied to bootloader version (bootloader ID); before calling any
RSSLIB function, the user must check within the dedicated section in this document, if it
depends or not on a bootloader ID. If the RSSLIB function is dependent on bootloader ID,

202/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

the user must read this ID using BL_ID C defined macro from the CMSIS device header file
(BL_ID is one-byte long value). Then, the user firmware must call the right function
according to bootloader ID value.
RSSLIB functions are split between non-secure callable and secure callable function.
The RSS library functions are described within sections hereafter.

CloseExitHDP_BL90
Bootloader ID:
CloseExitHDP_BL90 function is compliant for bootloader ID 0x90.
Secure attribute:
Secure callable function.
Prototype:
uint32_t CloseExitHDP_BL90(uint32_t HdpArea, uint32_t
VectorTableAddr)
Arguments:
• HdpArea:
Input parameter, bitfield that identifies which HDP area to close. Values can be either:
RSSLIB_HDP_AREA1_Msk, RSSLIB_HDP_AREA2_Msk or
RSSLIB_HDP_AREA1_Msk |RSSLIB_HDP_AREA2_Msk.
• VectorTableAddr:
Input parameter,address of the next vector table to apply.
The vector table format is the one used by the Cortex®-M33 core.
Description:
User calls CloseExitHDP_BL90 to close Flash HDP secure memory area and jump to
the reset handler embedded within the vector table which address is passed as input
parameter.
CloseExitHDP_BL90 sets the SP provided by the passed vector table, however it is up
to the caller to first set the new vector table. Then it clears all general-purpose Cortex®-
M33 registers (r0, r1, …) before jumping to new vector table reset handler.
On successful execution, the function does not return and does not push LR onto the
stack.
In case of failure (bad input parameter value), this function returns RSSLIB_ERROR.
Please refer to section Section 6.5.3: Secure hide protection (HDP) to get more details
on Flash memory HDP protection.

CloseExitHDP_BL91
Bootloader ID:
CloseExitHDP_BL91 function is compliant for bootloader ID 0x91 up to 0x9F.
Secure attribute:
Secure callable function.
Prototype:
uint32_t CloseExitHDP_BL91(uint32_t HdpArea, uint32_t
VectorTableAddr)

RM0438 Rev 7 203/2194

243
Embedded Flash memory (FLASH) RM0438

Arguments:
• HdpArea:
Input parameter, bitfield that identifies which HDP area to close. Values can be either:
RSSLIB_HDP_AREA1_Msk, RSSLIB_HDP_AREA2_Msk or
RSSLIB_HDP_AREA1_Msk |RSSLIB_HDP_AREA2_Msk.
• VectorTableAddr:
Input parameter,address of the next vector table to apply.
The vector table format is the one used by the Cortex®-M33 core.
Description:
The user calls CloseExitHDP_BL91 to close Flash HDP secure memory area and jump
to the reset handler embedded within the vector table which address is passed as input
parameter.
CloseExitHDP_BL91 sets the SP provided by the passed vector table, however it is up
to the caller to first set the new vector table. Then it clears all general-purpose
ACortex®-M33 registers (r0, r1, …) before jumping to new vector table reset handler.
On successful execution, the function does not return and does not push LR onto the
stack.
In case of failure (bad input parameter value), this function returns RSSLIB_ERROR.
Please refer to section Section 6.5.3: Secure hide protection (HDP) to get more details
on Flash memory HDP protection.

6.7 FLASH memory protection

The Flash interface implements different protection mechanisms:
• Write protection (WRP)
• Readout protection (RDP)
• Secure protection when TrustZone is active
– Up to two secure watermak-based non-volatile areas
– Up to two secure block-based volatile areas
– Up to two secure hide protection areas

6.7.1 Write protection (WRP)

The user area in Flash memory can be protected against unwanted write operations.
Depending on the DBANK option bit configuration, it allows either to specify:
• In single-bank mode (DBANK=0): four write-protected (WRP) areas can be defined in
each bank, with page size (4 Kbytes) granularity.
• In dual-bank mode (DBANK=1): two write-protected (WRP) areas can be defined in
each bank, with page (2 Kbytes) granularity.
Each area is defined by a start page offset and an end page offset related to the physical
Flash bank base address. These offsets are defined in the WRP address registers: Flash
WPR1 area A address register (FLASH_WRP1AR), Flash WPR1 area B address register
(FLASH_WRP1BR), Flash WPR2 area A address register (FLASH_WRP2AR), Flash
WPR2 area B address register (FLASH_WRP2BR).

204/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Dual bank mode (DBANK=1)

The bank “x” WRP “y” area (x=1,2 and y=A,B) is defined from the address: bank “x” base
address + [WRPxy_STRT x 0x800] (included) to the address: bank “x” base address +
[(WRPxy_END+1) x 0x800] (excluded).

Single bank mode (DBANK=0)

The WRPx “y” area (x=1,2 and y=A,B) is defined from the address: base address +
[WRPy_STRT x 0x800] (included) to the address: base address + [(WRPy_END+1) x
0x1000] (excluded).
For example, to protect by WRP from the address 0x0806 2800 (included) to the address
0x0807 07FF (included):
• If boot in Flash is done in bank 1, FLASH_WRP1AR register must be programmed
with:
– WRP1A_STRT = 0xC5.
– WRP1A_END = 0xE0.
WRP1B_STRT and WRP1B_END in FLASH_WRP1BR can be used instead (area “B”
in bank 1).
• If the two banks are swapped, the protection must apply to bank 2, and
FLASH_WRP2AR register must be programmed with:
– WRP2A_STRT = 0xC5.
– WRP2A_END = 0xE0.
WRP2B_STRT and WRP2B_END in FLASH_WRP2BR can be used instead (area “B
in bank 2).
When WRP is active, it cannot be erased or programmed. Consequently, a software mass
erase cannot be performed if one area is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted,
the secure or non-secure write protection error flag (NSWRPERR or SECWRPERR) is set
in the FLASH_NSSR or FLASH_SECSR register. This flag is also set for any write access
to:
– System Flash memory.
– OTP area.
Note: When the memory readout protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory (secure or non-secure) if the CPU debug features are
connected (JTAG or single wire) or boot code is being executed from RAM or system Flash,
even if WRP is not activated.
Note: To validate the WRP options, the option bytes must be reloaded through the OBL_LAUNCH
bit in Flash control register.
Note: When DBANK=0, it is the user’s responsibility to make sure that no overlapping occurs on
the WRP zone.

RM0438 Rev 7 205/2194

243
Embedded Flash memory (FLASH) RM0438

Table 40. WRP protection

WRP registers values
WRP protection area
(x=1/2 y= A/B)

WRPxy_STRT =
Page WRPxy is protected
WRPxy_END
WRPxy_STRT >
No WRP area.
WRPxy_END
WRPxy_STRT < The pages from WRPxy_STRT to WRPxy_END are
WRPxy_END protected

6.7.2 Readout protection (RDP)

The readout protection is activated by setting the RDP option byte and then, by applying
OBL launch or power-on reset to reload the new RDP option byte. The readout protection
protects the Flash main memory, the option bytes, the backup registers and the SRAMs.

Readout protection levels when Trustzone is disabled

There are three levels of readout protection from no protection (level 0) to maximum
protection or no debug (level 2).
The Flash memory is protected according to the RDP option byte value shown in the table
below.

Table 41. Flash memory readout protection status (TZEN=0)

RDP byte value Readout protection level

0xAA Level 0
Any value except 0xAA or 0xCC Level 1
0xCC Level 2

Level 0: no protection
Read, program and erase operations into the Flash main memory area are possible. The
option bytes, the SRAMs and the backup registers are also accessible by all operations.

Level 1: readout protection

• User mode: code executing in user mode (boot Flash) can access Flash main
memory, option bytes, SRAMs and backup registers with all operations (read, erase,
program).
• Debug, boot RAM and bootloader modes: in debug mode or when code is running
from boot RAM or bootloader, the Flash main memory, the backup registers and the
SRAM2 are totally inaccessible. In Debug and boot RAM modes an intrusion is
detected and a read or write access to the Flash or backup SRAM generates a bus
error and a hard fault interrupt. The on-the-fly decryption region (OTFDEC on
OCTOSPI) is read as zero.

206/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Level 2: no debug
• The protection level 1 is guaranteed.
• All debug features are disabled.
• The boot from SRAM (boot RAM mode) and the boot from system memory (bootloader
mode) are no longer available.
• When booting from Flash, all operations are allowed on the Flash main memory. Read,
erase and program accesses to Flash memory and SRAMs from user code are
allowed.
• Option bytes cannot be programmed nor erased except the SWAP_BANK option bit.
Thus, the level 2 cannot be removed: it is an irreversible operation. When attempting to
modify the options bytes, the protection error flag OPTWERR is set in the
FLASH_NSSR register and an interrupt can be generated.
Note: The debug feature is also disabled under reset.

Table 42. Access status versus protection level and execution modes when TZEN=0
User execution (boot from
Debug/ bootloader(1)
Flash)
Area RDP level
Read Write Erase Read Write Erase

Flash main 1 Yes Yes Yes No No No(2)

memory 2 Yes Yes Yes NA NA NA

System 1 Yes No No Yes No No

memory(3) 2 Yes No No NA NA NA

Option 1 Yes Yes(2) Yes Yes Yes(2) Yes

bytes(4) 2 Yes No (5)
No NA NA NA
1 Yes Yes(6) NA Yes Yes(6) NA
OTP
2 Yes Yes(6) NA NA NA NA

Backup 1 Yes Yes NA No No NA(7)

registers 2 Yes Yes NA NA NA NA
1 Yes Yes NA No No NA(8)
SRAM2
2 Yes Yes NA NA NA NA
(9)
OTFDEC 1 Yes Yes Yes No Yes Yes
regions
(OCTOSPI) 2 Yes Yes Yes NA NA NA

1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. The Flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
3. The system memory is only read-accessible whatever the protection level (0, 1 or 2) and execution mode.
4. Option bytes are only accessible through the Flash registers interface and OPSTRT bit.
5. SWAP_BANK option, bit can be modified.
6. OTP can only be written once.
7. The backup registers are erased when RDP changes from level 1 to level 0.
8. All SRAMs are erased when RDP changes from level 1 to level 0.
9. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.

RM0438 Rev 7 207/2194

243
Embedded Flash memory (FLASH) RM0438

Readout protection levels when Trustzone is enabled

There are four levels of readout protection from no protection (level 0) to maximum
protection or no debug (level 2).
The Flash memory is protected according to the RDP option byte value shown in the table
below.

Table 43. Flash memory readout protection status (TZEN=1)

RDP byte value Readout protection level

0xAA Level 0
0x55 Level 0.5
Any value except 0xAA or 0x55 or 0xCC Level 1
0xCC Level 2

Level 0: no protection
Read, program and erase operations into the Flash main memory area are possible. The
option bytes, the SRAMs and the backup registers are also accessible by all operations.
When booting from RSS, the debug access is disabled while executing RSS code.

Level 0.5: non-secure debug only

All read and write operations (if no write protection is set) from/to the non-secure Flash
memory are possible. The debug access to secure area is prohibited. Debug access to non-
secure area remains possible.
• User mode: code executing in user mode (boot Flash) can access Flash main
memory, option bytes, SRAMs and backup registers with all operations (read, erase,
program).
• Non-secure debug mode: non-secure debug is possible when the CPU is in non-
secure state. The secure Flash memory, the secure backup registers and SRAMs area
are inaccessible; the non-secure Flash memory, the non-secure backup registers and
the non-secure SRAMs area remain accessible for debug purpose.
• RSS mode: when booting from RSS, the debug access is disabled while executing
RSS code.
• Boot RAM mode: boot from SRAM is not possible.

Level 1: readout protection

• User mode: code executing in user mode (boot Flash) can access Flash main
memory, option bytes, SRAMs and backup registers with all operations (read, erase,
program).
• Non-secure debug mode: non-secure debug is possible when the CPU is in non-
secure state. However, an intrusion is detected in case of debug access: the Flash
main memory, the backup registers and the SRAM2 are totally inaccessible; any read
or write access to these memories generates a bus error and a hard fault interrupt. The
on-the-fly decryption region (OTFDEC on OCTOSPI) is read as zero.
• RSS mode: when booting from RSS, the debug access is disabled while executing the
RSS code.
• Boot RAM mode: boot from SRAM is no longer possible.

208/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Level 2: no debug
When the readout protection level 2 is set:
• The protection level 1 is guaranteed.
• All debug features are disabled.
• The boot from SRAM (boot RAM mode) and the boot from system memory (bootloader
mode) are no longer available.
• Boot from RSS is possible.
• When booting from Flash or RSS, all operations are allowed on the Flash main
memory. Read, erase and program accesses to Flash memory and SRAMs from user
code are allowed.
• Option bytes cannot be programmed nor erased except the SWAP_BANK option bit.
Thus, the level 2 cannot be removed: it is an irreversible operation. When attempting to
modify the options bytes, the protection error flag OPTWERR is set in the
FLASH_NSSR register and an interrupt can be generated.
Note: The debug feature is also disabled under reset.

Table 44. Access status versus protection level and execution modes when TZEN=1
User execution (boot from
Debug/ bootloader(1)
Flash)
Area RDP level
Read Write Erase Read Write Erase
(2)
0.5 Yes Yes Yes Yes Yes(2) Yes(2)
Flash main
1 Yes Yes Yes No No No(3)
memory
2 Yes Yes Yes NA NA NA
0.5 Yes No No Yes No No
System
1 Yes No No Yes No No
memory(4)
2 Yes Yes Yes NA NA NA
0.5 Yes Yes(3) Yes Yes Yes(3) Yes
Option
1 Yes Yes(3) Yes Yes Yes(3) Yes
bytes(5)
(6)
2 Yes No No NA NA NA
0.5 Yes Yes(7) NA Yes Yes(7) NA
OTP 1 Yes Yes(7) NA Yes Yes(7)
NA
(7)
2 Yes Yes NA NA NA NA
(2)
0.5 Yes Yes NA Yes Yes(2) NA(8)
Backup
1 Yes Yes NA No No NA(8)
registers
2 Yes Yes NA NA NA NA
(2)
0.5 Yes Yes NA Yes Yes(2) NA(9)
SRAM2 1 Yes Yes NA No No NA(9)
2 Yes Yes NA NA NA NA

RM0438 Rev 7 209/2194

243
Embedded Flash memory (FLASH) RM0438

Table 44. Access status versus protection level and execution modes when TZEN=1
User execution (boot from
Debug/ bootloader(1)
Flash)
Area RDP level
Read Write Erase Read Write Erase

0.5 Yes Yes Yes No(10) Yes Yes

OTFDEC
regions 1 Yes Yes Yes No(10) Yes Yes
(OCTOSPI)
2 Yes Yes Yes NA NA NA
1. When the protection level 2 is active, the debug port and the bootloader mode are disabled.
2. Dependent on TrustZone security access rights.
3. The Flash main memory is erased when the RDP option byte regresses from level 1 to level 0.
4. The system memory is only read-accessible whatever the protection level (0, 1 or 2) and execution mode.
5. Option bytes are only accessible through the Flash registers interface and OPSTRT bit.
6. SWAP_BANK option bit can be modified.
7. All SRAMs are erased when RDP changes from level 1 to level 0.
8. The backup registers are erased when RDP changes from level 1 to level 0.
9. All SRAMs are erased when RDP changes from level 1 to level 0.
10. The OTFDEC keys are erased when the RDP option byte changes from level 1 to level 0.

Device life cycle managed by readout protection (RDP) transitions

It is easy to move from level 0 or level 0.5 to level 1 by changing the value of the RDP byte
to any value (except 0xCC). By programming the 0xCC value in the RDP byte, it is possible
to go to level 2 either directly from level 0 or from level 0.5 or level 1. Once in level 2, it is no
longer possible to modify the readout protection level.
When the RDP is reprogrammed to the value 0xAA to move from level 0.5 or from level 1 to
level 0, a mass erase of the Flash main memory is performed. The backup registers, all
SRAMs and the OTFDEC keys are also erased. The OTP area is not erased.
When the RDP is programmed to the value 0x55 to move from level 1 to level 0.5, a partial
mass erase of Flash main memory is performed. Only non-secure watermark-based areas
are erased (even if it is defined as secure by block-based). The backup registers, the
OTFDEC keys and all SRAMs are mass erased. The OTP area is not erased. The RDP
level 0.5 and partial non-secure erase are only available when TrustZone is active.
When TrustZone is active, in case of RDP level 0.5 or level 1, the RDP regression to level 0
or level 0.5 can only be done by debug interface or by system bootloader.
Note: Full mass erase is performed only when level 1 or level 0.5 is active and level 0 requested.
When the protection level is increased (0->0.5, 0->1, 0.5->1, 1->2,
0->2, 0.5->2) there is no mass erase.
To validate the protection level change, the option bytes must be reloaded through the
OBL_LAUNCH bit in Flash non-secure control register.
Note: Before launching a RDP regression, the software must invalidate the ICACHE and wait for
the BUSYF bit to get cleared.

210/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Figure 16. RDP level transition scheme when TrustZone is disabled (TZEN=0l)
Write
RDP /= 0XAA and
RDP /= 0xCC
Write
RDP = 0xCC Level 1
Write
RDP ≠ 0xAA
RDP = 0xAA
RDP ≠ 0xCC
Mass erase

Level 2 Level 0
RDP = 0xCC RDP = 0xAA
Write
RDP = 0xCC Write
RDP = 0xAA
RDP increase + option bytes modification

RDP regression

RDP unchanged.

RDP unchanged. Only SWAP_BANK option bit can be

modified. MSv49343V1

Figure 17. RDP level transition scheme when TrustZone is enabled (TZEN=1)

Write
Write RDP /= 0XAA, 0x55 And 0xCC
RDP = 0xCC Level 1
RDP ≠ 0xAA
RDP ≠ 0x55
RDP ≠ 0xCC Write
RDP = 0xAA
Mass erase

Level 0.5
RDP = 0x55

Level 2 Level 0
RDP = 0xCC RDP = 0xAA
Write Write
RDP = 0xCC RDP = 0xAA
RDP increase + option bytes modification.
RDP unchanged. Only SWAP_BANK option bit
can be modified.
RDP regression. Full mass erase (secure and non-secure).
RDP unchanged.
RDP regression. Partial mass erase (non-secure only)

Note: RDP regression can only be done by debug interface or by system bootloader MSv49344V1

Summary of Flash memory and Flash registers access control

Table 45 to Table 47 summarize all the Flash memory access versus RDP level, WPR and
HDP protection when TrustZone is active and disabled.

RM0438 Rev 7 211/2194

243
Embedded Flash memory (FLASH) RM0438

Table 45. Flash access versus RDP level when TrustZone is active (TZEN=1)
RDP level-1
RDP level-0, RDP level-0.5, RDP level-1 no intrusion(1) or
with
RDP level-2
intrusion(2)

Access type Secure page

Non-secure Non-secure or
HDP area
page secure page
(HDPxEN=1 and Others(3)
HDPx_ACCDIS= 1)

Fetch Bus error

RAZ, Flash illegal RAZ OK
Read Bus error
access event
Secure Write WI, NO WRP: OK
SECWRPERR WRP pages: WI
WI, SECWRPERR flag WI,
Page flag set, Flash and
set SECWRPERR
erase illegal access SECWRPERR
event flag set flag set

Fetch Bus error

OK
Read RAZ, Flash illegal access event Bus error
Non- Write NO WRP: OK
Secure
WRP pages: WI WI, NSWRPERR flag set, WI,
Page and NSWRPERR Flash illegal access event NSWRPERR
erase flag set flag set
1. Level 1 no intrusion = when booting from user Flash and no debug access.
2. Level 1 with intrusion = when debug access is detected.
3. Others refers to other Flash memory secure configuration than the one described for HDP protections.
Example: Flash secure HDP area enabled but ACCDIS=0.

Table 46. Flash access versus RDP level when TrustZone is disabled (TZEN=0)
RDP level-1
Access
RDP level-0, RDP level-1 no intrusion(1) or RDP level-2 with
type
intrusion(2)

Fetch
OK
Read Bus error
Write
NO WRP: OK WI and
Erase WRP pages: WI and NSWRPERR flag set NSWRPERR
flag set
1. Level 1 no intrusion = when booting from user Flash and no debug access.
2. RDP Level 1 with intrusion = when booting from user Flash and no debug access.

212/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Table 47. Flash mass erase versus RDP level when TrustZone is active (TZEN = 1)
RDP level-1
RDP level-0, RDP level-0.5, RDP level-1 no intrusion(1) or
with
RDP level-2
intrusion(2)
Access type
Secure Flash
Non-secure Mix non-secure Non-secure or
Flash HDP area (HDPxEN=1 and secure Flash secure Flash
Others(3)
and HDPx_ACCDIS = 1)

WI, NO WRP: OK WI,

Bank
SECWRPERR WRP pages: SECWRPERR WI,
or
Secure flag set, Flash WI, SECWRPERR flag set WI and flag set, Flash SECWRPERR
mass
illegal access SECWRPERR illegal access flag set
erase
event flag set event

NO WRP: OK
Bank
WRP pages: WI,
Non- or
WI and WI, NSWRPERR flag set, Flash illegal access event NSWRPERR
secure mass
NSWRPERR flag set
erase
flag set
1. RDP Level 1 no intrusion = when booting from user Flash and no debug access.
2. RDP Level 1 with intrusion = when booting from user Flash and debug access is detected.
3. Others refers to other Flash secure configuration than the one described for HDP protections. Example: Flash secure,
HDP area enabled but HDPxACCDIS = 0.

Table 48. Flash system memory, RSS and OTP accesses(1)

System memory
Access type OTP RSS
(bootloader)

Fetch Bus error

RAZ
Read RAZ, and a Flash illegal access event
Secure
WI, SECWRPERR flag set, WI,
Write
Flash illegal access event SECWRPERR flag set
Fetch Bus error Bus error
OK RAZ, Flash illegal access
Read OK
event(2)
Non-secure
(TZEN = 0 or OK
TZEN = 1) if not virgin: WI,
Write WI and NSWRPERR flag set WI, NSWRPERR,
NSPROGERR Flash illegal access event(3)
flag set
1. Valid for all RDP levels.
2. Flash illegal access event is only generated when TZEN=1.

RM0438 Rev 7 213/2194

243
Embedded Flash memory (FLASH) RM0438

Table 49. Flash registers access

Non-secure register Secure register
Access type
PRIV=1 PRIV=0 PRIV=1 PRIV=0

Secure/ Privileged/
Fetch Bus error
non-secure unprivileged
Privileged OK
Secure(1)
Read/ Unprivileged RAZ/WI OK RAZ/WI OK
Write Privileged OK
Non- RAZ/WI and a Flash register
secure(2) Unprivileged RAZ/WI OK illegal access event(3)

1. Secure access is only valid when TrsutZone is active (TZEN=1).

2. Non-secure access are valid when TrsutZone is active or disabled.
3. Flash register illegal access event is only generated when TZEN=1.

6.8 FLASH interrupts

Table 50. Flash interrupt request
Interrupt Event flag/interrupt Interrupt enable
Interrupt event Event flag
Vector clearing method control bit

Secure end of operation SECEOP(1) Write SECEOP=1 SECEOPIE

FLASH_S Secure operation error SECOPERR(2) Write SECOPERR=1 SECERRIE
Secure read error SECRDERR Write SECRDERR=1 SECRDERRIE
Non-secure End of opera-
NSEOP(3) Write NSEOP=1 NSEOPIE
tion
FLASH Non-secure operation
NSOPERR(4) Write NSOPERR=1 NSERRIE
error
ECC correction ECCC Write ECCC=1 ECCCIE
1. SECEOP or NSEOP are set only if SECEOPIE or is NSEOPIE is set.
2. SECOPERR is set only if SECERRIE is set.
3. SECEOP is set only if SECEOPIE is set.
4. NSOPERR is set only if NSERRIE is set.

214/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9 FLASH registers

6.9.1 Flash access control register (FLASH_ACR)

This register is non-secure. It can be read and written by both secure and non-secure
access. This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLEEP RUN_P
LVEN Res. Res. Res. Res. Res. Res. Res. Res. Res. LATENCY[3:0]
_PD D
rw rw rw rw rw rw rw

--

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 LVEN: Flash low-voltage enable
This bit can only be written when it is unlocked by writing the FLASH_LVEKEYR register.
When set, this bit enable the flash low voltage and bypass the voltage range selected by
PWR. This bit must be set when using the external SMPS.
When this bit is cleared, it is locked again.
0: Flash low voltage is disabled. Flash low voltage is managed by the power controller PWR.
1: Flash low voltage is enabled.
Bit 14 SLEEP_PD: Flash power-down mode during Sleep or Low-power sleep mode
This bit determines whether the Flash memory is in power-down mode or Idle mode when
the device is in Sleep or Low-power sleep mode.
0: Flash in Idle mode during Sleep and Low-power sleep modes
1: Flash in power-down mode during Sleep and Low-power sleep modes
Caution: The Flash must not be put in power-down while a program or an erase operation is
on-going.

RM0438 Rev 7 215/2194

243
Embedded Flash memory (FLASH) RM0438

Bit 13 RUN_PD: Flash power-down mode during Run or Low-power run mode
This bit is write-protected with FLASH_PDKEYR.
This bit determines whether the Flash memory is in power-down mode or Idle mode when
the device is in Run or Low-power run mode. The Flash memory can be put in power-down
mode only when the code is executed from RAM. The Flash must not be accessed when
RUN_PD is set.
0: Flash in Idle mode
1: Flash in Power-down mode
Caution: The Flash must not be put in power-down while a program or an erase operation is
on-going.
Bits 12:4 Reserved, must be kept at reset value.
Bits 3:0 LATENCY[3:0]: Latency
These bits represent the ratio of the SYSCLK (system clock) period to the Flash
access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
0011: Three wait states
0100: Four wait states
...1111: Fifteen wait states

6.9.2 Flash power-down key register (FLASH_PDKEYR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PDKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PDKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 PDKEYR[31:0]: Power-down in Run mode Flash key

The following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR:
PDKEY1: 0x0415 2637
PDKEY2: 0xFAFB FCFD

216/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9.3 Flash non-secure key register (FLASH_NSKEYR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 NSKEYR[31:0]: Flash non secure key

The following values must be written consecutively to unlock the FLACH_NSCR register
allowing Flash non-secure programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB

6.9.4 Flash secure key register (FLASH_SECKEYR)

This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 SECKEYR[31:0]: Flash secure key

The following values must be written consecutively to unlock the FLACH_SECCR register
allowing flash secure programming/erasing operations:
KEY1: 0x4567 0123
KEY2: 0xCDEF 89AB

RM0438 Rev 7 217/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.5 Flash option key register (FLASH_OPTKEYR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPTKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPTKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 OPTKEYR[31:0]: Option byte key

The following values must be written consecutively to unlock the FLACH_OPTR register
allowing option byte programming/erasing operations:
KEY1: 0x0819 2A3B
KEY2: 0x4C5D 6E7F

6.9.6 Flash low voltage key register (FLASH_LVEKEYR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LVEKEYR[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LVEKEYR[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 LVEKEYR[31:0]: Flash low voltage key

The following values must be written consecutively to unlock the LVEN bit in FLASH_ACR
register:
LVEKEY1: 0xF4F5 F6F7h
LVEKEY2: 0x0A1B 2C3D

218/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9.7 Flash status register (FLASH_NSSR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. NSBSY
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSPR
OPTW NSPG NSSIZE NSPGA NSWR NSOPE
Res. Res. Res. Res. Res. Res. Res. OGER Res. NSEOP
ERR SERR RR ERR PERR RR
R
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 NSBSY: Busy
This indicates that a Flash secure or non-secure operation is in progress. This is set on the
beginning of a Flash operation and reset when the operation finishes or when an error
occurs.
Bit 15 Reserved, must be kept at reset value.
Bit 14 Reserved, must be kept at reset value.
Bit 13 OPTWERR: Option write error
Set by hardware when the options bytes are written with an invalid configuration.
Cleared by writing 1.
Refer to Section 6.3.8: Flash errors flags for full conditions of error flag setting.
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 NSPGSERR: Non-secure programming sequence error
This bit is set by hardware when programming sequence is not correct. It is cleared by
writing 1.
Refer to Section 6.3.8: Flash errors flags for full conditions of error flag setting.
Bit 6 NSSIZERR: Non-secure size error
Set by hardware when the size of the access is a byte or half-word during a non-secure
program sequence. Only double word programming is allowed (consequently: word access).
Cleared by writing 1.
Bit 5 NSPGAERR: Non-secure programming alignment error
Set by hardware when the first word to be programmed is not aligned with a double word
address, or the second word does not belong to the same double word address.
Cleared by writing 1.

RM0438 Rev 7 219/2194

243
Embedded Flash memory (FLASH) RM0438

Bit 4 NSWRPERR: Non-secure write protection error

Set by hardware when an non-secure address to be erased/programmed belongs to a write-
protected part (by WRP, HDP or RDP level 1) of the Flash memory.
Cleared by writing 1.
Refer to Section 6.3.8: Flash errors flags for full conditions of error flag setting.
Bit 3 NSPROGERR: Non-secure programming error
Set by hardware when a non-secure double-word address to be programmed contains a
value different from '0xFFFF FFFF' before programming, or when already fully programmed
to '0x0000 0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 NSOPERR: Non-secure operation error
Set by hardware when a Flash memory non-secure operation (program / erase) completes
unsuccessfully.
This bit is set only if non-secure error interrupts are enabled (NSERRIE = 1).
Cleared by writing ‘1’.
Bit 0 NSEOP: Non-secure End of operation
Set by hardware when one or more Flash memory non-secure operation (programming /
erase) has been completed successfully.
This bit is set only if the non-secure end of operation interrupts are enabled (NSEOPIE = 1).
Cleared by writing 1.

6.9.8 Flash status register (FLASH_SECSR)

This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Y
r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECP SECP
SECSIZ SECPG SECW SECOP SECEO
Res. Res. Res. Res. Res. Res. Res. Res. GSER ROGE Res.
ERR AERR RPERR ERR P
R RR
rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

220/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 SECBSY: Busy
This indicates that a Flash secure or non-secure operation is in progress. This is set on the
beginning of a Flash operation and reset when the operation finishes or when an error
occurs.
Bit 15 Reserved, must be kept at reset value.
Bits 14:8 Reserved, must be kept at reset value.
Bit 7 SECPGSERR: Secure programming sequence error
Set by hardware when a NSSTRT bit is set by a secure access. Set also by hardware when
SECPROGERR, SECSIZERR, SECPGAERR, SECWRPERR or SECPGSER is set due to a
previous programming error.
Cleared by writing 1.
Refer to Section 6.3.8: Flash errors flags for full conditions of error flag setting.
Bit 6 SECSIZERR: Secure size error
Set by hardware when the size of the access is a byte or half-word during a secure program
sequence. Only double word programming is allowed (consequently: word access).
Cleared by writing 1.
Bit 5 SECPGAERR: Secure programming alignment error
Set by hardware when the first word to be programmed is not aligned with a double word
address, or the second word does not belong to the same double word address.
Cleared by writing 1.
Bit 4 SECWRPERR: Secure write protection error
Set by hardware when an secure address to be erased/programmed belongs to a write-
protected part (by WRP, HDP or RDP level 1) of the Flash memory.
Cleared by writing 1.
Refer to Section 6.3.8: Flash errors flags for full conditions of error flag setting.
Bit 3 SECPROGERR: Secure programming error
Set by hardware when a secure double-word address to be programmed contains a value
different from '0xFFFF FFFF' before programming, or already fully programmed to '0x0000
0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 SECOPERR: Secure operation error
Set by hardware when a Flash memory secure operation (program / erase) completes
unsuccessfully.
This bit is set only if secure error interrupts are enabled (SECERRIE = 1).
Cleared by writing ‘1’.
Bit 0 SECEOP: Secure end of operation
Set by hardware when one or more Flash memory secure operation (programming / erase)
has been completed successfully.
This bit is set only if the secure end of operation interrupts are enabled (SECEOPIE = 1).
Cleared by writing 1.

RM0438 Rev 7 221/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.9 Flash non-secure control register (FLASH_NSCR)

This register can only be written when the SECBSY, NSBSY or OBL_LAUNCH are reset.
Otherwise, the write access is stalled till SECBSY and NSBSY are reset.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x28
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSLO OPTL OBL_LAU NSERRI NSEOP OPTST NSSTR
Res. Res. Res. Res. Res. Res. Res. Res. Res.
CK OCK NCH E IE RT T
rs rs rc_w1 rw rw rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSME NSMER
Res. Res. Res. NSBKER Res. NSPNB[6:0] NSPER NSPG
R2 1
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 NSLOCK: FLASH_NSCR Lock

This bit is set only. When set, the FLASH_NSCR register is locked. It is cleared by hardware
after detecting the unlock sequence in FLASH_NSKEYR register.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Bit 30 OPTLOCK: Options Lock
This bit is set only. When set, all bits concerning user option in FLASH_OPTCR register This
bit is cleared by hardware after detecting the unlock sequence. The NSLOCK bit must be
cleared before doing the unlock sequence for OPTLOCK bit.
In case of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 29:28 Reserved, must be kept at reset value.
Bit 27 OBL_LAUNCH: Force the option byte loading
When set to 1, this bit forces the option byte reloading. This bit is cleared only when the
option byte loading is complete. It cannot be written if OPTLOCK is set.
0: Option byte loading complete
1: Option byte loading requested
Bit 26 Reserved, must be kept at reset value.
Bit 25 NSERRIE: Non-secure error interrupt enable
This bit enables the interrupt generation when the NSOPERR bit in the FLASH_NSSR is set
to 1.
0: NSOPERR error interrupt disabled
1: NSOPERR error interrupt enabled

222/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Bit 24 NSEOPIE: Non-secure End of operation interrupt enable

This bit enables the interrupt generation when the NSEOP bit in the FLASH_NSSR is set to
1.
0: NSEOP Interrupt disabled
1: NSEOP Interrupt enabled
Bits 23:18 Reserved, must be kept at reset value.
Bit 17 OPTSTRT: Options modification start
This bit triggers an options operation when set. It can not be written if OPTLOCK bit is set.
This bit is set only by software, and is cleared when the NSBSY bit is cleared in
FLASH_NSSR.
Bit 16 NSSTRT: Non-secure start
This bit triggers a non-secure erase operation when set. If NSMER1, NSMER2 and NSPER
bits are reset and the NSSTRT bit is set, the NSPGERR is set. This condition should be
forbidden.
This bit is set only by software, and is cleared when the NSBSY bit is cleared in
FLASH_NSSR.
Bit 15 NSMER2: Non-secure Bank 2 Mass erase
This bit triggers the bank 2 non-secure mass erase (all bank 2 user pages) when set.
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 NSBKER: Non-secure page number MSB (bank selection)
This bit must be only set when DBANK=1.
0: Bank 1 is selected for non-secure page erase
1: Bank 2 is selected for non-secure page erase.
Bit 10 Reserved, must be kept at reset value.
Bits 9:3 NSPNB[6:0]: Non-secure page number selection
These bits select the page to erase:
00000000:page 0
00000001:page 1
...
11111111:page 127
Bit 2 NSMER1: Non-secure bank 1 mass erase
This bit triggers the bank 1 non-secure mass erase (all bank 1 user pages) when set.
Bit 1 NSPER: Non-secure page erase
0: Non-secure page erase disabled
1: Non-secure page erase enabled
Bit 0 NSPG: Non-secure programming
0: Non-secure Flash programming disabled
1: Non-secure Flash programming enabled

RM0438 Rev 7 223/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.10 Flash secure control register (FLASH_SECCR)

This register can only be written when the SECBSY, NSBSY or OBL_LAUNCH are reset.
Otherwise, the write access stalls till SECBSY and NSBSY are reset.
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x2C
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECL SECIN SECER SECEO SECST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OCK V RIE PIE RT
rs rs rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECM SECBKE SECME SECPE
Res. Res. Res. Res. SECPNB[6:0] SECPG
ER2 R R1 R
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SECLOCK: FLASH_SECCR Lock

This bit is set only. When set, the FLASH_SECCR register is locked. It is cleared by
hardware after detecting the unlock sequence in FLASH_SECKEYR register.
In case of an unsuccessful unlock operation, this bit remains set until the next system reset.
Bit 30 Reserved, must be kept at reset value.
Bit 29 SECINV: Flash security state invert
This bit inverts the flash security state
Bits 28:26 Reserved, must be kept at reset value.
Bit 25 SECERRIE: Secure error interrupt enable
This bit enables the interrupt generation when the SECOPERR bit in the FLASH_SECSR is
set to 1.
0: SECOPERR error interrupt disabled
1: SECOPERR error interrupt enabled
Bit 24 SECEOPIE: Secure End of operation interrupt enable
This bit enables the interrupt generation when the SECEOP bit in the FLASH_SECSR is set
to 1.
0: SECEOP Interrupt disabled
1: SECEOP Interrupt enabled
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 SECSTRT: Secure start
This bit triggers a non-secure erase operation when set. If SECMER1, SECMER2 and
SECPER bits are reset and the SECSTRT bit is set, the SECPGERR is set. This condition
should be forbidden.
This bit is set only by software, and is cleared when the SECBSY bit is cleared in
FLASH_SECSR.

224/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Bit 15 SECMER2: Secure bank 2 mass erase

This bit triggers the bank 2 secure mass erase (all bank 2 user pages) when set.
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 SECBKER: Secure page number MSB (bank selection)
This bit must be only set when DBANK=1.
0: Bank 1 is selected for secure page erase
1: Bank 2 is selected for secure page erase
When DBANK=0, this bit must be kept cleared.
Bit 10 Reserved, must be kept at reset value.
Bits 9:3 SECPNB[6:0]: Secure page number selection
These bits select the page to erase:
00000000:page 0
00000001:page 1
...
11111111:page 127
Bit 2 SECMER1: Secure bank 1 mass erase
This bit triggers the bank 1 secure mass erase (all bank 1 user pages) when set.
Bit 1 SECPER: Secure page erase
0: Secure page erase disabled
1: Secure page erase enabled
Bit 0 SECPG: Non-secure programming
0: Secure Flash programming disabled
1: Secure Flash programming enabled

6.9.11 Flash ECC register (FLASH_ECCR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x30
Reset value: 0x0000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYSF_ BK_EC
ECCD ECCC ECCD2 ECCC2 Res. Res. Res. ECCIE Res. Res. Res. ADDR_ECC[18:16]
ECC C
rc_w1 rc_w1 rc_w1 rc_w1 rw rw rw r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR_ECC[15:0]
r r r r r r r r r r r r r r r r

RM0438 Rev 7 225/2194

243
Embedded Flash memory (FLASH) RM0438

Bit 31 ECCD: ECC detection

DBANK=0
Set by hardware when two ECC errors have been detected (only if ECCC/ECCC2/ECCD/
ECCD2 are previously cleared). When this bit is set, a NMI is generated.
Cleared by writing 1.
DBANK=1
Set by hardware when two ECC errors have been detected on 64-bits LSB (bits 63:0) (only if
ECCC/ECCC2/ECCD/ ECCD2 are previously cleared). When this bit is set, a NMI is
generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected. An interrupt is
generated if ECCIE is set.
Cleared by writing 1.
Bit 29 ECCD2: ECC2 detection
DBANK=0
Set by hardware when two ECC errors have been detected on 64-bits MSB (bits127:64).
This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are previously cleared). When this bit is
set, a NMI is generated.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bit 28 ECCC2: ECC correction
DBANK=0
Set by hardware when one ECC error has been detected and corrected on 64-bits MSB
(bits127:64). This bit is set (only if ECCC/ECCC2/ECCD/ECCD2 are previously cleared). An
interrupt is generated if ECCIE is set.
Cleared by writing 1.
DBANK=1
Reserved, must be kept at reset value.
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 ECCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled.
DBANK=0
This bit enables the interrupt generation when the ECCC or ECCC2 bits in the
FLASH_ECCR register are set.
DBANK=1
This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR register is
set.
Bit 23 Reserved, must be kept at reset value.
Bit 22 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is located in
the system Flash.

226/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Bit 21 BK_ECC: ECC fail bank

DBANK=1
This bit indicates which bank is concerned by the ECC error correction or by the
double ECC error detection.
0: bank 1
1: bank 2
DBANK=0
If SYSF_ECC is 1, it indicates which bank is concerned by the ECC error
If SYSF_ECC is 0, reserved, must be kept cleared.
Bits 20:19 Reserved, must be kept at reset value.
Bits 18:0 ADDR_ECC[18:0]: ECC fail address
This bit indicates which address is concerned by the ECC error correction or by the double
ECC error detection.

6.9.12 Flash option register (FLASH_OPTR)

This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x40
ST production value: 0x7FEFF8AA (Register bits 0 to 31 are loaded with values from Flash
memory at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA15_ nBOOT nSWB SRAM2 SRAM2 DB256 SWAP_ WWDG IWDG_ IWDG_ IWDG_
TZEN Res. Res. Res. DBANK
PUPEN 0 OOT0 _RST _PE K BANK _SW STDBY STOP SW
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nRST_ nRST_ nRST_
Res. Res. BOR_LEV[2:0] RDP[7:0]
SHDW STDBY STOP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 TZEN: Global TrustZone security enable

0: Global TrustZone security disabled.
1: Global TrustZone security enabled.
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 PA15_PUPEN: PA15 pull-up enable
0: USB power delivery dead-battery enabled/ TDI pull-up deactivated
1: USB power delivery dead-battery disabled/ TDI pull-up activated
Bit 27 nBOOT0: nBOOT0 option bit
0: nBOOT0 = 0
1: nBOOT0 = 1

RM0438 Rev 7 227/2194

243
Embedded Flash memory (FLASH) RM0438

Bit 26 nSWBOOT0: Software BOOT0

0: BOOT0 taken from the option bit nBOOT0
1: BOOT0 taken from PH3/BOOT0 pin
Bit 25 SRAM2_RST: SRAM2 erase when system reset
0: SRAM2 erased when a system reset occurs
1: SRAM2 is not erased when a system reset occurs
Bit 24 SRAM2_PE: SRAM2 parity check enable
0: SRAM2 parity check enable
1: SRAM2 parity check disable
Bit 23 Reserved, must be kept at reset value.
Bit 22 DBANK:
0: Single bank mode with 128 bits data read width
1: Dual bank mode with 64 bits data
This bit can only be written when all protection (secure, HDP) are disabled.
Bit 21 DB256K: Dual-bank on 256 Kbytes Flash memory devices
0: 256 Kbytes single Flash: contiguous address in bank1
1: 256 Kbytes dual-bank Flash with contiguous addresses.
Bit 20 SWAP_BANK: Swap banks
It must be only used in dual-bank mode (DBANK=1). It can only be written when all the Flash
memory is non-secure. Otherwise the OPTWERR is set.
0: Bank 1 and bank 2 address are not swapped.
1: Bank 1 and bank 2 address are swapped.
Bit 19 WWDG_SW: Window watchdog selection
0: Hardware window watchdog
1: Software window watchdog
Bit 18 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
0: Independent watchdog counter is frozen in Standby mode
1: Independent watchdog counter is running in Standby mode
Bit 17 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Independent watchdog counter is frozen in Stop mode
1: Independent watchdog counter is running in Stop mode
Bit 16 IWDG_SW: Independent watchdog selection
0: Hardware independent watchdog
1: Software independent watchdog
Bit 15 Reserved, must be kept at reset value.
Bit 14 nRST_SHDW:
0: Reset generated when entering the Shutdown mode
1: No reset generated when entering the Shutdown mode
Bit 13 nRST_STDBY:
0: Reset generated when entering the Standby mode
1: No reset generate when entering the Standby mode
Bit 12 nRST_STOP:
0: Reset generated when entering the Stop mode
1: No reset generated when entering the Stop mode

228/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Bit 11 Reserved, must be kept at reset value.

Bits 10:8 BOR_LEV[2:0]: BOR reset level
These bits contain the VDD supply level threshold that activates/releases the reset.
000: BOR Level 0. Reset level threshold is around 1.7 V
001: BOR Level 1. Reset level threshold is around 2.0 V
010: BOR Level 2. Reset level threshold is around 2.2 V
011: BOR Level 3. Reset level threshold is around 2.5 V
100: BOR Level 4. Reset level threshold is around 2.8 V
Bits 7:0 RDP[7:0]: Readout protection level
0xAA: Level 0, readout protection not active
0x55: Level 0.5, readout protection not active, only non-secure debug access is possible.
Only available when TrustZone is active (TZEN=1)
0xCC: Level 2, chip readout protection active
Others: Level 1, memories readout protection active
Note: Refer to Section : Level 1: readout protection for more details.

6.9.13 Flash non-secure boot address 0 register (FLASH_NSBOOTADD0R)

This register can not be written if OPTLOCK bit is set.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x44
ST production value: 0x0800007F (The option bytes are loaded with values from the Flash
memory at reset release)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD0[24:9]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD0[8:0] Res. Res. Res. Res. Res. Res. Res.
w w w w w w w w w

Bits 31:7 NSBOOTADD0[24:0]: Non-secure Boot base address 0

The non-secure boot memory address can be programmed to any address in the valid
address range with a granularity of 128 bytes.
The NSBOOTADD0[24:0] correspond to address [31:7]. The NSBOOTADD0 option bytes
are selected following the Boot pin or nSWBOOTO state.
Example:
NSBOOTADD0[24:0] = 0x0100000: Boot from non-secure Flash (0x0800 0000)
NSBOOTADD0[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)
NSBOOTADD0[24:0] = 0x0040000: Boot from non-secure SRAM1 on S-Bus(0x2000 0000)
Bits 6:0 Reserved, must be kept at reset value.

RM0438 Rev 7 229/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.14 Flash non-secure boot address 1 register (FLASH_NSBOOTADD1R)

This register can not be written if OPTLOCK bit is set.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x48
ST production value: 0x0BF9007F (The option bytes are loaded with values from the Flash
memory at reset release)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NSBOOTADD1[24:9]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NSBOOTADD1[8:0] Res. Res. Res. Res. Res. Res. Res.
w w w w w w w w w

Bits 31:7 NSBOOTADD1[24:0]: Non-secure boot address 1

The non-secure boot memory address can be programmed to any address in the valid
address range with a granularity of 128 bytes.
The NSBOOTADD1[24:0] correspond to address [31:7]. The NSBOOTADD0 option bytes
are selected following the boot pin or nSWBOOTO state.
Example:
NSBOOTADD1[24:0] = 0x0100000: Boot from non-secure Flash (0x0800 0000)
NSBOOTADD1[24:0] = 0x017F200: Boot from system memory bootloader (0x0BF9 0000)
NSBOOTADD1[24:0] = 0x0040000: Boot from non-secure SRAM1 on S-Bus(0x2000 0000)
Bits 6:0 Reserved, must be kept at reset value.

6.9.15 Flash secure boot address 0 register (FLASH_SECBOOTADD0R)

This register can not be written if OPTLOCK bit is set.
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x4C
ST production value: 0x0C00007C (The option bytes are loaded with values from the Flash
memory at reset release)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access.

230/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBOOTADD0[24:9]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BOOT_
SECBOOTADD0[8:0] Res. Res. Res. Res. Res. Res.
LOCK
w w w w w w w w w rs

Bits 31:7 SECBOOTADD0[24:0]: Secure boot base address 0

The secure boot memory address can be programmed to any address in the valid address
range with a granularity of 128 bytes.
The SECBOOTADD0[24:0] correspond to address [31:7] The SECBOOTADD0 option bytes
are selected following the boot pin or nSWBOOTO state.
Example:
SECBOOTADD0[24:0] = 0x018 0000: Boot from secure Flash (0x0C00 0000)
SECBOOTADD0[24:0] = 0x01F F000: Boot from RSS (0x0FF8 0000)
SECBOOTADD0[24:0] = = 0x060 0000: Boot from secure SRAM1 on S-Bus (0x3000 0000)
Bits 6:1 Reserved, must be kept at reset value.
Bit 0 BOOT_LOCK: BOOT LOCK
When set, the boot is always forced to base address value programmed in
SECBOOTADD0[24:0] option bytes whatever the boot selection option.
When set, it cannot be cleared.

6.9.16 Flash bank 1 secure watermak1 register (FLASH_SECWM1R1)

This register can not be written if OPTLOCK bit is set.
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x50
ST production value: 0xFFFFFF80 (Register bits are loaded with values from Flash memory
at OBL. Reserved bits are read as “1”)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. SECWM1_PEND[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. SECWM1_PSTRT[6:0]
rw rw rw rw rw rw rw

RM0438 Rev 7 231/2194

243
Embedded Flash memory (FLASH) RM0438

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 SECWM1_PEND[6:0]: End page of first secure area
DBANK=1
SECWM1_PEND contains the last page of the secure area in bank 1.
DBANK=0
SECWM1_PEND contains the last page of the first secure area for all memory.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 SECWM1_PSTRT[6:0]: Start page of first secure area
DBANK=1
SECWM1_PSTRT contains the first page of the secure area in bank 1.
DBANK=0
SECWM1_PSTRT contains the first page of the first secure area for all memory.

6.9.17 Flash secure watermak1 register 2 (FLASH_SECWM1R2)

This register can not be written if OPTLOCK bit is set.
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x54
ST production value: 0x7F807F80 (Register bits are loaded with values from Flash memory
at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP1E
Res. Res. Res. Res. Res. Res. Res. Res. HDP1_PEND[6:0]
N
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 HDP1EN: Hide protection first area enable

0: No HDP area 1
1: HDP first area is enabled.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:16 HDP1_PEND[6:0]: End page of first hide protection area
DBANK=1
HDP1_PEND contains the last page of the HDP area in bank1.
DBANK=0
HDP1_PEND contains the last page of the first HDP area for all memory.
Bits 15:0 Reserved, must be kept at reset value.

232/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9.18 Flash WPR1 area A address register (FLASH_WRP1AR)

This register can not be written if OPTLOCK bit is set.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x58
ST production value: 0xFF80FFFF (Register bits are loaded with values from Flash memory
at OBL. Reserved bits are read as “1”)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_PEND[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1A_PSTRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP1A_PEND[6:0]: Bank 1 WPR first area “A” end page
DBANK=1
WRP1A_PEND contains the last page of the first WPR area in bank 1.
DBANK=0
WRP1A_PEND contains the last page of the first WPR area for all memory.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1A_PSTRT[6:0]: bank 1 WPR first area “A” start page
DBANK=1
WRP1A_PSTRT contains the first page of the first WPR area for bank1.
DBANK=0
WRP1A_PSTRT contains the first page of the first WPR area for all memory.

RM0438 Rev 7 233/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.19 Flash WPR1 area B address register (FLASH_WRP1BR)

This register can not be written if OPTLOCK bit is set.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x5C
ST production value: 0xFF80FFFF (Register bits are loaded with values from Flash memory
at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_PEND[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP1B_PSTRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP1B_PEND[6:0]: Bank 1 WRP second area “B” end page
DBANK=1
WRP1B_PEND contains the last page of the second WRP area in bank1.
DBANK=0
WRP1B_PEND contains the last page of the second WRP area for all memory.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP1B_PSTRT[6:0]: Bank 1 WRP second area “B” start page
DBANK=1
WRP1B_PSTRT contains the first page of the second WRP area for bank1.
DBANK=0
WRP1B_PSTRT contains the first page of the second WRP area for all memory.

234/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9.20 Flash secure watermak2 register (FLASH_SECWM2R1)

This register can not be written if OPTLOCK bit is set.
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x60
ST production value: 0xFFFFFF80 (Register bits are loaded with values from Flash memory
at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. SECWM2_PEND[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. SECWM2_PSTRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 SECWM2_PEND[6:0]: End page of second secure area
DBANK=1
SECWM2_PEND contains the last page of the secure area in bank 2.
DBANK=0
SECWM2_PEND contains the last page of the second secure area for all memory.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 SECWM2_PSTRT[6:0]: Start page of second secure area
DBANK=1
SECWM2_PSTRT contains the first page of the secure area in bank 2.
DBANK=0
SECWM2_PSTRT contains the first page of the second secure area for all memory.

RM0438 Rev 7 235/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.21 Flash secure watermak2 register 2 (FLASH_SECWM2R2)

This register can not be written if OPTLOCK bit is set.
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x64
ST production value: 0x7F807F80 (Register bits are loaded with values from Flash memory
at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HDP2E
Res. Res. Res. Res. Res. Res. Res. Res. HDP2_PEND[6:0]
N
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

Bit 31 HDP2EN: Hide protection second area enable

0: No HDP area 2
1: HDP second area is enabled.
Bits 30:23 Reserved, must be kept at reset value.
Bits 22:16 HDP2_PEND[6:0]: End page of hide protection second area
DBANK=1
HDP2_PEND contains the last page of the HDP area in bank 2.
DBANK=0
HDP2_PEND contains the last page of the second HDP area for all memory.
Bits 15:0 Reserved, must be kept at reset value.

236/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9.22 Flash WPR2 area A address register (FLASH_WRP2AR)

This register can not be written if OPTLOCK bit is set.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x68
ST production value: 0xFF80FFFF (Register bits are loaded with values from Flash memory
at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_PEND[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2A_PSTRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP2A_PEND[6:0]: Bank 2 WPR first area “A” end page
DBANK=1
WRP2A_PEND contains the last page of the first WRP area in bank2.
DBANK=0
WRP2A_PEND contains the last page of the third WRP area for all memory.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2A_PSTRT[6:0]: Bank 2 WPR first area “A” start page
DBANK=1
WRP2A_PSTRT contains the first page of the first WRP area for bank2.
DBANK=0
WRP2A_PSTRT contains the first page of the third WRP area for all memory.

RM0438 Rev 7 237/2194

243
Embedded Flash memory (FLASH) RM0438

6.9.23 Flash WPR2 area B address register (FLASH_WRP2BR)

This register can not be written if OPTLOCK bit is set.
This register is non-secure. It can be read and written by both secure and non-secure
access.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x6C
ST production value: 0xFF80FFFF (Register bits are loaded with values from Flash memory
at OBL)
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_PEND[6:0]
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. WRP2B_PSTRT[6:0]
rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 WRP2B_PEND[6:0]: Bank 2 WPR second area “B” end page
DBANK=1
WRP2B_PEND contains the last page of the second WRP area in bank 2.
DBANK=0
WRP2B_PEND contains the last page of the fourth WRP area for all memory.
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 WRP2B_PSTRT[6:0]: Bank 2 WPR second area “B” start page
DBANK=1
WRP2B_PSTRT contains the first page of the second WRP area for bank 2.
DBANK=0
WRP2B_PSTRT contains the first page of the fourth WRP area for all memory.

238/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

6.9.24 FLASH secure block based bank 1 register (FLASH_SECBB1Rx)

(where x=1..4)
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0x80 + 4 *(x - 1), (x=1..4)
Reset value: 0x0000 0000
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB1[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB1[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SECBB1[31:0]: page secure/non-secure attribution

This bit is used to set the page security attribution in bank 1 when dual bank mode or for the
all memory in single bank mode.
DBANK=1
0:Page (32 * x+y) in bank 1 is non secure
1:Page (32 * x+y) i in bank 1 is secure
DBANK=0
0:Page (32 * x+y) in all memory is non secure
1:Page (32 * x+y) in all memory is secure

6.9.25 FLASH secure block based bank 2 register (FLASH_SECBB2Rx)

(where x=1..4)
This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0xA0 + 4 *(x - 1), (x=1..4)
Reset value: 0x0000 0000
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SECBB2[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SECBB2[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 239/2194

243
Embedded Flash memory (FLASH) RM0438

Bits 31:0 SECBB2[31:0]: page secure/non-secure attribution

This bit is used to set the page security attribution in bank 2. This must be only used in dual
bank mode. In single bank mode, writing this bit has no effect and written data is ignored.
DBANK=1
0:Page (32 * x+y) in bank 2 is non secure
1:Page (32 * x+y) i in bank 2 is secure
DBANK=0
Reserved, must be kept at reset value.

6.9.26 FLASH secure HDP control register (FLASH_SECHDPCR)

This register is secure. It can be read and written only by secure access. A non-secure
read/write access is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
FLASH_PRIVCFGR register.
Address offset: 0xC0
Reset value: 0x0000 0000
Access: no wait state when no option bytes modification is on going; word, half-word and
byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HDP2_ HDP1_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ACCDI ACCDI
S S
rs rs

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 HDP2_ACCDIS: HDP2 area access disable
When set, this bit is only cleared by a system reset
0:Access to HDP2 area is granted
1:Access to HDP2 area is denied and options bytes modification listed in Table 34: Default
secure option bytes after TZEN activation are denied
Bit 0 HDP1_ACCDIS: HDP1 area access disable
When set, this bit is only cleared by a system reset
0:Access to HDP1 area is granted
1:Access to HDP1 area is denied and options bytes modification listed in Table 34: Default
secure option bytes after TZEN activation are denied

6.9.27 FLASH privilege configuration register (FLASH_PRIVCFGR)

This register can be read by both privileged and unprivileged access.
When the system is secure (TZEN =1),this register can be read by secure and non-secure
access. It is write-protected against non-secure write access when the Flash is secure. A
non-secure write access is ignored and generates an illegal access event.
Address offset: 0xC4

240/2194 RM0438 Rev 7

RM0438 Embedded Flash memory (FLASH)

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIV

rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 PRIV: Privilege protection
This bit can be read by both privileged or unprivileged, secure and non-secure access. when
set, it can only be cleared by a privileged access.
0: All Flash registers can be read and written by privileged or unprivileged access.
1: All Flash registers can be read and written by privileged access only.
If the Flash is not secure (no secure area defined), the PRIV bit can be written by a secure or
non-secure privileged access.
If the Flash is secure, the PRIV bit can be written only by a secure privileged access:
– A non-secure write access is ignored and generates an illegal access event.
– A secure unprivileged write access on PRIV bit is ignored

6.9.28 FLASH register map and reset values

Table 51. Flash interface - register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SLEEP_PD
RUN_PD
LVEN

LATENCY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_ACR
0x00 [3:0]

Reset value 0 0 0 0 0 0 0

FLASH_PDKEYR PDKEYR[31:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_NSKEYR NSKEYR[31:0]
0x08
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_SECKEYR SECKEYR[31:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_OPTKEYR OPTKEYR[31:0]
0x10
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FLASH_LVEKEYR LVEKEYR[31:0]
0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NSPROGERR
NSWRPERR
NSPGSERR

NSPGAERR
OPTWERR

NSSIZERR

NSOPERR
NSEOP
NSBSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.

FLASH_NSSR
0x20

Reset value 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 241/2194

243
 0x58
0x54
0x50
0x48
0x44
0x40
0x30
0x28
0x24

0x4C
0x2C
Offset

242/2194
DD1R
DD0R

ADD0R

FLASH_
FLASH_
Register

Reset value
Reset value

Reset value
Reset value

SECWM1R2
SECWM1R1
FLASH_OPTR
FLASH_ECCR
FLASH_NSCR
FLASH_SECSR

FLASH_SECCR

FLASH_WRP1AR
FLASH_NSBOOTA
FLASH_NSBOOTA

FLASH_SECBOOT

ST production value
ST production value
1

ST production value 1
ST production value 0
ST production value 0
ST production value 0
ST production value 0
0
1
Res. HDP1EN Res. TZEN ECCD SECLOCK NSLOCK Res. 31

0
0
0
0
1
Res. Res. Res. Res. ECCC Res. OPTLOCK Res. 30

0
0
0
0
Res. Res. Res. Res. ECCD2 SECINV Res. Res. 29

0
0
0
1
0
Res. Res. Res. PA15_PUPEN ECCC2 Res. Res. Res. 28

1
1
1
1
0
Res. Res. Res. nBOOT0 Res. Res. OBL_LAUNCH Res. 27

1
0
0
1
Embedded Flash memory (FLASH)

Res. Res. Res. nSWBOOT0 Res. Res. Res. Res. 26

0
1
0
1
0
Res. Res. Res. SRAM2_RST Res. SECERRIE NSERRIE Res. 25

0
1
0
1
0
0
Res. Res. Res. SRAM2_PE ECCCIE SECEOPIE NSEOPIE Res. 24

0
1
0
Res. Res. Res. Res. Res. Res. Res. Res. 23

0
0
1
0
1
0
1
0
DBANK SYSF_ECC Res. Res. Res. 22

0
0
1
0
1
0
1
0
DB256K BK_ECC Res. Res. Res. 21

0
0
1
0
1
0
0
0
SWAP_BANK Res. Res. Res. 20

0
0
1
0
1
0
1
0
WWDG_SW Res. Res. Res. 19

0
0
1
0
0
0
1
0
IWDG_STDBY Res. Res. Res. 18

RM0438 Rev 7
0
0
1
0
0
0
1
0
0

HDP1_PEND[6:0]
IWDG_STOP Res. OPTSTRT Res. 17

WRP1A_PEND[6:0]
NSBOOTADD1[24:0]
NSBOOTADD0[24:0]

SECWM1_PEND[6:0]
SECBOOTADD0[24:0]
0

0
0
0

0
1
0
1
0
1
0

IWDG_SW SECSTRT NSSTRT SECBSY 16

0

0
0
0
0
0

Res. Res. Res. Res. SECMER2 NSMER2 Res. 15

0
0
0
1
Res. Res. Res. nRST_SHDW 0 Res. Res. Res. 14

0
0
0
1
0
Res. Res. Res. nRST_STDBY Res. Res. Res. 13

0
0
0
1
0

Res. Res. Res. nRST_STOP Res. Res. Res. 12

0
0
0
0

0
0

Res. Res. Res. Res. SECBKER NSBKER Res. 11

0

0
0
0
0
0

Res. Res. Res. Res. Res. 10

0
0
0
0
0

Res. Res. Res. BOR_LEV[2:0] Res. 9

0
0
0
0
0
ADDR_ECC[20:0]

Res. Res. Res. Res. 8

0
0
0
1
0
0

Res. Res. Res. SECPNB[7:0] SECPGSERR 7

Table 51. Flash interface - register map and reset values (continued)

Res. Res. Res. Res. NSPNB[6:0] SECSIZERR 6

0 1
0 0
0 0

1 1
0 0
0 0

Res. Res. Res. Res. SECPGAERR 5

Res. Res. Res. Res. RDP[7:0] SECWRPERR 4
0 1
0 0
0 0

1 1
0 0
0 0

Res. Res. Res. Res. SECPROGERR 3

0
0
0

1
0
0

Res. Res. Res. Res. SECMER1 NSMER1 Res. 2

Res. Res. Res. Res. SECPER NSPER SECOPERR 1

WRP1A_PSTRT[6:0]
0
1 0
0 0
0 0
0 0

1 1
0 0
0 0

SECWM1_PSTRT[6:0]
RM0438

Res. BOOT_LOCK Res. Res. SECPG NSPG SECEOP 0

RM0438 Embedded Flash memory (FLASH)

Table 51. Flash interface - register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_WRP1BR WRP1B_PEND[6:0] WRP1B_PSTRT[6:0]
0x5C
ST production value 0 0 0 0 0 0 0 1 1 1 1 1 1 1

FLASH_ Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SECWM2_PEND[6:0] SECWM2_PSTRT[6:0]
SECWM2R1
0x60
ST production value 1 1 1 1 1 1 1 0 0 0 0 0 0 0
HDP2EN

FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
HDP2_PEND[6:0]
SECWM2R2
0x64

ST production value 1 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_WRP2AR WRP2A_PEND[6:0] WRP2A_PSTRT[6:0]
0x68
ST production value 0 0 0 0 0 0 0 1 1 1 1 1 1 1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_WRP2BR WRP2B_PEND[6:0] WRP2B_PSTRT[6:0]
0x6C
ST production value 0 0 0 0 0 0 0 1 1 1 1 1 1 1

0x80 + 4 FLASH_
SECBB1[y]
SECBB1Rx
*(x - 1),
(x=1..4) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0xA0 + 4 FLASH_
SECBB2[y]
SECBB2Rx
*(x - 1),
(x=1..4) Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

HDP2_ACCDIS
HDP1_ACCDIS
FLASH_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SECHDPCR
0xC0

Reset value 0 0

FLASH_

PRIV
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0xC4 PRIVCFGR

Reset value 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

RM0438 Rev 7 243/2194

243
Instruction cache (ICACHE) RM0438

7 Instruction cache (ICACHE)

7.1 Introduction
The instruction cache (ICACHE) is introduced on C-AHB code bus of Cortex-M33 processor
to improve performance when fetching instruction and data from both internal and external
memories.
Some specific features like dual master port, hit-under-miss and critical-word-first refill
policy, allow close to zero wait states performance in most use cases.

7.2 ICACHE main features

The main features of ICACHE are described below:
• Bus interface
– one 32-bit AHB slave port, the execution port (input from Cortex-M33 C-AHB code
interface)
– two 32-bit AHB master ports: master1 and master2 ports (outputs to Fast and
Slow buses of main AHB busmatrix, respectively)
– one 32-bit AHB slave port for control (input from AHB peripherals interconnect, for
ICACHE registers access)
• Cache access
– 0 wait-state on hits
– Hit-under-miss capability: ability to serve processor requests (access to cached
data) during an ongoing line refill due to a previous cache miss
– Dual master access: feature used to decouple the traffic according to targeted
memory. For example, ICACHE assigns fast traffic (addressing FLASH and SRAM
memories) to the AHB master1 port, and slow traffic (addressing external
memories sitting on OCTOSPI and FMC interfaces) to AHB master2 port, thus
preventing processor stalls on lines refills from external memories. This allows ISR
(interrupt service routine) fetching on internal FLASH memory to take place in
parallel with a cache line refill from external memory.
– Minimal impact on interrupt latency, thanks to dual master
– Optimal cache line refill thanks to WRAP bursts of the size of the cache line (such
as WRAP4 for 128-bit cache line)
– 2-ways set-associative default configuration with possibility to configure as 1-way,
means direct mapped cache, for applications needing very-low-power
consumption profile
• Memory address remap
– Possibility to remap input address falling into up to four memory regions (used to
remap aliased code in external memories to the internal Code region, for
execution)
• Replacement and refill
– pLRU-t replacement policy (pseudo-least-recently-used, based on binary tree),
algorithm with best complexity/performance balance
– Critical-word-first refill policy, minimizing processor stalls

244/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

– Possibility to configure burst type of AHB memory transaction for remapped

regions: INCRw or WRAPw (size w aligned on cache line size)
• Performance counters
ICACHE implements two performance counters:
– Hit monitor counter (32-bit)
– Miss monitor counter (16-bit)
• Error management
– Possibility to detect an unexpected cacheable write access, to flag an error and
optionally to raise an interrupt
• TrustZone® security support
• Maintenance operation
– Cache invalidate: full cache invalidation, fast command, non interruptible

7.3 ICACHE implementation

Table 52. ICACHE features
Feature ICACHE

Number of ways 2
Cache size 8 Kbytes
Cache line width 16 bytes
range granularity of memory regions to be remapped 2 Mbytes
Number of regions to remap 4
Data size of AHB fast master1 interface 32 bits
Data size of AHB slow master2 interface 32 bits

7.4 ICACHE functional description

The purpose of the instruction cache is to cache instruction fetches or instruction memories
loads, coming from the processor. As such ICACHE only manages read transactions and
does not manage write transactions.
For error management purpose, in case a write cacheable transaction is presented (this
only happens in case of bad software programming), ICACHE sets an error flag and, if
enabled, raises an interrupt to the processor.

RM0438 Rev 7 245/2194

261
Instruction cache (ICACHE) RM0438

7.4.1 ICACHE block diagram

Figure 18. ICACHE block diagram

Configuration

AHB
slave port

Configuration interface
Region 0 cfg Region 2 cfg Hit monitor Control

Region 1 cfg Region 3 cfg Miss monitor Status

Cortex_M33

Master1
port
Execution port interface

Cache control logic

Master ports interface

AHB
Execution

Main AHB
port Cache
C-AHB

FSM
AHB
Master2
port
pLRU-t REMAP
AHB
IT Icache

Cache memory port

Cache Cache
TAG data
memories memories
ICACHE n ways n ways
MSv48191V2

7.4.2 ICACHE reset and clocks

ICACHE is clocked on Cortex-M33 C-AHB bus clock.
When the ICACHE reset signal is released, a cache invalidate procedure is automatically
launched, making ICACHE busy (ICACHE_SR = 0x0000 0001).
When this procedure is finished:
• ICACHE is invalidated: “cold cache”, with all cache line valid bits = 0 (ICACHE must be
filled up)
• ICACHE_SR = 0x0000 0002 (reflecting the cache is no more busy)
• ICACHE is disabled: the EN bit in ICACHE_CR holds its reset state (=0).
Note: When disabled, ICACHE is bypassed, except the remapping mechanism that is still
functional: the slave input requests (remapped or not) are just forwarded to the master
port(s).

246/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

7.4.3 ICACHE TAG memory

The ICACHE TAG memory contains:
• address tags, that indicate which data are contained in the cache data memories
• validity bits
There is one valid bit per cache line (per way).
The valid bit is set when a cache line is refilled (after a miss).
Valid bits are reset in any of the below cases:
• after ICACHE reset is released
• when cache is disabled, by setting the EN bit low in the ICACHE_CR register (by
software)
• when executing ICACHE invalidate command, by setting the CACHEINV bit high in the
ICACHE_CR register (by software)
When a cacheable transaction is received at input execution port, its AHB address
(HADDR_in) is split into the following fields (see table below for definition of B and W):
• HADDR_in[B-1:0]: address byte offset, indicates which byte to select inside a cache
line.
• HADDR_in[B+W-1:B]: address way index, indicates which cache line to select inside
each way.
• HADDR_in[31:B+W]: tag address, to be compared to TAG memory address to check if
the requested data is already available (meaning valid) inside the ICACHE.
The table below gives a summary of ICACHE main parameters for TAG memory
dimensioning and Figure 19 shows the functional view of TAG and data memories, for a
n-way set associative ICACHE.

Table 53. TAG memory dimensioning parameters

for n-way set associative operating mode (default)
Parameter Value Example

Cache size S Kbytes = s bytes (s = 1024 x S) 8 Kbytes = 8192 bytes

Cache number of ways n 2
Cache line size L-byte = l-bit (l = 8 x L) 16-byte = 128-bit
Number of cache lines (per way) LpW = s / (n x L) lines / way 256 lines / way
Address byte offset size B = log2(L) bit 4-bit
Address way index size W = log2(LpW) bit 8-bit
TAG address size T = (32 - W - B) bit 20-bit

RM0438 Rev 7 247/2194

261
Instruction cache (ICACHE) RM0438

Figure 19. ICACHE TAG and data memories functional view

T-bit W-bit B-bit

AHB_address
(HADDR_in) TAG Index Offset

way selection
pLRU-t (for replacement)

Vn-1 TAG_Way(n-1) Data_Way(n-1)

V0 TAG_Way0 Data_Way0

LpW lines / way

LpW lines / way

TAG memory Data memory

n ways n ways
T-bit l-bit

==
== Cache hit/miss, in Way(n-1)
Cache hit/miss, in Way0
MSv48192V2

7.4.4 Direct mapped ICACHE (1-way cache)

Default configuration (at reset) is 2-way set associative cache (WAYSEL = 1 in
ICACHE_CR), but the user can configure ICACHE as direct mapped by writing
WAYSEL = 0 (only possible when cache is disabled, EN=0 in ICACHE_CR).
The table below gives a summary of ICACHE main parameters for TAG memory in case the
direct mapped cache operating mode is selected.

Table 54. TAG memory dimensioning parameters

for direct mapped cache mode
Parameter Value Example

Cache size S Kbytes = s bytes (s = 1024 x S) 8 Kbytes = 8192 bytes

Cache number of ways 1 1
Cache line size L-byte = l-bit (l = 8 x L) 16-byte=128-bit
Number of cache lines LpW = s / L lines 512 lines
Address byte offset size B = log2(L) bit 4-bit
Address way index size W = log2(LpW) bit 9-bit
TAG address size T = (32 - W - B) bit 19-bit

248/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

All cache operations (such as read, refill, remapping, invalidation) remain the same in direct
mapped configuration; the only difference is the absence of a replacement algorithm in case
of line eviction (as explained in Section 7.4.8), since only one way (the unique one) is
possible for any data refill.

7.4.5 ICACHE enable

In order to activate the ICACHE functioning, the EN bit must be set in the ICACHE_CR
register.
When ICACHE is disabled, it is bypassed and all transactions are copied from slave port to
master ports in the same clock cycle.
It is recommended to initialize or to modify the main memory content (the region to be later
cached) with ICACHE disabled, and to enable ICACHE only when this region remains
unchanged (an enabled ICACHE detects cacheable write transactions as errors).
In order to insure performance determinism, it is recommended to wait for the end of a
potential cache invalidate procedure before enabling the ICACHE. This invalidate procedure
occurs when hardware reset signal is released, when ICACHE_CR.CACHEINV is set or
when ICACHE_CR.EN is cleared. During the procedure, ICACHE_SR.BUSYF is set, and
once finished, ICACHE_SR.BUSYF is cleared and ICACHE_SR.BSYENDF is set (raising
the ICACHE interrupt if enabled on such a busy end condition).
Software must test BUSYF and/or BSYENDF values before enabling the ICACHE. Else, if
ICACHE is enabled before the end of an invalidate procedure, any cache access (while
BUSYF still at 1) is treated as non cacheable, and its performance depends on the main
memory access time.
The address remapping is performed, whether ICACHE is enabled or not, if input
transaction address falls into memory regions defined and enabled in ICACHE_CRRx (see
Figure 20).
ICACHE is by default disabled at boot.

7.4.6 Cacheable and non-cacheable traffic

ICACHE is developed for Cortex-M33 core. It is placed on C-AHB bus, and thus caches the
Code memory region, ranging from address 0x0000 0000 to 0x1FFF FFFF of the memory
map.
In order to make some other memory regions cacheable, ICACHE supports a memory
region remapping feature. It allows to define up to four external memory regions, which
addresses have an alias in the Code region. Addressing these external memory regions
through their Code alias address allows the memory request to be routed to the C-AHB bus
and to be managed by ICACHE.
Typically, any external memory space physically mapped at an address somewhere in
range [0x6000 0000:0x9FFF FFFF] can be aliased with an address in range
[0x0000 0000:0x07FF FFFF] or [0x1000 0000:0x1FFF FFFF].
For a given memory request in the Code region, ICACHE implements the address
remapping functionality first. If aliased, it is the remapped address which is then cached,
and, if needed, provided to the master port to address the main AHB busmatrix. The
destination physical address does not need further manipulation on the AHB bus.

RM0438 Rev 7 249/2194

261
Instruction cache (ICACHE) RM0438

The remapping functionality is available also for non-cacheable traffic and when cache is
disabled.
Further details on address remapping are provided in Section 7.4.7.
An incoming memory request to ICACHE is defined as cacheable according to its AHB
transaction memory lookup attribute, as shown in Table 55. This AHB attribute depends on
the MPU programming for the addressed region.

Table 55. ICACHE cacheability for AHB transaction

AHB Lookup attribute Cacheability

1 Cacheable
0 Non cacheable

In case of non cacheable access, ICACHE is bypassed, meaning that the AHB transaction
is propagated unchanged to the master output port, except the transaction address which
may be modified due to the address remapping feature (see Section 7.4.7).
The bypass, and eventual remap logic, does not increase the latency of the access to the
targeted memory.
In case of cacheable access, the ICACHE behaves as explained in Section 7.4.8.
Cacheable memory regions are defined and programmed by the user in the memory
protection unit (MPU), that is responsible for the generation of the AHB attribute signals for
any transaction addressing a given region.
Table 56 summarizes product memories programmable configurations.

Table 56. Configurations of product memories

Cacheable Remapped in ICACHE
Product memory
(MPU programming) (ICACHE_CRRx programming)

FLASH Yes or No Not required

SRAM Not recommended Not required
Yes Required
External memories Required if the user wants external
(OCTOSPI, FMC) No code fetching on C-AHB bus
(else on S-AHB bus)

7.4.7 Address remapping

ICACHE allows to define an alias address in Code region for up to four external memory
regions.
The address remapping is applied on the Code alias address, transforming it into the
destination external physical address.
The remapping operation is fully software configurable by programming ICACHE_CRRx
register (x = 0 to 3, number of remapped regions). This programming can be done only
when ICACHE is disabled.

250/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

Each region x can be individually enabled with the REN bit in ICACHE_CRRx. Once
enabled, the remap operation occurs even if ICACHE is disabled or if the transaction is not
cacheable.
Remap regions can have different size: each region size can be programmed in the RSIZE
field of its ICACHE_CRRx register. The size of each region is a power of two multiple of
range granularity (2 Mbytes), with a minimum region size of 2 Mbytes and a maximum
region size of 128 Mbytes.
The address remapping mechanism is based on the matching of an incoming AHB address
(HADDR_in) with a given Code sub-region base address, and the modification of this
address into its (remapped) external physical address, as follows:
• HADDR_in belongs to region x if HADDR_in[31:RI] = 000:BASEADDR[28:RI], where:
– 000:BASEADDR is the code sub-region base address programmed in the
BASEADDR field of ICACHE_CRRx.
– RI defines the number of significant bits to consider. RI = log2(region size) with a
minimum value of 21 (for a 2-Mbyte region) and a maximum value of 27
(for a 128-Mbyte region)
• If region x is enabled, the master port output AHB address (HADDR_out) is then
composed by concatenating the two below parts:
– REMAPADDR[31:RI] field of ICACHE_CRRx as MSBs
– HADDR_in[RI-1:0] as LSBs.
The figure below describes the matching and the output address generation.

Figure 20. ICACHE remapping address mechanism

31 RI RI-1 0
HADDR_in

REMAPADDR[31:RI]

Address in region x
000:BASEADDR[28:RI] == 0 1

31 RI RI-1 0
HADDR_out HADDR_in[RI-1:0]

MSv48194V2

The table below summarizes all possible configurations of BASEADDR and REMAPADDR
sizes (number of significant MSBs) in ICACHE_CRRx, depending on RSIZE.

Table 57. ICACHE remap region size, base address and remap address
Region size (Mbytes) Base address size (MSBs) Remap address (MSBs)

2 8 11
4 7 10
8 6 9
16 5 8
32 4 7

RM0438 Rev 7 251/2194

261
Instruction cache (ICACHE) RM0438

Table 57. ICACHE remap region size, base address and remap address (continued)
Region size (Mbytes) Base address size (MSBs) Remap address (MSBs)

64 3 6
128 2 5

Care must be taken while programming BASEADDR and REMAPADDR fields in

ICACHE_CRRx: if programmed value is bigger than expected (in terms of number of MSBs,
see Table 57), the unnecessary extra LSBs are ignored.
Typical remapping example: a 128-Mbyte FMC region (NOR/SRAM) physically located in
the external address range [0x6800 0000:0x6FFF FFFF], remapped in Code section range
[0x1000 0000:0x17FF FFFF]:
• REMAPADDR[31:21] = 0x340
• BASEADDR[28:21] = 0x80
• HADDR_in[31:27] is compared to 000:BASEADDR[28:27], and
HADDR_in/BASEADDR[26:21] are ignored for the comparison.
If the comparison matches:
• HADDR_out[31:27] gets REMAPADDR[31:27] (in place of HADDR_in[31:27])
• HADDR_out[26:0] gets HADDR_in[26:0]
The software can program the kind of AHB burst that is generated by ICACHE master ports
on busmatrix (for cache line refill), by setting the HBURST bit in ICACHE_CRRx with:
• WRAP for remapped external memories accessed through OCTOSPI interface that
can support WRAP burst mode, providing the benefit of the critical-word-first feature
performance:
– WRAP burst size = cache line size
– WRAP burst start address = word address of the first data requested by the core
• INCR: INCR burst mode for external memories accessed through FMC interface that
does not support WRAP burst mode (losing the benefit of critical-word-first feature):
– INCR burst size = cache line size
– INCR burst start address = address aligned on the boundary of the cache line
containing the requested word.
Note: Coherency is needed when programming SAU (secure attribution unit) and MPU (memory
protection unit) attributes for both the external regions and their aliased Code sub-regions.

7.4.8 Cacheable accesses

When ICACHE receives a cacheable transaction from Cortex-M33, ICACHE checks if the
address requested is present in its TAG memory and if the corresponding cache line is
valid.

252/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

There are then three alternatives:

• Address is present inside the TAG memory, cache line is valid: cache hit, the data is
read from cache and provided to the processor in the same cycle.
• Address is not present in the TAG memory: cache miss, the data is read from main
memory and provided to the processor, and a cache line refill is performed.
The critical-word-first policy insures minimum wait cycles for the processor, since read
data can be provided while cache is still performing cache line refill (associated latency
is the latency of fetching one word from main memory).
In case no address remap occurs, the burst generated on ICACHE master bus is
WRAPw (w being the cache line width, in words); if an address remap occurs, the kind
of burst depends on the HBURST bit programmed in the corresponding
ICACHE_CRRx register.
The AHB transaction attributes are also propagated to main AHB busmatrix on the
master port selected for the line refill.
• Address is not present in TAG memory but belongs to the refill burst from main memory
that is currently ongoing: cache hit (hit-under-miss feature).
This happens during cache line refill, ICACHE is capable of providing the requested
data as soon as the data is available at its master interface, thus avoiding a miss
(fetching data from main memory).
In case of cache refill (due to cache miss), ICACHE selects which cache line is written with
the refill data:
• In direct map (1-way) mode, only one line can be used to store the refill data, the line
pointed by the index of the input address.
• In n-way set associative mode, one line among 2 can be used (the line pointed by the
address index, in each of the 2 ways). The way selection is based on a pLRU-t
replacement algorithm. This algorithm points, for each index, on the way candidate for
the next refill.
If ever the cache line where the refill data must be written, is already valid, the targeted
cache line must be invalidated first; this is true whatever the direct map or n-way set
associative cache mode.

7.4.9 Dual master cache

ICACHE can implement a dual port AHB master on main AHB busmatrix: master1 and
master2 ports. This allows to split the traffic going to different destination memories.
The non-remapped traffic goes systematically to master1 port. The re-mapped traffic to
external memories must be routed on master2 port by programming the MSTSEL bit of
ICACHE_CRRx (on a region basis).
Typically, code can be fetched as follows:
• internal FLASH memory and internal SRAM on master1 port (Fast bus)
• external FLASH/RAM (through OCTOSPI/FMC interfaces) on master2 port (Slow bus)
For systems not implementing external memories, it is also possible to decouple the traffic
to the internal FLASH memory from the traffic to the internal SRAM (when remapped by the
ICACHE). This feature allows to prevent further processor stalls on misses.
Alongside with hit-under-miss, this dual master feature allows the processor to have an
alternative path in case of fetching from different memories.

RM0438 Rev 7 253/2194

261
Instruction cache (ICACHE) RM0438

7.4.10 ICACHE security

ICACHE implements a v8-M TrustZone as defined by Arm.
ICACHE configuration registers are protected at system level.

7.4.11 ICACHE maintenance

The software can invalidate the whole content of the ICACHE by programming the
CACHEINV bit in the ICACHE_CR register.
When CACHEINV is set, the ICACHE control logic sets the BUSYF flag in ICACHE_SR and
launches the invalidate cache operation, reseting each TAG valid bit to 0 (one valid bit per
cache line). The CACHEINV bit of ICACHE_CR is also automatically cleared.
Once the invalidate operation is finished, ICACHE automatically clears the BUSYF flag and
sets the BSYENDF flag in the ICACHE_SR register.
If enabled on this flag condition (BSYENDIE = 1 in ICACHE_IER), the ICACHE interrupt is
raised.
Then, the (empty) cache is available again.

7.4.12 ICACHE performance monitoring

ICACHE provides two monitors for performance analysis: a 32-bit hit monitor and a 16-bit
miss monitor.
• The hit monitor counts the AHB-transactions at the input of ICACHE (execution port)
that do not generate a transaction on ICACHE output (master1 or master2 port).
It also takes into account all accesses whose address is present in the TAG memory or
in the refill buffer (due to a previous miss, and whose data is coming, or is soon to
come, from cache master port) (see Section 7.4.8)
• The miss monitor counts the AHB-transactions at the input of the ICACHE (execution
port) that generate a transaction on ICACHE output (master1 or master2 port).
It also takes into account all accesses whose address is not present neither in the TAG
memory nor in the refill buffer.
Upon reaching their maximum values, monitors do not wrap over.
Hit and miss monitors can be enabled and reset by software allowing the analysis of specific
pieces of code.
The software can perform the following tasks:
• Enable/stop the hit monitor through the HITMEN bit in ICACHE_CR.
• Reset the hit monitor by setting the HITMRST bit in ICACHE_CR.
• Enable/stop the miss monitor through the MISSMEN bit in ICACHE_CR.
• Reset the miss monitor by setting the MISSMRST bit in ICACHE_CR.
To reduce power consumption, these monitors are disabled (stopped) by default.

7.4.13 ICACHE Boot

ICACHE is disabled (EN = 0 in ICACHE_CR) at Boot.
Code remapping at Boot is not needed for Cortex®-M33 since it implements the VTOR
(vector tables) that allows a boot start address definition different than 0x0.

254/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

Once Boot is finished, ICACHE can be enabled (software setting the EN bit to 1 in
ICACHE_CR).

7.5 ICACHE low-power modes

At product level, using ICACHE reduces the power consumption by fetching instructions
from the internal ICACHE most of the time, rather than from the bigger and then more power
consuming main memories. This reduction is even higher if the cached main memories are
external.
Applications with a lower-performance profile (in terms of hit ratio) and stringent low-power
consumption constraints, may benefit from the lower power consumption of an ICACHE
configured as direct mapped. This single way cache configuration is obtained by
programming WAYSEL = 0 in ICACHE_CR (see Figure 19). The power consumption is then
reduced by accessing, for each request, only the necessary cut of TAG and data memories.
Meanwhile, the cache effect still improves fetch performance; even if for most codes
execution, it is a little less efficient than with an n-way set associative cache mode.

7.6 ICACHE error management and interrupts

In case an unsupported cacheable write request is detected (functional error), ICACHE
generates an error by setting the ERRF flag in ICACHE_SR. In such a case, an interrupt is
generated if the corresponding interrupt enable bit is set (ERRIE = 1 in ICACHE_IER).
The other possible interrupt generation is at the end of a cache invalidation operation. When
the cache-busy state is finished, ICACHE sets the BSYENDF flag in ICACHE_SR. An
interrupt is then generated if the corresponding interrupt enable bit is set (BSYENDIE = 1 in
ICACHE_IER).
Both interrupts use the same ICACHE interrupt vector.

Table 58. ICACHE interrupts

Interrupt
Interrupt event Event flag Enable control bit Interrupt clear method
vector

ERRF flag in ERRIE bit in Set CERRF bit to 1 in

Functional error
ICACHE_SR ICACHE_IER ICACHE_FCR
ICACHE
End of busy state BSYENDF flag in BSYENDIE bit in Set CBSYENDF bit to 1 in
(invalidate finished) ICACHE_SR ICACHE_IER ICACHE_FCR

ICACHE also propagates all AHB bus errors (such as security issues, address decoding
issues) from master1 or master2 port back to the execution port.

RM0438 Rev 7 255/2194

261
Instruction cache (ICACHE) RM0438

7.7 ICACHE registers

7.7.1 ICACHE control register (ICACHE_CR)

Address offset: 0x000
Reset value: 0x0000 0004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MISSMRST

MISSMEN
HITMRST

HITMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CACHEINV
WAYSEL

EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw w rw

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 MISSMRST: miss monitor reset
0: no effect
1: reset cache miss monitor
Bit 18 HITMRST: hit monitor reset
0: no effect
1: reset cache hit monitor
Bit 17 MISSMEN: miss monitor enable
0: cache miss monitor switched off. Stopping the monitor does not reset it.
1: cache miss monitor enabled
Bit 16 HITMEN: hit monitor enable
0: cache hit monitor switched off. Stopping the monitor does not reset it.
1: cache hit monitor enabled
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 WAYSEL: cache associativity mode selection
This bit allows user to choose ICACHE set-associativity. It can be written by software only when
cache is disabled (EN = 0).
0: direct mapped cache (1-way cache)
1: n-way set associative cache (reset value)
Bit 1 CACHEINV: cache invalidation
Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance
operation). Writing 0 has no effect.
0: no effect
1: invalidate entire cache (all cache lines valid bit = 0)
Bit 0 EN: enable
0: cache disabled
1: cache enabled

256/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

7.7.2 ICACHE status register (ICACHE_SR)

Address offset: 0x004
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BSYENDF

BUSYF
ERRF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 ERRF: cache error flag
0: no error
1: an error occurred during the operation (cacheable write)
Bit 1 BSYENDF: busy end flag
0: cache busy
1: full invalidate CACHEINV operation finished
Bit 0 BUSYF: busy flag
0: cache not busy on a CACHEINV operation
1: cache executing a full invalidate CACHEINV operation

7.7.3 ICACHE interrupt enable register (ICACHE_IER)

Address offset: 0x008
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSYENDIE
ERRIE

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

RM0438 Rev 7 257/2194

261
Instruction cache (ICACHE) RM0438

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 ERRIE: interrupt enable on cache error
Set by software to enable an interrupt generation in case of cache functional error (cacheable write
access)
0: interrupt disabled on error
1: interrupt enabled on error
Bit 1 BSYENDIE: interrupt enable on busy end
Set by software to enable an interrupt generation at the end of a cache invalidate operation.
0: interrupt disabled on busy end
1: interrupt enabled on busy end
Bit 0 Reserved, must be kept at reset value.

7.7.4 ICACHE flag clear register (ICACHE_FCR)

Address offset: 0x00C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CBSYENDF
CERRF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

w w

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 CERRF: clear cache error flag
Set by software.
0: no effect
1: clears ERRF flag in ICACHE_SR
Bit 1 CBSYENDF: clear busy end flag
Set by software.
0: no effect
1: clears BSYENDF flag in ICACHE_SR.
Bit 0 Reserved, must be kept at reset value.

258/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

7.7.5 ICACHE hit monitor register (ICACHE_HMONR)

Address offset: 0x010
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HITMON[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HITMON[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 HITMON[31:0]: cache hit monitor counter

7.7.6 ICACHE miss monitor register (ICACHE_MMONR)

Address offset: 0x014
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MISSMON[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 MISSMON[15:0]: cache miss monitor counter

7.7.7 ICACHE region x configuration register (ICACHE_CRRx)

Address offset: 0x020 + 4 * x, (x = 0 to 3)
Reset value: 0x0000 0200
Define a Code alias address for external regions, making them cacheable. BASEDADDR
and REMAPADDR fields are write locked (read only) when ICACHE_CR.EN is high.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HBURST

MSTSEL

Res. Res. Res. REMAPADDR[31:21]

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REN Res. Res. Res. RSIZE[2:0] Res. BASEADDR[28:21]
rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 259/2194

261
Instruction cache (ICACHE) RM0438

Bit 31 HBURST: output burst type for region x

0: WRAP
1: INCR
Bits 30:29 Reserved, must be kept at reset value.
Bit 28 MSTSEL: AHB cache master selection for region x
0: no action (master1 selected by default)
1: master2 selected
Bit 27 Reserved, must be kept at reset value.
Bits 26:16 REMAPADDR[31:21]: remapped address for region x
This field replaces the alias address defined by BASEADDR field.
The only useful bits are [31:RI], where 21 ≤ RI ≤ 27 is the number of bits of RSIZE (see
Section 7.4.7). If the programmed value has more LSBs, the useless bits are ignored.
Bit 15 REN: enable for region x
0: disabled
1: enabled
Bits 14:12 Reserved, must be kept at reset value.
Bits 11:9 RSIZE[2:0]: size for region x
000: reserved
001: 2 Mbytes
010: 4 Mbytes
011: 8 Mbytes
100: 16 Mbytes
101: 32 Mbytes
110: 64 Mbytes
111: 128 Mbytes
Bit 8 Reserved, must be kept at reset value.
Bits 7:0 BASEADDR[28:21]: base address for region x
This alias address is replaced by REMAPADDR field.
The only useful bits are [28:RI], where 21 ≤ RI ≤ 27 is the number of bits of RSIZE (see
Section 7.4.7). If the programmed value has more LSBs, the useless bits are ignored.

7.7.8 ICACHE register map

Table 59. ICACHE register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
MISSMRST

CACHEINV
MISSMEN
HITMRST

WAYSEL
HITMEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ICACHE_CR
EN

0x000

Reset value 0 0 0 0 1 0 0
BSYENDF
BUSYF
ERRF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ICACHE_SR
0x004

Reset value 0 0 1

260/2194 RM0438 Rev 7

RM0438 Instruction cache (ICACHE)

Table 59. ICACHE register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
BSYENDIE
ERRIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
ICACHE_IER
0x008

Reset value 0 0

CBSYENDF
CERRF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
ICACHE_FCR
0x00C

Reset value 0 0
ICACHE_
HITMON[31:0]
0x010 HMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ICACHE_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MISSMON[15:0]
0x014 MMONR
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x018 to
Reserved Reserved
0x01C

RSIZE[2:0]
HBURST

MSTSEL

REN
Res.
Res.

Res.
Res.

Res.
Res.
Res.

Res.
Res.
ICACHE_CRR0 REMAPADDR[31:21] BASEADDR[28:21]
0x020

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

RSIZE[2:0]
HBURST

MSTSEL

REN
Res.
Res.

Res.
Res.

Res.
Res.
Res.

Res.
Res.
ICACHE_CRR1 REMAPADDR[31:21] BASEADDR[28:21]
0x024

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RSIZE[2:0]
HBURST

MSTSEL

REN
Res.
Res.

Res.
Res.

Res.
Res.
Res.

Res.
ICACHE_CRR2 REMAPADDR[31:21] Res. BASEADDR[28:21]
0x028

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RSIZE[2:0]
HBURST

MSTSEL

REN
Res.
Res.

Res.
Res.

Res.
Res.
Res.

Res.
Res.

ICACHE_CRR3 REMAPADDR[31:21] BASEADDR[28:21]

0x02C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

RM0438 Rev 7 261/2194

261
Power control (PWR) RM0438

8 Power control (PWR)

The power controller (PWR) main features are:

• Power supplies and supply domains
– Core domains (VCORE)
– VDD domain
– Backup domain (VBAT)
– Analog domain (VDDA)
– Supply for the SMPS power stage (available on SMPS packages)
– VDDIO2 domain on Port G
– VDDUSB for USB transceiver
• System supply voltage regulation
– SMPS step down converter
– Voltage regulator (LDO)
– External SMPS mode
• Power supply supervision
– POR/PDR monitor
– BOR monitor
– PVD monitor
– PVM monitor (VDDA, VDDUSB, VDDIO2)
– Temperature threshold monitor
– Upper VDD voltage threshold monitor
• Power management
– Operating modes
– Voltage scaling control
– Low-power modes
• VBAT battery charging
• TrustZone security

8.1 Power supplies and supply domains

The STM32L552xx and STM32L562xx devices require a 1.71 V to 3.6 V operating supply
voltage (VDD). Several peripherals are supplied through independent power domains: VDDA,
VDDIO2, VDDUSB. Those supplies must not be provided without a valid operating supply on
the VDD pin.
• VDD = 1.71 V to 3.6 V
VDD is the external power supply for the I/Os, the internal regulator (or the SMPS step
down converter depending on the device) and the system analog such as reset, power
management and internal clocks. It is provided externally through VDD pins.
• VDDA = 1.62 V (ADCs/COMPs) / 1.8 V (DACs/OPAMPs) / 2.4 V (VREFBUF) to 3.6 V
VDDA is the external analog power supply for A/D converters, D/A converters, voltage
reference buffer, operational amplifiers and comparators. The VDDA voltage level is
independent from the VDD voltage. VDDA should be preferably connected to VDD when

262/2194 RM0438 Rev 7

RM0438 Power control (PWR)

these peripherals are not used.

• VDDSMPS = 2 V to 3.6 V
VDDSMPS is the external power supply for the SMPS step down converter. It is
provided externally through VDDSMPS supply pin, and shall be connected to the same
supply as VDD.
• VLXSMPS is the switched SMPS step down converter output.
• V15SMPS are the power supply for the system regulator. It is provided externally through
the SMPS step down converter VLXSMPS output.
Note: The SMPS power supply pins are available only on a specific package with SMPS step
down converter option.
• VDD12 = 1.05 to 1.32 V
VDD12 is the external power supply bypassing the internal regulator when connected
to an external SMPS. It is provided externally through VDD12 pins and only available
on packages with the external SMPS supply option. VDD12 does not require any
external decoupling capacitance and cannot support any external load.
Note: The VDD12 power supply pins are available only on a specific package with external SMPS
option.
• VDDUSB = 3.0 V to 3.6 V
VDDUSB is the external independent power supply for USB transceivers. The VDDUSB
voltage level is independent from the VDD voltage. VDDUSB should be preferably
connected to VDD when the USB is not used.
The VDDUSB power supply may not be present as a dedicated pin, but to be internally
bonded to VDD. For such devices, VDD has to respect the VDDUSB supply range when
the USB is used.
• VDDIO2 = 1.08 V to 3.6 V
VDDIO2 is the external power supply for 14 I/Os (Port G[15:2]). The VDDIO2 voltage level
is independent from the VDD voltage and should preferably be connected to VDD when
PG[15:2] are not used.
• VBAT = 1.55 V to 3.6 V
VBAT is the power supply for RTC, external clock 32 kHz oscillator and backup registers
(through power switch) when VDD is not present. VBAT is internally bonded to VDD for
small packages without dedicated pin.
• VREF-, VREF+
VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the
internal voltage reference buffer when enabled.
When VDDA < 2 V, VREF+ must be equal to VDDA.
When VDDA > 2 V, VREF+ must be between 2 V and VDDA.
VREF+ can be grounded when ADC and DAC are not active.
The internal voltage reference buffer supports two output voltages, which are
configured with VRS bit in the VREFBUF_CSR register:
– VREF+ around 2.048 V. This requires VDDA equal to or higher than 2.4 V.
– VREF+ around 2.5 V. This requires VDDA equal to or higher than 2.8 V.
On some packages, VREF- and VREF+ pins are not available. When not available on
the package, they are internally bonded to respectively VSSA and VDDA.

RM0438 Rev 7 263/2194

326
Power control (PWR) RM0438

When the VREF+ is double-bonded with VDDA in a package, the internal voltage
reference buffer is not available and must be kept disable (refer to related device
datasheet for packages pinout description).
VREF- must always be equal to VSSA.
In the STM32L552xx and STM32L562xx devices, the I/Os, the embedded LDO regulator
and the system analog peripherals (such as PLLs and reset block) are fed by VDD supply
source. The embedded linear voltage regulator is used to supply the internal digital power
VCORE. VCORE is the power supply for digital peripherals and memories.

Figure 21. STM32L552xx and STM32L562xx power supply overview

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring

Reset block
Temp. sensor
VCORE domain
3 x PLL, HSI, MSI
VCORE domain
Standby circuitry Core
VSS (Wakeup logic,
IWDG) SRAM1
VDD SRAM2
VCORE (1)

MR Digital
peripherals
SPMS LPR

Flash memory

Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

unused block
MSv49301V2

1. VCORE is provided by either MR or LPR, depending on the operating power mode.

264/2194 RM0438 Rev 7

RM0438 Power control (PWR)

In the STM32L552xxxP and STM32L562xxxP devices, the I/Os and system analog
peripherals (such as PLLs, and reset block) are fed by VDD supply source. The VCORE,
power supply for digital peripherals and memories is generated from external SMPS.

Figure 22. STM32L552xxxP and STM32L562xxxP power supply overview

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring

Reset block
Temp. sensor
3 x PLL, HSI, MSI VCORE domain
Standby circuitry
VSS (Wakeup logic, Core
IWDG)
VDD SRAM1
VCORE SRAM2
MR
Digital
peripherals
SMPS LPR

2x VDD12(1)(2) Flash memory

Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

unused blocks
MSv49336V2

1. If the selected package has the external SMPS option but no external SMPS is used by the application (the
embedded LDO is used instead), the VDD12 pins are kept unconnected.
2. VDD12 is intended to be connected with external SMPS (switched-mode power supply) to generate the
VCORE logic supply in Run, Sleep and Stop 0 modes only.

RM0438 Rev 7 265/2194

326
Power control (PWR) RM0438

In the STM32L552xxxQ and STM32L562xxxQ devices, the I/Os, the embedded SMPS step
down converter and the system analog peripherals (such as PLLs and reset block) are fed
by VDD supply source. The embedded linear main voltage regulator that provides the VCORE
supply for digital peripherals and memories is fed by the SMSP step down converter output.

Figure 23. STM32L552xxxQ and STM32L562xxxQ power supply overview

VDDA domain
2 x A/D converters
VDDA 2 x comparators
2 x D/A converters
VSSA 2 x operational amplifiers
Voltage reference buffer

VDDUSB
USB transceivers
VSS
VDDIO2 domain
VDDIO2 VDDIO2
I/O ring
VSS

VDD domain
VDDIO1 I/O ring

Reset block
Temp. sensor
3 x PLL, HSI, MSI
VCORE domain
VCORE domain
Standby circuitry Core
VSS (Wakeup logic,
IWDG) SRAM1
VDD SRAM2
VCORE
2 x V15SMPS MR Digital
VLXSMPS peripherals
VDDSMPS SMPS
(1)(2) LPR
VSSSMPS
Flash memory
Low voltage detector

Backup domain
LSE crystal 32 K osc
VBAT
BKP registers
RCC BDCR register
RTC

MSv49332V2

1. Refer to Figure 24 for SMPS step down converter power supply scheme.
2. During Low-power sleep, Low-power run, Stop 1, Stop 2, Standby and Shutdown modes, the SMPS step
down converter is switched to Open mode. In Low-power sleep, Low-power run, Stop 1, Stop 2 and
Standby with SRAM2 retention modes, the low-power regulator is used to provide the VCORE.
The SMPS is used in Run, Sleep and Stop 0 modes. It supplies the main regulator which provides the
VCORE.
Note: If the selected package has the SMPS step down converter option but the SMPS is not used
by the application (and the embedded LDO is used instead), it is recommended to set the
SMPS power supply pins as follows:
- VDDSMPS and VLXSMPS connected to VSS
- V15SMPSconnected to VDD.

266/2194 RM0438 Rev 7

RM0438 Power control (PWR)

8.1.1 Independent analog peripherals supply

To improve ADC and DAC conversion accuracy and to extend the supply flexibility, the
analog peripherals have an independent power supply which can be separately filtered and
shielded from noise on the PCB.
• The analog peripherals voltage supply input is available on a separate VDDA pin.
• An isolated supply ground connection is provided on VSSA pin.
The VDDA supply voltage can be different from VDD. The presence of VDDA must be checked
before enabling any of the analog peripherals supplied by VDDA (A/D converter, D/A
converter, comparators, operational amplifiers, voltage reference buffer).
The VDDA supply can be monitored by the peripheral voltage monitoring (PVM), and
compared with two thresholds (1.65 V for PVM3 or 1.8 V for PVM4), refer to Section 8.3.3:
Peripheral voltage monitoring (PVM) for more details.
When a single supply is used, VDDA can be externally connected to VDD through the
external filtering circuit in order to ensure a noise-free VDDA reference voltage.

ADC and DAC reference voltage

To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to
VREF+ a separate reference voltage lower than VDDA. VREF+ is the highest voltage,
represented by the full scale value, for an analog input (ADC) or output (DAC) signal.
VREF+ can be provided either by an external reference of by an internal buffered voltage
reference (VREFBUF).
The internal voltage reference is enabled by setting the ENVR bit in the Section 23.4.1:
VREFBUF control and status register (VREFBUF_CSR). The voltage reference is set to
2.5 V when the VRS bit is set and to 2.048 V when the VRS bit is cleared. The internal
voltage reference can also provide the voltage to external components through VREF+ pin.
Refer to the device datasheet and to Section 23: Voltage reference buffer (VREFBUF) for
further information.

8.1.2 Independent I/O supply rail

Some I/Os from port G (PG[15:2]) are supplied from a separate supply rail. The power
supply for this rail can range from 1.08 V to 3.6 V and is provided externally through the
VDDIO2 pin. The VDDIO2 voltage level is completely independent from VDD or VDDA. The
VDDIO2 pin is available only for some packages. Refer to the pinout diagrams or tables in the
related device datasheet(s) for I/O list(s).
After reset, the I/Os supplied by VDDIO2 are logically and electrically isolated and therefore
are not available. The isolation must be removed before using any I/O from PG[15:2], by
setting the IOSV bit in the PWR_CR2 register, once the VDDIO2 supply is present.
The VDDIO2 supply is monitored by the peripheral voltage monitoring (PVM2) and compared
with the internal reference voltage (3/4 VREFINT, around 0.9V), refer to Section 8.3.3:
Peripheral voltage monitoring (PVM) for more details.

8.1.3 Independent USB transceivers supply

The USB transceivers are supplied from a separate VDDUSB power supply pin. VDDUSB
range is from 3.0 V to 3.6 V and is completely independent from VDD or VDDA.

RM0438 Rev 7 267/2194

326
Power control (PWR) RM0438

After reset, the USB features supplied by VDDUSB are logically and electrically isolated and
therefore are not available. The isolation must be removed before using the USB peripheral,
by setting the USV bit in the PWR_CR2 register, once the VDDUSB supply is present.
The VDDUSB supply is monitored by the peripheral voltage monitoring (PVM1) and
compared with the internal reference voltage (VREFINT, around 1.2 V), refer to Section 8.3.3:
Peripheral voltage monitoring (PVM) for more details.

8.1.4 Battery backup domain

To retain the content of the backup registers and supply the RTC function when VDD is
turned off, the VBAT pin can be connected to an optional backup voltage supplied by a
battery or by another source.
The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to PC15 I/Os, allowing
the RTC to operate even when the main power supply is turned off. The switch to the VBAT
supply is controlled by the power-down reset embedded in the Reset block.

Warning: During tRSTTEMPO (temporization at VDD startup) or after a PDR

has been detected, the power switch between VBAT and VDD
remains connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
connect an external low-drop diode between this power
supply and the VBAT pin.

If no external battery is used in the application, it is recommended to connect VBAT

externally to VDD with a 100 nF external ceramic decoupling capacitor.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following pins are available:
• PC13, PC14 and PC15, which can be used as GPIO pins
• PC13, PC14 and PC15, which can be configured by RTC or LSE (refer to Section 41.3:
RTC functional description on page 1402)
• PA0/TAMP_IN2/TAMP_OUT1 and PE6/TAMP_IN3/TAMP_OUT6 when they are
configured by the tamper as tamper pins
Note: Due to the fact that the analog switch can transfer only a limited amount of current (3 mA),
the use of GPIO PC13 to PC15 in Output mode is restricted: the speed has to be limited to
2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source
(for example to drive a LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
• PC13, PC14 and PC15 can be controlled only by RTC or LSE (refer to Section 41.3:

268/2194 RM0438 Rev 7

RM0438 Power control (PWR)

RTC functional description)

• PA0/TAMP_IN2 and PE6/TAMP_IN3 when they are configured by the tamper as
tamper pins

Backup domain access

After a system reset, the backup domain (RTC registers and backup registers) is protected
against possible unwanted write accesses. To enable access to the backup domain,
proceed as follows:
1. Enable the power interface clock by setting the PWREN bits in the Section 9.8.13: RCC
APB1 peripheral reset register 1 (RCC_APB1RSTR1)
2. Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the
backup domain
3. Select the RTC clock source in the RCC Backup domain control register (RCC_BDCR).
4. Enable the RTC clock by setting the RTCEN [15] bit in the RCC Backup domain control
register (RCC_BDCR).

VBAT battery charging

When VDD is present, It is possible to charge the external battery on VBAT through an
internal resistance.
The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 kOhm resistor
depending on the VBRS bit value in the PWR_CR4 register.
The battery charging is enabled by setting VBE bit in the PWR_CR4 register. It is
automatically disabled in VBAT mode.

8.2 System supply voltage regulation

8.2.1 Voltage regulator

Two embedded linear voltage regulators supply all the digital circuitries, except for the
Standby circuitry and the backup domain. The main regulator output voltage (VCORE) can be
programmed by software to three different power ranges (Range 0, Range 1 and Range 2)
in order to optimize the consumption depending on the system’s maximum operating
frequency (refer to Section 9.3.10: Clock source frequency versus voltage scaling and to
Section 6.3.3: Read access latency).
At power-on reset or a system reset, the main regulator voltage Range 2 is selected by
default.
The voltage regulators are always enabled after a reset. Depending on the application
modes, the VCORE supply is provided either by the main regulator (MR) or by the low-power
regulator (LPR).
• In Run, Sleep and Stop 0 modes, both regulators are enabled and the main regulator
(MR) supplies full power to the VCORE domain (core, memories and digital peripherals).
• In Low-power run and Low-power sleep modes, the main regulator is off and the low-
power regulator (LPR) supplies low power to the VCORE domain, preserving the
contents of the registers, SRAM1 and SRAM2.
• In Stop 1 and Stop 2 modes, the main regulator is off and the low-power regulator
(LPR) supplies low-power to the VCORE domain, preserving the contents of the

RM0438 Rev 7 269/2194

326
Power control (PWR) RM0438

registers, SRAM1and SRAM2.

• In Standby mode, the SRAM2 content can be fully or partially (only 4 Kbytes)
preserved (depending on RRS[1:0] bits in the PWR_CR3 register), the main regulator
(MR) is off and the low-power regulator (LPR) provides the supply to SRAM2 only. The
core, digital peripherals (except Standby circuitry and backup domain) and SRAM1 are
powered off.
• In Standby mode, both regulators are powered off. The contents of the registers,
SRAM1 and SRAM2 is lost except for the Standby circuitry and the backup domain.
• In Shutdown mode, both regulators are powered off. When exiting from Shutdown
mode, a power-on reset is generated. Consequently, the contents of the registers, all
SRAMs is lost, except for the backup domain.

8.2.2 Embedded SMPS step down converter

The built-in SMPS step down converter is a power-efficient DC/DC non-linear switching
regulator that improves low-power performance when the VDD voltage is high enough. The
SMPS step down converter automatically enters in Bypass mode when the VDD voltage falls
below a VDD minimum value following the selected voltage range and switched back to the
selected operating mode when VDD rises above the minimum value.
When the SMPS step down converter is enabled, it can be configured in:
• High-power mode (HPM): achieving a high efficiency at high current load.
SMPS high-power mode is used in all ranges (0, 1 and 2).
It is the default selected mode after POR reset.
• Low-power mode (LPM): achieving a high efficiency at low current load.
When enabled, the voltage scaling must not be modified. This mode shall be only
selected in Range 2 and when power consumption does not exceed 30 mA.
• Bypass mode:
When the Bypass mode is enabled, the SMPS step down converter is switched OFF
and it is possible to change the voltage scaling. This mode can be forced by software
by setting the SMPSBYP bit in PWR_CR4 register. The Bypass mode can be enabled
or disabled on the fly at any time by the application software whatever the selected
operation mode.
In Range 0 and Range 1, the SMPS Bypass mode is selected automatically when VDD
drops below 2.05 V.
In Range 2, if VDD is less than 2.05 V, the SMPS Bypass mode must be forced by
software. For this purpose, the PVD0 should monitor the VDD power supply and the
software must force bypass mode by setting the SMPSBYP bit in PWR_CR4 register.

The following table summarizes the SMPS behavior depending on the main regulator
range, VDD and consumption.

270/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Table 60. SMPS modes summary

SMPS mode
Ranges Max AHB clock VCORE
VDD ≤ 2.05 V VDD > 2.05 V

HP mode
Automatic Bypass mode
Range 0 110 MHz 1.28 V Max current consumption = 120 mA
V15SMPS = VDD
V15SMPS = 1.6 V
HP mode
Automatic Bypass mode
Range 1 80 MHz 1.2 V Max current consumption = 80 mA
V15SMPS = VDD
V15SMPS = 1.5 V
Software Bypass LP mode or HP mode
Range 2 26 MHz 1.0 V mode(1) Max current consumption = 30 mA
V15SMPS = VDD V15SMPS = 1.3 V
1. There is no automatic SMPS bypass in Range 2. The user application should use PVD0 to monitor VDD supply and request
the SMPS Bypass mode.

Refer to Table 61 for SMPS step down converter operating mode.

Table 61. SMPS step down converter operating mode

SMPSBYP bit SMPSLPEN bit SMPSHPRDY flag Description

0 0 1 High-power mode
0 1 0 Low-power mode
1 x x Bypass mode

The sequence to go from Low-power to High-power mode is:

1. Clearing the SMPSLPEN bit in the PWR_CR4 register
2. Check that the SMPSHPRDY flag is set in PWR_SR1 register
The sequence to go from High-power to Low-power mode is:
1. Configure the system frequency and voltage scaling
2. Set the SMPSLPEN bit in the PWR_CR4 register
Note: If the Bypass mode is active and the SMPSLPEN bit is set, the switch to SMPS Low-power
mode is delayed until the SMPS step down converter exits the Bypass mode.
Note: The SMPS step down converter operating mode and Voltage scaling range selection shall
be changed only in RUN mode.

8.2.3 SMPS step down converter power supply scheme

The SMPS step down converter requires an external coil with typical value of 4.7 µH to be
connected between the dedicated VLXSMPS pin to VSSSMPS via a capacitor of 4.7µF. It is
switched OFF when:
• LPREG is used
or
• SMPS is configured in Bypass mode by software in RUN/SLEEP modes (SMPSBYP
bit set in PWR_CR4).

RM0438 Rev 7 271/2194

326
Power control (PWR) RM0438

Thus, only main regulator is used by the application.

Refer to Figure 24 below.

Figure 24. SMPS step down converter power supply scheme

VDD VDDSMPS
VLXSMPS SMPS
Step Down
Converter
V15SMPS
V15SMPS VCORE
Main
VSSSMPS VDD regulator
VSS

MSv49346V1

If the selected package is with the SMPS step down converter option but it is never used by
the application, it is recommended to set the SMPS power supply pins as follows:
• VDDSMPS and VLXSMPS connected to VSS
• V15SMPSconnected to VDD

8.2.4 SMPS step down converter versus low-power mode

The SMPS step down converter operating mode depends on the selected operating and
upon the system operating modes (LP)Run, (LP)Sleep, Stop 0, Stop 1, Stop 2, Standby, and
Shutdown.
During Stop 1, Stop 2, Standby and Shutdown modes the SMPS step down converter is
switched to Open mode (see Table 62). When exiting from low-power modes (except
Shutdown) the SMPS step down converter is set by hardware to the mode selected prior to
the low-power mode selection. The SMPS step down converter mode configuration bits in
PWR_CR4 (SMPSLEN or SMPSBYP) are retained in Standby mode.
After POR reset, the SMPS step down converter is in High-power mode.

Table 62. SMPS step down converter versus low-power modes

SMPS step down
System operating mode Description
converter state

SMPS in HPM or LPM mode and, in ranges

0/1 it switches to Bypass mode following
Run, Sleep ON
VDD minimum value versus the selected
voltage range
Stop 0 ON SMPS in HPM or LPM mode
Stop 1, Stop 2, Low power run,
Low power sleep, Open SMPS is bypassed, LPR regulator is used
Standby with SRAM2 retention
Standby and Shutdown Open SMPS is bypassed

Note: It is recommended to enable the SMPS bypass mode prior entering Stop modes in order to
reduce the wake up time.

272/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Note: If the Bypass mode is requested, entering Stop 1 or Stop 2 or Low-power run or Low-power
sleep modes shall be delayed until the SMPS BYPASS ready flag SMPSBYPRDY is set.
Note: In Low-power run mode, the following bits shall not be modified (PWR_CR4: SMPSLPEN,
SMPSFSTEN, SMPSBYP).

SMPS step down converter fast startup

After POR reset, the SMPS step down converter starts in High-power mode and in Slow-
startup mode. The low-startup feature is selected to limit the inrush current after power-on
reset.
However, it is possible to configure a faster startup on the fly and it is applied for next SMPS
startup (after a wakeup from low-power mode - except Shutdown and VBAT modes) or for
next SMPS output voltage change (Bypass or VOS change). The fast startup is selected by
setting the SMPSFSTEN bit in the PWR_CR4 register.
Note: Setting the SMPSFSTEN bit in the PWR_CR4 register allows also a faster switch to Bypass
mode (i.e. V15SMPS reaching VDD).
Note: The timing needed for Bypass mode to be effective (i.e. SMPSBYPRDY flag is set) is
counted starting from V15 already at target value (1.3V (Range 2); 1.5V (Range 1); 1.6V
(Range 0)). This timing is determined by the parameter V15 slew rate, depending itself on
the fact that fast startup is enabled or disabled. Refer to the device datasheet.

8.2.5 Dynamic voltage scaling management

The dynamic voltage scaling is a power management technique which consists in
increasing or decreasing the voltage used for the digital peripherals (VCORE), according to
the application performance and power consumption needs.
Dynamic voltage scaling to increase VCORE is known as overvolting. It allows the device to
improve its performance.
Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to
save power, particularly in laptop and other mobile devices where the energy comes from a
battery and is thus limited.
The main regulator operates in the following ranges:
• Main regulator Range 0: high performance;
It provides a typical output voltage at 1.28 V. It is used when the system clock
frequency is up to 110 MHz. The Flash access time for read access is minimum, write
and erase operations are possible.
• Main regulator Range 1: medium performance;
It provides a typical output voltage at 1.2 V. It is used when the system clock frequency
is up to 80 MHz. The Flash access time for read access is minimum, write and erase
operations are possible.
• Main regulator Range 2: low-power range.
It provides a typical output voltage at 1.0 V. The system clock frequency can be up to
26 MHz.The Flash access time for a read access is increased as compared to Range
1; write and erase operations are not possible.
Voltage scaling is selected through the VOS[1:0] bits in the PWR_CR1 register. The main
regulator voltage Range 2 is selected by default.
Note: In Low-power run mode, the VOS[1:0] must not be modified.

RM0438 Rev 7 273/2194

326
Power control (PWR) RM0438

Voltage scaling and SMPS step down converter

When the SMPS step down converter is selected, the VOS[1:0] bits must not be modified
when the SMPS is in a low-power mode.
When the voltage scaling is updated, the SMPS step down converter output voltage is
scaled automatically following the selected voltage range.
The sequence to go from Range 0 /Range 1 to Range 2 is:
1. In case of switching from Range 0 to Range 2, the system clock must be divided
by 2 using the AHB prescaler before switching to a lower system frequency for at
least 1 us and then reconfigure the AHB prescaler.
2. Reduce the system frequency to a value lower than 26 MHz.
3. Adjust number of wait states according new frequency target in Range 2
(LATENCY bits in the FLASH_ACR).
4. Program the VOS[1:0] bits to “10” in the PWR_CR1 register.
The sequence to go from Range 2 to Range 1/Range 0 is:
1. Program the VOS[1:0] bits to “01” in the PWR_CR1 register.
2. Wait until the VOSF flag is cleared in the PWR_SR2 register.
3. Adjust number of wait states according new frequency target in Range 0 or
Range 1 (LATENCY bits in the FLASH_ACR).
4. Increase the system frequency by following below procedure:
– If the system frequency is 26 MHz < SYSCLK <= 80 MHz:
- Configure and switch to PLL for a new system frequency.
– If the system frequency is SYSCLK > 80 MHz:
- The system clock must be divided by 2 using the AHB prescaler before switching
to a higher system frequency.
- Configure and switch to PLL for a new system frequency.
- Wait for at least 1us and then reconfigure the AHB prescaler to get the needed
HCLK clock frequency.
The sequence to switch from Range 1 to Range 0 is:
1. The system clock must be divided by 2 using the AHB prescaler before switching
to a higher system frequency.
2. Adjust the number of wait states according to the new frequency target in range1
3. Configure and switch to new system frequency.
4. Wait for at least 1us and then reconfigure the AHB prescaler to get the needed
HCLK clock frequency.
The sequence to switch from Range 0 boost mode to Range 1 mode is:
1. Adjust the number of wait states according to the new frequency target in Range 0
default mode
2. Configure and switch to new system frequency.

8.2.6 VDD12 domain and external SMPS

VDD12 is intended to be connected with external SMPS (switched-mode power supply) to
generate the VCORE logic supply in Run, Sleep and Stop 0 modes only.

274/2194 RM0438 Rev 7

RM0438 Power control (PWR)

VDD12 pins correspond to the internal VCORE powering the digital part of Core, RAMs,
FLASH and peripherals. This significantly improves the power consumption with a gain from
50% or more depending of the external SMPS performances.
The main benefit occurs in Run and Sleep modes whereas in Stop 0 mode, the gain is less
significant.
The figure below shows a schematic to understand how the internal regulator stops
supplying VCORE when an external voltage VDD12 is provided.
As VDD12 shares the same pin as output of the internal regulator, applying a slightly higher
voltage (typically +50 mV) on the VDD12 blocks, the PMOS and the regulator consumption
is negligible.

Figure 25. Internal main regulator overview

VDD

PMOS
Switch VCORE
VDD12

Vsmps
Voltage regulator
Ref

MSv44809V1

A switch, controlled by the chosen GPIO, is inserted between the external SMPS output and
VDD12.
There are two possible states:
• Connected: Switch is closed so external SMPS powers VDD12
• Disconnected: Switch is open and VDD12 is disconnected from external SMPS output
Proper software management through GPIOs to enable/disable external SMPS and to
connect/disconnect external SMPS through the switch, is required to conform with the rules
described below. See also Section 8.2.5: Dynamic voltage scaling management.

RM0438 Rev 7 275/2194

326
Power control (PWR) RM0438

It is mandatory to respect the following rules to avoid any damage or instability on either
digital parts or internal regulators:
• In Run, Sleep and Stop 0 modes, VDD12 can be connected and should respect
– VDD12 < 1.32 V
– VDD12 ≥ VCORE + 50 mV giving for main regulator
Range 0, VCORE =1.28 V so VDD12 should be greater than 1.33 V, but this cannot
match previous rule VDD12 < 1.32 V, so it is not a functional use case with an
external SMPS.
Range 1, VCORE = 1.2 V so VDD12 should be greater than 1.25 V.
Range 2, VCORE = 1.0 V so VDD12 should be greater than 1.05 V
– VDD12 ≥ 1.08 V in Range 1 when 80 MHz ≥ SYSCLK frequency ≥ 26 MHz
– VDD12 ≥ 1.14 V in Range 0 when SYSCLK frequency > 80 MHz
• In all other modes, such as LPRun, LPSleep, Stop 1, Stop 2, Standby and Shutdown
modes, VDD12 must be disconnected from external SMPS output. This means that the
pin must be connected to a high impedance output:
– VDD12 connected to HiZ (voltage is provided by internal regulators)
• Transitions of VDD12 from connected to disconnected is only allowed when SYSCLK
frequency ≤ 26 MHz to avoid to big voltage drop on main regulator side.
Note: In case of asynchronous reset while having the VDD12 ≤ 1.25 V, VDD12 should switch to HiZ
in less than regulator switching time from Range 2 to Range 1 (~1 us).
Note: VDD12 Range 2 is extended down to 1.00 V for better efficiency, thus following formula
applies when bit EXTSMPSEN in the Power control register 4 (PWR_CR4) is set:
Range 2, VCORE = 0.95 V so VDD12 should be greater than 1.00 V
Note: For more details on VDD12 management, refer to AN4978 “Design recommendations for
STM32L4xxxx with external SMPS, for ultra-low-power applications with high performance”.

8.3 Power supply supervision

8.3.1 Power-on reset (POR) / power-down reset (PDR) /

brown-out reset (BOR)
The device has an integrated power-on reset (POR) / power-down reset (PDR), coupled
with a brown-out reset (BOR) circuitry. The BOR is active in all power modes except
Shutdown mode, and cannot be disabled.
Five BOR thresholds can be selected through option bytes.
During power-on, the BOR keeps the device under reset until the supply voltage VDD
reaches the specified VBORx threshold. When VDD drops below the selected threshold, a
device reset is generated. When VDD is above the VBORx upper limit, the device reset is
released and the system can start.
For more details on the brown-out reset thresholds, refer to the electrical characteristics
section in the datasheet.
During Stop 2 and Standby modes, it is possible to set the BOR in Ultra-low-power mode to
further reduce the current consumption by setting the ULPMEN bit in PWR_CR3 register.

276/2194 RM0438 Rev 7

RM0438 Power control (PWR)

For Stop 2 mode, the BOR Ultra-low-power mode can be set if the BORH is set, otherwise
there is no power consumption optimization.

Figure 26. Brown-out reset waveform

VDD
VBOR0 (rising edge)

hysteresis
VBOR0 (falling edge)

Temporization
tRSTTEMPO

Reset
MS31444V5

1. The reset temporization tRSTTEMPO is present only for the BOR lowest threshold (VBOR0).

8.3.2 Programmable voltage detector (PVD)

The user can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register 2 (PWR_CR2).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control register 2 (PWR_CR2), to indicate if VDD is
higher or lower than the PVD threshold. This event is internally connected to the EXTI line16
and can generate an interrupt if enabled through the EXTI registers.
The rising/falling edge sensitivity of the EXTI Line16 should be configured according to PVD
output behavior. For example, if the EXTI line 16 is configured to rising edge sensitivity, the
interrupt is generated when VDD drops below the PVD threshold. As an example the
service routine could perform emergency shutdown tasks.
During during Stop 2 and Standby modes, it is possible to set the PDV in Ultra-low-power
mode to further reduce the current consumption by setting the ULPMEN bit in PWR_CR3
register.
For Stop 2 mode, the PVD Ultra-low-power mode can be set if the PVD is set, otherwise if
PVD is disabled, there is no power consumption optimization.

RM0438 Rev 7 277/2194

326
Power control (PWR) RM0438

Figure 27. PVD thresholds

V DD

V PVD threshold 100 mV

hysteresis

PVD output

MS31445V2

8.3.3 Peripheral voltage monitoring (PVM)

Only VDD is monitored by default, as it is the only supply required for all system-related
functions. The other supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD
and can be monitored with four peripheral voltage monitoring (PVM).
Each of the four PVMx (x=1, 2, 3, 4) is a comparator between a fixed threshold VPVMx and
the selected power supply. PVMOx flags indicate if the independent power supply is higher
or lower than the PVMx threshold: PVMOx flag is cleared when the supply voltage is above
the PVMx threshold, and is set when the supply voltage is below the PVMx threshold.
Each PVM output is connected to an EXTI line and can generate an interrupt if enabled
through the EXTI registers. The PVMx output interrupt is generated when the independent
power supply drops below the PVMx threshold and/or when it rises above the PVMx
threshold, depending on EXTI line rising/falling edge configuration.
Each PVM can remain active in Stop 0, Stop 1 and Stop 2 modes, and the PVM interrupt
can wake up from the Stop mode.

Table 63. PVM features

PVM Power supply PVM threshold EXTI line

PVM1 VDDUSB VPVM1 (around 1.2 V) 35

PVM2 VDDIO2 VPVM2 (around 0.9 V) 36
PVM3 VDDA VPVM3 (around 1.65 V) 37
PVM4 VDDA VPVM4 (around 1.8 V) 38

The independent supplies (VDDA, VDDIO2 and VDDUSB) are not considered as present by
default, and a logical and electrical isolation is applied to ignore any information coming
from the peripherals supplied by these dedicated supplies.
• If these supplies are shorted externally to VDD, the application should assume they are
available without enabling any peripheral voltage monitoring.
• If these supplies are independent from VDD, the peripheral voltage monitoring (PVM)

278/2194 RM0438 Rev 7

RM0438 Power control (PWR)

can be enabled to confirm whether the supply is present or not.

The following sequence must be done before using the USB peripheral:
1. If VDDUSB is independent from VDD:
a) Enable the PVM1 by setting PVME1 bit in the Power control register 2
(PWR_CR2).
b) Wait for the PVM1 wakeup time.
c) Wait until PVMO1 bit is cleared in the Power status register 2 (PWR_SR2).
d) Optional: Disable the PVM1 for consumption saving.
2. Set the USV bit in the Power control register 2 (PWR_CR2) to remove the VDDUSB
power isolation.
The following sequence must be done before using any I/O from PG[15:2]:
1. If VDDIO2 is independent from VDD:
a) Enable the PVM2 by setting PVME2 bit in the Power control register 2
(PWR_CR2).
b) Wait for the PVM2 wakeup time.
c) Wait until PVMO2 bit is cleared in the Power control register 2 (PWR_CR2).
d) Optional: Disable the PVM2 for consumption saving.
2. Set the IOSV bit in the Power control register 2 (PWR_CR2) to remove the VDDIO2
power isolation.
The following sequence must be done before using any of these analog peripherals: analog
to digital converters, digital to analog converters, comparators, operational amplifiers,
voltage reference buffer:
1. If VDDA is independent from VDD:
a) Enable the PVM3 (or PVM4) by setting PVME3 (or PVME4) bit in the Power
control register 2 (PWR_CR2).
b) Wait for the PVM3 (or PVM4) wakeup time.
c) Wait until PVMO3 (or PVMO4) bit is cleared in the Power status register 2
(PWR_SR2).
d) Optional: Disable the PVM3 (or PVM4) for consumption saving.
Enable the analog peripheral, which automatically removes the VDDA isolation.

8.3.4 Upper voltage threshold monitoring

The upper VDD voltage monitoring is enabled by setting the bit VMONEN in the
TAMP_CFGR register.
If the upper VDD voltage monitoring internal tamper is enabled in the TAMP peripheral
(ITAMP1E=1 in the TAMP_CR1 register), a tamper event is generated when the VDD
domain voltage is above the specified threshold.
The upper VDD monitoring can be periodical. This feature is enabled by setting the bit
WUTMONEN in the TAMP configuration register TAMP_CFGR.
In this case, the monitoring is controlled by the RTC wakeup timer PWM resulting from the
WUTF flag automatic clear and depending on the bitsfield WUTOCLR in the RTC_WUTR
register. For more details, refer to the RTC section.

RM0438 Rev 7 279/2194

326
Power control (PWR) RM0438

The monitoring is enabled during the PWM high level and disabled during the PWM low
level.
Note: For threshold value, refer to the product datasheet.
Note: In case the VDD is below the functional range, a Brown-out reset is generated.

8.3.5 Temperature threshold monitoring

The temperature monitoring is enabled by setting the bit TMONEN in the TAMP_CFGR
register.
If the temperature monitoring internal tamper is enabled in the TAMP peripheral
(ITAMP2E=1 in the TAMP_CR1 register), a tamper event is generated when the
temperature is above or below the specified thresholds.
The temperature monitoring can be periodical. This feature is enabled by setting the bit
WUTMONEN in the TAMP configuration register TAMP_CFGR.
In this case, the monitoring is controlled by the RTC wakeup timer PWM resulting from the
WUTF flag automatic clear and depending on the bitfield WUTOCLR in the RTC_WUTR
register. For more details, refer to the RTC section.
The monitoring is enabled during the PWM high level and disabled during the PWM low
level.
Note: For thresholds values, refer to the product datasheet.

8.4 Power management

8.4.1 Power modes

By default, the microcontroller is in Run mode after a system or a power reset. Several low-
power modes are available to save power when the CPU does not need to be kept running,
for example when waiting for an external event. It is up to the user to select the mode that
gives the best compromise between low-power consumption, short startup time and
available wakeup sources.
The device features eight low-power modes:
• Sleep mode: CPU clock off, all peripherals including Cortex®-M33 core such as NVIC
and SysTick can run and wake up the CPU when an interrupt or an event occurs. Refer
to Section 8.4.5: Sleep mode.
• Low-power run mode: This mode is achieved when the system clock frequency is
reduced below 2 MHz. The code is executed from the SRAM or the Flash memory. The
regulator is in Low-power mode to minimize the regulator's operating current. Refer to
Section 8.4.3: Low-power run mode (LP run).
• Low-power sleep mode: This mode is entered from the Low-power run mode: Cortex®-
M33 is off. Refer to Section 8.4.6: Low-power sleep mode (LP sleep).
• Stop 0, Stop 1 and Stop 2 modes: SRAM1, SRAM2 and all registers content are
retained. All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and
the HSE are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with the wakeup capability can enable the HSI16 RC during the Stop

280/2194 RM0438 Rev 7

RM0438 Power control (PWR)

mode to detect their wakeup condition.

In Stop 2 mode, most of the VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wakeup sources, a smaller
wakeup time but a higher consumption than Stop 2. In Stop 0 mode, the main regulator
remains ON, which allows the fastest wakeup time but with much higher consumption.
The active peripherals and wakeup sources are the same as in Stop 1 mode.
The system clock, when exiting from Stop 0, Stop 1 or Stop 2 mode, can be either MSI
up to 48 MHz or HSI16, depending on the software configuration.
Refer to Section 8.4.7: Stop 0 mode and Section 8.4.9: Stop 2 mode.
• Standby mode: VCORE domain is powered off. However, it is possible to preserve the
full SRAM2 content or only 4 Kbytes:
– Standby mode with full or only the upper 4 Kbytes of SRAM2 retention when the
RRS[1:0] bits are set to ‘01’ or ‘10’ respectively in the PWR_CR3 register. In this
case, the SRAM2 is supplied by the low-power regulator.
– Standby mode when the RRS[1:0] bits are cleared in PWR_CR3 register. In this
case the main regulator and the low-power regulator are powered off.
All clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 and the HSE
are disabled. The LSI and the LSE can be kept running.
The RTC can remain active (Standby mode with RTC, Standby mode without RTC).
The system clock, when exiting Standby modes, is MSI from 1 MHz up to 8 MHz.
Refer to Section 8.4.10: Standby mode.
• Shutdown mode: VCORE domain is powered off. All clocks in the VCORE domain are
stopped, the PLL, the MSI, the HSI16, the LSI and the HSE are disabled. The LSE can
be kept running. The system clock, when exiting the Shutdown mode, is MSI at 4 MHz.
In this mode, the supply voltage monitoring is disabled and the product behavior is not
guaranteed in case of a power voltage drop. Refer to Section 8.4.11: Shutdown mode.
In addition, the power consumption in Run mode can be reduced by one of the following
means:
• Slowing down the system clocks
• Gating the clocks to the APB and AHB peripherals when they are unused.

RM0438 Rev 7 281/2194

326
Power control (PWR) RM0438

Figure 28. Low-power modes possible transitions

Low power sleep mode

Sleep mode Low power run mode Shutdown mode

Stop 1 mode Run mode Standby mode

Stop 0 mode Stop 2 mode

MS33361V2

282/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Table 64. Low-power mode summary

Voltage
Wakeup Wakeup regulators
Mode name Entry Effect on clocks
source(1) system clock
MR LPR

WFI or Return CPU clock OFF

Sleep Any interrupt
from ISR Same as before no effect on other
(Sleep-now or ON ON
entering Sleep mode clocks or analog clock
Sleep-on-exit) WFE Wakeup event sources
Low-power Same as low-power
Set LPR bit Clear LPR bit None OFF ON
run run clock
Set LPR bit + WFI CPU clock OFF
or Return Any interrupt Same as before OFF ON
Low-power no effect on other
from ISR entering Low-power
sleep clocks or analog clock
sleep mode
Set LPR bit + WFE Wakeup event sources OFF ON
LPMS=”000” +
SLEEPDEEP bit +
Stop 0 ON
WFI or Return
HSI16 when STOP-
from ISR or WFE
WUCK=1 in
Any EXTI line
LPMS=”001” + RCC_CFGR
(configured in the
SLEEPDEEP bit + MSI with the fre-
Stop 1 EXTI registers)
WFI or Return quency before enter-
Specific peripher-
from ISR or WFE ing the Stop mode
als events
when STOP-
LPMS=”010” +
WUCK=0.
SLEEPDEEP bit +
Stop 2 WFI or Return
ON
from ISR or WFE
LPMS=”011”+ Set All clocks OFF except OFF
RRS[1:0] bits to LSI and LSE
Standby with “10”+ SLEEPDEEP
SRAM2_4KB bit + WFI or Return
from ISR or WFE
LPMS=”011”+ Set WKUP pin edge,
RRS bits to “01”+ RTC event,
Standby with MSI from 1 MHz up
SLEEPDEEP bit + external reset in
SRAM2_Full to 8 MHz
WFI or Return NRST pin,
from ISR or WFE IWDG reset

LPMS=”011” +
Clear RRS bits +
Standby SLEEPDEEP bit + OFF OFF
WFI or Return
from ISR or WFE
LPMS=”1--” + WKUP pin edge,
SLEEPDEEP bit + RTC event, All clocks OFF except
Shutdown MSI 4 MHz OFF OFF
WFI or Return external reset in LSE
from ISR or WFE NRST pin

1. Refer to Table 65: Functionalities depending on the working mode.

RM0438 Rev 7 283/2194

326
Power control (PWR) RM0438

Table 65. Functionalities depending on the working mode(1)

Stop 0/1 Stop 2 Standby Shutdown

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

CPU Y - Y - - - - - - - - - -
Flash memory
O(2) O(2) O(2) O(2) - - - - - - - - -
(2 Mbytes)
SRAM1
Y Y(3) Y Y(3) Y - Y - - - - - -
(192 Kbytes)
SRAM2 (64 Kbytes) Y Y(3) Y Y(3) Y - Y - O(4) - - - -
FSMC O O O O - - - - - - - - -
OctoSPI O O O O - - - - - - - - -
OTFDEC O O O O - - - - - - - - -
Backup registers Y Y Y Y Y - Y - Y - Y - Y
Brownout reset
Y Y Y Y Y Y Y Y Y Y - - -
(BOR)
Programmable
voltage detector O O O O O O O O - - - - -
(PVD)
Peripheral voltage
monitor (PVMx; O O O O O O O O - - - - -
x=1,2,3,4)
DMA O O O O - - - - - - - - -
High speed internal (5) (5)
O O O O - - - - - - -
(HSI16)
-
Oscillator HSI48 O O - - - - - - - - - -
High speed external
O O O O - - - - - - - - -
(HSE)
Low speed internal
O O O O O - O - O - - - -
(LSI)
Low speed external
O O O O O - O - O - O - O
(LSE)
Multi speed internal
O O O O - - - - - - - - -
(MSI)
Clock security
O O O O - - - - - - - - -
system (CSS)
Clock security
O O O O O O O O O O - - -
system on LSE

284/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Table 65. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

VDD voltage
monitoring,
O O O O O O O O O O - - -
temperature
monitoring
RTC / TAMP O O O O O O O O O O O O O
Number of RTC
8 8 8 8 8 O 8 O 8 O 8 O 3
Tamper pins
USB, UCPD O(8) O(8) - - - O - - - - - - -
USARTx
O O O O O(6) O(6) - - - - - - -
(x=1,2,3,4,5)
Low-power UART
O O O O O(6) O(6) O(6) O(6) - - - - -
(LPUART)
I2Cx (x=1,2,4) O O O O O(7) O(7) - - - - - - -
(7)
I2C3 O O O O O O(7) O(7) O(7) - - - - -
SPIx (x=1,2,3) O O O O - - - - - - - - -
FDCAN1 O O O O - - - - - - - - -
SDMMC1 O O O O - - - - - - - - -
SAIx (x=1,2) O O O O - - - - - - - - -
DFSDM1 O O O O - - - - - - - - -
ADCx (x=1,2) O O O O - - - - - - - - -
DACx (x=1,2) O O O O O - - - - - - - -
VREFBUF O O O O O - - - - - - - -
OPAMPx (x=1,2) O O O O O - - - - - - - -
COMPx (x=1,2) O O O O O O O O - - - - -
Temperature
O O O O - - - - - - - - -
sensor
Timers (TIMx) O O O O - - - - - - - - -
Low-power timer 1,
3 (LPTIM1 and O O O O O O O O - - - - -
LPTIM3)
Low-power timer 2
O O O O O O - - - - - - -
(LPTIM2)

RM0438 Rev 7 285/2194

326
Power control (PWR) RM0438

Table 65. Functionalities depending on the working mode(1) (continued)

Stop 0/1 Stop 2 Standby Shutdown

Wakeup capability

Wakeup capability

Wakeup capability

Wakeup capability
Low- Low-
Peripheral Run Sleep power power VBAT
run sleep - - - -

Independent
O O O O O O O O O O - - -
watchdog (IWDG)
Window watchdog
O O O O - - - - - - - - -
(WWDG)
SysTick timer O O O O - - - - - - - - -
Touch sensing
O O O O - - - - - - - - -
controller (TSC)
Random number
O(8) O(8) - - - - - - - - - - -
generator (RNG)
AES hardware
O O O O - - - - - - - - -
accelerator
HASH hardware
O O O O - - - - - - - - -
accelerator
PKA O O O O - - - - - - - - -
CRC calculation
O O O O - - - - - - - - -
unit
5 5
(9) (11)
GPIOs O O O O O O O O pins pins -
(10) (10)

1. Legend: Y = yes (enable). O = optional (disable by default, can be enabled by software). - = not available.
Gray cells highlight the wakeup capability in each mode.
2. The Flash can be configured in Power-down mode. By default, it is not in Power-down mode.
3. The SRAM clock can be gated on or off.
4. 4 Kbytes or full SRAM2 content is preserved depending on RRS[1:0] bits configuration in PWR_CR3 register.
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from standby/shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

286/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop 1,
Stop 2, Standby or Shutdown mode while the debug features are used. This is due to the
fact that the Cortex®-M33 core is no longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 52.2.5: Debug and low-power modes.

8.4.2 Run mode

Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering the Sleep mode.
For more details, refer to Section 9.8.3: RCC clock configuration register (RCC_CFGR).

Peripheral clock gating

In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.

8.4.3 Low-power run mode (LP run)

To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the system frequency should not exceed
2 MHz.
Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.

I/O states in Low-power run mode

In Low-power run mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power run mode

To enter the Low-power run mode, proceed as follows:
1. Optional: Jump into the SRAM and power-down the Flash by setting the RUN_PD bit in
the Flash access control register (FLASH_ACR).
2. Decrease the system clock frequency below 2 MHz.
3. Force the regulator in Low-power mode by setting the LPR bit in the PWR_CR1
register.
Refer to Table 66: Low-power run on how to enter the Low-power run mode.

RM0438 Rev 7 287/2194

326
Power control (PWR) RM0438

Exiting the Low-power run mode

To exit the Low-power run mode, proceed as follows:
1. Force the regulator in Main mode by clearing the LPR bit in the PWR_CR1 register.
2. Wait until REGLPF bit is cleared in the PWR_SR2 register.
3. Increase the system clock frequency.
Refer to Table 66: Low-power run on how to exit the Low-power run mode.

Table 66. Low-power run

Low-power run mode Description

Decrease the system clock frequency below 2 MHz

Mode entry
LPR = 1
LPR = 0
Mode exit Wait until REGLPF = 0
Increase the system clock frequency
Wakeup latency Regulator wakeup time from low-power mode

8.4.4 Low-power modes

Entering into a low-power mode
Low-power modes are entered by the MCU by executing the WFI (wait for interrupt), or
WFE (wait for event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M33
system control register is set on Return from ISR.
Entering into a low-power mode through WFI or WFE is executed only if no interrupt is
pending or no event is pending.

Exiting from a low-power mode

From Sleep mode and Stop mode the MCU exits the low-power mode depending on the
way the low-power mode was entered:
• If the WFI instruction or return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
• If the WFE instruction is used to enter the low-power mode, the MCU exits the low-
power mode as soon as an event occurs. The wakeup event can be generated either
by:
– NVIC IRQ interrupt.
- When SEVONPEND = 0 in the Cortex®-M33 system control register. By enabling
an interrupt in the peripheral control register and in the NVIC. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared.
Only NVIC interrupts with sufficient priority wakeup and interrupt the MCU.
- When SEVONPEND = 1 in the Cortex®-M33 System Control register.
By enabling an interrupt in the peripheral control register and optionally in the
NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and

288/2194 RM0438 Rev 7

RM0438 Power control (PWR)

when enabled the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt
clear pending register) have to be cleared.
All NVIC interrupts wakes up the MCU, even the disabled ones. Only enabled
NVIC interrupts with sufficient priority wake up and interrupt the MCU.
– Event
Configuring a EXTI line in Event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
From Standby modes, and Shutdown modes the MCU exits the low-power mode through an
external reset (NRST pin), an IWDG reset, a rising edge on one of the enabled WKUPx pins
or a RTC event occurs (see Figure 395: RTC block diagram).
After waking up from Standby or Shutdown mode, program execution restarts in the same
way as after a Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).

8.4.5 Sleep mode

I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Sleep mode

The Sleep mode is entered according Section : Entering into a low-power mode, when the
SLEEPDEEP bit in the Cortex®-M33 System Control register is clear.
Refer to Table 67: Sleep mode for details on how to enter the Sleep mode.

Exiting the Sleep mode

The Sleep mode is exit according Section : Exiting from a low-power mode.
Refer to Table 67: Sleep mode for more details on how to exit the Sleep mode.

Table 67. Sleep mode

Sleep-now mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M33 system control register.
Mode entry On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M33 System Control register.

RM0438 Rev 7 289/2194

326
Power control (PWR) RM0438

Table 67. Sleep mode (continued)

Sleep-now mode Description

If WFI or return from ISR was used for entry

Interrupt: refer to Table 104: STM32L552xx and STM32L562xx vector
table
If WFE was used for entry and SEVONPEND = 0:
Mode exit Wakeup event: refer to Section 17.3: EXTI functional description
If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 104: STM32L552xx
and STM32L562xx vector table or Wakeup event: refer to Section 17.3:
EXTI functional description
Wakeup latency None

8.4.6 Low-power sleep mode (LP sleep)

Refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.

I/O states in Low-power sleep mode

In Low-power sleep mode, all I/O pins keep the same state as in Run mode.

Entering the Low-power sleep mode

The Low-power sleep mode is entered from Low-power run mode according to Section :
Entering into a low-power mode, when the SLEEPDEEP bit in the Cortex®-M33 system
control register is clear.
Refer to Table 68: Low-power sleep for details on how to enter the Low-power sleep mode.

Exiting the Low-power sleep mode

The Low-power sleep mode is exit according to Section : Exiting from a low-power mode.
When exiting the Low-power sleep mode by issuing an interrupt or an event, the MCU is in
Low-power run mode.
Refer to Table 68: Low-power sleep for details on how to exit the Low-power sleep mode.

290/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Table 68. Low-power sleep

Low-power sleep-now
Description
mode

Low-power sleep mode is entered from the Low-power run mode.

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0
– No interrupt (for WFI) or event (for WFE) is pending
Refer to the Cortex®-M33 System Control register.
Mode entry Low-power sleep mode is entered from the Low-power run mode.
On return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1
– No interrupt is pending
Refer to the Cortex®-M33 System Control register.
If WFI or Return from ISR was used for entry
Interrupt: refer to Table 104: STM32L552xx and STM32L562xx vector
table
If WFE was used for entry and SEVONPEND = 0:
Wakeup event: refer to Section 17.3: EXTI functional description
Mode exit If WFE was used for entry and SEVONPEND = 1:
Interrupt even when disabled in NVIC: refer to Table 104: STM32L552xx
and STM32L562xx vector table
Wakeup event: refer to Section 17.3: EXTI functional description
After exiting the Low-power sleep mode, the MCU is in Low-power run
mode.
Wakeup latency None

8.4.7 Stop 0 mode

The Stop 0 mode is based on the Cortex®-M33 Deepsleep mode combined with the
peripheral clock gating. The voltage regulator is configured in Main regulator mode. In Stop
0 mode, all clocks in the VCORE domain are stopped; the PLL, the MSI, the HSI16 and the
HSE oscillators are disabled. Some peripherals with the wakeup capability (I2Cx (x=1,2,3),
U(S)ARTx(x=1,2...5) and LPUART) can switch on the HSI16 to receive a frame, and switch
off the HSI16 after receiving the frame if it is not a wakeup frame. In this case, the HSI16
clock is propagated only to the peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 0 mode. The consumption is increased when
thresholds higher than VBOR0 are used.

I/O states in Stop 0 mode

In the Stop 0 mode, all I/O pins keep the same state as in the Run mode.

Entering the Stop 0 mode

The Stop 0 mode is entered according Section : Entering into a low-power mode, when the
SLEEPDEEP bit in the Cortex®-M33 System Control register is set.

RM0438 Rev 7 291/2194

326
Power control (PWR) RM0438

Refer to Table 69: Stop 0 mode for details on how to enter the Stop 0 mode.
If Flash memory programming is ongoing, the Stop 0 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 0 mode entry is delayed until the APB
access is finished.
In Stop 0 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its key register or by
hardware option. Once started, it cannot be stopped except by a reset. See
Section 39.3: IWDG functional description.
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC Backup domain
control register (RCC_BDCR).
• Internal RC oscillator (LSI): LSI clock or LSI clock divided by 128, this is configured by
the LSION and LSIPRE bits in the RCC control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC
Backup domain control register (RCC_BDCR).
Several peripherals can be used in Stop 0 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1,
LPTIM2, I2Cx (x=1,2,3,4) U(S)ARTx(x=1,2...5), LPUART.
The DACx (x=1,2), the OPAMPs and the comparators can be used in Stop 0 mode, the
PVMx (x=1,2,3,4) and the PVD as well. If they are not needed, they must be disabled by
software to save their power consumptions.
The ADCx (x=1,2,3), temperature sensor and VREFBUF buffer can consume power during
the Stop 0 mode, unless they are disabled before entering this mode.

Exiting the Stop 0 mode

The Stop 0 mode is exit according Section : Entering into a low-power mode.
Refer to Table 69: Stop 0 mode for details on how to exit Stop 0 mode.
When exiting Stop 0 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows wakeup at higher frequency, up to 48 MHz.
When exiting the Stop 0 mode, the MCU is either in Run mode (Range 0, Range 1 or Range
2) or in Low-power run mode if the bit LPR is set in the PWR_CR1 register.

292/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Table 69. Stop 0 mode

Stop 0 mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “000” in PWR_CR1

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
Mode entry – SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “000” in PWR_CR1
Note: To enter Stop 0 mode, all EXTI Line pending bits (in EXTI rising
edge pending register (EXTI_RPR2)), and the peripheral flags
generating wakeup interrupts must be cleared. Otherwise, the Stop
0 mode entry procedure is ignored and program execution
continues.
If WFI or Return from ISR was used for entry
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 104: STM32L552xx and STM32L562xx vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in Event mode. Refer to Section 17.3: EXTI
Mode exit
functional description.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer
toTable 104: STM32L552xx and STM32L562xx vector table.
Wakeup event: refer to Section 17.3: EXTI functional description
Longest wakeup time between: MSI or HSI16 wakeup time and Flash
Wakeup latency
wakeup time from Stop 0 mode.

8.4.8 Stop 1 mode

The Stop 1 mode is the same as Stop 0 mode except that the main regulator is OFF, and
only the low-power regulator is ON. Stop 1 mode can be entered from Run mode and from
Low-power run mode.
Refer to Table 70: Stop 1 mode for details on how to enter and exit Stop 1 mode.

RM0438 Rev 7 293/2194

326
Power control (PWR) RM0438

Table 70. Stop 1 mode

Stop 1 mode Description

WFI (wait for interrupt) or WFE (wait for event) while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “001” in PWR_CR1

On Return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
Mode entry – SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “001” in PWR_CR1
Note: To enter Stop 1 mode, all EXTI Line pending bits (in EXTI rising
edge pending register (EXTI_RPR1)), and the peripheral flags
generating wakeup interrupts must be cleared. Otherwise, the Stop
1 mode entry procedure is ignored and program execution
continues.
If WFI or Return from ISR was used for entry
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 104: STM32L552xx and STM32L562xx vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in Event mode. Refer to Section 17.3: EXTI
Mode exit
functional description.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer
toTable 104: STM32L552xx and STM32L562xx vector table.
Wakeup event: refer to Section 17.3: EXTI functional description
Longest wakeup time between: MSI or HSI16 wakeup time and regulator
Wakeup latency wakeup time from low-power mode + Flash wakeup time from Stop 1
mode.

8.4.9 Stop 2 mode

The Stop 2 mode is based on the Cortex®-M33 Deepsleep mode combined with peripheral
clock gating. In Stop 2 mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
the HSI16 and the HSE oscillators are disabled. Some peripherals with wakeup capability
(I2C3 and LPUART) can switch on the HSI16 to receive a frame, and switch off the HSI16
after receiving the frame if it is not a wakeup frame. In this case the HSI16 clock is
propagated only to the peripheral requesting it.
SRAM1, SRAM2 and register contents are preserved.
The BOR is always available in Stop 2 mode. The consumption is increased when
thresholds higher than VBOR0 are used.
Note: The comparators outputs, the LPUART outputs and the LPTIM1 outputs are forced to low
speed (OSPEEDy=00) during the Stop 2 mode.

294/2194 RM0438 Rev 7

RM0438 Power control (PWR)

I/O states in Stop 2 mode

In the Stop 2 mode, all I/O pins keep the same state as in the Run mode.

Entering Stop 2 mode

The Stop 2 mode is entered according Section : Entering into a low-power mode, when the
SLEEPDEEP bit in the Cortex®-M33 System Control register is set.
Refer to Table 71: Stop 2 mode for details on how to enter the Stop 2 mode.
Stop 2 mode can only be entered from Run mode. It is not possible to enter Stop 2 mode
from the Low-power run mode.
If Flash memory programming is ongoing, the Stop 2 mode entry is delayed until the
memory access is finished.
If an access to the APB domain is ongoing, The Stop 2 mode entry is delayed until the APB
access is finished.
In Stop 2 mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 39.3: IWDG functional description in Section 39: Independent watchdog
(IWDG).
• Real-time clock (RTC): this is configured by the RTCEN bit in the RCC Backup domain
control register (RCC_BDCR).
• Internal RC oscillator (LSI): LSI clock or LSI clock divided by 128, this is configured by
the LSION and LSIPRE bits in the RCC control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the RCC
Backup domain control register (RCC_BDCR).
Several peripherals can be used in Stop 2 mode and can add consumption if they are
enabled and clocked by LSI or LSE, or when they request the HSI16 clock: LPTIM1, I2C3,
LPUART.
The comparators can be used in Stop 2 mode, the PVMx (x=1,2,3,4) and the PVD as well. If
they are not needed, they must be disabled by software to save their power consumptions.
The ADCx, OPAMPx, DACx, temperature sensor and VREFBUF buffer can consume power
during Stop 2 mode, unless they are disabled before entering this mode.
All the peripherals which cannot be enabled in Stop 2 mode must be either disabled by
clearing the enable bit in the peripheral itself, or put under reset state by setting the
corresponding bit in the RCC AHB1 peripheral reset register (RCC_AHB1RSTR), RCC
AHB2 peripheral reset register (RCC_AHB2RSTR), RCC AHB3 peripheral reset register
(RCC_AHB3RSTR), RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1), RCC
APB1 peripheral reset register 2 (RCC_APB1RSTR2), RCC APB2 peripheral reset register
(RCC_APB2RSTR).

Exiting Stop 2 mode

The Stop 2 mode is exit according to Section : Exiting from a low-power mode.
Refer to Table 71: Stop 2 mode for details on how to exit Stop 2 mode.

RM0438 Rev 7 295/2194

326
Power control (PWR) RM0438

When exiting Stop 2 mode by issuing an interrupt or a wakeup event, the HSI16 oscillator is
selected as system clock if the bit STOPWUCK is set in RCC clock configuration register
(RCC_CFGR). The MSI oscillator is selected as system clock if the bit STOPWUCK is
cleared. The wakeup time is shorter when HSI16 is selected as wakeup system clock. The
MSI selection allows wakeup at higher frequency, up to 48 MHz.
When exiting the Stop 2 mode, the MCU is in Run mode (Range 0, Range 1 or Range 2
depending on VOS bit in PWR_CR1).

Table 71. Stop 2 mode

Stop 2 mode Description

WFI (wait for interrupt) or WFE (wait for event) while:

– SLEEPDEEP bit is set in Cortex®-M33 system control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “010” in PWR_CR1

On return from ISR while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
Mode entry – SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “010” in PWR_CR1
Note: To enter Stop 2 mode, all EXTI Line pending bits (in EXTI rising
edge pending register (EXTI_RPR2)), and the peripheral flags gen-
erating wakeup interrupts must be cleared. Otherwise, the Stop
mode entry procedure is ignored and program execution continues.
If WFI or Return from ISR was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 104: STM32L552xx and STM32L562xx vector table.
If WFE was used for entry and SEVONPEND = 0:
Any EXTI Line configured in Event mode. Refer to Section 17.3: EXTI
Mode exit functional description.
If WFE was used for entry and SEVONPEND = 1:
Any EXTI Line configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 104: STM32L552xx and STM32L562xx vector table.
Any EXTI Line configured in Event mode. Refer to Section 17.3: EXTI
functional description.
Longest wakeup time between: MSI or HSI16 wakeup time and regulator
Wakeup latency wakeup time from low-power mode + Flash wakeup time from Stop 2
mode.

8.4.10 Standby mode

The Standby mode permits the achievement of the lowest power consumption with BOR. It
is based on the Cortex®-M33 Deepsleep mode, with the voltage regulators disabled (except
when SRAM2 content is preserved). The PLL, the HSI16, the MSI and the HSE oscillators
are also switched off.

296/2194 RM0438 Rev 7

RM0438 Power control (PWR)

SRAM1 and register contents are lost except for registers in the Backup domain and
Standby circuitry (see Figure 21). SRAM2 content can be can be partially or fully preserved
depending on RRS[1:0] bits configuration in PWR_CR3. In this case the Low-power
regulator is ON and provides the supply to SRAM2 only.
The BOR is always available in Standby mode. The consumption is increased when
thresholds higher than VBOR0 are used.

I/O states in Standby mode

In the Standby mode, the IO’s are by default in floating state. If the APC bit of PWR_CR3
register has been set, the I/Os can be configured either with a pull-up (refer to
PWR_PUCRx registers (x=A,B,C,D,E,F,G,H)), or with a pull-down (refer to PWR_PDCRx
registers (x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx
or PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.
Some I/Os (listed in Section 11.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug and can only be configured to their respective reset pull-up or pull-down state during
Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to
‘1’, or to be configured to floating state if the bit is kept at ‘0’.
The RTC outputs on PC13 are functional in Standby mode. PC14 and PC15 used for LSE
are also functional. 5 wakeup pins (WKUPx, x=1,2...5) and tamper inputs are available.

Entering Standby mode

The Standby mode is entered according Section : Entering into a low-power mode, when
the SLEEPDEEP bit in the Cortex®-M33 System Control register is set.
Refer to Table 72: Standby mode for details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
• Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 39.3: IWDG functional description in Section 39: Independent watchdog
(IWDG).
• Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR).
• Internal RC oscillator (LSI): LSI clock or LSI clock divided by 128, this is configured by
the LSION and LSIPRE bits in the Control/status register (RCC_CSR).
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR).

Exiting Standby mode

The Standby mode is exited according Section : Entering into a low-power mode. The SBF
status flag in the Power control register 3 (PWR_CR3) indicates that the MCU was in
Standby mode. All registers are reset after wakeup from Standby except for Power control
register 3 (PWR_CR3).
Refer to Table 72: Standby mode for more details on how to exit Standby mode.

RM0438 Rev 7 297/2194

326
Power control (PWR) RM0438

When exiting Standby mode, I/O’s that were configured with pull-up or pull-down during
Standby through registers PWR_PUCRx or PWR_PDCRx keep this configuration upon
exiting Standby mode until the bit APC of PWR_CR3 register has been cleared. Once the
bit APC is cleared, they are either configured to their reset values or to the pull-up/pull-down
state according the GPIOx_PUPDR registers. The content of the PWR_PUCRx or
PWR_PDCRx registers however is not lost and can be re-used for a sub-sequent entering
into Standby mode.
Some I/Os (listed in Section 11.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug and have internal pull-up or pull-down activated after reset so is configured at this
reset value as well when exiting Standby mode.
For IO’s, with a pull-up or pull-down pre-defined after reset (some JTAG/SW IO’s) or with
GPIOx_PUPDR programming done after exiting from Standby, in case those programming
is different from the PWR_PUCRx or PWR_PDCRx programmed value during Standby,
both a pull-down and pull-up are applied until the bit APC is cleared, releasing the
PWR_PUCRx or PWR_PDCRx programmed value.

Table 72. Standby mode

Standby mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “011” in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)

On return from ISR while:

Mode entry – SLEEPDEEP bit is set in Cortex®-M33 System Control register
– SLEEPONEXIT = 1
– No interrupt is pending
– LPMS = “011” in PWR_CR1 and
– WUFx bits are cleared in power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wakeup source (RTC Alarm
A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is cleared
WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset,
Mode exit
BOR reset
Wakeup latency Reset phase

298/2194 RM0438 Rev 7

RM0438 Power control (PWR)

8.4.11 Shutdown mode

The Shutdown mode allows to achieve the lowest power consumption. It is based on the
Deepsleep mode, with the voltage regulator disabled. The VCORE domain is consequently
powered off. The PLL, the HSI16, the MSI, the LSI and the HSE oscillators are also
switched off.
SRAM1, SRAM2 and register contents are lost except for registers in the Backup domain.
The BOR is not available in Shutdown mode. No power voltage monitoring is possible in this
mode, therefore the switch to Backup domain is not supported.

I/O states in Shutdown mode

In the Shutdown mode, are by default in floating state. If the APC bit of PWR_CR3 register
has been set, the I/Os can be configured either with a pull-up (refer to PWR_PUCRx
registers (x=A,B,C,D,E,F,G,H), or with a pull-down (refer to PWR_PDCRx registers
(x=A,B,C,D,E,F,G,H)), or can be kept in analog state if none of the PWR_PUCRx or
PWR_PDCRx register has been set. The pull-down configuration has highest priority over
pull-up configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same IO.
However this configuration is lost when exiting the Shutdown mode due to the power-on
reset.
Some I/Os (listed in Section 11.3.1: General-purpose I/O (GPIO)) are used for JTAG/SW
debug and can only be configured to their respective reset pull-up or pull-down state during
Standby mode setting their respective bit in the PWR_PUCRx or PWR_PDCRx registers to
‘1’, or to be configured to floating state if the bit is kept at ‘0’.
The RTC outputs on PC13 are functional in Shutdown mode. PC14 and PC15 used for LSE
are also functional. Five wakeup pins (WKUPx, x=1,2...5) and the three RTC tampers are
available.

Entering Shutdown mode

The Shutdown mode is entered according Entering into a low-power mode, when the
SLEEPDEEP bit in the Cortex®-M33 System Control register is set.
Refer to Table 73: Shutdown mode for details on how to enter Shutdown mode.
In Shutdown mode, the following features can be selected by programming individual
control bits:
• Real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR). Caution: in case of VDD power-down the RTC content is
lost.
• External 32.768 kHz oscillator (LSE): this is configured by the LSEON bit in the Backup
domain control register (RCC_BDCR).

Exiting Shutdown mode

The Shutdown mode is exit according Section : Exiting from a low-power mode. A power-on
reset occurs when exiting from Shutdown mode. All registers (except for the ones in the
Backup domain) are reset after wakeup from Shutdown.
Refer to Table 73: Shutdown mode for more details on how to exit Shutdown mode.
When exiting Shutdown mode, I/Os that were configured with pull-up or pull-down during
Shutdown through registers PWR_PUCRx or PWR_PDCRx lose their configuration and are

RM0438 Rev 7 299/2194

326
Power control (PWR) RM0438

configured in floating state or to their pull-up pull-down reset value (for some I/Os listed in
Section 11.3.1: General-purpose I/O (GPIO)).

Table 73. Shutdown mode

Shutdown mode Description

WFI (Wait for Interrupt) or WFE (Wait for Event) while:

– SLEEPDEEP bit is set in Cortex®-M33 System Control register
– No interrupt (for WFI) or event (for WFE) is pending
– LPMS = “1XX” in PWR_CR1
– WUFx bits are cleared in power status register 1 (PWR_SR1)

On return from ISR while:

Mode entry – SLEEPDEEP bit is set in Cortex®-M33 System Control register
– SLEEPONEXT = 1
– No interrupt is pending
– LPMS = “1XX” in PWR_CR1 and
– WUFx bits are cleared in power status register 1 (PWR_SR1)
– The RTC flag corresponding to the chosen wakeup source (RTC
Alarm A, RTC Alarm B, RTC wakeup, tamper or timestamp flags) is
cleared
Mode exit WKUPx pin edge, RTC event, external Reset in NRST pin
Wakeup latency Reset phase

8.4.12 Auto-wakeup from a low-power mode

The RTC can be used to wakeup the MCU from a low-power mode without depending on an
external interrupt (Auto-wakeup mode). The RTC provides a programmable time base for
waking up from Stop (0, 1 or 2) or Standby mode at regular intervals. For this purpose, two
of the three alternative RTC clock sources can be selected by programming the
RTCSEL[1:0] bits in the RCC Backup domain control register (RCC_BDCR):
• Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with very low-power consumption.
• Low-power internal RC Oscillator (LSI)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wakeup from Stop mode with an RTC event (alarm, wake-up timer, timestamp), it is
necessary to:
• Configure the EXTI Line 17 for non-secure interrupt and EXTI Line 18 for secure
interrupts to be sensitive to rising edge
• Configure the RTC to generate the RTC event (alarm, wake-up timer, timestamp)
To wakeup from Standby mode, there is no need to configure the EXTI Line 17 or
EXTI Line 18.

8.5 PWR TrustZone security

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR
register, some PWR register fields can be secured against non-secure access.

300/2194 RM0438 Rev 7

RM0438 Power control (PWR)

The PWR TrustZone security allows to secure the following features through the security
configuration register PWR_SECCFGR:
• Low-power mode
• Wake-up (WKUP) pins
• Voltage detection and monitoring
• VBAT mode
Other PWR configuration bits are secure when:
• The system clock selection is secure in RCC, the voltage scaling (VOS) configuration is
secure
• A GPIO is configured as secure, its corresponding bit for Pull-up/Pull-down
configuration in Standby mode is secure
• The RTC is secure, the backup domain write protection DBP bit in PWR_CR1 register
is secure.
• The UCPD is secure, the UCPD_DBDIS and UCPD_STDBY bits are secure in the
PWR_CR3 register.
Table 74 gives a summary of the PWR secured bits following the security configuration bit in
the PWR_SECCFGR register. When one security configuration bit is set, some
configuration bits are secured. The PWR registers may contain secure and non-secure bits:
• Secured bits: read and write operations are only allowed by a secure access. Non-
secure read or write accesses are RAZ/WI. There is no illegal access event generated.
• Non-secure bits: no restriction. Read and write operations are allowed by both secure
and non-secure accesses.
A non-secure write access to PWR_SECCFGR register is WI and generates an illegal
access event. An illegal access interrupt is generated if the PWR illegal access interrupt is
enabled in the TZIC_IER2 register. There is no restriction for non-secure read access.
When the TrustZone security is disabled (TZEN = 0 in FLASH_OPTR register), all registers
are non-secure. The PWR_SECCFGR secure register and security status registers are
RAZ/WI.
.

Table 74. PWR Security configuration summary

Non-secure
Secure configura- Security configura-
Secured bits Register name access on secure
tion register tion bit
bits

Read is OK.
PWR_SECCFGR NA(1) - PWR_SECCFGR WI and illegal
access event
Read is OK.
PWR_SECCFGR At least one bit is set PRIV PWR_PRIVCFGR WI and illegal
access event(2)

RM0438 Rev 7 301/2194

326
Power control (PWR) RM0438

Table 74. PWR Security configuration summary

Non-secure
Secure configura- Security configura-
Secured bits Register name access on secure
tion register tion bit
bits

LPMS[1:0],
PWR_CR1
LPR RAZ/WI
LPMSEC RRS[1:0] PWR_CR3
CSBF,
PWR_SCR WI
CWUFx

WUPxSEC or LPM- WUPx PWR_CR3

SEC(1) WUPPx PWR_CR4
RAZ/WI
PWR_SECCFGR All bits in PWR_CR2 PWR_CR2
ULPMEN PWR_CR3
VDMSEC SMPSBYP,
EXTSMPSEN,
PWR_CR4
SMPSFSTEN,
SMPSLPEN
RAZ/WI
DBP PWR_CR1
VBSEC
VBRS, VBE PWR_CR4
APCSEC APC PWR_CR3
UCPD_DBDIS and
TZSC_SECFGR UCPD1SEC PWR_CR3
UCPD_STDBY
RCC_SECCFGR CKSYSSEC VOS[1:0] PWR_CR1
PWR_PUCRx (x = A, RAZ/WI
PUy (y=0..15)
GPIOx_SECCFGR B..H)
SECy (y=0..15)
(x=A,B..H) PWR_PDCRx (x = A,
PDy (y=0..15)
B..H)
1. PWR_SECCFGR register is always secure.
2. Illegal access event is generated only when the PWR_PRIVCFGR is secure.

8.5.1 PWR Privileged and Unprivileged modes

The PWR registers can be can be read and written by privileged and unprivileged accesses
depending on PRIV bit in PWR_PRIVCFGR register.
• When the PRIV bit is reset, all PWR registers could be read and written by both
privileged or unprivileged access.
• When the PRIV bit is set, all PWR registers could be read and written by privileged
access only (except PWR_SR1, PWR_SR2 and PWR_SECFGR registers).
Unprivileged access to a privileged registers is RAZ/WI.

8.6 PWR registers

The peripheral registers can be accessed by half-words (16-bit) or words (32-bit).

302/2194 RM0438 Rev 7

RM0438 Power control (PWR)

8.6.1 Power control register 1 (PWR_CR1)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on PWR_SECCFGR and RCC_SECCFGR configuration regis-
ters. A non-secure read/write access on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is reset after wakeup from Standby mode.
Address offset: 0x00
Reset value: 0x0000 0400

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. LPR Res. Res. Res. VOS[1:0] DBP Res. Res. Res. Res. Res. LPMS[2:0]
rw rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 LPR: Low-power run
When this bit is set, the regulator is switched from Main mode (MR) to Low-power run mode
(LPR).
Note: Stop 2 mode cannot be entered when LPR bit is set. Stop 1 is entered instead.
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:9 VOS[1:0]: Voltage scaling range selection
00: Range 0
01: Range 1
10: Range 2
11: Cannot be written (forbidden by hardware).
Bit 8 DBP: Disable backup domain write protection.
In reset state, the RTC and backup registers are protected against parasitic write access.
This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 LPMS[2:0]: Low-power mode selection
These bits select the low-power mode entered when CPU enters the Deepsleep mode.
000: Stop 0 mode
001: Stop 1 mode
010: Stop 2 mode
011: Standby mode
1xx: Shutdown mode
Note: If LPR bit is set, Stop 2 mode cannot be selected and Stop 1 mode shall be entered
instead of Stop 2.
Note: In Standby mode, SRAM2 can be preserved or not, depending on RRS bit configuration
in PWR_CR3.

RM0438 Rev 7 303/2194

326
Power control (PWR) RM0438

8.6.2 Power control register 2 (PWR_CR2)

When the system is secure (TZEN =1), this register is protected against non-secure access
when VDMSEC=1 in the PWR_SECCFGR register. A non-secure read/write access is
RAZ/WI and generates and illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Address offset: 0x04
Reset value: 0x0000 0000
This register is reset when exiting the Standby mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. USV IOSV Res. PVME4 PVME3 PVME2 PVME1 PLS[2:0] PVDE
rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 USV: VDDUSB USB supply valid
This bit is used to validate the VDDUSB supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use the USB peripheral. If VDDUSB is not always
present in the application, the PVM can be used to determine whether this supply is ready or
not.
0: VDDUSB is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDUSB is valid.
Bit 9 IOSV: VDDIO2 Independent I/Os supply valid
This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.
Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the
application, the PVM can be used to determine whether this supply is ready or not.
0: VDDIO2 is not present. Logical and electrical isolation is applied to ignore this supply.
1: VDDIO2 is valid.
Bit 8 Reserved, must be kept at reset value.
Bit 7 PVME4: Peripheral voltage monitoring 4 enable: VDDA vs. 1.8 V
0: PVM4 (VDDA monitoring vs. 1.8 V threshold) disable.
1: PVM4 (VDDA monitoring vs. 1.8 .V threshold) enable.
Bit 6 PVME3: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V
0: PVM3 (VDDA monitoring vs. 1.62V threshold) disable.
1: PVM3 (VDDA monitoring vs. 1.62V threshold) enable.
Bit 5 PVME2: Peripheral voltage monitoring 2 enable: VDDIO2 vs. 0.9V
0: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) disable.
1: PVM2 (VDDIO2 monitoring vs. 0.9V threshold) enable.

304/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Bit 4 PVME1: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V

0: PVM1 (VDDUSB monitoring vs. 1.2V threshold) disable.
1: PVM1 (VDDUSB monitoring vs. 1.2V threshold) enable.
Bits 3:1 PLS[2:0]: Power voltage detector level selection.
These bits select the voltage threshold detected by the power voltage detector:
000: VPVD0 around 2.0 V
001: VPVD1 around 2.2 V
010: VPVD2 around 2.4 V
011: VPVD3 around 2.5 V
100: VPVD4 around 2.6 V
101: VPVD5 around 2.8 V
110: VPVD6 around 2.9 V
111: External input analog voltage PVD_IN (compared internally to VREFINT)
Note: These bits are write-protected when the bit PVDL (PVD Lock) is set in the
SYSCFG_CBR register.
These bits are reset only by a system reset.
Bit 0 PVDE: Power voltage detector enable
0: Power voltage detector disable.
1: Power voltage detector enable.
Note: This bit is write-protected when the bit PVDL (PVD Lock) is set in the SYSCFG_CBR
register.
This bit is reset only by a system reset.

8.6.3 Power control register 3 (PWR_CR3)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on PWR_SECCFGR and TZSC_SECCFGR configuration. A non-
secure read/write access on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register versus a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with the PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UCPD_ UCPD_ ULPM
Res. Res. APC RRS[1:0] Res. Res. Res. EWUP5 EWUP4 EWUP3 EWUP2 EWUP1
DBDIS STDBY EN

rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 305/2194

326
Power control (PWR) RM0438

Bits 31:15 Reserved, must be kept at reset value.

Bit 14 UCPD_DBDIS: USB Type-C and power delivery dead dattery disable
After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a
pulldown effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to
stop this pull-down or to hand over control to the UCPD (which should therefore be initialized
before doing the disable).
0: enable USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2
pins
1: disable USB Type-C dead battery pull-down behavior on UCPDx_CC1 and UCPDx_CC2
pins
Bit 13 UCPD_STDBY: USB Type-C and power delivery Standby mode
When set, this bit allows to memorize the UCPD configuration in Standby mode.
This bit must be written to ‘1’ just before entering Standby mode when using UCPD, and it
must be written to 0 after exiting the Standby mode and before writing any UCPD registers.
Bit 12 Reserved, must be kept at reset value.
Bit 11 ULPMEN: Ultra-low-power mode enable
When this bit is set, the BOR and PVD are in Ultra-low-power mode during Stop 2 and
Standby mode in order to further reduce the current consumption.
0: BORL, BORH and PVD operating in Default mode.
1: Enable Ultra-low-power mode for BORL, BORH and PVD during Stop 2 and Standby
mode.
In Stop 2 mode, ULPMEN can be set if BORH and PVD are enabled, otherwise there is no
power consumption optimization.
Bit 10 APC: Apply pull-up and pull-down configuration
When this bit is set, the I/O pull-up and pull-down configurations defined in the PWR_PUCRx
and PWR_PDCRx registers are applied. When this bit is cleared, the PWR_PUCRx and
PWR_PDCRx registers are not applied to the I/Os, instead the I/Os are in Floating mode
during Standby or configured according GPIO controller GPIOx_PUPDR register during Run
mode.
Bits 9:8 RRS[1:0]: SRAM2 retention in Standby mode
00: SRAM2 is powered off in Standby mode (SRAM2 content is lost).
01: Full SRAM2 is powered by the low-power regulator in Standby mode (Full SRAM2
content is kept).
10: Only the upper 4 Kbytes of SRAM2 are powered by the low-power regulator in Standby
mode (upper 4 Kbytes of SRAM2 content 0x2003 F000 - 0x2003 FFFF is kept).
11: Reserved
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 EWUP5: Enable wakeup pin WKUP5
When this bit is set, the external wakeup pin WKUP5 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs.The active edge is
configured via the WUPP5 bit in the PWR_CR4 register.
Bit 3 EWUP4: Enable wakeup pin WKUP4
When this bit is set, the external wakeup pin WKUP4 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WUPP4 bit in the PWR_CR4 register.

306/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Bit 2 EWUP3: Enable wakeup pin WKUP3

When this bit is set, the external wakeup pin WKUP3 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WUPP3 bit in the PWR_CR4 register.
Bit 1 EWUP2: Enable wakeup pin WKUP2
When this bit is set, the external wakeup pin WKUP2 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WUPP2 bit in the PWR_CR4 register.
Bit 0 EWUP1: Enable wakeup pin WKUP1
When this bit is set, the external wakeup pin WKUP1 is enabled and triggers a wakeup from
Standby or Shutdown event when a rising or a falling edge occurs. The active edge is
configured via the WUPP1 bit in the PWR_CR4 register.

8.6.4 Power control register 4 (PWR_CR4)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on PWR_SECCFGR configuration. A non-secure read/write
access on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with the PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EXTS
SMPSL SMPS SMPS
MPSE Res. Res. VBRS VBE Res. Res. Res. WUPP5 WUPP4 WUPP3 WUPP2 WUPP1
PEN FSTEN BYP
N
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 SMPSLPEN: Enable SMPS low-power mode
When this enable the SMPS low-power mode. When set, it is forbidden to modify the voltage
scaling configuration.
0: SMPS low-power mode disable
1: SMPS low-power mod enable
Bit 14 SMPSFSTEN: Enable SMPS fast soft start
0: SMPS fast soft start disable
1: SMPS fast soft start enable.

RM0438 Rev 7 307/2194

326
Power control (PWR) RM0438

Bit 13 EXTSMPSEN: Enable external SMPS mode

This bit is used for external SMPS mode, it must be set when the external SMPS switch is
closed.
0: Disable the external SMPS mode
1: Enable external SMPS mode
Bit 12 SMPSBYP: SMPS Bypass mode
This bit is used to force the SMPS step down converter in Bypass mode.
0: SMPS Bypass mode disable
1: SMPS Bypass mode enable
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 VBRS: VBAT battery charging resistor selection
0: Charge VBAT through a 5 kOhms resistor
1: Charge VBAT through a 1.5 kOhms resistor
Bit 8 VBE: VBAT battery charging enable
0: VBAT battery charging disable
1: VBAT battery charging enable
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WUPP5: Wakeup pin WKUP5 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP5
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 3 WUPP4: Wakeup pin WKUP4 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP4
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 2 WUPP3: Wakeup pin WKUP3 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP3
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 1 WUPP2: Wakeup pin WKUP2 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP2
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)
Bit 0 WUPP1: Wakeup pin WKUP1 polarity
This bit defines the polarity used for an event detection on external wake-up pin, WKUP1
0: Detection on high level (rising edge)
1: Detection on low level (falling edge)

8.6.5 Power status register 1 (PWR_SR1)

This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is not reset when exiting Standby modes and with the PWRRST bit in the
RCC_APB1RSTR1 register.
Access: 2 additional APB cycles are needed to read this register vs. a standard APB read.
Address offset: 0x10

308/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Reset value: 0x00A0 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMPS EXTS SMPS
HPRD Res. MPSR BYPR Res. Res. Res. SBF Res. Res. Res. WUF5 WUF4 WUF3 WUF2 WUF1
Y DY DY
r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 SMPSHPRDY: SMPS High-power mode ready
This bit is set when the SMPS step down converter is in High-power mode.
Bit 14 Reserved, must be kept at reset value.
Bit 13 EXTSMPSRDY: External SMPS mode ready
This bit is set when the main regulator is ready and can be switched in external SMPS mode.
When set, the external SMPS switch can be closed.
Bit 12 SMPSBYPRDY: SMPS BYPASS ready
This bit is set when the SMPS step down converter is in Bypass mode. It is cleared when the
SMPS exits the Bypass mode when it is switched to High-power or Low-power mode.
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 SBF: Standby flag
This bit is set by hardware when the device enters the Standby mode and is cleared by
setting the CSBF bit in the PWR_SCR register, or by a power-on reset. It is not cleared by the
system reset.
0: The device did not enter the Standby mode
1: The device entered the Standby mode.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WUF5: Wakeup flag 5
This bit is set when a wakeup event is detected on wakeup pin, WKUP5. It is cleared by
writing ‘1’ in the CWUF5 bit of the PWR_SCR register.
Bit 3 WUF4: Wakeup flag 4
This bit is set when a wakeup event is detected on wakeup pin,WKUP4. It is cleared by
writing ‘1’ in the CWUF4 bit of the PWR_SCR register.
Bit 2 WUF3: Wakeup flag 3
This bit is set when a wakeup event is detected on wakeup pin, WKUP3. It is cleared by
writing ‘1’ in the CWUF3 bit of the PWR_SCR register.
Bit 1 WUF2: Wakeup flag 2
This bit is set when a wakeup event is detected on wakeup pin, WKUP2. It is cleared by
writing ‘1’ in the CWUF2 bit of the PWR_SCR register.
Bit 0 WUF1: Wakeup flag 1
This bit is set when a wakeup event is detected on wakeup pin, WKUP1. It is cleared by
writing ‘1’ in the CWUF1 bit of the PWR_SCR register.

RM0438 Rev 7 309/2194

326
Power control (PWR) RM0438

8.6.6 Power status register 2 (PWR_SR2)

This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is partially reset when exiting Standby/Shutdown modes.
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PVMO PVMO PVMO PVMO REGLP REGLP
PVDO VOSF Res. Res. Res. Res. Res. Res. Res. Res.
4 3 2 1 F S
r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 PVMO4: Peripheral voltage monitoring output: VDDA vs. 1.8 V
0: VDDA voltage is above PVM4 threshold (around 1.8 V).
1: VDDA voltage is below PVM4 threshold (around 1.8 V).
Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the
PVM4 output is valid after the PVM4 wakeup time.
Bit 14 PVMO3: Peripheral voltage monitoring output: VDDA vs. 1.62 V
0: VDDA voltage is above PVM3 threshold (around 1.62 V).
1: VDDA voltage is below PVM3 threshold (around 1.62 V).
Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the
PVM3 output is valid after the PVM3 wakeup time.
Bit 13 PVMO2: Peripheral voltage monitoring output: VDDIO2 vs. 0.9 V
0: VDDIO2 voltage is above PVM2 threshold (around 0.9 V).
1: VDDIO2 voltage is below PVM2 threshold (around 0.9 V).
Note: PVMO2 is cleared when PVM2 is disabled (PVME2 = 0). After enabling PVM2, the
PVM2 output is valid after the PVM2 wakeup time.
Bit 12 PVMO1: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V
0: VDDUSB voltage is above PVM1 threshold (around 1.2 V).
1: VDDUSB voltage is below PVM1 threshold (around 1.2 V).
Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the
PVM1 output is valid after the PVM1 wakeup time.
Bit 11 PVDO: Power voltage detector output
0: VDD is above the selected PVD threshold
1: VDD is below the selected PVD threshold
Bit 10 VOSF: Voltage scaling flag
A delay is required for the internal regulator to be ready after the voltage scaling has been
changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits
of the PWR_CR1 register.
0: The regulator is ready in the selected voltage range
1: The regulator output voltage is changing to the required voltage level

310/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Bit 9 REGLPF: Low-power regulator flag

This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits
from the Low-power run mode, this bit remains at 1 until the regulator is ready in Main mode.
A polling on this bit must be done before increasing the product frequency.
This bit is cleared by hardware when the regulator is ready.
0: The regulator is ready in Main mode (MR)
1: The regulator is in Low-power mode (LPR)
Bit 8 REGLPS: Low-power regulator started
This bit provides the information whether the low-power regulator is ready after a power-on
reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still
cleared, the wakeup from Standby mode time may be increased.
0: The low-power regulator is not ready
1: The low-power regulator is ready
Bits 7:0 Reserved, must be kept at reset value.

8.6.7 Power status clear register (PWR_SCR)

When the system is secure (TZEN =1), this register is protected against non-secure access
when LPMSEC=1 in the PWR_SECCFGR register. A non-secure read/write access is
RAZ/WI and generates and illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: 3 additional APB cycles are needed to write this register vs. a standard APB write.
Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. CSBF Res. Res. Res. CWUF5 CWUF4 CWUF3 CWUF2 CWUF1
w w w w w w

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 CSBF: Clear standby flag
Setting this bit clears the SBF flag in the PWR_SR1 register.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 CWUF5: Clear wakeup flag 5
Setting this bit clears the WUF5 flag in the PWR_SR1 register.
Bit 3 CWUF4: Clear wakeup flag 4
Setting this bit clears the WUF4 flag in the PWR_SR1 register.

RM0438 Rev 7 311/2194

326
Power control (PWR) RM0438

Bit 2 CWUF3: Clear wakeup flag 3

Setting this bit clears the WUF3 flag in the PWR_SR1 register.
Bit 1 CWUF2: Clear wakeup flag 2
Setting this bit clears the WUF2 flag in the PWR_SR1 register.
Bit 0 CWUF1: Clear wakeup flag 1
Setting this bit clears the WUF1 flag in the PWR_SR1 register.

8.6.8 Power Port A pull-up control register (PWR_PUCRA)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x20.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port A pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PA[y] when APC bit is set in PWR_CR3 register.
If the corresponding PDy bit is also set, the pull-up is not activated and the pull-down is
activated instead with highest priority.

8.6.9 Power Port A pull-down control register (PWR_PDCRA)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).

312/2194 RM0438 Rev 7

RM0438 Power control (PWR)

This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x24.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port A pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PA[y] when APC bit is set in PWR_CR3 register.

8.6.10 Power Port B pull-up control register (PWR_PUCRB)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
Address offset: 0x28.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port B pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PB[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

RM0438 Rev 7 313/2194

326
Power control (PWR) RM0438

8.6.11 Power Port B pull-down control register (PWR_PDCRB)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
Address offset: 0x2C.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port B pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PB[y] when APC bit is set in PWR_CR3 register.

8.6.12 Power Port C pull-up control register (PWR_PUCRC)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
Address offset: 0x30.
Reset value: 0x0000 0000

314/2194 RM0438 Rev 7

RM0438 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port C pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PC[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

8.6.13 Power Port C pull-down control register (PWR_PDCRC)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
Address offset: 0x34.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port C pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PC[y] when APC bit is set in PWR_CR3 register.

8.6.14 Power Port D pull-up control register (PWR_PUCRD)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.

RM0438 Rev 7 315/2194

326
Power control (PWR) RM0438

This register is protected against non-privileged access when PRIV=1 in the

PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x38.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port D pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PD[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

8.6.15 Power Port D pull-down control register (PWR_PDCRD)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
Address offset: 0x3C.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port D pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PD[y] when APC bit is set in PWR_CR3 register.

316/2194 RM0438 Rev 7

RM0438 Power control (PWR)

8.6.16 Power Port E pull-up control register (PWR_PUCRE)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x20.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port E pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PE[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PDy bit is also set.

8.6.17 Power Port E pull-down control register (PWR_PDCRE)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x44.
Reset value: 0x0000 0000

RM0438 Rev 7 317/2194

326
Power control (PWR) RM0438

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port E pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PE[y] when APC bit is set in PWR_CR3 register.

8.6.18 Power Port F pull-up control register (PWR_PUCRF)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x48.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port F pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PF[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PFy bit is also set.

8.6.19 Power Port F pull-down control register (PWR_PDCRF)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.

318/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x4C.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port F pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PF[y] when APC bit is set in PWR_CR3 register.

8.6.20 Power Port G pull-up control register (PWR_PUCRG)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x50.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port G pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PG[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PGy bit is also set.

RM0438 Rev 7 319/2194

326
Power control (PWR) RM0438

8.6.21 Power Port G pull-down control register (PWR_PDCRG)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x54.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port G pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PG[y] when APC bit is set in PWR_CR3 register.

8.6.22 Power Port H pull-up control register (PWR_PUCRH)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x58.
Reset value: 0x0000 0000

320/2194 RM0438 Rev 7

RM0438 Power control (PWR)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PU15 PU14 PU13 PU12 PU11 PU10 PU9 PU8 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PU[15:0]: Port H pull-up bit y (y=0..15)
When set, this bit activates the pull-up on PH[y] when APC bit is set in PWR_CR3 register.
The pull-up is not activated if the corresponding PHy bit is also set.

8.6.23 Power Port H pull-down control register (PWR_PDCRH)

When the system is secure (TZEN =1), some register fields are protected against non-
secure access depending on GPIO secure bit configuration. A non-secure read/write access
on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register is protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.
Access: Additional APB cycles are needed to access this register vs. a standard APB
access (3 for a write and 2 for a read).
This register is not reset when exiting Standby modes and with PWRRST bit in the
RCC_APB1RSTR1 register.
Address offset: 0x5C.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 PD[15:0]: Port H pull-down bit y (y=0..15)
When set, this bit activates the pull-down on PH[y] when APC bit is set in PWR_CR3 register.

8.6.24 Power secure configuration register (PWR_SECCFGR)

When the system is secure (TZEN =1), this register provides write access security and can
be written only when the access is secure. A non-secure write access is WI and generates
an illegal access event. There are no read restrictions
When the system is not secure (TZEN=0), this register is RAZ/WI.
This register can be protected against non-privileged access when PRIV=1 in the
PWR_PRIVCFGR register.

RM0438 Rev 7 321/2194

326
Power control (PWR) RM0438

Address offset: 0x78.

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
APCSE VDMSE LPMSE WUP5S WUP4S WUP3S WUP2S WUP1S
Res. Res. Res. Res. VBSEC Res. Res. Res.
C C C EC EC EC EC EC
rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 APCSEC: APC security
0: APC bit in PWR_CR3 can be read and written by secure or non-secure access.
1: APC bit in PWR_CR3 can be read and written by secure access only
Bit 10 VBSEC: Voltage battery security
0: VBRS and VBE bits in PWR_CR4 and DPB bit in PWR_CR1 can be read and written by
secure or non-secure access.
1: VBRS and VBE bits in PWR_CR4 and DPB bit in PWR_CR1 can be read and written by
secure access only.
Refer to Table 74 for full list of secured bits.
Bit 9 VDMSEC: Voltage detection and monitoring security
0: PWR_CR2 and some bit fields in PWR_CR3 and PWR_CR4 registers can be read and
written by secure or non-secure access.
1: PWR_CR2 and some bit fields in PWR_CR3 and PWR_CR4 registers can be read and
written by secure access only.
Refer to Table 74 for full list of secured bits.
Bit 8 LPMSEC: Low-power mode security
0: Low-power mode and WKUPx related bit field in PWR_CR1, PWR_CR3, PWR_CR4 and
PWR_SCR can be read and written by secure or non-secure access.
1: Low-power mode and WKUPx related bit field in PWR_CR1, PWR_CR3, PWR_CR4 and
PWR_SCR can be read and written by secure access only
Note: This bit has a priority over WKUPxSEC bit.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 WUP5SEC: WKUP5 pin security
0: The bits related to the WKUP5 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure or non-secure access.
1: The bits related to the WKUP5 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure access only
Bit 3 WUP4SEC: WKUP4 pin security
0: The bits related to the WKUP4 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure or non-secure access.
1: The bits related to the WKUP4 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure access only

322/2194 RM0438 Rev 7

RM0438 Power control (PWR)

Bit 2 WUP3SEC: WKUP3 pin security

0: The bits related to the WKUP3 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure or non-secure access.
1: The bits related to the WKUP3 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure access only
Bit 1 WUP2SEC: WKUP2 pin security
0: The bits related to the WKUP2 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure or non-secure access.
1: The bits related to the WKUP2 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure access only
Bit 0 WUP1SEC: WKUP1 pin security
0: The bits related to the WKUP1 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure or non-secure access.
1: The bits related to the WKUP1 wakeup pin in PWR_CR3 and PWR_CR4 can be read and
written by secure access only

8.6.25 Power privilege configuration register (PWR_PRIVCFGR)

This register can be read by both privileged and unprivileged access.
When the system is secure (TZEN =1),this register can be read by secure and non-secure
access. It is write-protected against non-secure write access when at least one bit is set in
the PWR_SECCFGR register
Address offset: 0x80.
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIV
rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 PRIV: Privilege protection
Set and reset by software.
This bit can be read by both privileged or unprivileged access. when set, it can only be
cleared by a privileged access.
0: All PWR registers can be read and written with privileged or non-privileged access.
1: All PWR registers (except PWR_SR1, PWR_SR2 and PWR_SECFGR registers) can be
read and written only with privileged access. An unprivileged access to PWR registers is
RAZ/WI.
If the PWR is not secure, the PRIV bit can be written by a secure or non-secure privileged
access.
If TrustZone security is enabled (TZEN = 1), if the PWR is secure, the PRIV bit can be written
only by a secure privileged access:
– A non-secure write access generates an illegal access event and write is ignored.
– A secure unprivileged write access on PRIV bit is ignored.

RM0438 Rev 7 323/2194

326
 0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x0C
Offset
8.6.26

324/2194
PWR_SR2
PWR_SR1
PWR_CR4
PWR_CR3
PWR_CR2
PWR_CR1

PWR_SCR
reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_PUCRB
PWR_PDCRA
PWR_PUCRA
Register name
Power control (PWR)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18
PWR register map and reset values

RM0438 Rev 7
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16

0
PU15 PD15 PU15 Res. PVMO4 SMPSHPRDY SMPSLPEN Res. Res. Res. 15
0

PU14 PD14 PU14 Res. PVMO3 Res. SMPSFSTEN UCPD_DBDIS Res. LPR 14
0 0

PU13 PD13 PU13 Res. PVMO2 EXTSMPSRDY EXTSMPSEN UCPD_STDBY Res. Res. 13

0 0
0 0 0 0
PU12 PD12 PU12 Res. PVMO1 SMPSBYPRDY SMPSBYP Res Res. Res. 12
Table 75. PWR register map and reset values

PU11 PD11 PU11 Res. PVDO Res. Res. ULPMEN Res. Res. 11
PU10 PD10 PU10 Res. VOSF Res. Res. APC USV 10
VOS [1:0]
0 0

PU9 PD9 PU9 Res. REGLPF Res. VBRS IOSV 9

RRS[1:0]

0
0 0 0 0 0 0 0 0
0
0 0
0 0 0 0
0 1 0

PU8 PD8 PU8 CSBF REGLPS SBF VBE Res. DBP 8

PU7 PD7 PU7 Res. Res. Res. Res. Res. PVME4 Res. 7
PU6 PD6 PU6 Res. Res. Res. Res. Res. PVME3 Res. 6
PU5 PD5 PU5 Res. Res. Res. Res. Res. PVME2 Res. 5
PU4 PD4 PU4 CWUF5 Res. WUF5 WUPP5 EWUP5 PVME1 Res. 4
PU3 PD3 PU3 CWUF4 Res. WUF4 WUPP4 EWUP4 Res. 3
PU2 PD2 PU2 CWUF3 Res. WUF3 WUPP3 EWUP3 PLS [2:0] 2
PU1 PD1 PU1 CWUF2 Res. WUF2 WUPP2 EWUP2 LPMS [2:0] 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0

0
RM0438

PU0 PD0 PU0 CWUF1 Res. WUF1 WUPP1 EWUP1 PVDE

 0x80
0x78
0x58
0x54
0x50
0x48
0x44
0x20
0x38
0x34
0x30

0x5C
0x4C
0x3C
0x2C
Offset
RM0438

GR
GR
reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

PWR_SECCF
PWR_PDCRF
PWR_PUCRF
PWR_PDCRE
PWR_PUCRE
PWR_PDCRB

PWR_PDCRH
PWR_PUCRH
PWR_PDCRD
PWR_PUCRD
PWR_PDCRC
PWR_PUCRC

PWR_PDCRG
PWR_PUCRG

PWR_PRIVCF
Register name

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

RM0438 Rev 7
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 17
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 16
Res. Res. PD15 PU15 PD15 PU15 PD15 PU15 PD15 PU15 PD15 PU15 PD15 PU15 PD15 15
Res. Res. PD14 PU14 PD14 PU14 PD14 PU14 PD14 PU14 PD14 PU14 PD14 PU14 PD14 14
Res. Res. PD13 PU13 PD13 PU13 PD13 PU13 PD13 PU13 PD13 PU13 PD13 PU13 PD13 13
Res. Res. PD12 PU12 PD12 PU12 PD12 PU12 PD12 PU12 PD12 PU12 PD12 PU12 PD12 12
Res. APCSEC PD11 PU11 PD11 PU11 PD11 PU11 PD11 PU11 PD11 PU11 PD11 PU11 PD11 11
Res. VBSEC PD10 PU10 PD10 PU10 PD10 PU10 PD10 PU10 PD10 PU10 PD10 PU10 PD10 10
Res. VDMSEC PD9 PU9 PD9 PU9 PD9 PU9 PD9 PU9 PD9 PU9 PD9 PU9 PD9 9
Table 75. PWR register map and reset values (continued)

0 0 0 0
Res. LPMSEC PD8 PU8 PD8 PU8 PD8 PU8 PD8 PU8 PD8 PU8 PD8 PU8 PD8 8
Res. Res. PD7 PU7 PD7 PU7 PD7 PU7 PD7 PU7 PD7 PU7 PD7 PU7 PD7 7
Res. Res. PD6 PU6 PD6 PU6 PD6 PU6 PD6 PU6 PD6 PU6 PD6 PU6 PD6 6
Res. Res. PD5 PU5 PD5 PU5 PD5 PU5 PD5 PU5 PD5 PU5 PD5 PU5 PD5 5
Res. WUP5SEC PD4 PU4 PD4 PU4 PD4 PU4 PD4 PU4 PD4 PU4 PD4 PU4 PD4 4
Res. WUP4SEC PD3 PU3 PD3 PU3 PD3 PU3 PD3 PU3 PD3 PU3 PD3 PU3 PD3 3
Res. WUP3SEC PD2 PU2 PD2 PU2 PD2 PU2 PD2 PU2 PD2 PU2 PD2 PU2 PD2 2
Res. WUP2SEC PD1 PU1 PD1 PU1 PD1 PU1 PD1 PU1 PD1 PU1 PD1 PU1 PD1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0

0
0
Power control (PWR)

325/2194
PRIV WUP1SEC PD0 PU0 PD0 PU0 PD0 PU0 PD0 PU0 PD0 PU0 PD0 PU0 PD0

326
Power control (PWR) RM0438

Refer to Section 2.3 on page 87 for the register boundary addresses.

326/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9 Reset and clock control (RCC)

9.1 Reset
There are three types of reset:
• a system reset
• a power reset
• a Backup domain reset

9.1.1 Power reset

A power reset is generated when one of the following events occurs:
• a Brownout reset (BOR)
• when exiting from Standby mode
• when exiting from Shutdown mode
A Brownout reset, including power-on or power-down reset (POR/PDR), sets all registers to
their reset values except the ones in the Backup domain.
When exiting Standby mode, all registers in the VCORE domain are set to their reset value.
Registers outside the VCORE domain (RTC, WKUP, IWDG, and Standby/Shutdown modes
control) are not impacted.
When exiting Shutdown mode, a Brownout reset is generated, resetting all registers except
those in the Backup domain.

9.1.2 System reset

A system reset sets all registers to their reset values except the reset flags in RCC
control/status register (RCC_CSR) and the registers in the Backup domain.
A system reset is generated when one of the following events occurs:
• a low level on the NRST pin (external reset)
• a window watchdog event (WWDG reset)
• an independent watchdog event (IWDG reset)
• a software reset (SW reset) (see Software reset)
• a low-power mode security reset (see Low-power mode security reset)
• an option byte loader reset (see Option byte loader reset)
• a Brownout reset
The reset source can be identified by checking the reset flags in RCC control/status register
(RCC_CSR).
These sources act on the NRST pin and this pin is always kept low during the delay phase.
The reset service routine vector is selected via the Boot option bytes.
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.

RM0438 Rev 7 327/2194

427
Reset and clock control (RCC) RM0438

In case on an internal reset, the internal pull-up RPU is deactivated in order to save the
power consumption through the pull-up resistor.

Figure 29. Simplified diagram of the reset circuit

VDD

RPU
System reset

External
reset Filter
NRST WWDG reset
IWDG reset
Pulse Software reset
generator
(min 20 μs) Low-power manager reset
Option byte loader reset
POR

MSv40966V2

Software reset
The SYSRESETREQ bit in Cortex®-M33 application interrupt and reset control register
must be set to force a software reset on the device.

Low-power mode security reset

To avoid that critical applications mistakenly enter a low-power mode, two low-power mode
security resets are available. If enabled in option bytes, the resets are generated in any of
the following conditions:
• Entering Standby mode: this type of reset is enabled by resetting nRST_STDBY bit in
user option bytes. In this case, whenever a Standby mode entry sequence is
successfully executed, the device is reset instead of entering Standby mode.
• Entering Stop mode: this type of reset is enabled by resetting nRST_STOP bit in user
option bytes. In this case, whenever a Stop mode entry sequence is successfully
executed, the device is reset instead of entering Stop mode.
• Entering Shutdown mode: this type of reset is enabled by resetting nRST_SHDW bit in
user option bytes. In this case, whenever a Shutdown mode entry sequence is
successfully executed, the device is reset instead of entering Shutdown mode.
For further information on the user option bytes, refer to Section 6.4.1: Option bytes
description.

Option byte loader reset

The option byte loader reset is generated when the OBL_LAUNCH bit (#27) is set in the
FLASH_CR register. This bit is used to launch the option byte loading by software.

328/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.1.3 Backup domain reset

The Backup domain has two specific resets.
A Backup domain reset is generated when one of the following events occurs:
• a software reset, triggered by setting the BDRST bit in the RCC Backup domain control
register (RCC_BDCR)
• a VDD or VBAT power on, if both supplies have previously been powered off
A Backup domain reset only affects the LSE oscillator, the RTC, the backup registers, the
SRAM2 and the RCC_BDCR register.

9.2 RCC pins and internal signals

Table 76 lists the RCC inputs and output signals connected to package pins or balls.

Table 76. RCC input/output signals connected to package pins or balls

Signal
Signal name Description
type

NRST I/O System reset, can be used to provide reset to external devices
OSC32_IN I 32 kHz oscillator input
OSC32_OUT O 32 kHz oscillator output
OSC_IN I System oscillator input
OSC_OUT O System oscillator output
MCO1 O Output clock 1 for external devices
SAI1_EXTCLK I External kernel clock input for SAI1 digital audio interface
SAI2_EXTCLK I External kernel clock input for SAI2 digital audio interface

9.3 Clocks
Four different clock sources can be used to drive the system clock (SYSCLK):
• HSI16 (high-speed internal)16 MHz RC oscillator clock
• MSI (multispeed internal) RC oscillator clock
• HSE oscillator clock, from 4 to 48 MHz
• PLL clock
The MSI is used as system clock source after startup from reset, configured at 4 MHz.
The devices have the following additional clock sources:
• 32 kHz low-speed internal RC (LSI RC) that drives the independent watchdog and
optionally the RTC used for auto-wakeup from Stop and Standby modes
• 32.768 kHz low-speed external crystal (LSE crystal) that optionally drives the real-time
clock (RTCCLK)
• RC 48 MHz internal clock sources (HSI48) to potentially drive the USB FS, the
SDMMC and the RNG

RM0438 Rev 7 329/2194

427
Reset and clock control (RCC) RM0438

Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Several prescalers can be used to configure the AHB frequency, the APB1 and APB2
domains. The maximum frequency of the AHB, APB1 and APB2 domains is 110 MHz.
All the peripheral clocks are derived from their bus clock (HCLK, PCLK1 or PCLK2) except
the following ones:
• The 48 MHz clock used for USB FS, SDMMC and RNG, is derived from one of the
following sources (selected by software):
– main PLL VCO (PLL48M1CLK)
– PLLSAI1 VCO (PLL48M2CLK)
– MSI clock
– HSI48 internal oscillator
When the MSI clock is auto-trimmed with the LSE, it can be used by the USB FS
device.
When available, the HSI48 clock can be coupled to the clock recovery system (CRS)
allowing adequate clock connection for the USB FS (crystal less solution).
• The ADCs clock is derived from one of the following sources (selected by software):
– system clock (SYSCLK)
– PLLSAI1 VCO (PLLADC1CLK)
• The U(S)ARTs clocks are derived from one of the following sources (selected by
software):
– system clock (SYSCLK)
– HSI16 clock
– LSE clock
– APB1 or APB2 clock (PCLK1 or PCLK2, depending on which APB is mapped to
the U(S)ART)
The wakeup from Stop mode is supported only when the clock is HSI16 or LSE.
• The I2Cs clocks are derived from one of the following sources (selected by software):
– system clock (SYSCLK)
– HSI16 clock
– APB1 clock (PCLK1)
The wakeup from Stop mode is supported only when the clock is HSI16.
• The SAI1 and SAI2 clocks are derived from one of the following sources (selected by
software):
– an external clock mapped on SAI1_EXTCLK for SAI1 and SAI2_EXTCLK for SAI2
– PLLSAI1 VCO (PLLSAI1CLK)
– PLLSAI2 VCO (PLLSAI2CLK)
– main PLL VCO (PLLSAI3CLK)
– HSI16 clock
• The DFSDM audio clock which is derived from one of the following sources (selected
by software):
– SAI1 clock
– HSI clock

330/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

– MSI clock
• The OCTOSPI kernel clock is derived from one of the following sources (selected by
software):
– system clock
– PLL48M1CLK
– MSI clock
• The FDCAN kernel clock is derived from one of the following sources (selected by
software):
– PLL48M1CLK
– PLLSAI1CLK
– HSE clock
• The low-power timers (LPTIMx) clocks are derived from one of the following sources
(selected by software):
– LSI clock
– LSE clock
– HSI16 clock
– APB1 clock (PCLK1)
– external clock mapped on LPTIMx_IN1
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE, or in external clock mode.
• The RTC clock is derived from one of the following sources (selected by software):
– LSE clock
– LSI clock
– HSE clock divided by 32
The functionality in Stop mode (including wakeup) is supported only when the clock is
LSI or LSE.
• The IWDG clock which is always the LSI 32 kHz clock.
• The UCPD kernel clock is derived from HSI16 clock. The HSI16 RC oscillator must be
enabled prior enabling the UCPD.
The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or directly with the Cortex®
clock (HCLK), configurable in the SysTick control and status register.
FCLK acts as Cortex®-M33 free-running clock.

RM0438 Rev 7 331/2194

427
Reset and clock control (RCC) RM0438

Figure 30. Clock tree

to IWDG
LSI RC 32 kHz /1 or /128

LSCO

to RTC
OSC32_OUT
LSE OSC
/32
32.768 kHz
OSC32_IN
LSE to PWR
LSI
MSI to AHB bus, core, memory and DMA
MCO HSI16
/ 1→16 HSE AHB PRESC HCLK FCLK Cortex free running clock
SYSCLK / 1,2,..512
PLLCLK to Cortex system timer
HSI48 /8
Clock
source APB1 PRESC PCLK1
control / 1,2,4,8,16 to APB1 peripherals
OSC_OUT HSE OSC
4-48 MHz
HSE x1 or x2
to TIMx
OSC_IN Clock MSI x=2..7
SYSCLK
detector HSI16 LSE
HSI16 to USARTx
SYSCLK X=2..5
HSI RC to LPUART1
16 MHz

HSI16
MSI RC SYSCLK to I2Cx
100 kHz – 48 MHz x=1,2,3,4

RC 48 MHz LSI
LSE to LPTIMx
HSI16 x=1,2
MSI
PLL HSI16 MSI
/M
HSE OCTOSPI clock
/P PLLSAI3CLK

/Q PLL48M1CLK CRS clock

PLLCLK PCLK2
/R APB2 PRESC
to APB2 peripherals
HSI16 / 1,2,4,8,16
MSI
/M HSI16 x1 or x2
PLLSAI1 HSE to TIMx
PLLSAI1CLK x=1,8,15,16,17
/P
/Q PLL48M2CLK
LSE
PLLADC1CLK HSI16 to
/R SYSCLK USART1

48 SDMMC clock
HSI16 MSI MHz
48 MHz clock to USB, RNG

SYSCLK
to ADC

FDCAN HSI16
To UCPD1
MSI HSE
HSI16 MSI
/M
PLLSAI2 HSE HSI16
/P PLLSAI2CLK DFSDM
audio clock
/Q
HSI16 to SAI1
/R

SAI1_EXTCLK
to SAI2
SAI2_EXTCLK
MSv49302V3

1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the datasheet.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by a programmable factor (1, 2 or 4).
When the programmable factor is ‘1’, the AHB prescaler must be equal to ‘1’.

332/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.3.1 HSE clock

The high-speed external clock signal (HSE) can be generated from two possible clock
sources:
• HSE external crystal/ceramic resonator
• HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 31. HSE/ LSE clock sources

Clock source Hardware configuration

OSC_IN OSC_OUT
External clock
GPIO

External
source

OSC_IN OSC_OUT
Crystal/Ceramic
resonators

CL1 CL2
Load
capacitors

RM0438 Rev 7 333/2194

427
Reset and clock control (RCC) RM0438

External crystal/ceramic resonator (HSE crystal)

The 4 to 48 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 31. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the HSE
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the RCC clock interrupt enable register
(RCC_CIER).
The HSE crystal can be switched on and off using the HSEON bit in the RCC clock control
register (RCC_CR).

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
48 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the RCC clock
control register (RCC_CR). The external clock signal (square, sinus or triangle) with
~40-60 % duty cycle depending on the frequency (refer to the datasheet) must drive the
OSC_IN pin while the OSC_OUT pin can be used a GPIO (see Figure 31).

9.3.2 HSI16 clock

The HSI16 clock signal is generated from an internal 16 MHz RC oscillator.
The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no
external components). It also has a faster startup time than the HSE crystal oscillator.
However, even with calibration, the frequency is less accurate than an external crystal
oscillator or ceramic resonator.
The HSI16 clock can be selected as system clock after wakeup from Stop modes (Stop 0,
Stop 1 or Stop 2). Refer to Section 9.4: Low-power modes. It can also be used as a backup
clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 9.3.11: Clock
security system (CSS).

Calibration
The RC oscillator frequencies may vary from one chip to another due to manufacturing
process variations, this is why each device is factory calibrated by ST for 1 % accuracy at
TA = 25°C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC internal
clock sources calibration register (RCC_ICSCR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. The HSI16 frequency can be trimmed in the application using the
HSITRIM[6:0] in the RCC internal clock sources calibration register (RCC_ICSCR).
For more details on how to measure the HSI16 frequency variation, refer to Section 9.3.18:
Internal/external clock measurement with TIM15/TIM16/TIM17.
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI16 RC is
stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by
hardware.

334/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

The HSI16 RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI16 signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 9.3.11: Clock security system (CSS) on page 339.

9.3.3 MSI clock

The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be
adjusted by software by using the MSIRANGE[3:0] bits in the RCC clock control register
(RCC_CR). Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
1 MHz, 2 MHz, 4 MHz (default value), 8 MHz, 16 MHz, 24 MHz, 32 MHz and 48 MHz.
The MSI clock is used as system clock after restart from Reset, wakeup from Standby and
Shutdown low-power modes. After restart from Reset, the MSI frequency is set to its default
value 4 MHz. Refer to Section 9.4: Low-power modes.
The MSI clock can be selected as system clock after a wakeup from Stop mode (Stop 0,
Stop 1 or Stop 2). Refer to Section 9.4: Low-power modes. It can also be used as a backup
clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 9.3.11: Clock
security system (CSS).
The MSI RC oscillator has the advantage of providing a low-cost (no external components)
low-power clock source. In addition, when used in PLL-mode with the LSE, it provides a
very accurate clock source that can be used by the USB FS device, and feed the main PLL
to run the system at the maximum speed 110 MHz.
The MSIRDY flag in the RCC clock control register (RCC_CR) indicates whether the MSI
RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by
hardware. The MSI RC can be switched on and off by using the MSION bit in the RCC clock
control register (RCC_CR).

Hardware auto calibration with LSE (PLL-mode)

When a 32.768 kHz external oscillator is present in the application, it is possible to configure
the MSI in a PLL-mode by setting the MSIPLLEN bit in the RCC clock control register
(RCC_CR). When configured in PLL-mode, the MSI automatically calibrates itself thanks to
the LSE. This mode is available for all MSI frequency ranges. At 48 MHz, the MSI in PLL-
mode can be used for the USB FS device, saving the need of an external high-speed
crystal.

Software calibration
The MSI RC oscillator frequency may vary from one chip to another due to manufacturing
process variations, this is why each device is factory calibrated by ST for 1 % accuracy at an
ambient temperature, TA = 25 °C. After reset, the factory calibration value is loaded in the
MSICAL[7:0] bits in the RCC internal clock sources calibration register (RCC_ICSCR). If the
application is subject to voltage or temperature variations, this may affect the RC oscillator
speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in
the RCC_ICSCR register. For more details on how to measure the MSI frequency variation
please refer to Section 9.3.18: Internal/external clock measurement with
TIM15/TIM16/TIM17.

RM0438 Rev 7 335/2194

427
Reset and clock control (RCC) RM0438

9.3.4 HSI48 clock

The HSI48 clock signal is generated from an internal 48 MHz RC oscillator and can be used
directly for USB and for random number generator (RNG) as well as SDMMC.
The internal 48 MHz RC oscillator is mainly dedicated to provide a high-precision clock to
the USB peripheral by means of a special clock recovery system (CRS) circuitry. The CRS
can use the USB SOF signal, the LSE or an external signal to automatically and quickly
adjust the oscillator frequency on-fly. It is disabled as soon as the system enters Stop or
Standby mode. When the CRS is not used, the HSI48 RC oscillator runs on its default
frequency which is subject to manufacturing process variations.
For more details on how to configure and use the CRS peripheral please refer to Section 10:
Clock recovery system (CRS).
The HSI48RDY flag in the RCC_CRRCR register indicates whether the HSI48 RC oscillator
is stable or not. At startup, the HSI48 RC oscillator output clock is not released until this bit
is set by hardware.
The HSI48 can be switched on and off using the HSI48ON bit in the RCC_CRRCR register.

9.3.5 PLL
The device embeds three PLLs: PLL, PLLSAI1 and PLLSAI2. Each PLL provides up to
three independent outputs. The internal PLLs can be used to multiply the HSI16, HSE or
MSI output clock frequency. The PLLs input frequency must be between 4 and 16 MHz. The
selected clock source for each PLL is divided by a dedicated programmable factor PLLM,
PLLSAI1M, PLLSAI2M, from 1 to 8 to provide a clock frequency in the requested input
range. Refer to Figure 30: Clock tree, RCC PLL configuration register (RCC_PLLCFGR),
RCC PLLSAI1 configuration register (RCC_PLLSAI1CFGR) and RCC PLLSAI2
configuration register (RCC_PLLSAI2CFGR).
The PLLs configuration (selection of the input clock and multiplication factor) must be done
before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed.
To modify the PLL configuration, proceed as follows:
1. Disable the PLL by clearing PLLON to 0 in RCC clock control register (RCC_CR).
2. Wait until PLLRDY bit is cleared. The PLL is now fully stopped.
3. Change the desired parameter.
4. Enable the PLL again by setting PLLON bit to 1.
5. Enable the desired PLL outputs by configuring PLLPEN, PLLQEN, PLLREN bits in
RCC PLL configuration register (RCC_PLLCFGR).
An interrupt can be generated when the PLL is ready, if enabled in the RCC clock interrupt
enable register (RCC_CIER).

336/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

The same procedure is applied for changing the configuration of PLLSAI1 or PLLSAI2:
1. Disable the PLLSAI1/PLLSAI2 by clearing PLLSAI1ON/PLLSAI2ON to 0 in RCC clock
control register (RCC_CR).
2. Wait until PLLSAI1RDY/PLLSAI2RDY bit is cleared. The PLLSAI1/PLLSAI2 is now fully
stopped.
3. Change the desired parameter.
4. Enable the PLLSAI1/PLLSAI2 again by setting PLLSAI1ON/PLLSAI2ON bit to 1.
5. Enable the desired PLL outputs by configuring PLLSAI1PEN/PLLSAI2PEN,
PLLSAI1QEN, PLLSAI1REN bits in RCC PLLSAI1 configuration register
(RCC_PLLSAI1CFGR) or RCC PLLSAI2 configuration register (RCC_PLLSAI2CFGR).
The PLL output frequency must not exceed 110 MHz.
The enable bit of each PLL output clock (PLLPEN, PLLQEN, PLLREN, PLLSAI1PEN,
PLLSAI1QEN, PLLSAI1REN and PLLSAI2PEN) can be modified at any time without
stopping the corresponding PLL.
The PLLREN bit cannot be cleared if PLLCLK is used as system clock.

9.3.6 LSE clock

The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the
advantage of providing a low-power but highly accurate clock source to the real-time clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in RCC Backup domain control
register (RCC_BDCR). The crystal oscillator driving strength can be changed at runtime
using the LSEDRV[1:0] bits in the RCC Backup domain control register (RCC_BDCR) to
obtain the best compromise between robustness and short start-up time on one side and
low-power-consumption on the other side. The LSE drive can be decreased to the lower
drive capability (LSEDRV = 00) when the LSE is ON. However, once LSEDRV is selected,
the drive capability can not be increased if LSEON = 1.
The LSERDY flag in the RCC Backup domain control register (RCC_BDCR) indicates
whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not
released until this bit is set by hardware. An interrupt can be generated if enabled in the
RCC clock interrupt enable register (RCC_CIER).

External source (LSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to
1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC AHB1
peripheral clocks enable in Sleep and Stop modes register (RCC_AHB1SMENR). The
external clock signal (square, sinus or triangle) with ~50 % duty cycle has to drive the
OSC32_IN pin while the OSC32_OUT pin can be used as GPIO. See Figure 31.

9.3.7 LSE system clock

The LSE system clock (LSESYS) is generated by RCC to:
• a peripheral when source clock is the LSE as LPTIM, USART, LPUART, TIMER, CRS
• the system in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE
functionality is enabled
By default the LSESYS clock is disabled. To enable the LSESYS clock, proceed as follows:

RM0438 Rev 7 337/2194

427
Reset and clock control (RCC) RM0438

1. Wait the LSE clock is ready and set the LSEON and LSERDY bits in RCC Backup
domain control register (RCC_BDCR).
2. Set the LSESYSEN bit in RCC_BDCR.
3. Wait the LSESYS clock is ready and set the LSESYSRDY bit in RCC_BDCR.

9.3.8 LSI clock

The LSI RC acts as a low-power clock source that can be kept running in Stop and Standby
mode for the independent watchdog (IWDG) and RTC. The clock frequency is either 32 kHz
or 250 Hz depending on the LSIPRE bit in RCC control/status register (RCC_CSR). When
using the IWDG, only the 32 kHz LSI clock is selected and forced on. For more details, refer
to the electrical characteristics section of the datasheet.
The LSI RC can be switched on and off using the LSION bit in the RCC control/status
register (RCC_CSR).
The LSI prescaler clock (LSIPRE bit in RCC_CSR) is only taken into account when the
LSION bit is reset.
The LSIRDY flag in the RCC control/status register (RCC_CSR) indicates if the LSI
oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware.
An interrupt can be generated if enabled in the RCC clock interrupt enable register
(RCC_CIER).

9.3.9 System clock (SYSCLK) selection

Four different clock sources can be used to drive the system clock (SYSCLK):
• MSI oscillator
• HSI16 oscillator
• HSE oscillator
• PLL
The system clock maximum frequency is 110 MHz. After a system reset, the MSI oscillator,
at 4 MHz, is selected as system clock. When a clock source is used directly or through the
PLL as a system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source becomes ready. Status bits in the RCC
internal clock sources calibration register (RCC_ICSCR) indicate which clock(s) is (are)
ready and which clock is currently used as a system clock.
Clock source switching conditions:
• Switching from HSE or HSI or MSI to PLL with AHB frequency (HCLK) higher than
80 MHz
• Switching from PLL with HCLK higher than 80 MHz to HSE or HSI or MSI
Transition state:
• Set the AHB prescaler HPRE[3:0] bits in RCC_CFGR to divide the system frequency
by 2.
• Switch system clock to PLL.
• Wait for at least 1 µs and then reconfigure AHB prescaler bits to the needed HCLK
frequency.

338/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.3.10 Clock source frequency versus voltage scaling

Table 77 gives the different clock source frequencies depending on the product voltage
range.

Table 77. Clock source frequency

Clock frequency
Product voltage
range
MSI HSI16 HSE PLL/PLLSAI1/PLLSAI2

Range 0 48 MHz 16 MHz 48 MHz 110 MHz

Range 1 48 MHz 16 MHz 48 MHz 80 MHz
Range 2 24 MHz range 16 MHz 26 MHz 26 MHz

9.3.11 Clock security system (CSS)

CSS can be activated by software. In this case, the clock detector is enabled after the HSE
oscillator startups delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled, a clock
failure event is sent to the break input of the advanced-control timers (TIM1/TIM8 and
TIM15/16/17) and an interrupt is generated to inform the software about the failure (clock
security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI
is linked to the Cortex®-M33 NMI (non-maskable interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSSI occurs and a NMI is
automatically generated. The NMI is executed indefinitely unless the CSSI pending bit is
cleared. As a consequence, in the NMI ISR, the user must clear the CSSI by setting the
CSSC bit in the RCC clock interrupt clear register (RCC_CICR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the MSI or the HSI16 oscillator depending on the
STOPWUCK configuration in the RCC clock configuration register (RCC_CFGR), and the
disabling of the HSE oscillator. If the HSE clock (divided or not) is the clock entry of the PLL
used as system clock when the failure occurs, the PLL is disabled too.

9.3.12 Clock security system on LSE

A clock security system on LSE can be activated by software writing the LSECSSON bit in
the RCC Backup domain control register (RCC_BDCR). This bit can be disabled only by a
hardware reset or RTC software reset, or after a failure detection on LSE. LSECSSON must
be written after LSE and LSI are enabled (LSEON and LSION enabled) and ready (LSERDY
and LSIRDY set by hardware, LSIPRE disabled), and after the RTC clock has been
selected by RTCSEL.
The CSS on LSE is working in all modes except VBAT. It is working also under system reset
(excluding power-on reset). If a failure is detected on the external 32 kHz oscillator, the LSE
clock is no longer supplied to the RTC but no hardware action is made to the registers. If the
MSI was in PLL-mode, this mode is disabled.
The CSS on LSE failure is detected by a tamper event.

RM0438 Rev 7 339/2194

427
Reset and clock control (RCC) RM0438

In Standby mode a wakeup is generated. In other modes a TAMP interrupt can be sent to
wake up the software (see Table 310: TAMP interconnection and Section 42.5: TAMP
interrupts).
The software must then disable the LSECSSON bit, stop the defective 32 kHz oscillator
(disabling LSEON), and change the RTC clock source (no clock or LSI or HSE, with
RTCSEL), or take any required action to secure the application.
The frequency of LSE oscillator have to be higher than 30 kHz to avoid false positive CSS
detection.

9.3.13 ADC clock

The ADC clock is derived from the system clock, or from the PLLSAI1 or the PLLSAI2
output. It can reach 110 MHz and can be divided by the following prescalers values:
1,2,4,6,8,10,12,16,32,64,128 or 256 by configuring the ADC1_CCR register. It is
asynchronous to the AHB clock.
Alternatively, the ADC clock can be derived from the AHB clock of the ADC bus interface,
divided by a programmable factor (1, 2 or 4). This programmable factor is configured using
the CKMODE bit fields in the ADC123_CCR register.
If the programmed factor is 1, the AHB prescaler must be set to 1.

9.3.14 RTC clock

The RTCCLK clock source can be either the HSE / 32, LSE or LSI clock. It is selected by
programming the RTCSEL[1:0] bits in the RCC Backup domain control register
(RCC_BDCR). This selection cannot be modified without resetting the Backup domain. The
system must always be configured so as to get a PCLK frequency greater then or equal to
the RTCCLK frequency for a proper operation of the RTC.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
• If LSE is selected as RTC clock, the RTC continues to work even if the VDD supply is
switched off, provided the VBAT supply is maintained.
• If LSI is selected as the RTC clock, the RTC state is not guaranteed if the VDD supply is
powered off.
• If the HSE clock divided by a prescaler is used as the RTC clock, the RTC state is not
guaranteed if the VDD supply is powered off or if the internal voltage regulator is
powered off (removing power from the VCORE domain).
When the RTC clock is LSE or LSI, the RTC remains clocked and functional under system
reset.

9.3.15 Timer clock

The timer clock frequencies are automatically defined by hardware.
There are two cases:
• If the APB prescaler equals 1, the timer clock frequencies are set to the APB domain
frequency.
• Otherwise, they are set to twice (×2) the APB domain frequency.

340/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.3.16 Watchdog clock

If the independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced on and cannot be disabled. After the LSI oscillator
temporization, the LSI 32 kHz clock is provided to the IWDG.

9.3.17 Clock-out capability

• MCO
The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. One of eight clock signals can be selected as MCO clock.
– LSI
– LSE
– SYSCLK
– HSI16
– HSI48
– HSE
– PLLCLK
– MSI
The selection is controlled by the MCOSEL[3:0] bits of the RCC clock configuration
register (RCC_CFGR). The selected clock can be divided with the MCOPRE[2:0] field
of the RCC clock configuration register (RCC_CFGR).
• LSCO
Another output (LSCO) allows one of the low-speed clocks below to be output onto the
external LSCO pin:
– LSI
– LSE
This output remains available in Stop (Stop 0, Stop 1 and Stop 2) and Standby modes.
The selection is controlled by the LSCOSEL bit and enabled with the LSCOEN in the
RCC Backup domain control register (RCC_BDCR).
The MCO clock output requires the corresponding alternate function selected on the MCO
pin. The LSCO pin must be left in default POR state.

9.3.18 Internal/external clock measurement with TIM15/TIM16/TIM17

It is possible to indirectly measure the frequency of all on-board clock sources by mean of
the TIM15, TIM16 or TIM17 channel 1 input capture, as represented Figure 32, Figure 33
and Figure 34.

RM0438 Rev 7 341/2194

427
Reset and clock control (RCC) RM0438

Figure 32. Frequency measurement with TIM15 in capture mode

TIM 15

TI1_RMP

GPIO TI1

LSE

MS33433V1

The input capture channel of the Timer 15 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP bit in the TIM15_OR register. The
possibilities are the following ones:
• TIM15 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM15 Channel1 is connected to the LSE.

Figure 33. Frequency measurement with TIM16 in capture mode

TIM16

TI1_RMP[1:0]
GPIO
TI1
LSI
LSE
RTC wakeup interrupt
MS33434V1

The input capture channel of the Timer 16 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM16_OR register.
The possibilities are the following ones:
• TIM16 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM16 Channel1 is connected to the LSI clock.
• TIM16 Channel1 is connected to the LSE clock.
• TIM16 Channel1 is connected to the RTC wakeup interrupt signal. In this case the RTC
interrupt should be enabled.

342/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Figure 34. Frequency measurement with TIM17 in capture mode

TIM17

TI1_RMP[1:0]
GPIO
TI1
MSI
HSE/32
MCO
MS33435V1

The input capture channel of the Timer 17 can be a GPIO line or an internal clock of the
MCU. This selection is performed through the TI1_RMP[1:0] bits in the TIM17_OR register.
The possibilities are the following ones:
• TIM17 Channel1 is connected to the GPIO. Refer to the alternate function mapping in
the device datasheets.
• TIM17 Channel1 is connected to the MSI Clock.
• TIM17 Channel1 is connected to the HSE/32 Clock.
• TIM17 Channel1 is connected to the microcontroller clock output (MCO), this selection
is controlled by the MCOSEL[3:0] bits of the RCC_CFGR register.

Calibration of the HSI16 and the MSI

For TIM15 and TIM16, the primary purpose of connecting the LSE to the channel 1 input
capture is to be able to precisely measure the HSI16 and MSI system clocks (for this, either
HSI16 or MSI must be used as system clock source). The number of HSI16 (MSI,
respectively) clock counts between consecutive edges of the LSE signal provides a
measure of the internal clock period. Taking advantage of the high precision of LSE crystals
(typically a few tens of ppms), it is possible to determine the internal clock frequency with
the same resolution, and trim the source to compensate manufacturing, process,
temperature and/or voltage related frequency deviations.
The MSI and HSI16 oscillator both have dedicated user-accessible calibration bits for this
purpose.
The basic concept consists in providing a relative measurement (such as the HSI16/LSE
ratio). The precision is therefore closely related to the ratio between the two clock sources.
The higher the ratio is, the better the measurement is. If LSE is not available, HSE/32 is the
better option in order to reach the most precise calibration possible.
It is however not possible to have a good enough resolution when the MSI clock is low
(typically below 1 MHz). In this case, the following steps are needed:
1. Accumulate the results of several captures in a row.
2. Use the timer input capture prescaler (up to 1 capture every 8 periods).
3. Use the RTC wakeup interrupt signal (when the RTC is clocked by the LSE) as the
input for the channel1 input capture. This improves the measurement precision. For
this purpose the RTC wakeup interrupt must be enabled.

RM0438 Rev 7 343/2194

427
Reset and clock control (RCC) RM0438

Calibration of the LSI

The calibration of the LSI follows the same pattern that for the HSI16, but changing the
reference clock. It is necessary to connect LSI clock to the channel 1 input capture of the
TIM16. Then defining the HSE as system clock source, the number of its clock counts
between consecutive edges of the LSI signal provides a measure of the internal low-speed
clock period.
The basic concept consists in providing a relative measurement (such as the HSE/LSI
ratio). The precision is therefore closely related to the ratio between the two clock sources.
The higher the ratio is, the better the measurement is.

9.3.19 Peripheral clock enable registers

(RCC_AHBxENR, RCC_APBxENRy)
Each peripheral clock can be enabled by the corresponding EN bit in the RCC_AHBxENR
and RCC_APBxENRy registers.
When the peripheral clock is not active, read or write accesses to the peripheral registers
are not supported.
The enable bit has a synchronization mechanism to create a glitch-free clock for the
peripheral. After the enable bit is set, there is a 2-clock-cycles delay before the clock is
active.
Caution: Just after enabling the clock for a peripheral, the software must wait for a delay before
accessing the peripheral registers.

9.4 Low-power modes

• AHB and APB peripheral clocks, including DMA clock, can be disabled by software.
• Sleep and Low-power sleep modes stop the CPU clock. The memory interface clocks
(Flash memory, SRAM1 and SRAM2 interfaces) can be stopped by software during
Sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep
mode when all the clocks of the peripherals connected to them are disabled.
• Stop modes (Stop 0, Stop 1 and Stop 2) stop all the clocks in the VCORE domain and
disable the three PLL, HSI16, MSI and HSE oscillators.
All U(S)ARTs, LPUARTs and I2Cs have the capability to enable the HSI16 oscillator
even when the MCU is in Stop mode (if HSI16 is selected as the clock source for that
peripheral).
All U(S)ARTs and LPUARTs can also be driven by the LSE oscillator when the system
is in Stop mode (if LSE is selected as clock source for that peripheral) and the LSE
oscillator is enabled (LSEON). In that case the LSE remains always ON in Stop mode
(no capability to turn on the LSE oscillator).
• Standby and Shutdown modes stop all the clocks in the VCORE domain and disable the
PLLs, HSI16, MSI and HSE oscillators.
The CPU’s deepsleep mode can be overridden for debugging by setting the DBG_STOP or
DBG_STANDBY bits in the DBGMCU_CR register.
When exiting Stop modes (Stop 0, Stop 1 or Stop 2), the system clock is either MSI or
HSI16, depending on the software configuration of the STOPWUCK bit in the RCC_CFGR
register. The frequency (range and user trim) of the MSI oscillator is the one configured

344/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

before entering Stop mode. The user trim of HSI16 is kept. If the MSI was in PLL-mode
before entering Stop mode, the PLL-mode stabilization time must be waited for after wakeup
even if the LSE was kept ON during the Stop mode.
When leaving the Standby and Shutdown modes, the system clock is MSI. The MSI
frequency at wakeup from Standby mode is configured with the MSISRANGE is the
RCC_CSR register, from 1 to 8 MHz. The MSI frequency at wakeup from Shutdown mode is
4 MHz. The user trim is lost.
If a Flash memory programming operation is on going, Stop, Standby and Shutdown modes
entry is delayed until the Flash memory interface access is finished. If an access to the APB
domain is ongoing, Stop, Standby and Shutdown modes entry is delayed until the APB
access is finished.

9.5 RCC TrustZone® security

When the TrustZone security is activated by the TZEN option bit in the FLASH_OPTR
register, the RCC is able to secure RCC configuration and status bits from being modified by
non-secure accesses.
This is configured through the security configuration register RCC_SECCFGR to prevent
non-secure access to read or modify the following features:
• HSE, HSE-CSS, HSI, MSI, LSI, LSE, LSE-CSS, HSI48 configuration and status bits
• main PLL, PLLSAI1, PLLSAI2, AHB prescaler configuration and status bits
• system clock SYSCLK and HSI48 source clock selection and status bits
• MCO clock output configuration and STOPWUCK bit
• reset flag RMVF configuration
When a peripheral is configured as secure, its related clock, reset, clock source selection
and clock enable during low-power modes control bits are also secure in the
RCC_AHBxENR, RCC_APBxENR, RCC_AHBxSMEN, RCC_APBxSMEN, RCC_CCIPR1
and RCC_CCIPR2 registers.
A peripheral is secure when:
• For securable peripherals by TZSC (TrustZone security controller), the SEC security bit
corresponding to this peripheral is set in the TZSC_SECCFGRx register.
• For TrustZone-aware peripherals, a security feature of this peripheral is enabled
through its dedicated bits.
Table 78 gives a summary of the RCC secured bits following the security configuration bit in
the RCC_SECCFGR register.
When one security configuration bit is set, some configuration and status bits are secured.
The RCC registers may contain secure and non-secure bits:
• Secured bits: read and write operations are only allowed by a secure access. Non-
secure read or write accesses are RAZ/WI. There is no illegal access event generated.
• Non-secure bits: no restriction. Read and write operations are allowed by both secure
and non-secure accesses.
• A non-secure read/write access to RCC_SECCFGR register is RAZ/WI and generates
an illegal access event. An illegal access interrupt is generated if the RCC illegal
access interrupt is enabled in the TZIC_IER2 register.

RM0438 Rev 7 345/2194

427
Reset and clock control (RCC) RM0438

When the TrustZone security is disabled (TZEN = 0 in FLASH_OPTR register), all registers
are non-secure. The RCC_SECCFGR secure register and security status registers are
RAZ/WI.

Table 78. RCC security configuration summary

Configuration bit in Corresponding
Secured bits
RCC_SECCFGR register

HSION, HSIKERON, HSIRDY, HSIASFS RCC_CR

HSICAL[7:0], HSITRIM[6:0] RCC_ICSCR
HSISEC
HSIRDYIE RCC_CIER
HSIRDYC RCC_CICR
HSEON, HSERDY, HSEBYP, HSECSSON RCC_CR
HSESEC HSERDYIE RCC_CIER
HSERDYC, HSECSSC RCC_CICR
MSION, MSIRDY, MSIPLLEN, MSIRGSEL, MSISRANGE[3:0] RCC_CR
MSICAL[7:0], MSITRIM[7:0] RCC_ICSCR
MSISEC
MISIRANGE[3:0] RCC_CSR
MSIRDYIE RCC_CIER
LSIO, LSIRDY, LSIPRE RCC_CSR
LSISEC LSIRDYIE RCC_CIER
LSIRDYC RCC_CICR
LSECSSON, LSECSSD, LSEDRV[1:0], LSEBYP, LSERDY,
RCC_BDCR
LSEON, LSCOSEL, LSCOEN
LSESEC
LSERDYIE, LSECSSIE RCC_CIER
LSERDYC, LSECSSC RCC_CICR
SW[1:0], SWS[1:0], STOPWUCK, MCOSEL[3:0], MCOPRE[2:0], RCC_CFGR
SYSCLKSEC
VOS[1:0] PWR_CR1
PRESCSEC HPRE[3:0], PPRE1[2:0], PPRE2[2:0] RCC_CFGR
PLLSRC[1:0], PLLM[3:0], PLLN[6:0], PLLPDIV[4:0], PLLR[1:0],
RCC_PLLCFGR
PLLREN, PLLQ[1:0], PLLP, PLLPEN, PLLQEN

PLLSEC PLLRDY, PLLON RCC_CR

PLLRDYIE RCC_CIER
PLLRDYC RCC_CICR
PLLSAI1PDIV[4:0], PLLSAI1R[1:0], PLLSAI1REN, PLLSAI1Q[1:0],
PLLSAI1QEN, PLLSAI1P, PLLSAI1PEN, PLLSAI1N[6:0], RCC_PLLSAI1CFGR
PLLSAI1M[3:0], PLLSAI1SRC[1:0]
PLLSAI1SEC PLLSAI1RDY, PLLSAI1ON RCC_CR
PLLSAI1RDYIE RCC_CIER
PLLSAI1RDYC RCC_CICR

346/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Table 78. RCC security configuration summary (continued)

Configuration bit in Corresponding
Secured bits
RCC_SECCFGR register

PLLSAI2PDIV[4:0], PLLSAI2P, PLLSAI2PEN, PLLSAI2N[6:0],

RCC_PLLSAI2CFGR
PLLSAI2M[3:0], PLLSAI2SRC[1:0]

PLLSAI2SEC PLLSAI2RDY, PLLSAI2ON RCC_CR

PLLSAI2RDYIE RCC_CIER
PLLSAI2RDYC RCC_CICR
HSI48CAL[8:0], HSI48RDY RCC_CRRCR
HSI48SEC HSI48RDYE RCC_CIER
HSI48RDYC RCC_CICR
CLK48MSEC CLK48MSEL[1:0] RCC_CCIPR1
RMVFSEC RMVF RCC_CSR

9.6 RCC Privileged and Unprivileged mode

By default, after reset, all RCC registers can be read or written in both Privileged and
Unprivileged modes except RCC privilege bit (PRIV bit in RCC_CR) that can be written in
Privilege mode only.
When the PRIV bit is set in RCC_CR register:
• Writing the RCC registers is possible only in privileged mode.
• All RCC registers can be read only in privileged mode except RCC security status
registers (RCC_AHBxSECSR, RCC_APBx_SECSR, RCC_SECSR) and PRIV bit in
RCC_CR register.
• An unprivileged access to a privileged RCC register is discarded. RAZ/WI.

9.7 RCC interrupts

The RCC provides three interrupt lines:
• rcc_it: general interrupt line providing events when the PLLs are ready or when the
oscillators are ready
• rcc_hsecss_it: interrupt line dedicated to the failure detection of the HSE CSS (clock
security system)
• rcc_lsecss_it: interrupt line dedicated to the failure detection of the LSE CSS
The interrupt enable is controlled via RCC clock interrupt enable register (RCC_CIER),
except for the HSE CSS failure. When the HSE CSS feature is enabled, it not possible to
mask the interrupt generation.
The interrupt flags can be checked via RCC clock interrupt flag register (RCC_CIFR), and
those flags can be cleared via RCC clock interrupt clear register (RCC_CICR).
Note: The interrupt flags are not relevant if the corresponding interrupt enable bit is not set.
Table 79 gives a summary of the interrupt sources and the way to control them.

RM0438 Rev 7 347/2194

427
Reset and clock control (RCC) RM0438

Table 79. Interrupt sources and control(1)

Interrupt
Interrupt Interrupt Enable
Description Interrupt clear method internal
vector event flag control bit
signal

LSIRDYF LSI ready LSIRDYIE Set LSIRDYC to 1

LSERDYF LSE ready LSERDYIE Set LSERDYC to 1
HSIDRYF HSI ready HSIDRYIE Set HSIRDYC to 1
HSERDYF HSE ready HSERDYIE Set HSERDYC to 1
RCC
CSIRDYF CSI ready CSIRDYIE Set CSIRDYC to 1 rcc_it
RCC_S
HSI48RDYF HSI48 ready HSI48RDYIE Set HSI48RDYC to 1
PLLRDYF PLL ready PLLRDYIE Set PLLRDYC to 1
PLLSAI1RDYF PLLSAI1 ready PLLSAI1RDYIE Set PLLSAI1RDYC to 1
PLLSAI2RDYF PLLSAI2 ready PLLSAI2RDYIE Set PLLSAI2RDYC to 1
TAMP
ITAMP3F LSE CSS failure ITAMP3IE (2) Set CITAMP3F to 1 rcc_lsecss_it
TAMP_S
NMI HSECSSF HSE CSS failure -(3) Set HSECSSC to 1 rcc_hsecss_it
1. When TrustZone is enabled, two interrupt vectors are available for secure and non-secure events.
2. The security system feature must also be enabled (LSECSSON = 1), in order to generate interrupts.
3. It is not possible to mask this interrupt when the security system feature is enabled (HSECSSON = 1).

348/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8 RCC registers

9.8.1 RCC clock control register (RCC_CR)

Address offset: 0x000
Reset value: 0x0000 0063
HSEBYP is cleared upon power-on reset. It is not affected upon other types of reset.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PLLSAI2RDY

PLLSAI1RDY
PLLSAI2ON

PLLSAI1ON

HSERDY
HSEBYP
PLLRDY

CSSON

HSEON
PRIV Res. PLLON Res. Res. Res. Res.

rw r rw r rw r rw rs rw r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIKERON

MSIRGSEL

MSIPLLEN
HSIASFS

MSIRDY
HSIRDY

Res. Res. Res. Res. HSION MSIRANGE[3:0] MSION

rw r rw rw rw rw rw rw rs rw r rw

Bit 31 PRIV: RCC privilege

Set and reset by software. This bit can be read by both privileged or unprivileged access.
when set, it can only be cleared by a privileged access.
0: RCC registers can be accessed by a privileged or non-privileged access.
1: RCC registers can be accessed only by a privileged access except RCC_AHBxSECSR,
RCC_APBx_SECSR and RCC_SECSR.
An unprivileged access to RCC registers is RAZ/WI.
If TrustZone security is enabled (TZEN = 1), when the RCC is not secure, the PRIV bit can
be written by a secure or non-secure privileged access.
If the RCC is secure, the PRIV bit can be written only by a secure privileged access. A non-
secure write access is ignored.
A secure unprivileged write access on PRIV bit is ignored.
Bit 30 Reserved, must be kept at reset value.
Bit 29 PLLSAI2RDY: SAI2 PLL clock ready flag
Set by hardware to indicate that the PLLSAI2 is locked.
0: PLLSAI2 unlocked
1: PLLSAI2 locked
Bit 28 PLLSAI2ON: SAI2 PLL enable
Set and cleared by software to enable PLLSAI2.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI2 OFF
1: PLLSAI2 ON
Bit 27 PLLSAI1RDY: SAI1 PLL clock ready flag
Set by hardware to indicate that the PLLSAI1 is locked.
0: PLLSAI1 unlocked
1: PLLSAI1 locked

RM0438 Rev 7 349/2194

427
Reset and clock control (RCC) RM0438

Bit 26 PLLSAI1ON: SAI1 PLL enable

Set and cleared by software to enable PLLSAI1.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI1 OFF
1: PLLSAI1 ON
Bit 25 PLLRDY: main PLL clock ready flag
Set by hardware to indicate that the main PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: main PLL enable
Set and cleared by software to enable the main PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be
reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: clock security system enable
Set by software to enable the clock security system. When CSSON is set, the clock detector
is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if a HSE
clock failure is detected. This bit is set only and is cleared by reset.
0: clock security system OFF (clock detector OFF)
1: clock security system ON (clock detector ON if the HSE oscillator is stable, OFF if not).
Bit 18 HSEBYP: HSE crystal oscillator bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit set, to be used by the device. The HSEBYP bit
can be written only if the HSE oscillator is disabled.
0: HSE crystal oscillator not bypassed
1: HSE crystal oscillator bypassed with external clock
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable.
0: HSE oscillator not ready
1: HSE oscillator ready
Note: Once the HSEON bit is cleared, HSERDY goes low after 6 HSE clock cycles.
Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop, Standby or Shutdown
mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system
clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 HSIASFS: HSI16 automatic start from Stop
Set and cleared by software. When the system wakeup clock is MSI, this bit is used to
wakeup the HSI16 is parallel of the system wakeup.
0: HSI16 oscillator is not enabled by hardware when exiting Stop mode with MSI as wakeup
clock.
1: HSI16 oscillator is enabled by hardware when exiting Stop mode with MSI as wakeup
clock.

350/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 10 HSIRDY: HSI16 clock ready flag

Set by hardware to indicate that HSI16 oscillator is stable. This bit is set only when HSI16 is
enabled by software by setting HSION.
0: HSI16 oscillator not ready
1: HSI16 oscillator ready
Note: Once the HSION bit is cleared, HSIRDY goes low after 6 HSI16 clock cycles.
Bit 9 HSIKERON: HSI16 always enable for peripheral kernels.
Set and cleared by software to force HSI16 ON even in Stop modes. The HSI16 can only
feed USARTs and I2Cs peripherals configured with HSI16 as kernel clock. Keeping the
HSI16 ON in Stop mode allows to avoid slowing down the communication speed because of
the HSI16 startup time. This bit has no effect on HSION value.
0: No effect on HSI16 oscillator.
1: HSI16 oscillator is forced ON even in Stop mode.
Bit 8 HSION: HSI16 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI16 oscillator when entering Stop, Standby or Shutdown
mode.
Set by hardware to force the HSI16 oscillator ON when STOPWUCK=1 or HSIASFS = 1
when leaving Stop modes, or in case of failure of the HSE crystal oscillator.
This bit is set by hardware if the HSI16 is used directly or indirectly as system clock.
0: HSI16 oscillator OFF
1: HSI16 oscillator ON
Bits 7:4 MSIRANGE[3:0]: MSI clock ranges
These bits are configured by software to choose the frequency range of MSI when
MSIRGSEL is set.12 frequency ranges are available:
0000: range 0 around 100 kHz
0001: range 1 around 200 kHz
0010: range 2 around 400 kHz
0011: range 3 around 800 kHz
0100: range 4 around 1M Hz
0101: range 5 around 2 MHz
0110: range 6 around 4 MHz (reset value)
0111: range 7 around 8 MHz
1000: range 8 around 16 MHz
1001: range 9 around 24 MHz
1010: range 10 around 32 MHz
1011: range 11 around 48 MHz
others: not allowed (hardware write protection)
Note: Warning: MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is
ready (MSIRDY=1). MSIRANGE must NOT be modified when MSI is ON and NOT
ready (MSION=1 and MSIRDY=0)
Bit 3 MSIRGSEL: MSI clock range selection
Set by software to select the MSI clock range with MSIRANGE[3:0]. Write 0 has no effect.
After a standby or a reset MSIRGSEL is at 0 and the MSI range value is provided by
MSISRANGE in CSR register.
0: MSI Range is provided by MSISRANGE[3:0] in RCC_CSR register
1: MSI Range is provided by MSIRANGE[3:0] in the RCC_CR register

RM0438 Rev 7 351/2194

427
Reset and clock control (RCC) RM0438

Bit 2 MSIPLLEN: MSI clock PLL enable

Set and cleared by software to enable/ disable the PLL part of the MSI clock source.
MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set
by hardware).There is a hardware protection to avoid enabling MSIPLLEN if LSE is not
ready.
This bit is cleared by hardware when LSE is disabled (LSEON = 0) or when the Clock
Security System on LSE detects a LSE failure (refer to RCC_CSR register).
0: MSI PLL OFF
1: MSI PLL ON
Bit 1 MSIRDY: MSI clock ready flag
This bit is set by hardware to indicate that the MSI oscillator is stable.
0: MSI oscillator not ready
1: MSI oscillator ready
Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles.
Bit 0 MSION: MSI clock enable
This bit is set and cleared by software.
Cleared by hardware to stop the MSI oscillator when entering Stop, Standby or Shutdown
mode.
Set by hardware to force the MSI oscillator ON when exiting Standby or Shutdown mode.
Set by hardware to force the MSI oscillator ON when STOPWUCK=0 when exiting from Stop
modes, or in case of a failure of the HSE oscillator
Set by hardware when used directly or indirectly as system clock.
0: MSI oscillator OFF
1: MSI oscillator ON

9.8.2 RCC internal clock sources calibration register (RCC_ICSCR)

Address offset: 0x004
Reset value: 0x40XX 00XX
X is factory-programmed.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. HSITRIM[6:0] HSICAL[7:0]
rw rw rw rw rw rw rw r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSITRIM[7:0] MSICAL[7:0]
rw rw rw rw rw rw rw rw r r r r r r r r

Bit 31 Reserved, must be kept at reset value.

Bits 30:24 HSITRIM[6:0]: HSI16 clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature that
influence the frequency of the HSI16.

352/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 23:16 HSICAL[7:0]: HSI16 clock calibration

These bits are initialized at startup with the factory-programmed HSI16 calibration trim value.
When HSITRIM is written, HSICAL is updated with the sum of HSITRIM and the factory trim
value.
Bits 15:8 MSITRIM[7:0]: MSI clock trimming
These bits provide an additional user-programmable trimming value that is added to the
MSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the MSI.
Bits 7:0 MSICAL[7:0]: MSI clock calibration
These bits are initialized at startup with the factory-programmed MSI calibration trim value.
When MSITRIM is written, MSICAL is updated with the sum of MSITRIM and the factory trim
value.

9.8.3 RCC clock configuration register (RCC_CFGR)

Address offset: 0x008
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states are inserted only if the access occurs during clock source switch.
From 0 to 15 wait states are inserted if the access occurs when the APB or AHB prescalers
values update is on going.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. MCOPRE[2:0] MCOSEL[3:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STOPWUCK

Res. PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]

rw rw rw rw rw rw rw rw rw rw rw r r rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:28 MCOPRE[2:0]: microcontroller clock output prescaler
These bits are set and cleared by software.
It is highly recommended to change this prescaler before MCO output is enabled.
000: MCO divided by 1
001: MCO divided by 2
010: MCO divided by 4
011: MCO divided by 8
100: MCO divided by 16
Others: not allowed

RM0438 Rev 7 353/2194

427
Reset and clock control (RCC) RM0438

Bits 27:24 MCOSEL[3:0]: microcontroller clock output

Set and cleared by software.
0000: MCO output disabled, no clock on MCO
0001: SYSCLK system clock selected
0010: MSI clock selected
0011: HSI16 clock selected
0100: HSE clock selected
0101: Main PLL clock selected
0110: LSI clock selected
0111: LSE clock selected
1000: Internal HSI48 clock selected
Others: reserved
Note: This clock output may have some truncated cycles at startup or during MCO clock
source switching.
Bits 23:16 Reserved, must be kept at reset value.
Bit 15 STOPWUCK: wakeup from Stop and CSS backup clock selection
Set and cleared by software to select the system clock used when exiting Stop mode.
The selected clock is also used as emergency clock for the clock security system on HSE.
Warning: STOPWUCK must not be modified when the CSS is enabled by HSECSSON bit in
the RCC_CR register and the system clock is HSE (SWS=”10”) or a switch on HSE is
requested (SW=”10”).
0: MSI oscillator selected as wakeup from stop clock and CSS backup clock
1: HSI16 oscillator selected as wakeup from stop clock and CSS backup clock
Bit 14 Reserved, must be kept at reset value.
Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2)
Set and cleared by software to control the division factor of the APB2 clock (PCLK2).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
Bits 10:8 PPRE1[2:0]:APB low-speed prescaler (APB1)
Set and cleared by software to control the division factor of the APB1 clock (PCLK1).
0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

354/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 7:4 HPRE[3:0]: AHB prescaler

Set and cleared by software to control the division factor of the AHB clock.
Caution: Depending on the device voltage range, the software must set correctly
these bits to ensure that the system frequency does not exceed the
maximum allowed frequency (for more details, refer to Section 8.2.5:
Dynamic voltage scaling management). After a write operation to these
bits and before decreasing the voltage range, this register must be read
to be sure that the new value has been taken into account.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
Bits 3:2 SWS[1:0]: system clock switch status
Set and cleared by hardware to indicate which clock source is used as system clock.
00: MSI oscillator used as system clock
01: HSI16 oscillator used as system clock
10: HSE used as system clock
11: PLL used as system clock
Bits 1:0 SW[1:0]: system clock switch
Set and cleared by software to select system clock source (SYSCLK).
Configured by hardware to force MSI oscillator selection when exiting Standby or Shutdown
mode. Configured by hardware to force MSI or HSI16 oscillator selection when exiting Stop
mode or in case of failure of the HSE oscillator, depending on STOPWUCK value.
00: MSI selected as system clock
01: HSI16 selected as system clock
10: HSE selected as system clock
11: PLL selected as system clock

RM0438 Rev 7 355/2194

427
Reset and clock control (RCC) RM0438

9.8.4 RCC PLL configuration register (RCC_PLLCFGR)

Address offset: 0x00C
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLLQEN
PLLREN

PLLPEN
PLLPDIV[4:0] PLLR[1:0] Res. PLLQ[1:0] Res. Res. PLLP

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. PLLN[6:0] PLLM[3:0] Res. Res. PLLSRC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 PLLPDIV[4:0]: Main PLL division factor for PLLSAI3CLK

Set and cleared by software to control the SAI1 or SAI2 clock frequency.
PLLSAI3CLK output clock frequency = VCO frequency / PLLPDIV.
00000: PLLSAI3CLK is controlled by the bit PLLP
00001: Reserved
00010: PLLSAI3CLK = VCO / 2
....
11111: PLLSAI3CLK = VCO / 31
Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock)
Set and cleared by software to control the frequency of the main PLL output clock PLLCLK.
This output can be selected as system clock. These bits can be written only if PLL is
disabled.
PLLCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8
00: PLLR = 2
01: PLLR = 4
10: PLLR = 6
11: PLLR = 8
Caution: The software must set these bits correctly not to exceed 110 MHz on
this domain.
Bit 24 PLLREN: Main PLL PLLCLK output enable
Set and reset by software to enable the PLLCLK output of the main PLL (used as system
clock).
This bit cannot be written when PLLCLK output of the PLL is used as system clock.
In order to save power, when the PLLCLK output of the PLL is not used, the value of
PLLREN must be 0.
0: PLLCLK output disabled
1: PLLCLK output enabled

356/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 23 Reserved, must be kept at reset value.

Bits 22:21 PLLQ[1:0]: Main PLL division factor for PLL48M1CLK (48 MHz clock)
Set and cleared by software to control the frequency of the main PLL output clock
PLL48M1CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLL is disabled.
PLL48M1CLK output clock frequency = VCO frequency / PLLQ with PLLQ = 2, 4, 6, or 8
00: PLLQ = 2
01: PLLQ = 4
10: PLLQ = 6
11: PLLQ = 8
Caution: The software must set these bits correctly not to exceed 80 MHz on this
domain.
Bit 20 PLLQEN: Main PLL PLL48M1CLK output enable
Set and reset by software to enable the PLL48M1CLK output of the main PLL.
In order to save power, when the PLL48M1CLK output of the PLL is not used, the value of
PLLQEN must be 0.
0: PLL48M1CLK output disabled
1: PLL48M1CLK output enabled
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLP: Main PLL division factor for PLLSAI3CLK (SAI1 and SAI2 clock)
Set and cleared by software to control the frequency of the main PLL output clock
PLLSAI3CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
PLL is disabled.
When the PLLPDIV[4:0] is set to 0x0, PLLSAI3CLK output clock frequency = VCO
frequency / PLLP with PLLP =7, or 17.
0: PLLP = 7
1: PLLP = 17
Caution: The software must set these bits correctly not to exceed 80 MHz on this
domain.
Bit 16 PLLPEN: Main PLL PLLSAI3CLK output enable
Set and reset by software to enable the PLLSAI3CLK output of the main PLL.
In order to save power, when the PLLSAI3CLK output of the PLL is not used, the value of
PLLPEN must be 0.
0: PLLSAI3CLK output disabled
1: PLLSAI3CLK output enabled
Bit 15 Reserved, must be kept at reset value.

RM0438 Rev 7 357/2194

427
Reset and clock control (RCC) RM0438

Bits 14:8 PLLN[6:0]: Main PLL multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO.
These bits can be written only when the PLL is disabled.
VCO output frequency = VCO input frequency * PLLN with 8 ≤ PLLN ≤ 86
0000000: PLLN = 0 wrong configuration
0000001: PLLN = 1 wrong configuration
...
0000111: PLLN = 7 wrong configuration
0001000: PLLN = 8
0001001: PLLN = 9
...
1111111: PLLN = 127 wrong configuration
Caution: The software must set correctly these bits to secure that the VCO output
frequency is between 64 and 344 MHz.
Bits 7:4 PLLM[3:0]: Division factor for the main PLL input clock
Set and cleared by software to divide the PLL input clock before the VCO.
These bits can be written only when all PLLs are disabled.
VCO input frequency = PLL input clock frequency / PLLM with 1 ≤ PLLM ≤ 8
0000: PLLM = 1
0001: PLLM = 2
0010: PLLM = 3
0011: PLLM = 4
0100: PLLM = 5
0101: PLLM = 6
0110: PLLM = 7
0111: PLLM = 8
...
1111: PLLM = 16
Caution: The software must set these bits correctly to ensure that the VCO input
frequency is between 4 to 16 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSRC[1:0]: Main PLL entry clock source
Set and cleared by software to select PLL clock source.
These bits can be written only when the PLL is disabled.
In order to save power, when no PLL is used, the value of PLLSRC must be 00.
00: No clock sent to PLL
01: MSI clock selected as PLL clock entry
10: HSI16 clock selected as PLL clock entry
11: HSE clock selected as PLL clock entry

358/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.5 RCC PLLSAI1 configuration register (RCC_PLLSAI1CFGR)

Address offset: 0x010
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI1 clock outputs according to the formulas:
• f(VCOSAI1 clock) = f(PLL clock input) * (PLLSAI1N / PLLM)
• f(PLLSAI1_P) = f(VCOSAI1 clock) / PLLSAI1PDIV
• f(PLLSAI1_Q) = f(VCOSAI1 clock) / PLLSAI1Q
• f(PLLSAI1_R) = f(VCOSAI1 clock) / PLLSAI1R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLLSAI1QEN
PLLSAI1REN

PLLSAI1PEN
PLLSAI1P
PLLSAI1PDIV[4:0] PLLSAI1R[1:0] Res. PLLSAI1Q[1:0] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLSAI1SRC[1:0]
Res. PLLSAI1N[6:0] PLLSAI1M[3:0] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 PLLSAI1PDIV[4:0]: PLLSAI1 division factor for PLLSAI1CLK

Set and cleared by software to control the SAI1 or SAI2 clock frequency.
PLLSAI1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1PDIV.
00000: PLLSAI1CLK controlled by PLLSAI1P bit
00001: reserved
00010: PLLSAI1CLK = VCOSAI1 / 2
....
11111: PLLSAI1CLK = VCOSAI1 / 31
Note: This bit can be written only when the PLLSAI1 is disabled.
Bits 26:25 PLLSAI1R[1:0]: PLLSAI1 division factor for PLLADC1CLK (ADC clock)
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLLADC1CLK. This output can be selected as ADC clock.
These bits can be written only if PLLSAI1 is disabled.
PLLADC1CLK output clock frequency = VCOSAI1 frequency / PLLSAI1R, with
PLLSAI1R = 2, 4, 6, or 8.
00: PLLSAI1R = 2
01: PLLSAI1R = 4
10: PLLSAI1R = 6
11: PLLSAI1R = 8

RM0438 Rev 7 359/2194

427
Reset and clock control (RCC) RM0438

Bit 24 PLLSAI1REN: PLLSAI1 PLLADC1CLK output enable

Set and reset by software to enable the PLLADC1CLK output of the PLLSAI1 (used as clock
for ADC).
In order to save power, when the PLLADC1CLK output of the PLLSAI1 is not used, the value
of PLLSAI1REN must be 0.
0: PLLADC1CLK output disabled
1: PLLADC1CLK output enabled
Bit 23 Reserved, must be kept at reset value.
Bits 22:21 PLLSAI1Q[1:0]: PLLSAI1 division factor for PLL48M2CLK (48 MHz clock)
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLL48M2CLK. This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits can be written only if PLLSAI1 is disabled.
PLL48M2CLK output clock frequency = VCOSAI1 frequency / PLLSAI1Q with
PLLSAI1Q = 2, 4, 6, or 8
00: PLLSAI1Q = 2
01: PLLSAI1Q = 4
10: PLLSAI1Q = 6
11: PLLSAI1Q = 8
Caution: The software must set these bits correctly not to exceed 110 MHz on
this domain.
Bit 20 PLLSAI1QEN: PLLSAI1 PLL48M2CLK output enable
Set and reset by software to enable the PLL48M2CLK output of the PLLSAI1.
In order to save power, when the PLL48M2CLK output of the PLLSAI1 is not used, the value
of PLLSAI1QEN must be 0.
0: PLL48M2CLK output disablde
1: PLL48M2CLK output enabled
Bits 19:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI1P: PLLSAI1 division factor for PLLSAI1CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the PLLSAI1 output clock
PLLSAI1CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
PLLSAI1 is disabled.
When the PLLSAI1PDIV[4:0] is set to 0x0, PLLSAI1CLK output clock frequency = VCOSAI1
frequency / PLLSAI1P with PLLSAI1P =7, or 17
0: PLLSAI1P = 7
1: PLLSAI1P = 17
Bit 16 PLLSAI1PEN: PLLSAI1 PLLSAI1CLK output enable
Set and reset by software to enable the PLLSAI1CLK output of the PLLSAI1.
In order to save power, when the PLLSAI1CLK output of the PLLSAI1 is not used, the value
of PLLSAI1PEN must be 0.
0: PLLSAI1CLK output disabled
1: PLLSAI1CLK output enabled
Bit 15 Reserved, must be kept at reset value.

360/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 14:8 PLLSAI1N[6:0]: PLLSAI1 multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO.
These bits can be written only when the PLLSAI1 is disabled.
VCOSAI1 output frequency = VCOSAI1 input frequency x PLLSAI1N, with
8 ≤ PLLSAI1N ≤ 86.
0000000: PLLSAI1N = 0 wrong configuration
0000001: PLLSAI1N = 1 wrong configuration
...
0000111: PLLSAI1N = 7 wrong configuration
0001000: PLLSAI1N = 8
0001001: PLLSAI1N = 9
...
1111111: PLLSAI1N = 127
Caution: The software must set correctly these bits to ensure that the VCO output
frequency is between 64 and 344 MHz.
Bits 7:4 PLLSAI1M[3:0]: Division factor for PLLSAI1 input clock
Set and reset by software to divide the PLLSAI1 input clock before the VCO.
These bits can be written only when PLLSAI1 is disabled.
VCO input frequency = PLLSAI1 input clock frequency / PLLSAI1M with 1 ≤ PLLSAI1 ≤ 16.
0000: PLLSAI1M = 1
0001: PLLSAI1M = 2
0010: PLLSAI1M = 3
0011: PLLSAI1M = 4
0100: PLLSAI1M = 5
0101: PLLSAI1M = 6
0110: PLLSAI1M = 7
0111: PLLSAI1M = 8
1000: PLLSAI1M = 9
...
1111: PLLSAI1M= 16
Caution: The software must set these bits correctly to ensure that the VCO input
frequency ranges from 2.66 to 8 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSAI1SRC[1:0]: Main PLLSAI1 entry clock source
Set and cleared by software to select PLLSAI1 clock source.
These bits can be written only when PLLSAI1 is disabled.
In order to save power, when PLLSAI1 is not used, the value of PLLSAI1 must be 00.
00: No clock sent to PLLSAI1
01: MSI clock selected as PLLSAI1 clock entry
10: HSI16 clock selected as PLLSAI1 clock entry
11: HSE clock selected as PLLSAI1 clock entry

RM0438 Rev 7 361/2194

427
Reset and clock control (RCC) RM0438

9.8.6 RCC PLLSAI2 configuration register (RCC_PLLSAI2CFGR)

Address offset: 0x014
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI2 clock outputs according to the formulas:
• f(VCOSAI2 clock) = f(PLL clock input) × (PLLSAI2N / PLLM)
• f(PLLSAI2_P) = f(VCOSAI2 clock) / PLLSAI2P
• f(PLLSAI2_R) = f(VCOSAI2 clock) / PLLSAI2R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLLSAI2PEN
PLLSAI2P
PLLSAI2PDIV[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLSAI2SRC[1:0]
Res. PLLSAI2N[6:0] PLLSAI2M[3:0] Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 PLLSAI2PDIV[4:0]: PLLSAI2 division factor for PLLSAI2CLK

Set and cleared by software to control the SAI1 or SAI2 clock frequency.
PLLSAI2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2PDIV.
00000: PLLSAI2CLK controlled by the bit PLLSAI2P
00001: reserved
00010: PLLSAI2CLK = VCOSAI2 / 2
....
11111: PLLSAI2CLK = VCOSAI2 / 31
Bits 26:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI2P: PLLSAI2 division factor for PLLSAI2CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the PLLSAI2 output clock
PLLSAI2CLK. This output can be selected for SAI1 or SAI2.
These bits can be written only if PLLSAI2 is disabled.
When the PLLSAI2PDIV[4:0] is set to 0x0, PLLSAI2CLK output clock frequency = VCOSAI2
frequency / PLLSAI2P with PLLSAI2P =7 or 17.
0: PLLSAI2P = 7
1: PLLSAI2P = 17
Bit 16 PLLSAI2PEN: PLLSAI2 PLLSAI2CLK output enable
Set and reset by software to enable the PLLSAI2CLK output of the PLLSAI2.
In order to save power, when the PLLSAI2CLK output of the PLLSAI2 is not used, the value
of PLLSAI2PEN must be 0.
0: PLLSAI2CLK output disabled
1: PLLSAI2CLK output enabled
Bit 15 Reserved, must be kept at reset value.

362/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 14:8 PLLSAI2N[6:0]: PLLSAI2 multiplication factor for VCO

Set and cleared by software to control the multiplication factor of the VCO.
These bits can be written only when the PLLSAI2 is disabled.
VCOSAI2 output frequency = VCOSAI2 input frequency x PLLSAI2N, with
8 ≤ PLLSAI2N ≤ 86
0000000: PLLSAI2N = 0 wrong configuration
0000001: PLLSAI2N = 1 wrong configuration
...
0000111: PLLSAI2N = 7 wrong configuration
0001000: PLLSAI2N = 8
0001001: PLLSAI2N = 9
...
1111111: PLLSAI2N = 127 wrong configuration
Caution: The software must set correctly these bits to ensure that the VCO output
frequency is between 64 and 344 MHz.
Bits 7:4 PLLSAI2M[3:0]: Division factor for PLLSAI2 input clock
Set and reset by software to divide the PLLSAI2 input clock before the VCO.
These bits can be written only when PLLSAI2 is disabled.
VCO input frequency = PLLSAI2 input clock frequency / PLLM with 1 ≤ PLLSAI2N ≤ 16
0000: PLLSAI2M = 1
0001: PLLSAI2M = 2
0010: PLLSAI2M = 3
0011: PLLSAI1M = 4
0100: PLLSAI2M = 5
0101: PLLSAI2M = 6
0110: PLLSAI2M = 7
0111: PLLSAI2M = 8
1000: PLLSAI2M = 9
...
1111: PLLSAI2M= 16
Caution: The software must set these bits correctly to ensure that the VCO input
frequency is between 2.66 to 8 MHz.
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 PLLSAI2SRC[1:0]: Main PLLSAI2 entry clock source
Set and cleared by software to select PLLSAI2 clock source.
These bits can be written only when PLLSAI2 is disabled.
In order to save power, when PLLSAI2 is not used, the value of PLLSAI2 must be 00.
00: No clock sent to PLLSAI2
01: MSI clock selected as PLLSAI2 clock entry
10: HSI16 clock selected as PLLSAI2 clock entry
11: HSE clock selected as PLLSAI2 clock entry

RM0438 Rev 7 363/2194

427
Reset and clock control (RCC) RM0438

9.8.7 RCC clock interrupt enable register (RCC_CIER)

Address offset: 0x018
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLSAI2RDYIE

PLLSAI1RDYIE
HSI48RDYIE

HSERDYIE

LSERDYIE
PLLRDYIE

MSIRDYIE
HSIRDYIE

LSIRDYIE
Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSI48RDYIE: HSI48 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the internal HSI48
oscillator.
0: HSI48 ready interrupt disabled
1: HSI48 ready interrupt enabled
Bit 9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bit 7 PLLSAI2RDYIE: PLLSAI2 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLLSAI2 lock.
0: PLLSAI2 lock interrupt disabled
1: PLLSAI2 lock interrupt enabled
Bit 6 PLLSAI1RDYIE: PLLSAI1 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLSAI1L lock.
0: PLLSAI1 lock interrupt disabled
1: PLLSAI1 lock interrupt enabled
Bit 5 PLLRDYIE: PLL ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 4 HSERDYIE: HSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSE oscillator
stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 3 HSIRDYIE: HSI16 ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the HSI16 oscillator
stabilization.
0: HSI16 ready interrupt disabled
1: HSI16 ready interrupt enabled

364/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 2 MSIRDYIE: MSI ready interrupt enable

Set and cleared by software to enable/disable interrupt caused by the MSI oscillator
stabilization.
0: MSI ready interrupt disabled
1: MSI ready interrupt enabled
Bit 1 LSERDYIE: LSE ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSE oscillator
stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 0 LSIRDYIE: LSI ready interrupt enable
Set and cleared by software to enable/disable interrupt caused by the LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled

9.8.8 RCC clock interrupt flag register (RCC_CIFR)

Address offset: 0x01C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2RDYF

PLLSAI1RDYF
HSI48RDYF

HSERDYF

LSERDYF
PLLRDYF

MSIRDYF
HSIRDYF

LSIRDYF
Res. Res. Res. Res. Res. Res. CSSF

r r r r r r r r r r

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSI48RDYF: HSI48 ready interrupt flag
Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set in a
response to setting the HSI48ON (refer to RCC clock recovery RC register (RCC_CRRCR)).
Cleared by software setting the HSI48RDYC bit.
0: No clock ready interrupt caused by the HSI48 oscillator
1: Clock ready interrupt caused by the HSI48 oscillator
Bit 9 Reserved, must be kept at reset value.
Bit 8 CSSF: Clock security system interrupt flag
Set by hardware when a failure is detected in the HSE oscillator.
Cleared by software setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure

RM0438 Rev 7 365/2194

427
Reset and clock control (RCC) RM0438

Bit 7 PLLSAI2RDYF: PLLSAI2 ready interrupt flag

Set by hardware when the PLLSAI2 locks and PLLSAI2RDYDIE is set.
Cleared by software setting the PLLSAI2RDYC bit.
0: No clock ready interrupt caused by PLLSAI2 lock
1: Clock ready interrupt caused by PLLSAI2 lock
Bit 6 PLLSAI1RDYF: PLLSAI1 ready interrupt flag
Set by hardware when the PLLSAI1 locks and PLLSAI1RDYDIE is set.
Cleared by software setting the PLLSAI1RDYC bit.
0: No clock ready interrupt caused by PLLSAI1 lock
1: Clock ready interrupt caused by PLLSAI1 lock
Bit 5 PLLRDYF: PLL ready interrupt flag
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Bit 4 HSERDYF: HSE ready interrupt flag
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a
response to setting the HSION (refer to RCC clock control register (RCC_CR)). When
HSION is not set but the HSI16 oscillator is enabled by the peripheral through a clock
request, this bit is not set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Bit 2 MSIRDYF: MSI ready interrupt flag
Set by hardware when the MSI clock becomes stable and MSIRDYDIE is set.
Cleared by software setting the MSIRDYC bit.
0: No clock ready interrupt caused by the MSI oscillator
1: Clock ready interrupt caused by the MSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator

366/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.9 RCC clock interrupt clear register (RCC_CICR)

Address offset: 0x020
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLLSAI2RDYC

PLLSAI1RDYC
HSI48RDYC

HSERDYC

LSERDYC
PLLRDYC

MSIRDYC
HSIRDYC

LSIRDYC
Res. Res. Res. Res. Res. Res. CSSC

w w w w w w w w w w

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 HSI48RDYC: HSI48 oscillator ready interrupt clear
This bit is set by software to clear the HSI48RDYF flag.
0: No effect
1: Clear the HSI48RDYC flag
Bit 9 Reserved, must be kept at reset value.
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 7 PLLSAI2RDYC: PLLSAI2 ready interrupt clear
This bit is set by software to clear the PLLSAI2RDYF flag.
0: No effect
1: Clear PLLSAI2RDYF flag
Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear
This bit is set by software to clear the PLLSAI1RDYF flag.
0: No effect
1: Clear PLLSAI1RDYF flag
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag

RM0438 Rev 7 367/2194

427
Reset and clock control (RCC) RM0438

Bit 2 MSIRDYC: MSI ready interrupt clear

This bit is set by software to clear the MSIRDYF flag.
0: No effect
1: MSIRDYF cleared
Bit 1 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 0 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared

9.8.10 RCC AHB1 peripheral reset register (RCC_AHB1RSTR)

Address offset: 0x028
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TSCRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMAMUX1RST
FLASHRST

DMA2RST

DMA1RST
CRCRST

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 TSCRST: Touch sensing controller reset
Set and cleared by software.
0: No effect
1: Reset TSC
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
Set and cleared by software.
0: No effect
1: Reset CRC
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHRST: Flash memory interface reset
Set and cleared by software. This bit can be activated only when the Flash memory is in
power down mode.
0: No effect
1: Reset Flash memory interface

368/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 7:3 Reserved, must be kept at reset value.

Bit 2 DMAMUX1RST: DMAMUX1 reset
Set and cleared by software.
0: No effect
1: Reset DMAMUX1
Bit 1 DMA2RST: DMA2 reset
Set and cleared by software.
0: No effect
1: Reset DMA2
Bit 0 DMA1RST: DMA1 reset
Set and cleared by software.
0: No effect
1: Reset DMA1

9.8.11 RCC AHB2 peripheral reset register (RCC_AHB2RSTR)

Address offset: 0x02C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21
OTFDEC1RST 20 19 18 17 16
SDMMC1RST

HASHRST
RNGRST
PKARST

AESRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOGRST
GPIOHRST

GPIODRST

GPIOCRST
GPIOERST

GPIOBRST

GPIOARST
GPIOFRST
ADCRST

Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SDMMC1RST: SDMMC1 reset
Set and cleared by software.
0: No effect
1: Reset SDMMC1
Bit 21 OTFDEC1RST: OTFDEC reset
Set and cleared by software.
0: No effect
1: Reset OTFDEC
Bit 20 Reserved, must be kept at reset value.
Bit 19 PKARST: PKA reset
Set and cleared by software.
0: No effect
1: Reset PKA

RM0438 Rev 7 369/2194

427
Reset and clock control (RCC) RM0438

Bit 18 RNGRST: Random number generator reset

Set and cleared by software.
0: No effect
1: Reset RNG
Bit 17 HASHRST: Hash reset
Set and cleared by software.
0: No effect
1: Reset HASH
Bit 16 AESRST: AES hardware accelerator reset
Set and cleared by software.
0: No effect
1: Reset AES
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 ADCRST: ADC reset
Set and cleared by software.
0: No effect
1: Reset ADC interface
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHRST: IO port H reset
Set and cleared by software.
0: No effect
1: Reset IO port H
Bit 6 GPIOGRST: IO port G reset
Set and cleared by software.
0: No effect
1: Reset IO port G
Bit 5 GPIOFRST: IO port F reset
Set and cleared by software.
0: No effect
1: Reset IO port F
Bit 4 GPIOERST: IO port E reset
Set and cleared by software.
0: No effect
1: Reset IO port E
Bit 3 GPIODRST: IO port D reset
Set and cleared by software.
0: No effect
1: Reset IO port D

370/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 2 GPIOCRST: IO port C reset

Set and cleared by software.
0: No effect
1: Reset IO port C
Bit 1 GPIOBRST: IO port B reset
Set and cleared by software.
0: No effect
1: Reset IO port B
Bit 0 GPIOARST: IO port A reset
Set and cleared by software.
0: No effect
1: Reset IO port A

9.8.12 RCC AHB3 peripheral reset register (RCC_AHB3RSTR)

Address offset: 0x030
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1RST

FMCRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 OSPI1RST: OCTOSPI1 memory interface reset
Set and cleared by software.
0: No effect
1: Reset OCTOSPI1
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCRST: Flexible memory controller reset
Set and cleared by software.
0: No effect
1: Reset FMC

RM0438 Rev 7 371/2194

427
Reset and clock control (RCC) RM0438

9.8.13 RCC APB1 peripheral reset register 1 (RCC_APB1RSTR1)

Address offset: 0x038
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USART3RST

USART2RST
OPAMPRST
LPTIM1RST

UART5RST

UART4RST
DAC1RST

PWRRST

I2C3RST

I2C2RST

I2C1RST
CRSRST
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIM7RST

TIM6RST

TIM5RST

TIM4RST

TIM3RST

TIM2RST
SPI3RST

SPI2RST

Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw

Bit 31 LPTIM1RST: Low-power timer 1 reset

Set and cleared by software.
0: No effect
1: Reset LPTIM1
Bit 30 OPAMPRST: OPAMP interface reset
Set and cleared by software.
0: No effect
1: Reset OPAMP interface
Bit 29 DAC1RST: DAC1 interface reset
Set and cleared by software.
0: No effect
1: Reset DAC1 interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: No effect
1: Reset PWR
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 CRSRST: CRS reset
Set and cleared by software.
0: No effect
1: Reset the CRS
Bit 23 I2C3RST: I2C3 reset
Set and reset by software.
0: No effect
1: Reset I2C3
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: No effect
1: Reset I2C2

372/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 21 I2C1RST: I2C1 reset

Set and cleared by software.
0: No effect
1: Reset I2C1
Bit 20 UART5RST: UART5 reset
Set and cleared by software.
0: No effect
1: Reset UART5
Bit 19 UART4RST: UART4 reset
Set and cleared by software.
0: No effect
1: Reset UART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: No effect
1: Reset USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: No effect
1: Reset USART2
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: No effect
1: Reset SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: No effect
1: Reset SPI2
Bits 13:6 Reserved, must be kept at reset value.
Bit 5 TIM7RST: TIM7 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM7
Bit 4 TIM6RST: TIM6 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM6
Bit 3 TIM5RST: TIM5 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM5

RM0438 Rev 7 373/2194

427
Reset and clock control (RCC) RM0438

Bit 2 TIM4RST: TIM3 timer reset

Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 1 TIM3RST: TIM3 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM3
Bit 0 TIM2RST: TIM2 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM2

9.8.14 RCC APB1 peripheral reset register 2 (RCC_APB1RSTR2)

Address offset: 0x03C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1RST

USBFSRST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1RST
FDCAN1RST

LPTIM3RST

LPTIM2RST

I2C4RST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCPD1RST: UCPD1 reset
Set and cleared by software.
0: No effect
1: Reset UCPD1
Bit 22 Reserved, must be kept at reset value.
Bit 21 USBFSRST: USB FS reset
Set and cleared by software.
0: No effect
1: Reset USB FS
Bits 20:10 Reserved, must be kept at reset value.
Bit 9 FDCAN1RST: FDCAN1 reset
Set and cleared by software.
0: No effect
1: Reset FDCAN1

374/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 8:7 Reserved, must be kept at reset value.

Bit 6 LPTIM3RST: LPTIM3 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM3
Bit 5 LPTIM2RST: LPTIM2 reset
Set and cleared by software.
0: No effect
1: Reset LPTIM2
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 I2C4RST: I2C4 reset
Set and cleared by software
0: No effect
1: Reset I2C4
Bit 0 LPUART1RST: Low-power UART 1 reset
Set and cleared by software.
0: No effect
1: Reset LPUART1

9.8.15 RCC APB2 peripheral reset register (RCC_APB2RSTR)

Address offset: 0x040
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1RST

TIM17RST

TIM16RST

TIM15RST
SAI2RST

SAI1RST

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGRST
USART1RST

TIM8RST

TIM1RST
SPI1RST

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DFSDM1RST: Digital filters for sigma-delta modulators (DFSDM1) reset
Set and cleared by software.
0: No effect
1: Reset DFSDM1
Bit 23 Reserved, must be kept at reset value.

RM0438 Rev 7 375/2194

427
Reset and clock control (RCC) RM0438

Bit 22 SAI2RST: Serial audio interface 2 (SAI2) reset

Set and cleared by software.
0: No effect
1: Reset SAI2
Bit 21 SAI1RST: Serial audio interface 1 (SAI1) reset
Set and cleared by software.
0: No effect
1: Reset SAI1
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17RST: TIM17 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM17
Bit 17 TIM16RST: TIM16 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM16
Bit 16 TIM15RST: TIM15 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM15
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1RST: USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 TIM8RST: TIM8 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM8
Bit 12 SPI1RST: SPI1 reset
Set and cleared by software.
0: No effect
1: Reset SPI1
Bit 11 TIM1RST: TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGRST: SYSCFG + COMP + VREFBUF reset
0: No effect
1: Reset SYSCFG + COMP + VREFBUF

376/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.16 RCC AHB1 peripheral clock enable register (RCC_AHB1ENR)

Address offset: 0x048
Reset value: 0x0000 0100
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

GTZCEN

TSCEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMAMUX1EN
FLASHEN

DMA2EN

DMA1EN
Res. Res. Res. CRCEN Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bit 22 GTZCEN: GTZC clock enable
Set and reset by software.
0: GTZC clock disabled
1: GTZC clock enabled
Bits 21:17 Reserved, must be kept at reset value.
Bit 16 TSCEN: Touch sensing controller clock enable
Set and cleared by software.
0: TSC clock disabled
1: TSC clock enabled
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bits 11:9 Reserved, must be kept at reset value.
Bit 8 FLASHEN: Flash memory interface clock enable
Set and cleared by software. This bit can be disabled only when the Flash is in power down
mode.
0: Flash memory interface clock disabled
1: Flash memory interface clock enabled
Bits 7:3 Reserved, must be kept at reset value.

RM0438 Rev 7 377/2194

427
Reset and clock control (RCC) RM0438

Bit 2 DMAMUX1EN: DMAMUX1 clock enable

Set and reset by software.
0: DMAMUX1 clock disabled
1: DMAMUX1 clock enabled
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled

9.8.17 RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)

Address offset: 0x04C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1EN
SDMMC1EN

HASHEN
RNGEN
PKAEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AESEN

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
GPIOGEN
GPIOHEN

GPIODEN

GPIOCEN
GPIOEEN

GPIOBEN

GPIOAEN
GPIOFEN

Res. Res. ADCEN Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SDMMC1EN: SDMMC1 clock enable
Set and cleared by software.
0: SDMMC1 clock disabled
1: SDMMC1 clock enabled
Bit 21 OTFDEC1EN: OTFDEC1 clock enable
Set and cleared by software.
0: OTFDEC1 clock disabled
1: OTFDEC1 clock enabled
Bit 20 Reserved, must be kept at reset value.

378/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 19 PKAEN: PKA clock enable

Set and cleared by software.
0: PKA clock disabled
1: PKA clock enabled
Bit 18 RNGEN: Random Number Generator clock enable
Set and cleared by software.
0: Random Number Generator clock disabled
1: Random Number Generator clock enabled
Bit 17 HASHEN: HASH clock enable
Set and cleared by software
0: HASH clock disabled
1: HASH clock enabled
Bit 16 AESEN: AES accelerator clock enable
Set and cleared by software.
0: AES clock disabled
1: AES clock enabled
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 ADCEN: ADC clock enable
Set and cleared by software.
0: ADC clock disabled
1: ADC clock enabled
Bits 12:8 Reserved, must be kept at reset value.
Bit 7 GPIOHEN: IO port H clock enable
Set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
Set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
Bit 5 GPIOFEN: IO port F clock enable
Set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 4 GPIOEEN: IO port E clock enable
Set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
Set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled

RM0438 Rev 7 379/2194

427
Reset and clock control (RCC) RM0438

Bit 2 GPIOCEN: IO port C clock enable

Set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
Set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
Set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled

9.8.18 RCC AHB3 peripheral clock enable register(RCC_AHB3ENR)

Address offset: 0x050
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1EN

FMCEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 OSPI1EN: OCTOSPI1 memory interface clock enable
Set and cleared by software.
0: OCTOSPI1 clock disabled
1: OCTOSPI1 clock enabled
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCEN: Flexible memory controller clock enable
Set and cleared by software.
0: FMC clock disabled
1: FMC clock enabled

380/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.19 RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)

Address: 0x058
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USART3EN

USART2EN
OPAMPEN
LPTIM1EN

UART5EN

UART4EN
DAC1EN

PWREN

I2C3EN

I2C2EN

I2C1EN
Res. Res. Res. CRSEN Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCAPBEN
WWDGEN

TIM7EN

TIM6EN

TIM5EN

TIM4EN

TIM3EN

TIM2EN
SPI3EN SPI2EN Res. Res. Res. Res. Res. Res.

rw rw rs rw rw rw rw rw rw rw

Bit 31 LPTIM1EN: Low-power timer 1 clock enable

Set and cleared by software.
0: LPTIM1 clock disabled
1: LPTIM1 clock enabled
Bit 30 OPAMPEN: OPAMP interface clock enable
Set and cleared by software.
0: OPAMP interface clock disabled
1: OPAMP interface clock enabled
Bit 29 DAC1EN: DAC1 interface clock enable
Set and cleared by software.
0: DAC1 interface clock disabled
1: DAC1 interface clock enabled
Bit 28 PWREN: Power interface clock enable
Set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enabled
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 CRSEN: CRS clock enable
Set and cleared by software.
0: CRS clock disabled
1: CRS clock enabled
Bit 23 I2C3EN: I2C3 clock enable
Set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled

RM0438 Rev 7 381/2194

427
Reset and clock control (RCC) RM0438

Bit 22 I2C2EN: I2C2 clock enable

Set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
Bit 21 I2C1EN: I2C1 clock enable
Set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 UART5EN: UART5 clock enable
Set and cleared by software.
0: UART5 clock disabled
1: UART5 clock enabled
Bit 19 UART4EN: UART4 clock enable
Set and cleared by software.
0: UART4 clock disabled
1: UART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
Set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
Set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3EN: SPI3 clock enable
Set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
Set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
Set by software to enable the window watchdog clock. Reset by hardware system reset.
This bit can also be set by hardware if the WWDG_SW option bit is reset.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 RTCAPBEN: RTC APB clock enable
Set and cleared by software
0: RTC APB clock disabled
1: RTC APB clock enabled
Bits 9:6 Reserved, must be kept at reset value.

382/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 5 TIM7EN: TIM7 timer clock enable

Set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Bit 4 TIM6EN: TIM6 timer clock enable
Set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bit 3 TIM5EN: TIM5 timer clock enable
Set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 timer clock enable
Set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 timer clock enable
Set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 timer clock enable
Set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled

9.8.20 RCC APB1 peripheral clock enable register 2 (RCC_APB1ENR2)

Address offset: 0x05C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
UCPD1EN

USBFSEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPUART1EN
FDCAN1EN

LPTIM3EN

LPTIM2EN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. I2C4EN

rw rw rw rw rw

RM0438 Rev 7 383/2194

427
Reset and clock control (RCC) RM0438

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCPD1EN: UCPD1 clock enable
Set and cleared by software.
0: UCPD1 clock disabled
1: UCPD1 clock enabled
Bit 22 Reserved, must be kept at reset value.
Bit 21 USBFSEN: USB FS clock enable
Set and cleared by software.
0: USB FS clock disabled
1: USB FS clock enabled
Bits 20:10 Reserved, must be kept at reset value.
Bit 9 FDCAN1EN: FDCAN1 clock enable
Set and cleared by software.
0: FDCAN1 clock disabled
1: FDCAN1 clock enabled
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3EN: Low-power timer 3clock enable
Set and cleared by software.
0: LPTIM3 clock disabled
1: LPTIM3 clock enabled
Bit 5 LPTIM2EN: Low-power timer 2 clock enable
Set and cleared by software.
0: LPTIM2 clock disabled
1: LPTIM2 clock enabled
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 I2C4EN: I2C4 clock enable
Set and cleared by software
0: I2C4 clock disabled
1: I2C4 clock enabled
Bit 0 LPUART1EN: Low-power UART 1 clock enable
Set and cleared by software.
0: LPUART1 clock disabled
1: LPUART1 clock enabled

384/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.21 RCC APB2 peripheral clock enable register (RCC_APB2ENR)

Address: 0x060
Reset value: 0x0000 0000
Access: word, half-word and byte access
Note: When the peripheral clock is not active, the peripheral registers read or write access is not
supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DFSDM1EN

TIM17EN

TIM16EN

TIM15EN
SAI2EN

SAI1EN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SYSCFGEN
USART1EN

TIM8EN

TIM1EN
SPI1EN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DFSDM1EN: DFSDM1 timer clock enable
Set and cleared by software.
0: DFSDM1 clock disabled
1: DFSDM1 clock enabled
Bit 23 Reserved, must be kept at reset value.
Bit 22 SAI2EN: SAI2 clock enable
Set and cleared by software.
0: SAI2 clock disabled
1: SAI2 clock enabled
Bit 21 SAI1EN: SAI1 clock enable
Set and cleared by software.
0: SAI1 clock disabled
1: SAI1 clock enabled
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17EN: TIM17 timer clock enable
Set and cleared by software.
0: TIM17 clock disabled
1: TIM17 clock enabled
Bit 17 TIM16EN: TIM16 timer clock enable
Set and cleared by software.
0: TIM16 clock disabled
1: TIM16 clock enabled
Bit 16 TIM15EN: TIM15 timer clock enable
Set and cleared by software.
0: TIM15 clock disabled
1: TIM15 clock enabled

RM0438 Rev 7 385/2194

427
Reset and clock control (RCC) RM0438

Bit 15 Reserved, must be kept at reset value.

Bit 14 USART1EN: USART1clock enable
Set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 TIM8EN: TIM8 timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF clock enable
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clock disabled
1: SYSCFG + COMP + VREFBUF clock enabled

9.8.22 RCC AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR)
Address offset: 0x068
Reset value: 0x00C1 1307
Access: no wait state, word, half-word and byte access
This register only configures the clock gating, not the clock source itself. Most of the
peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in
Stop mode. In this case setting the bit has no effect in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ICACHESMEN

GTZCSMEN

TSCSMEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAMUX1SMEN
SRAM1SMEN

FLASHSMEN

DMA2SMEN

DMA1SMEN

Res. Res. Res. CRCSMEN Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw

386/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 ICACHESMEN: Instruction cache ICACHE clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ICACHE clocks disabled by the clock gating during Sleep and Stop modes
1: ICACHE clocks enabled by the clock gating during Sleep and Stop modes
Bit 22 GTZCSMEN: GTZC clocks enable during Sleep and Stop modes
Set and cleared by software
0: GTZC clocks disabled by the clock gating during Sleep and Stop modes
1: GTZC clocks enabled by the clock gating during Sleep and Stop modes
Bits 21:17 Reserved, must be kept at reset value.
Bit 16 TSCSMEN: Touch sensing controller clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TSC clocks disabled by the clock gating during Sleep and Stop modes
1: TSC clocks enabled by the clock gating during Sleep and Stop modes
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSMEN: CRC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: CRC clocks disabled by the clock gating during Sleep and Stop modes
1: CRC clocks enabled by the clock gating during Sleep and Stop modes
Bits 11:10 Reserved, must be kept at reset value.
Bit 9 SRAM1SMEN: SRAM1 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM1 interface clocks disabled by the clock gating during Sleep and Stop modes
1: SRAM1 interface clocks enabled by the clock gating during Sleep and Stop modes
Bit 8 FLASHSMEN: Flash memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Flash memory interface clocks disabled by the clock gating during Sleep and Stop modes
1: Flash memory interface clocks enabled by the clock gating during Sleep and Stop modes
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1SMEN: DMAMUX1 clocks enable during Sleep and Stop modes.
Set and cleared by software.
0: DMAMUX1 clocks disabled by the clock gating during Sleep and Stop modes
1: DMAMUX1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 1 DMA2SMEN: DMA2 clocks enable during Sleep and Stop modes
Set and cleared by software during Sleep mode.
0: DMA2 clocks disabled by the clock gating during Sleep and Stop modes
1: DMA2 clocks enabled by the clock gating during Sleep and Stop modes
Bit 0 DMA1SMEN: DMA1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DMA1 clocks disabled by the clock gating during Sleep and Stop modes
1: DMA1 clocks enabled by the clock gating during Sleep and Stop modes

RM0438 Rev 7 387/2194

427
Reset and clock control (RCC) RM0438

9.8.23 RCC AHB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB2SMENR)
Address offset: 0x06C
Reset value: 0x006F 22FF
Access: no wait state, word, half-word and byte access
This register only configures the clock gating, not the clock source itself. Most of the
peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in
Stop mode. In this case setting the bit has no effect in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OTFDEC1SMEN
SDMMC1SMEN

HASHSMEN
RNGSMEN
PKASMEN

AESSMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2SMEN

GPIOGSMEN
GPIOHSMEN

GPIODSMEN

GPIOCSMEN
GPIOESMEN

GPIOBSMEN

GPIOASMEN
GPIOFSMEN
ADCSMEN

Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SDMMC1SMEN: SDMMC1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SDMMC1 clocks disabled by the clock gating during Sleep and Stop modes
1: SDMMC1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 21 OTFDEC1SMEN: OTFDEC1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OTFDEC1 clocks disabled by the clock gating during Sleep and Stop modes
1: OTFDEC1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 20 Reserved, must be kept at reset value.
Bit 19 PKASMEN: PKA clocks enable during Sleep and Stop modes
Set and cleared by software.
0: PKA clocks disabled by the clock gating during Sleep and Stop modes
1: PKA clocks enabled by the clock gating during Sleep and Stop modes
Bit 18 RNGSMEN: Random number generator (RNG) clocks enable during Sleep and Stop modes
Set and cleared by software.
0: RNG clocks disabled by the clock gating during Sleep and Stop modes
1: RNG clocks enabled by the clock gating during Sleep and Stop modes
Bit 17 HASHSMEN: HASH clock enable during Sleep and Stop modes
Set and cleared by software
0: HASH clocks disabled by the clock gating during Sleep and Stop modes
1: HASH clocks enabled by the clock gating during Sleep and Stop modes

388/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 16 AESSMEN: AES accelerator clocks enable during Sleep and Stop modes
Set and cleared by software.
0: AES clocks disabled by the clock gating during Sleep and Stop modes
1: AES clocks enabled by the clock gating during Sleep and Stop modes
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 ADCSMEN: ADC clocks enable during Sleep and Stop modes
Set and cleared by software.
0: ADC clocks disabled by the clock gating during Sleep and Stop modes
1: ADC clocks enabled by the clock gating during Sleep and Stop modes
Bits 12:10 Reserved, must be kept at reset value.
Bit 9 SRAM2SMEN: SRAM2 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SRAM2 interface clocks disabled by the clock gating during Sleep and Stop modes
1: SRAM2 interface clocks enabled by the clock gating during Sleep and Stop modes
Bit 8 Reserved, must be kept at reset value.
Bit 7 GPIOHSMEN: IO port H clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port H clocks disabled by the clock gating during Sleep and Stop modes
1: IO port H clocks enabled by the clock gating during Sleep and Stop modes
Bit 6 GPIOGSMEN: IO port G clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port G clocks disabled by the clock gating during Sleep and Stop modes
1: IO port G clocks enabled by the clock gating during Sleep and Stop modes
Bit 5 GPIOFSMEN: IO port F clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port F clocks disabled by the clock gating during Sleep and Stop modes
1: IO port F clocks enabled by the clock gating during Sleep and Stop modes
Bit 4 GPIOESMEN: IO port E clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port E clocks disabled by the clock gating during Sleep and Stop modes
1: IO port E clocks enabled by the clock gating during Sleep and Stop modes
Bit 3 GPIODSMEN: IO port D clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port D clocks disabled by the clock gating during Sleep and Stop modes
1: IO port D clocks enabled by the clock gating during Sleep and Stop modes

RM0438 Rev 7 389/2194

427
Reset and clock control (RCC) RM0438

Bit 2 GPIOCSMEN: IO port C clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port C clocks disabled by the clock gating during Sleep and Stop modes
1: IO port C clocks enabled by the clock gating during Sleep and Stop modes
Bit 1 GPIOBSMEN: IO port B clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port B clocks disabled by the clock gating during Sleep and Stop modes
1: IO port B clocks enabled by the clock gating during Sleep and Stop modes
Bit 0 GPIOASMEN: IO port A clocks enable during Sleep and Stop modes
Set and cleared by software.
0: IO port A clocks disabled by the clock gating during Sleep and Stop modes
1: IO port A clocks enabled by the clock gating during Sleep and Stop modes

9.8.24 RCC AHB3 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB3SMENR)
Address offset: 0x070
Reset value: 0x0000 0101
Access: no wait state, word, half-word and byte access
This register only configures the clock gating, not the clock source itself. Most of the
peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in
Stop mode. In this case setting the bit has no effect in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SMEN

FMCSMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 OSPI1SMEN: OCTOSPI1 memory interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OCTOSPI1 clocks disabled by the clock gating during Sleep and Stop modes
1: OCTOSPI1 clocks enabled by the clock gating during Sleep and Stop modes
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCSMEN: Flexible memory controller clocks enable during Sleep and Stop modes
Set and cleared by software.
0: FMC clocks disabled by the clock gating during Sleep and Stop modes
1: FMC clocks enabled by the clock gating during Sleep and Stop modes

390/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.25 RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 1 (RCC_APB1SMENR1)
Address: 0x078
Reset value: 0xF1FE CC3F
Access: no wait state, word, half-word and byte access
This register only configures the clock gating, not the clock source itself. Most of the
peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in
Stop mode. In this case setting the bit has no effect in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USART3SMEN

USART2SMEN
OPAMPSMEN
LPTIM1SMEN

UART5SMEN

UART4SMEN
DAC1SMEN

PWRSMEN

CRSSMEN

I2C3SMEN

I2C2SMEN

I2C1SMEN
Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCAPBSMEN
WWDGSMEN

TIM7SMEN

TIM6SMEN

TIM5SMEN

TIM4SMEN

TIM3SMEN

TIM2SMEN
SPI3SMEN

SPI2SMEN

Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw

Bit 31 LPTIM1SMEN: Low-power timer 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM1 clocks disabled by the clock gating during Sleep and Stop modes
1: LPTIM1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 30 OPAMPSMEN: OPAMP interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: OPAMP interface clocks disabled by the clock gating during Sleep and Stop modes
1: OPAMP interface clocks enabled by the clock gating during Sleep and Stop modes
Bit 29 DAC1SMEN: DAC1 interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DAC1 interface clocks disabled by the clock gating during Sleep and Stop modes
1: DAC1 interface clocks enabled by the clock gating during Sleep and Stop modes
Bit 28 PWRSMEN: Power interface clocks enable during Sleep and Stop modes
Set and cleared by software.
0: Power interface clocks disabled by the clock gating during Sleep and Stop modes
1: Power interface clocks enabled by the clock gating during Sleep and Stop modes
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 CRSSMEN: CRS clock enable during Sleep and Stop modes
Set and cleared by software.
0: CRS clocks disabled by the clock gating during Sleep and Stop modes
1: CRS clocks enabled by the clock gating during Sleep and Stop modes

RM0438 Rev 7 391/2194

427
Reset and clock control (RCC) RM0438

Bit 23 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C3 clocks disabled by the clock gating during Sleep and Stop modes
1: I2C3 clocks enabled by the clock gating during Sleep and Stop modes
Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C2 clocks disabled by the clock gating during Sleep and Stop modes
1: I2C2 clocks enabled by the clock gating during Sleep and Stop modes
Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C1 clocks disabled by the clock gating during Sleep and Stop modes
1: I2C1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART5 clocks disabled by the clock gating during Sleep and Stop modes
1: UART5 clocks enabled by the clock gating during Sleep and Stop modes
Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART4 clocks disabled by the clock gating during Sleep and Stop modes
1: UART4 clocks enabled by the clock gating during Sleep and Stop modes
Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART3 clocks disabled by the clock gating during Sleep and Stop modes
1: USART3 clocks enabled by the clock gating during Sleep and Stop modes
Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART2 clocks disabled by the clock gating during Sleep and Stop modes
1: USART2 clocks enabled by the clock gating during Sleep and Stop modes
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI3 clocks disabled by the clock gating during Sleep and Stop modes
1: SPI3 clocks enabled by the clock gating during Sleep and Stop modes
Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI2 clocks disabled by the clock gating during Sleep and Stop modes
1: SPI2 clocks enabled by the clock gating during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSMEN: Window watchdog clocks enable during Sleep and Stop modes
Set and cleared by software. This bit is forced to 1 by hardware when the hardware WWDG
option is activated.
0: Window watchdog clocks disabled by the clock gating during Sleep and Stop modes
1: Window watchdog clocks enabled by the clock gating during Sleep and Stop modes

392/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 10 RTCAPBSMEN: RTC APB clock enable during Sleep and Stop modes
Set and cleared by software
0: RTC APB clock disabled by the clock gating during Sleep and Stop modes
1: RTC APB clock enabled by the clock gating during Sleep and Stop modes
Bits 9:6 Reserved, must be kept at reset value.
Bit 5 TIM7SMEN: TIM7 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM7 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM7 clocks enabled by the clock gating during Sleep and Stop modes
Bit 4 TIM6SMEN: TIM6 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM6 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM6 clocks enabled by the clock gating during Sleep and Stop modes
Bit 3 TIM5SMEN: TIM5 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM5 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM5 clocks enabled by the clock gating during Sleep and Stop modes
Bit 2 TIM4SMEN: TIM4 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM4 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM4 clocks enabled by the clock gating during Sleep and Stop modes
Bit 1 TIM3SMEN: TIM3 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM3 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM3 clocks enabled by the clock gating during Sleep and Stop modes
Bit 0 TIM2SMEN: TIM2 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM2 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM2 clocks enabled by the clock gating during Sleep and Stop modes

RM0438 Rev 7 393/2194

427
Reset and clock control (RCC) RM0438

9.8.26 RCC APB1 peripheral clocks enable in Sleep and Stop modes
register 2 (RCC_APB1SMENR2)
Address offset: 0x07C
Reset value: 0x00A0 0223
Access: no wait state, word, half-word and byte access
This register only configures the clock gating, not the clock source itself. Most of the
peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in
Stop mode. In this case setting the bit has no effect in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UCPD1SMEN

USBFSSMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1SMEN
FDCAN1SMEN

LPTIM3SMEN

LPTIM2SMEN

I2C4SMEN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCPD1SMEN: UCPD1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UCPD1 clocks disabled by the clock gating during Sleep and Stop modes
1: UCPD1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 22 Reserved, must be kept at reset value.
Bit 21 USBFSSMEN: USB FS clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USB FS clocks disabled by the clock gating during Sleep and Stop modes
1: USB FS clocks enabled by the clock gating during Sleep and Stop modes
Bits 20:10 Reserved, must be kept at reset value.
Bit 9 FDCAN1SMEN: FDCAN1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: FDCAN1 clocks disabled by the clock gating during Sleep and Stop modes
1: FDCAN1 clocks enabled by the clock gating during Sleep and Stop modes
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SMEN:Low-power timer 3clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM3 clocks disabled by the clock gating during Sleep and Stop modes
1: LPTIM3 clocks enabled by the clock gating during Sleep and Stop modes

394/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 5 LPTIM2SMEN: Low-power timer 2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPTIM2 clocks disabled by the clock gating during Sleep and Stop modes
1: LPTIM2 clocks enabled by the clock gating during Sleep and Stop modes
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 I2C4SMEN: I2C4 clocks enable during Sleep and Stop modes
Set and cleared by software
0: I2C4 clocks disabled by the clock gating during Sleep and Stop modes
1: I2C4 clocks enabled by the clock gating during Sleep and Stop modes
Bit 0 LPUART1SMEN: Low-power UART 1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: LPUART1 clocks disabled by the clock gating during Sleep and Stop modes
1: LPUART1 clocks enabled by the clock gating during Sleep and Stop modes

9.8.27 RCC APB2 peripheral clocks enable in Sleep and Stop modes register
(RCC_APB2SMENR)
Address: 0x080
Reset value: 0x0167 7801
Access: word, half-word and byte access
This register only configures the clock gating, not the clock source itself. Most of the
peripherals are clocked by a single clock (AHB or APB clock), which is always disabled in
Stop mode. In this case setting the bit has no effect in Stop mode.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SMEN

TIM17SMEN

TIM16SMEN

TIM15SMEN
SAI2SMEN

SAI1SMEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGSMEN
USART1SMEN

TIM8SMEN

TIM1SMEN
SPI1SMEN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DFSDM1SMEN: DFSDM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: DFSDM1 clocks disabled by the clock gating during Sleep and Stop modes
1: DFSDM1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 23 Reserved, must be kept at reset value.

RM0438 Rev 7 395/2194

427
Reset and clock control (RCC) RM0438

Bit 22 SAI2SMEN: SAI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI2 clocks disabled by the clock gating during Sleep and Stop modes
1: SAI2 clocks enabled by the clock gating during Sleep and Stop modes
Bit 21 SAI1SMEN: SAI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SAI1 clocks disabled by the clock gating during Sleep and Stop modes
1: SAI1 clocks enabled by the clock gating during Sleep and Stop modes
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17SMEN: TIM17 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM17 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM17 clocks enabled by the clock gating during Sleep and Stop modes
Bit 17 TIM16SMEN: TIM16 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM16 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM16 clocks enabled by the clock gating during Sleep and Stop modes
Bit 16 TIM15SMEN: TIM15 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM15 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM15 clocks enabled by the clock gating during Sleep and Stop modes
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1SMEN: USART1clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART1clocks disabled by the clock gating during Sleep and Stop modes
1: USART1clocks enabled by the clock gating during Sleep and Stop modes
Bit 13 TIM8SMEN: TIM8 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM8 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM8 clocks enabled by the clock gating during Sleep and Stop modes
Bit 12 SPI1SMEN: SPI1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI1 clocks disabled by the clock gating during Sleep and Stop modes
1: SPI1 clocks enabled by the clock gating during Sleep and Stop modes
Bit 11 TIM1SMEN: TIM1 timer clocks enable during Sleep and Stop modes
Set and cleared by software.
0: TIM1 clocks disabled by the clock gating during Sleep and Stop modes
1: TIM1 clocks enabled by the clock gating during Sleep and Stop modes
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSMEN: SYSCFG + COMP + VREFBUF clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF clocks disabled by the clock gating during Sleep and Stop
modes
1: SYSCFG + COMP + VREFBUF clocks enabled by the clock gating during Sleep and Stop
modes

396/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.28 RCC peripherals independent clock configuration register 1

(RCC_CCIPR1)
Address: 0x088
Reset value: 0x0000 0000
Access: no wait states, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CLK48MSEL[1:0]

LPTIM3SEL[1:0]

LPTIM2SEL[1:0]

LPTIM1SEL[1:0]
FDCANSEL[1:0]
ADCSEL[1:0]

I2C3SEL[1:0]
Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPUART1SEL[1:0]

USART3SEL[1:0]

USART2SEL[1:0]

USART1SEL[1:0]
UART5SEL[1:0]

UART4SEL[1:0]
I2C2SEL[1:0]

I2C1SEL[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bits 29:28 ADCSEL[1:0]: ADCs clock source selection
These bits are set and cleared by software to select the clock source used by the ADC
interface.
00: No clock selected
01: PLLSAI1 “R” clock (PLLADC1CLK) selected
10: reserved
11: System clock selected
Bits 27:26 CLK48MSEL[1:0]: 48 MHz clock source selection
These bits are set and cleared by software to select the 48 MHz clock source used by
USB FS, RNG and SDMMC.
00: HSI48 clock selected
01: PLLSAI1 “Q” clock (PLL48M2CLK) selected
10: PLL “Q” clock (PLL48M1CLK) selected
11: MSI clock selected
Bits 25:24 FDCANSEL[1:0]: FDCAN clock source selection
These bits are set and cleared by software to select the FDCAN kernel clock source.
00: HSE clock selected
01: PLL “Q” clock (PLL48M1CLK) selected
10: PLLSAI1 “P” clock (PLLSAI1CLK) selected
11: reserved

RM0438 Rev 7 397/2194

427
Reset and clock control (RCC) RM0438

Bits 23:22 LPTIM3SEL[1:0]: Low-power timer 3 clock source selection

These bits are set and cleared by software to select the LPTIM3 clock source.
00: PCLK1 clock selected
01: LSI clock selected
10: HSI16 selected
11: LSE selected
Bits 21:20 LPTIM2SEL[1:0]: Low-power timer 2 clock source selection
These bits are set and cleared by software to select the LPTIM2 clock source.
00: PCLK1 selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
Bits 19:18 LPTIM1SEL[1:0]: Low-power timer 1 clock source selection
These bits are set and cleared by software to select the LPTIM1 clock source.
00: PCLK1 selected
01: LSI clock selected
10: HSI16 clock selected
11: LSE clock selected
Bits 17:16 I2C3SEL[1:0]: I2C3 clock source selection
These bits are set and cleared by software to select the I2C3 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: reserved
Bits 15:14 I2C2SEL[1:0]: I2C2 clock source selection
These bits are set and cleared by software to select the I2C2 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: reserved
Bits 13:12 I2C1SEL[1:0]: I2C1 clock source selection
These bits are set and cleared by software to select the I2C1 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: reserved
Bits 11:10 LPUART1SEL[1:0]: Low-power UART1 clock source selection
These bits are set and cleared by software to select the LPUART1 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 9:8 UART5SEL[1:0]: UART5 clock source selection
These bits are set and cleared by software to select the UART5 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected

398/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 7:6 UART4SEL[1:0]: UART4 clock source selection

This bit is set and cleared by software to select the UART4 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 5:4 USART3SEL[1:0]: USART3 clock source selection
This bit is set and cleared by software to select the USART3 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 3:2 USART2SEL[1:0]: USART2 clock source selection
This bit is set and cleared by software to select the USART2 clock source.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected
Bits 1:0 USART1SEL[1:0]: USART1 clock source selection
This bit is set and cleared by software to select the USART1 clock source.
00: PCLK2 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: LSE clock selected

9.8.29 RCC Backup domain control register (RCC_BDCR)

Address offset: 0x0090
Reset value: 0x0000 0000
Reset by Backup domain reset except LSCOSEL, LSCOEN and BDRST that are reset only
by Backup domain power-on reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: The bits of the RCC Backup domain control register (RCC_BDCR) are outside of the VCORE
domain. As a result, after reset, these bits are write-protected and the DBP bit in the Power
control register 1 (PWR_CR1) must be set before these can be modified. Refer to
Section 8.1.4: Battery backup domain for further information. These bits (except LSCOSEL,

RM0438 Rev 7 399/2194

427
Reset and clock control (RCC) RM0438

LSCOEN and BDRST) are only reset after a Backup domain reset (see Section 9.1.3:
Backup domain reset). Any internal or external reset does not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LSCOEN
LSCOSE
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BDRST

L
rw rw rw
15 14 13 12 11
LSESYSRDY 10 9 8 7 6 5 4 3 2 1 0

LSECSSON
LSESYSEN

LSECSSD

LSERDY
LSEBYP
RTCEN

Res. Res. Res. Res. RTCSEL[1:0] LSEDRV[1:0] LSEON

rw r rw rw rw r rw rw rw rw r rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 LSCOSEL: Low-speed clock output selection
Set and cleared by software.
0: LSI clock selected
1: LSE clock selected
Bit 24 LSCOEN: Low-speed clock output (LSCO) enable
Set and cleared by software.
0: LSCO disabled
1: LSCO enabled
Bits 23:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
Set and cleared by software.
0: Reset not activated
1: Reset the entire Backup domain and SRAM2
Bit 15 RTCEN: RTC clock enable
Set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:12 Reserved, must be kept at reset value.
Bit 11 LSESYSRDY: LSE system clock (LSESYS) ready
Set and cleared by hardware to indicate when the LSE system clock is stable.When the
LSESYSEN bit is set, the LSESYSRDY flag is set after two LSE clock cycles.
The LSE clock must be already enabled and stable (LSEON and LSERDY are set).
When the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator
clock cycles.
0: LSESYS clock not ready
1: LSESYS clock ready
Bit 10 Reserved, must be kept at reset value.

400/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 9:8 RTCSEL[1:0]: RTC clock source selection

Set by software to select the clock source for the RTC. Once the RTC clock source has been
selected, it cannot be changed anymore unless the Backup domain is reset, or unless a
failure is detected on LSE (LSECSSD is set). The BDRST bit can be used to reset them.
00: No clock selected
01: LSE oscillator clock selected
10: LSI oscillator clock selected
11: HSE oscillator clock divided by 32 selected
Bit 7 LSESYSEN: LSE system clock (LSESYS) enable
Set by software to enable always the LSE system clock generated by RCC. This clock can
be then used by any peripheral when its source clock is the LSE or at system level in case of
one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed.
The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by
the CSS on LSE, by a peripheral or any other source clock using LSE.
0: LSESYS only enabled when requested by a peripheral or system function
1: LSESYS enabled always generated by RCC
Bit 6 LSECSSD: CSS on LSE failure Detection
Set by hardware to indicate when a failure has been detected by the Clock Security System
on the external 32 kHz oscillator (LSE).
0: No failure detected on LSE (32 kHz oscillator)
1: Failure detected on LSE (32 kHz oscillator)
Bit 5 LSECSSON: CSS on LSE enable
Set by software to enable the Clock Security System on LSE (32 kHz oscillator).
LSECSSON must be enabled after the LSE oscillator is enabled (LSEON bit enabled) and
ready (LSERDY flag set by hardware), and after the RTCSEL bit is selected.
Once enabled this bit cannot be disabled, except after a LSE failure detection (LSECSSD
=1). In that case the software MUST disable the LSECSSON bit.
0: CSS on LSE (32 kHz external oscillator) OFF
1: CSS on LSE (32 kHz external oscillator) ON
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
Set by software to modulate the LSE oscillator’s drive capability.
00: ‘Xtal mode’ lower driving capability
01: ‘Xtal mode’ medium low driving capability
10: ‘Xtal mode’ medium high driving capability
11: ‘Xtal mode’ higher driving capability
The oscillator is in Xtal mode when it is not in bypass mode.

RM0438 Rev 7 401/2194

427
Reset and clock control (RCC) RM0438

Bit 2 LSEBYP: LSE oscillator bypass

Set and cleared by software to bypass oscillator in debug mode. This bit can be written only
when the external 32 kHz oscillator is disabled (LSEON=0 and LSERDY=0).
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: LSE oscillator ready
Set and cleared by hardware to indicate when the external 32 kHz oscillator is stable. After
the LSEON bit is cleared, LSERDY goes low after 6 external low-speed oscillator clock
cycles.
0: LSE oscillator not ready
1: LSE oscillator ready
Bit 0 LSEON: LSE oscillator enable
Set and cleared by software.
0: LSE oscillator OFF
1: LSE oscillator ON

9.8.30 RCC control/status register (RCC_CSR)

Address: 0x094
Reset value: 0x0C00 0600
Reset by system reset, except reset flags by power reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IWWDGRSTF
WWDGRSTF
LPWRRSTF

BORRSTF

OBLRSTF
SFTRSTF

PINRSTF

Res. RMVF Res. Res. Res. Res. Res. Res. Res.

r r r r r r r rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LSIPRE

Res. Res. Res. Res. MSISRANGE[3:0] Res. Res. Res. Res. Res. LSIRDY LSION

rw rw rw rw rw r rw

402/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 31 LPWRRSTF: Low-power reset flag

Set by hardware when a reset occurs due to illegal Stop, Standby or Shutdown mode entry.
Cleared by writing to the RMVF bit.
0: No illegal mode reset occurred
1: Illegal mode reset occurred
Bit 30 WWDGRSTF: Window watchdog reset flag
Set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWWDGRSTF: Independent window watchdog reset flag
Set by hardware when an independent watchdog reset domain occurs.
Cleared by writing to the RMVF bit.
0: No independent watchdog reset occurred
1: Independent watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
Set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 BORRSTF: BOR flag
Set by hardware when a BOR occurs.
Cleared by writing to the RMVF bit.
0: No BOR occurred
1: BOR occurred
Bit 26 PINRSTF: Pin reset flag
Set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 OBLRSTF: Option byte loader reset flag
Set by hardware when a reset from the option byte loading occurs.
Cleared by writing to the RMVF bit.
0: No reset from option byte loading occurred
1: Reset from option byte loading occurred
Bit 24 Reserved, must be kept at reset value.
Bit 23 RMVF: Remove reset flag
Set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
Bits 22:12 Reserved, must be kept at reset value.

RM0438 Rev 7 403/2194

427
Reset and clock control (RCC) RM0438

Bits 11:8 MSISRANGE[3:0]:MSI range after Standby mode

Set by software to chose the MSI frequency at startup. This range is used after exiting
Standby mode until MSIRGSEL is set. After a pad or a power-on reset, the range is always
4 MHz. MSISRANGE can be written only when MSIRGSEL = 1.
0100: Range 4 around 1 MHz
0101: Range 5 around 2 MHz
0101: Range 6 around 4 MHz (reset value)
0111: Range 7 around 8 MHz
others: reserved
Note: Changing the MSISRANGE does not change the current MSI frequency.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 LSIPRE: LSI frequency prescaler (LSI /128) enable
Set and reset by software.
This bit is used to enable the internal clock prescaler (/128) of the LSI clock. The LSIPRE bit
value is only taken into account when LSI is disabled (LSION and LSIRDY bits are reset)
0: LSI clock is not divided (LSI)
1: LSI clock is divided by 128 (LSI/128).
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: LSI oscillator ready
Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit
is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit can be set even if
LSION = 0 if the LSI is requested by the CSS on LSE, by the IWDG or by the RTC.
In case LSIPRE bit is set, the LSIRDY bit is set after 0.5 LSI clock cycle (~2ms) and when
LSION bit is reset, LSIRDY bit is reset after 1.5 LSI clock cycles (~6ms).
0: LSI oscillator not ready
1: LSI oscillator ready
Bit 0 LSION: LSI oscillator enable
Set and cleared by software.
0: LSI oscillator OFF
1: LSI oscillator ON

9.8.31 RCC clock recovery RC register (RCC_CRRCR)

Address: 0x098
Reset value: 0x0000 XXX0
X is factory-programmed.
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSI48RDY

HSI48ON

HSI48CAL[8:0] Res. Res. Res. Res. Res.

r r r r r r r r r r rw

404/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:7 HSI48CAL[8:0]: HSI48 clock calibration
These bits are initialized at startup with the factory-programmed HSI48 calibration trim value.
Bits 6:2 Reserved, must be kept at reset value.
Bit 1 HSI48RDY: HSI48 clock ready flag
Set by hardware to indicate that HSI48 oscillator is stable. This bit is set only when HSI48 is
enabled by software by setting HSI48ON.
0: HSI48 oscillator not ready
1: HSI48 oscillator ready
Bit 0 HSI48ON: HSI48 clock enable
Set and cleared by software.
Cleared by hardware to stop the HSI48 when entering in Stop, Standby or Shutdown modes.
0: HSI48 oscillator OFF
1: HSI48 oscillator ON

9.8.32 RCC peripherals independent clock configuration register 2

(RCC_CCIPR2)
Address: 0x09C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OSPISEL[1:0] Res. Res. Res. Res.
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADFSDMSEL[1:0]
SDMMCSEL

DFSDMSEL

Res. Res. Res. Res. SAI2SEL[2:0] SAI1SEL[2:0] I2C4SEL[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept at reset value.

Bits 21:20 OSPISEL[1:0]: OCTOSPI clock source selection
Set and reset by software. This bit allows to select the OCTOSPI clock source
00: System clock selected
01: MSI clock selected
10: PLL48M1CLK clock selected
11: reserved
Bits 19:15 Reserved, must be kept at reset value.

RM0438 Rev 7 405/2194

427
Reset and clock control (RCC) RM0438

Bit 14 SDMMCSEL: SDMMC clock selection

Set and reset by software.
This bit allows to select the SDMMC kernel clock source between PLLP clock (PLLSAI3CLK)
or clock from internal multiplexer.
It is recommended to change this bit only after reset and before enabling the SDMMC.
0: 48 MHz clock selected
1: PLLSAI3CLK selected, in case higher than 48 MHz is needed (for SDR50 mode)
Bits 13:11 Reserved, must be kept at reset value.
Bits 10:8 SAI2SEL[2:0]: SAI2 clock source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped, it is not possible to switch
to another clock. The user must switch to another clock before stopping the external clock.
000: PLLSAI1CLK clock selected
001: PLLSAI2CLK clock selected
010: PLLSAI3CLK clock selected
011: External clock SAI2_EXTCLK clock selected
100: HSI clock selected
Others: reserved
Bits 7:5 SAI1SEL[2:0]: SAI1 clock source selection
Set and reset by software.
If the selected clock is the external clock and this clock is stopped it is not possible to switch
to another clock. The user must switch to another clock before stopping the external clock.
000: PLLSAI1CLK clock selected
001: PLLSAI2CLK clock selected
010: PLLSAI3CLK clock selected
011: External clock SAI1_EXTCLK selected
100: HSI clock selected
Others: reserved
Bits 4:3 ADFSDMSEL[1:0]: Digital filter for sigma-delta modulator audio clock source selection
Set and reset by software.
00: SAI1clock selected
01: HSI clock selected
10: MSI clock selected
11: reserved
Bit 2 DFSDMSEL: Digital filter for sigma-delta modulator kernel clock source selection
Set and reset by software.
0: APB2 clock (PCLK2) selected
1: System clock selected
Bits 1:0 I2C4SEL[1:0]: I2C4 clock source selection
These bits are set and cleared by software.
00: PCLK1 selected
01: System clock (SYSCLK) selected
10: HSI16 clock selected
11: reserved

9.8.33 OCTOSPI delay configuration register (RCC_DLYCFGR)

Address: 0x0A4
Reset value: 0x0000 0000h

406/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Access: no wait state, word, half-word and byte access

This register allows to configure OCTOSPI’s delay cell.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OCTOSPI1_DLY
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 OCTOSPI1_DLY: Delay sampling configuration on OCTOSPI1 to be used for internal sampling
clock (called feedback clock) or for DQS data strobe.
Set and reset by software.
0000: 1 unitary delay
0001: 2 unitary delays
0010: 3 unitary delays
...
1111: 16 unitary delays

9.8.34 RCC secure configuration register (RCC_SECCFGR)

Address: 0x0B8
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN = 1), this register provides write access security and can
be read and written only by a secure access. A non-secure read and write access generates
an illegal access event and data is RAZ/WI.
When the system is not secure (TZEN = 0), this register is RAZ/WI.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2SEC

PLLSAI1SEC

SYSCLKSEC
CLK48MSEC

PRESCSEC
RMVFSEC

HSI48SEC

HSESEC
LSESEC
PLLSEC

MSISEC

HSISEC
LSISEC

Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 407/2194

427
Reset and clock control (RCC) RM0438

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 RMVFSEC: Remove reset flag security
Set and reset by software.
0: non secure
1: secure
Bit 11 HSI48SEC: HSI48 clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure
Bit 10 CLK48MSEC: 48 MHz clock source selection security
Set and reset by software.
0: non secure
1: secure
Bit 9 PLLSAI2SEC: PLLSAI2 clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure
Bit 8 PLLSAI1SEC: PLLSAI1 clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure
Bit 7 PLLSEC: main PLL clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure
Bit 6 PRESCSEC: AHBx/APBx prescaler configuration bits security
Set and reset by software.
0: non secure
1: secure
Bit 5 SYSCLKSEC: SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration
security
Set and reset by software.
0: non secure
1: secure
Bit 4 LSESEC: LSE clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure
Bit 3 LSISEC: LSI clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure

408/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 2 MSISEC: MSI clock configuration and status bits security

Set and reset by software.
0: non secure
1: secure
Bit 1 HSESEC: HSE clock configuration bits, status bits and HSE_CSS security
Set and reset by software.
0: non secure
1: secure
Bit 0 HSISEC: HSE clock configuration and status bits security
Set and reset by software.
0: non secure
1: secure

9.8.35 RCC secure status register (RCC_SECSR)

Address: 0x0BC
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN = 1), this register provides security status of security
configuration bits in RCC_SECCFGR register. Both privileged and unprivileged, accesses
are allowed.
When the system is not secure (TZEN = 0), this register is RAZ/WI.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PLLSAI2SECF

PLLSAI1SECF

SYSCLKSECF
CLK48MSECF

PRESCSECF
RMVFSECF

HSI48SECF

HSESECF
LSESECF
PLLSECF

MSISECF

HSISECF
LSISECF

Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bit 12 RMVFSECF: remove reset flag security flag
Set and reset by software.
0: non secure
1: secure
Bit 11 HSI48SECF: HSI48 clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 10 CLK48MSECF: 48 MHz clock source selection security flag
Set and reset by software.
0: non secure
1: secure

RM0438 Rev 7 409/2194

427
Reset and clock control (RCC) RM0438

Bit 9 PLLSAI2SECF: PLLSAI2 clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 8 PLLSAI1SECF: PLLSAI1 clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 7 PLLSECF: main PLL clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 6 PRESCSECF: AHBx/APBx prescaler configuration bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 5 SYSCLKSECF: SYSCLK clock selection, STOPWUCK bit, clock output on MCO configuration
security flag
Set and reset by software.
0: non secure
1: secure
Bit 4 LSESECF: LSE clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 3 LSISECF: LSI clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 2 MSISECF: MSI clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure
Bit 1 HSESECF: HSE clock configuration bits, status bits and HSE_CSS security flag
Set and reset by software.
0: non secure
1: secure
Bit 0 HSISECF: HSE clock configuration and status bits security flag
Set and reset by software.
0: non secure
1: secure

410/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.36 RCC AHB1 security status register (RCC_AHB1SECSR)

Address: 0x0E8
Reset value: 0x0040 0300
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN =1), this register provides AHB1 peripheral clock
security status. When a peripheral is configured as secure, its clock is also secure.
Both privileged and unprivileged, secure and non-secure accesses are allowed.
When the system is not secure (TZEN = 0), this register is RAZ.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ICACHESECF

GTZCSECF

TSCSECF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMAMUX1SECF
SRAM1SECF

FLASHSECF

DMA2SECF

DMA1SECF
CRCSECF

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r r

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 ICACHESECF: Instruction cache (ICACHE) clock security flag
This flag is set by hardware when ICACHE is secure.
0: non secure
1: secure
Bit 22 GTZCSECF: GTZC controller clock security flag
This flag is set by hardware when GTZC is secure.
0: non secure
1: secure
Bits 21:17 Reserved, must be kept at reset value.
Bit 16 TSCSECF: Touch sensing controller (TSC) clock security flag
This flag is set by hardware when TSC is secure.
0: non secure
1: secure
Bits 15:13 Reserved, must be kept at reset value.
Bit 12 CRCSECF: CRC clock security flag
This flag is set by hardware when CRC is secure.
0: non secure
1: secure
Bits 11:10 Reserved, must be kept at reset value.

RM0438 Rev 7 411/2194

427
Reset and clock control (RCC) RM0438

Bit 9 SRAM1SECF: SRAM1 clock security flag

This flag is set by hardware when SRAM1 is secure.
0: non secure
1: secure
Bit 8 FLASHSECF: Flash memory interface clock security flag
This flag is set by hardware when Flash memory is secure.
0: non secure
1: secure
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 DMAMUX1SECF: DMAMUX1 clock security flag
This flag is set by hardware when DMAMUX1 is secure.
0: non secure
1: secure
Bit 1 DMA2SECF: DMA2 clock security flag
This flag is set by hardware when DMA2 is secure.
0: non secure
1: secure
Bit 0 DMA1SECF: DMA1 clock security flag
This flag is set by hardware when DMA1 is secure.
0: non secure
1: secure

9.8.37 RCC AHB2 security status register (RCC_AHB2SECSR)

Address: 0x0EC
Reset value: 0x0020 02FF
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN =1), this register provides AHB2 peripheral clock
security status. When a peripheral is configured as secure, its clock is also secure.
Both privileged and unprivileged, secure and non-secure accesses are allowed.
When the system is not secure (TZEN = 0), this register is RAZ.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OTFDEC1SECF
SDMMC1SECF

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2SECF

GPIOGSECF
GPIOHSECF

GPIODSECF

GPIOCSECF
GPIOESECF

GPIOBSECF

GPIOASECF
GPIOFSECF

Res. Res. Res. Res. Res. Res. Res.

r r r r r r r r r

412/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 31:23 Reserved, must be kept at reset value.

Bit 22 SDMMC1SECF: SDMMC1 clock security flag
This flag is set by hardware when SDMMC1 is secure.
0: non secure
1: secure
Bit 21 OTFDEC1SECF: OTFDEC1 controller clock security flag
This flag is set by hardware when OTFDEC1 is secure.
0: non secure
1: secure
Bits 20:10 Reserved, must be kept at reset value.
Bit 9 SRAM2SECF: SRAM2 clock security flag
This flag is set by hardware when SRAM2 is secure.
0: non secure
1: secure
Bit 8 Reserved, must be kept at reset value.
Bit 7 GPIOHSECF: GPIOH clock security flag
This flag is set by hardware when GPIOH is secure.
0: non secure
1: secure
Bit 6 GPIOGSECF: GPIOG clock security flag
This flag is set by hardware when GPIOHG is secure.
0: non secure
1: secure
Bit 5 GPIOFSECF: GPIOF clock security flag
This flag is set by hardware when GPIOHF is secure.
0: non secure
1: secure
Bit 4 GPIOESECF: GPIOE clock security flag
This flag is set by hardware when GPIOE is secure.
0: non secure
1: secure
Bit 3 GPIODSECF: GPIOD clock security flag
This flag is set by hardware when GPIOD is secure.
0: non secure
1: secure

RM0438 Rev 7 413/2194

427
Reset and clock control (RCC) RM0438

Bit 2 GPIOCSECF: GPIOC clock security flag

This flag is set by hardware when GPIOC is secure.
0: non secure
1: secure
Bit 1 GPIOBSECF: GPIOB clock security flag
This flag is set by hardware when GPIOB is secure.
0: non secure
1: secure
Bit 0 GPIOASECF: GPIOA clock security flag
This flag is set by hardware when GPIOA is secure.
0: non secure
1: secure

9.8.38 RCC AHB3 security status register (RCC_AHB3SECSR)

Address: 0x0F0
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN =1), this register provides AHB3 peripheral clock
security status. When a peripheral is configured as secure, its clock is also secure.
Both privileged and unprivileged, secure and non-secure accesses are allowed.
When the system is not secure (TZEN = 0), this register is RAZ.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPI1SECF

FMCSECF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 OSPI1SECF: OCTOSPI1 clock security flag
This flag is set by hardware when OCTOSPI1 is secure.
0: non secure
1: secure
Bits 7:1 Reserved, must be kept at reset value.
Bit 0 FMCSECF: FMC clock security flag
This flag is set by hardware when FMC is secure.
0: non secure
1: secure

414/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

9.8.39 RCC APB1 security status register 1 (RCC_APB1SECSR1)

Address: 0x0F8
Reset value: 0x0000 0400
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN = 1), this register provides APB1 peripheral clock
security status. When a peripheral is configured as secure, its clock is also secure.
Both privileged and unprivileged, secure and non-secure accesses are allowed.
When the system is not secure (TZEN = 0), this register is RAZ.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPAMPSECF
LPTIM1SECF

UART5SECF

UART4SECF

UART3SECF

UART2SECF
DAC1SECF

PWRSECF

I2C3SECF

I2C2SECF

I2C1SECF
CRSSECF
Res. Res. Res. Res.

r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RTCAPBSECF
WWDGSECF

TIM7SECF

TIM6SECF

TIM5SECF

TIM4SECF

TIM3SECF

TIM2SECF
SPI3SECF

SPI2SECF

Res. Res. Res. Res. Res. Res.

r r r r r r r r r r

Bit 31 LPTIM1SECF: LPTIM1 clock security flag

This flag is set by hardware when LPTIM1 is secure.
0: non secure
1: secure
Bit 30 OPAMPSECF: OPAMP clock security flag
This flag is set by hardware when OPAMP is secure.
0: non secure
1: secure
Bit 29 DAC1SECF: DAC1 clock security flag
This flag is set by hardware when DAC1 is secure.
0: non secure
1: secure
Bit 28 PWRSECF: PWR clock security flag
This flag is set by hardware when PWR is secure.
0: non secure
1: secure
Bits 27:25 Reserved, must be kept at reset value.
Bit 24 CRSSECF: CRS clock security flag
This flag is set by hardware when CRS is secure.
0: non secure
1: secure

RM0438 Rev 7 415/2194

427
Reset and clock control (RCC) RM0438

Bit 23 I2C3SECF: I2C3 clock security flag

This flag is set by hardware when I2C3 is secure.
0: non secure
1: secure
Bit 22 I2C2SECF: I2C2 clock security flag
This flag is set by hardware when I2C2 is secure.
0: non secure
1: secure
Bit 21 I2C1SECF: I2C1 clock security flag
This flag is set by hardware when I2C1 is secure.
0: non secure
1: secure
Bit 20 UART5SECF: UART5 clock security flag
This flag is set by hardware when UART5 is secure.
0: non secure
1: secure
Bit 19 UART4SECF: UART4 clock security flag
This flag is set by hardware when UART4 is secure.
0: non secure
1: secure
Bit 18 UART3SECF: UART3 clock security flag
This flag is set by hardware when UART3 is secure.
0: non secure
1: secure
Bit 17 UART2SECF: UART2 clock security flag
This flag is set by hardware when UART2 is secure.
0: non secure
1: secure
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SECF: SPI3 clock security flag
This flag is set by hardware when SPI3 is secure.
0: non secure
1: secure
Bit 14 SPI2SECF: SPI2 clock security flag
This flag is set by hardware when SPI2 is secure.
0: non secure
1: secure
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGSECF: WWDG clock security flag
This flag is set by hardware when WWDG is secure.
0: non secure
1: secure
Bit 10 RTCAPBSECF: RTC APB clock security flag
This flag is set by hardware when RTC APB is secure.
0: non secure
1: secure

416/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bits 9:6 Reserved, must be kept at reset value.

Bit 5 TIM7SECF: TIM7 clock security flag
This flag is set by hardware when TIM7 is secure.
0: non secure
1: secure
Bit 4 TIM6SECF: TIM6 clock security flag
This flag is set by hardware when TIM6 is secure.
0: non secure
1: secure
Bit 3 TIM5SECF: TIM5 clock security flag
This flag is set by hardware when TIM5 is secure.
0: non secure
1: secure
Bit 2 TIM4SECF: TIM4 clock security flag
This flag is set by hardware when TIM4 is secure.
0: non secure
1: secure
Bit 1 TIM3SECF: TIM3 clock security flag
This flag is set by hardware when TIM3 is secure.
0: non secure
1: secure
Bit 0 TIM2SECF: TIM2 clock security flag
This flag is set by hardware when TIM2 is secure.
0: non secure
1: secure

RM0438 Rev 7 417/2194

427
Reset and clock control (RCC) RM0438

9.8.40 RCC APB1 security status register 2 (RCC_APB1SECSR2)

Address: 0x0FC
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN = 1), this register provides APB1 peripheral clock
security status. When a peripheral is configured as secure, its clock is also secure.
Both privileged and unprivileged, secure and non-secure accesses are allowed.
When the system is not secure (TZEN = 0), this register is RAZ.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

UCPD1SECF

USBFSSECF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LPUART1SECF
FDCAN1SECF

LPTIM3SECF

LPTIM2SECF

I2C4SECF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 UCPD1SECF: UCPD1 clock security flag
This flag is set by hardware when UCPD1 is secure.
0: non secure
1: secure
Bit 22 Reserved, must be kept at reset value.
Bit 21 USBFSSECF: USB FS clock security flag
This flag is set by hardware when USB FS is secure.
0: non secure
1: secure
Bits 20:10 Reserved, must be kept at reset value.
Bit 9 FDCAN1SECF: FDCAN1 clock security flag
This flag is set by hardware when FDCAN1 is secure.
0: non secure
1: secure
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 LPTIM3SECF: LPTIM3 clock security flag
This flag is set by hardware when LPTIM3 is secure.
0: non secure
1: secure

418/2194 RM0438 Rev 7

RM0438 Reset and clock control (RCC)

Bit 5 LPTIM2SECF: LPTIM2 clock security flag

This flag is set by hardware when LPTIM2 is secure.
0: non secure
1: secure
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 I2C4SECF: I2C4 clock security flag
This flag is set by hardware when I2C4 is secure.
0: non secure
1: secure
Bit 0 LPUART1SECF: LPUART1 clock security flag
This flag is set by hardware when LPUART1 is secure.
0: non secure
1: secure

9.8.41 RCC APB2 security status register (RCC_APB2SECSR)

Address: 0x100
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
When the system is secure (TZEN = 1), this register provides APB2 peripheral clock
security status. When a peripheral is configured as secure, its clock is also secure.
Both privileged and unprivileged, secure and non-secure accesses are allowed.
When the system is not secure (TZEN = 0), this register is RAZ.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM1SECF

TIM17SECF

TIM16SECF

TIM15SECF
SAI2SECF

SAI1SECF

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYSCFGSECF
USART1SECF

TIM8SECF

TIM1SECF
SPI1SECF

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

r r r r r

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 DFSDM1SECF: DFSDM1 clock security flag
This flag is set by hardware when DFSDM1 is secure.
0: non secure
1: secure
Bit 23 Reserved, must be kept at reset value.

RM0438 Rev 7 419/2194

427
Reset and clock control (RCC) RM0438

Bit 22 SAI2SECF: SAI2 clock security flag

This flag is set by hardware when SAI2 is secure.
0: non secure
1: secure
Bit 21 SAI1SECF: SAI1 clock security flag
This flag is set by hardware when SAI1 is secure.
0: non secure
1: secure
Bits 20:19 Reserved, must be kept at reset value.
Bit 18 TIM17SECF: TIM17 clock security flag
This flag is set by hardware when TIM17 is secure.
0: non secure
1: secure
Bit 17 TIM16SECF: TIM16 clock security flag
This flag is set by hardware when TIM16 is secure.
0: non secure
1: secure
Bit 16 TIM15SECF: TIM15 clock security flag
This flag is set by hardware when TIM15 is secure.
0: non secure
1: secure
Bit 15 Reserved, must be kept at reset value.
Bit 14 USART1SECF: USART1 clock security flag
This flag is set by hardware when USART1 is secure.
0: non secure
1: secure
Bit 13 TIM8SECF: TIM8 clock security flag
This flag is set by hardware when TIM8 is secure.
0: non secure
1: secure
Bit 12 SPI1SECF: SPI1 clock security flag
This flag is set by hardware when SPI1 is secure.
0: non secure
1: secure
Bit 11 TIM1SECF: TIM1 clock security flag
This flag is set by hardware when TIM1 is secure.
0: non secure
1: secure
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGSECF: SYSCFG clock security flag
This flag is set by hardware when SYSCFG is secure.
0: non secure
1: secure

420/2194 RM0438 Rev 7

 0x018
0x014
0x010
0x008
0x004
0x000

0x00C
Offset
9.8.42
RM0438

RCC_
RCC_
RCC_
Name

CFGR
CFGR

PLLSAI2
PLLSAI1
Register

RCC_CR

PLLCFGR

RCC_CIER

Reset value
Reset value
Reset value

RCC_CFGR
RCC_ICSCR
Reset value 0
Res. Res. Res. PRIV 31
Res. Res. 30
Res. PLLSAI2PDIV[4:0] PLLSAI1PDIV[4:0] MCOPRE[2:0] PLLSAI2RDY 29
Res. PLLSAI2ON 28

Reset value 0 0 0 0 0
PLLPDIV[4:0]
Res. PLLSAI1RDY 27
Res. Res. PLLSAI1ON 26
RCC register map

PLLSAI1R[1:0] PLLR[1:0] MCOSEL[3:0]

HSITRIM[6:0]
Res. Res. PLLRDY 25

Reset value 0 0 0 0 0 0 0 0
Reset value 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0
Res. Res. PLLSAI1REN PLLREN PLLON 24
Res. Res. Res. Res. Res. Res. 23
Res. Res. Res. Res. 22
PLLSAI1Q[1:0] PLLQ[1:0]
Res. Res. Res. Res. 21

0 0 0
0 0 0
Res. Res. PLLSAI1QEN PLLQEN Res. Res. 20
Res. Res. Res. Res. Res. CSSON 19
Res. Res. Res. Res. Res. HSEBYP 18
HSICAL[7:0]

RM0438 Rev 7
Res. PLLSAI2P PLLSAI1P PLLP Res. HSERDY 17

0 0
0 0
0 0
0 0 0 0

Res. PLLSAI2PEN PLLSAI1PEN PLLPEN Res. HSEON 16

0
Res. Res. Res. Res. STOPWUCK Res. 15
Res. Res. Res. 14
Res. Res. 13
Res. PPRE2[2:0] Res. 12
Res. HSIASFS 11
Table 80. RCC register map and reset values

0
HSI48RDYIE HSIRDY 10
PLLN[6:0]
MSITRIM[7:0]

Res. PPRE1[2:0] HSIKERON 9

PLLSAI2N[6:0]
PLLSAI1N[6:0]
The following table gives the RCC register map and the reset values.

Res. HSION 8
PLLSAI2RDYIE 7
PLLSAI1RDYIE PLLSAI2M[3:0] PLLSAI1M[3:0] HPRE[3:0] MSIRANGE[3:0] 6
PLLRDYIE 5

0 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0
PLLM[3:0]

HSERDYIE 4
HSIRDYIE Res. Res. Res. SWS[1:0] MSIRGSEL 3
MSIRDYIE Res. Res. Res. MSIPLLEN 2
MSICAL[7:0]

LSERDYIE PLLSAI2SRC[1:0] PLLSAI1SRC[1:0] PLLSRC[1:0] SW[1:0] MSIRDY 1

1 0 0 0 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x

0 0
0 0
0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 0 0 0 1 1

0 0 0 0 0 0 0 0
LSIRDYIE MSION 0
Reset and clock control (RCC)

421/2194
427
 0x034
0x030
0x028
0x020

0x02C
0x01C
Offset

422/2194
RCC_
RCC_
RCC_
RCC_
RCC_
Name
Register

Reserved
RCC_CIFR

RCC_CICR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

AHB3RSTR
AHB2RSTR
AHB1RSTR

0x03C APB1RSTR2
0x038 APB1RSTR1
Res. LPTIM1RST Res. Res. Res. Res. Res. 31
Res. OPAMPRST Res. Res. Res. Res. Res. 30
Res. DAC1RST Res. Res. Res. Res. Res. 29

Reset value 0 0 0 0
Res. PWRRST Res. Res. Res. Res. Res. 28
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. Res. 27

Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25
Res. CRSRST Res. Res. Res. Res. Res. 24

0
UCPD1RST I2C3RST Res. Res. Res. Res. Res. 23
Res. I2C2RST Res. SDMMC1RST Res. Res. Res. 22

0
0 0
USBFSRST I2C1RST Res. OTDFDEC1RST Res. Res. Res. 21
Res. UART5RST Res. Res. Res. Res. Res. 20
Res. UART4RST Res. PKARST Res. Res. Res. 19
Res. USART3RST Res. RNGRST Res. Res. Res. 18

RM0438 Rev 7
0 0 0 0 0 0 0 0
Res. USART2RST Res. HASHRST Res. Res. Res. 17

0 0 0 0
0
Res. Res. Res. AESRST TSCRST Res. Res. 16
Res. SPI3RST Res. Res. Res. Res. Res. 15

Reserved

0 0
Res. SPI2RST Res. Res. Res. Res. Res. 14

0
Res. Res. Res. ADCRST Res. Res. Res. 13
0

Res. Res. Res. Res. CRCRST. Res. Res. 12

Res. Res. Res. Res. Res. Res. Res. 11
0
0

Res. Res. Res. Res. Res. HSI48RDYC HSI48RDYF 10

0
FDCAN1RST Res. Res. Res. Res. Res. Res. 9
Table 80. RCC register map and reset values (continued)

0
0

Res. Res. OSPI1RST Res. FLASHRST CSSC CSSF 8

Res. Res. Res. GPIOHRST Res. PLLSAI2RDYC PLLSAI2RDYF 7
LPTIM3RST Res. Res. GPIOGRST Res. PLLSAI1RDYC PLLSAI1RDYF 6

0 0
LPTIM2RST TIM7RST Res. GPIOFRST Res. PLLRDYC PLLRDYF 5
Res. TIM6RST Res. GPIOERST Res. HSERDYC HSERDYF 4
Res. TIM5RST Res. GPIODRST Res. HSIRDYC HSIRDYF 3
Res. TIM4RST Res. GPIOCRST DMAMUX1RST MSIRDYC MSIRDYF 2
I2C4RST TIM3RST Res. GPIOBRST DMA2RST LSERDYC LSERDYF 1

0 0 0 0 0 0
0 0 0 0 0 0 0 0

0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0

0
0 0 0

LPUART1RST TIM2RST FMCRST GPIOARST DMA1RST LSIRDYC LSIRDYF 0

RM0438
 0x064
0x060
0x058
0x054
0x050
0x048
0x040

0x05C
0x04C
Offset
RM0438

RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
RCC_
Name
Register

Reserved
Reserved

APB2ENR
AHB3ENR
AHB2ENR
AHB1ENR

APB1ENR2
APB1ENR1
APB2RSTR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Res. Res. LPTIM1EN Res. Res. Res. Res. 31
Res. Res. OPAMPEN Res. Res. Res. Res. 30
Res. Res. DAC1EN Res. Res. Res. Res. 29

Reset value 0 0 0 0
Res. Res. PWREN Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. Res. 25

0
0

DFSDM1EN Res. CRSEN Res. Res. Res. DFSDM1RST 24

0
Res. UCPD1EN I2C3EN Res. Res. Res. Res. 23

0
SAI2EN Res. I2C2EN Res. SDMMC1EN GTZCEN SAI2RST 22

0 0
0
0 0
0 0

SAI1EN USBFSEN I2C1EN Res. OTFDEC1EN Res. SAI1RST 21

Res. Res. UART5EN Res. Res. Res. Res. 20
Res. Res. UART4EN Res. PKAEN Res. Res. 19
TIM17EN Res. USART3EN Res. RNGEN Res. TIM17RST 18

RM0438 Rev 7
0 0 0 0 0 0 0 0
TIM16EN Res. USART2EN Res. HASHEN Res. TIM16RST 17

0 0 0
0 0 0 0
0
0 0 0

TIM15EN Res. Res. Res. AESEN TSCEN. TIM15RST 16

Res. Res. SPI3EN Res. Res. Res. Res. 15

Reserved
Reserved

0 0
USART1EN Res. SPI2EN Res. Res. Res. USART1RST 14
0

TIM8EN Res. Res. Res. ADCEN Res. TIM8RST 13

0

SPI1EN Res. Res. Res. Res. CRCEN SPI1RST 12

0 0 0 0
0 0 0 0

TIM1EN Res. WWDGEN Res. Res. Res. TIM1RST 11

0 0
Res. Res. RTCAPBEN Res. Res. Res. Res. 10

0
Res. FDCAN1EN Res. Res. Res. Res. Res. 9
Table 80. RCC register map and reset values (continued)

0
1

Res. Res. Res. OSPI1EN Res. FLASHEN Res. 8

Res. Res. Res. Res. GPIOHEN Res. Res. 7
Res. LPTIM3EN Res. Res. GPIOGEN Res. Res. 6

0 0
Res. LPTIM2EN TIM7EN Res. GPIOFEN Res. Res. 5
Res. Res. TIM6EN Res. GPIOEEN Res. Res. 4
Res. Res. TIM5EN Res. GPIODEN Res. Res. 3
Res. Res. TIM4EN Res. GPIOCEN DMAMUX1EN Res. 2
Res. I2C4EN TIM3EN Res. GPIOBEN DMA2EN Res. 1
0 0 0 0 0 0

0
0 0 0 0 0 0 0 0

0 0
0

0
0 0 0

SYSCFGEN LPUART1EN TIM2EN FMCEN GPIOAEN DMA1EN SYSCFGRST 0

Reset and clock control (RCC)

423/2194
427
 0x084
0x080
0x078
0x074
0x070
0x068

0x07C
0x06C
Offset

424/2194
Name

SMENR
SMENR
SMENR
SMENR
Register

SMENR2
SMENR1

Reserved
Reserved

Reset value
RCC_APB2
Reset value
RCC_APB1
RCC_APB1
Reset value
Reset value
Reset value

RCC_AHB3
RCC_AHB2
Res. Res. LPTIM1SMEN Res. Res. RCC_AHB1
Res. 31
Res. Res. OPAMPSMEN Res. Res. Res. 30
Res. Res. DAC1SMEN Res. Res. Res. 29

Reset value 1 1 1 1
Res. Res. PWRSMEN Res. Res. Res. 28
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. 27

Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. 25

1
DFSDM1SMEN Res. CRSSMEN Res. Res. Res. 24

1
Res. UCPD1SMEN I2C3SMEN Res. Res. ICACHESMEN 23
1 1

SAI2SMEN Res. I2C2SMEN Res. SDMMC1SMEN GTZCSMEN 22

1 1
1
1 1
SAI1SMEN USBSFSSMEN I2C1SMEN Res. OTFDEC1SMEN Res. 21
Res. Res. UART5SMEN Res. Res. Res. 20
Res. Res. UART4SMEN Res. PKASMEN Res. 19
TIM17SMEN Res. USART3SMEN Res. RNGSMEN Res. 18

RM0438 Rev 7
1 1 1 1 1 1 1 1
TIM16SMEN Res. USART2SMEN Res. HASHSMEN Res. 17

1 1 1
1 1 1 1
1

TIM15SMEN Res. Res. Res. AESSMEN TSCSMEN 16

Res. Res. SPI3SMEN Res. Res. Res. 15

Reserved
Reserved

1 1
USART1SMEN Res. SPI2SMEN Res. Res. Res. 14
1

TIM8SMEN Res. Res. Res. ADCSMEN Res. 13

1

SPI1SMEN Res. Res. Res. Res. CRCSMEN 12

1 1 1 1
TIM1SMEN Res. WWDGSMEN Res. Res. Res. 11

1 1
Res. Res. RTCAPBSMEN Res. Res. Res. 10

1
1

Res. FDCAN1SMEN Res. Res. SRAM2SMEN SRAM1SMEN 9

Table 80. RCC register map and reset values (continued)

1
1 1

Res. Res. Res. OSPI1SMEN Res. FLASHSMEN 8

Res. Res. Res. Res. GPIOHSMEN Res. 7
Res. LPTIM3SMEN Res. Res. GPIOGSMEN Res. 6

1 1
Res. LPTIM2SMEN TIM7SMEN Res. GPIOFSMEN Res. 5
Res. Res. TIM6SMEN Res. GPIOESMEN Res. 4
Res. Res. TIM5SMEN Res. GPIODSMEN Res. 3
Res. Res. TIM4SMEN Res. GPIOCSMEN DMAMUX1SMEN 2
Res. I2C4SMEN TIM3SMEN Res. GPIOBSMEN DMA2SMEN 1
1 1 1 1 1 1

1
1 1 1 1 1 1 1 1

1 1
1 1 1

SYSCFGSMEN LPUART1SMEN TIM2SMEN FMCSMEN GPIOASMEN DMA1SMEN 0

RM0438
 to
0xA4
0x098
0x094
0x090
0x088

0x0A8

0x0B8
0x0B4
0x0A0
Offset

0x09C
RM0438

RCC_
RCC_
RCC_
RCC_
Name

CFGR
CRRCR

CCIPR2
CCIPR1
Register

Reserved
Reserved
RCC_DLY
RCC_CSR

SECCFGR

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

RCC_BDCR
Res. Res. Res. Res. LPWRRSTF Res. Res. 31
Res. Res. Res. Res. WWDGRSTF Res. Res. 30
Res. Res. Res. Res. IWWDGRSTF Res. ADCSEL[1:0] 29
Res. Res. Res. Res. SFTRSTF Res. 28
Res. Res. Res. Res. BORRSTF Res. CLK48MSEL[1:0] 27
Res. Res. Res. Res. PINRSTF Res. 26

Reset value 0 0 0 0 1 0 1
Res. Res. Res. Res. OBLRSTF LSCOSEL FDCANSEL[1:0] 25

0 0
Res. Res. Res. Res. Res. LSCOEN 24

0
Res. Res. Res. Res. RMVF Res. LPTIM3SEL[1:0] 23
Res. Res. Res. Res. Res. Res. 22
Res. Res. Res. Res. Res. 21
OSPISEL[1:0] LPTIM2SEL[1:0]

0 0
Res. Res. Res. Res. Res. 20
Res. Res. Res. Res. Res. Res. LPTIM1SEL[1:0] 19
Res. Res. Res. Res. Res. Res. 18

RM0438 Rev 7
Res. Res. Res. Res. Res. Res. I2C3SEL[1:0] 17
Res. Res. Res. Res. Res. BDRST 16
0 0

Res. Res. Res. Res. RTCEN I2C2SEL[1:0] 15

Reserved
Reserved
0
Res. Res. SDMMCSEL Res. Res. 14
Res. Res. Res. Res. Res. 13
I2C1SEL[1:0]
RMVFSEC Res. Res. Res. Res. 12
0

HSI48SEC Res. Res. LSESYSRDY LPUART1SEL[1:0] 11

CLK48MSEC Res. MSISRANGE[3:0] Res. 10
PLLSAI2SEC Res. SAI2SEL[2:0] 9
HSI48CAL[8:0]
RTCSEL[1:0] UART5SEL[1:0]
Table 80. RCC register map and reset values (continued)

0 1 1 0

PLLSAI1SEC Res. 8
PLLSEC Res. x x x x x x x x x Res. LSESYSEN UART4SEL[1:0] 7
PRESCSEC Res. SAI1SEL[2:0] Res. Res. LSECSSD 6
SYSCLKSEC Res. Res. Res. LSECSSON USART3SEL[1:0] 5
0

LSESEC Res. ADFSDMSEL[1:0] Res. LSIPRE LSEDRV[1:0] 4

LSISEC Res. Res. USART2SEL[1:0] 3
MSISEC DFSDMSEL Res. Res. LSEBYP 2
HSESEC HSI48RDY LSIRDY LSERDY 1

1_DLY
I2C4SEL[1:0] USART1SEL[1:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0
0 0 0 0 0 0 0 0 0 0

0 0 0 0
0 0

OCTOSPI
HSISEC HSI48ON LSION LSEON 0
Reset and clock control (RCC)

425/2194
427
 to

0x0F0

0x0F4
0x0E8
0x0E4
Offset

0x0C0

0x0FC
0x0BC

426/2194
RCC_
RCC_
RCC_
RCC_
Name

SECSR
Register

SECSR2
0x0F8 SECSR1
Reserved
Reserved

Reset value
RCC_APB1
RCC_APB1
Reset value
Reset value
Reset value
Reset value

AHB3SECSR
0x0EC AHB2SECSR
AHB1SECSR
Res. LPTIM1SECF Res. Res. Res. Res. 31
Res. OPAMPSECF Res. Res. Res. Res. 30
Res. DAC1SECF Res. Res. Res. Res. 29

Reset value 0 0 0 0
Res. PWRSECF Res. Res. Res. Res. 28
Reset and clock control (RCC)

Res. Res. Res. Res. Res. Res. 27

Res. Res. Res. Res. Res. Res. 26
Res. Res. Res. Res. Res. Res. 25
Res. CRSSECF Res. Res. Res. Res. 24

0
UCPD1SECF I2C3SECF Res. Res. ICACHESECF Res. 23

0 1
Res. I2C2SECF Res. SDMMC1SECF GTZCSECF Res. 22

0
0 1
USBFSSECF I2C1SECF Res. OTFDEC1SECF Res. Res. 21
Res. UART5SECF Res. Res. Res. Res. 20
Res. UART4SECF Res. Res. Res. Res. 19
Res. UART3SECF Res. Res. Res. Res. 18

RM0438 Rev 7
0 0 0 0 0 0 0 0
Res. UART2SECF Res. Res. 0 Res. Res. 17
Res. Res. Res. Res. TSCSECF Res. 16
Res. SPI3SECF Res. Res. Res. Res. 15

Reserved
Reserved

0 0
Res. SPI2SECF Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. 13
0

Res. Res. Res. Res. CRCESECF RMVFSECF 12

Res. WWDGSECF Res. Res. Res. HSI48SECF 11

0 1
Res. RTCAPBSECF Res. Res. Res. CLK48MSECF 10

0
1
FDCAN1SECF Res. Res. SRAM2SECF SRAM1SECF PLLSAI2SECF 9
Table 80. RCC register map and reset values (continued)

0
1 1

Res. Res. OSPI1SECF Res. FLASHSECF PLLSAI1SECF 8

Res. Res. Res. GPIOHSECF Res. PLLSECF 7
LPTIM3SECF Res. Res. GPIOGSECF Res. PRESCSECF 6

0 0
LPTIM2SECF TIM7SECF Res. GPIOFSECF Res. SYSCLKSECF 5
Res. TIM6SECF Res. GPIOESECF Res. LSESECF 4
Res. TIM5SECF Res. GPIODSECF Res. LSISECF 3
Res. TIM4SECF Res. GPIOCSECF DMAMUX1SECF MSISECF 2
I2C4SECF TIM3SECF Res. GPIOBSECF DMA2SECF HSESECF 1

0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0

0 0
1 1 1 1 1 1 1 1
0 0 0

LPUART1SECF TIM2SECF FMCSECF GPIOASECF DMA1SECF HSISECF 0

RM0438
RM0438 Reset and clock control (RCC)

Table 80. RCC register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Name

SYSCFGSECF
DFSDM1SECF

USART1SECF
TIM17SECF
TIM16SECF
TIM15SECF

TIM8SECF

TIM1SECF
SAI2SECF
SAI1SECF

SPI1SECF
RCC_ Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x100 APB2SECSR

Reset value 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

RM0438 Rev 7 427/2194

427
Clock recovery system (CRS) RM0438

10 Clock recovery system (CRS)

10.1 Introduction
The clock recovery system (CRS) is an advanced digital controller acting on the internal
fine-granularity trimmable RC oscillator HSI48. The CRS provides powerful means for
oscillator output frequency evaluation, based on comparison with a selectable
synchronization signal. It is capable of doing automatic adjustment of oscillator trimming
based on the measured frequency error value, while keeping the possibility of a manual
trimming.
The CRS is ideally suited to provide a precise clock to the USB peripheral. In such case, the
synchronization signal can be derived from the start-of-frame (SOF) packet signalization on
the USB bus, which is sent by a USB host at 1 ms intervals.
The synchronization signal can also be derived from the LSE oscillator output or it can be
generated by user software.

10.2 CRS main features

• Selectable synchronization source with programmable prescaler and polarity:
– External pin
– LSE oscillator output
– USB SOF packet reception
• Possibility to generate synchronization pulses by software
• Automatic oscillator trimming capability with no need of CPU action
• Manual control option for faster start-up convergence
• 16-bit frequency error counter with automatic error value capture and reload
• Programmable limit for automatic frequency error value evaluation and status reporting
• Maskable interrupts/events:
– Expected synchronization (ESYNC)
– Synchronization OK (SYNCOK)
– Synchronization warning (SYNCWARN)
– Synchronization or trimming error (ERR)

10.3 CRS implementation

Table 81. CRS features
Feature CRS1

TRIM width 7 bits

428/2194 RM0438 Rev 7

RM0438 Clock recovery system (CRS)

10.4 CRS functional description

10.4.1 CRS block diagram

Figure 35. CRS block diagram

CRS_SYNC
GPIO

SYNCSRC SWSYNC

OSC32_IN SYNC divider

LSE (/1,/2,/4,…,/128)
OSC32_OUT
SYNC

USB_DP
FELIM
USB
USB_DM

TRIM FEDIR FECAP

RCC RC 48 MHz 16-bit counter

RELOAD

HSI48 To USB
To RNG
MSv34708V1

10.4.2 Synchronization input

The CRS synchronization (SYNC) source, selectable through the CRS_CFGR register, can
be the signal from the LSE clock or the USB SOF signal. For a better robustness of the
SYNC input, a simple digital filter (2 out of 3 majority votes, sampled by the RC48 clock) is
implemented to filter out any glitches. This source signal also has a configurable polarity
and can then be divided by a programmable binary prescaler to obtain a synchronization
signal in a suitable frequency range (usually around 1 kHz).
For more information on the CRS synchronization source configuration, refer to
Section 10.7.2: CRS configuration register (CRS_CFGR).
It is also possible to generate a synchronization event by software, by setting the SWSYNC
bit in the CRS_CR register.

RM0438 Rev 7 429/2194

438
Clock recovery system (CRS) RM0438

10.4.3 Frequency error measurement

The frequency error counter is a 16-bit down/up counter which is reloaded with the RELOAD
value on each SYNC event. It starts counting down till it reaches the zero value, where the
ESYNC (expected synchronization) event is generated. Then it starts counting up to the
OUTRANGE limit where it eventually stops (if no SYNC event is received) and generates a
SYNCMISS event. The OUTRANGE limit is defined as the frequency error limit (FELIM field
of the CRS_CFGR register) multiplied by 128.
When the SYNC event is detected, the actual value of the frequency error counter and its
counting direction are stored in the FECAP (frequency error capture) field and in the FEDIR
(frequency error direction) bit of the CRS_ISR register. When the SYNC event is detected
during the downcounting phase (before reaching the zero value), it means that the actual
frequency is lower than the target (and so, that the TRIM value must be incremented), while
when it is detected during the upcounting phase it means that the actual frequency is higher
(and that the TRIM value must be decremented).

Figure 36. CRS counter behavior

CRS counter value

RELOAD

ESYNC

Down Up

Frequency
OUTRANGE error counter
(128 x FELIM) stopped

WARNING LIMIT
(3 x FELIM)
TOLERANCE LIMIT
(FELIM)

Trimming action: 0 +2 +1 0 -1 -2 0
CRS event: SYNCERR SYNCWARN SYNCOK SYNCWARN

SYNCMISS
MSv32122V1

430/2194 RM0438 Rev 7

RM0438 Clock recovery system (CRS)

10.4.4 Frequency error evaluation and automatic trimming

The measured frequency error is evaluated by comparing its value with a set of limits:
– TOLERANCE LIMIT, given directly in the FELIM field of the CRS_CFGR register
– WARNING LIMIT, defined as 3 * FELIM value
– OUTRANGE (error limit), defined as 128 * FELIM value
The result of this comparison is used to generate the status indication and also to control the
automatic trimming which is enabled by setting the AUTOTRIMEN bit in the CRS_CR
register:
• When the frequency error is below the tolerance limit, it means that the actual trimming
value in the TRIM field is the optimal one, hence no trimming action is needed.
– SYNCOK status indicated
– TRIM value not changed in AUTOTRIM mode
• When the frequency error is below the warning limit but above or equal to the tolerance
limit, it means that some trimming action is necessary but that adjustment by one
trimming step is enough to reach the optimal TRIM value.
– SYNCOK status indicated
– TRIM value adjusted by one trimming step in AUTOTRIM mode
• When the frequency error is above or equal to the warning limit but below the error
limit, it means that a stronger trimming action is necessary, and there is a risk that the
optimal TRIM value is not reached for the next period.
– SYNCWARN status indicated
– TRIM value adjusted by two trimming steps in AUTOTRIM mode
• When the frequency error is above or equal to the error limit, it means that the
frequency is out of the trimming range. This can also happen when the SYNC input is
not clean or when some SYNC pulse is missing (for example when one USB SOF is
corrupted).
– SYNCERR or SYNCMISS status indicated
– TRIM value not changed in AUTOTRIM mode
Note: If the actual value of the TRIM field is so close to its limits that the automatic trimming would
force it to overflow or underflow, then the TRIM value is set just to the limit and the
TRIMOVF status is indicated.
In AUTOTRIM mode (AUTOTRIMEN bit set in the CRS_CR register), the TRIM field of
CRS_CR is adjusted by hardware and is read-only.

10.4.5 CRS initialization and configuration

RELOAD value
The RELOAD value must be selected according to the ratio between the target frequency
and the frequency of the synchronization source after prescaling. It is then decreased by
one to reach the expected synchronization on the zero value. The formula is the following:
RELOAD = (fTARGET / fSYNC) - 1
The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a
synchronization signal frequency of 1 kHz (SOF signal from USB).

RM0438 Rev 7 431/2194

438
Clock recovery system (CRS) RM0438

FELIM value
The selection of the FELIM value is closely coupled with the HSI48 oscillator characteristics
and its typical trimming step size. The optimal value corresponds to half of the trimming step
size, expressed as a number of HSI48 oscillator clock ticks. The following formula can be
used:
FELIM = (fTARGET / fSYNC) * STEP[%] / 100% / 2
The result must be always rounded up to the nearest integer value to obtain the best
trimming response. If frequent trimming actions are not needed in the application, the
hysteresis can be increased by slightly increasing the FELIM value.
The reset value of the FELIM field corresponds to (fTARGET / fSYNC) = 48000 and to a typical
trimming step size of 0.14%.
Caution: There is no hardware protection from a wrong configuration of the RELOAD and FELIM
fields which can lead to an erratic trimming response. The expected operational mode
requires proper setup of the RELOAD value (according to the synchronization source
frequency), which is also greater than 128 * FELIM value (OUTRANGE limit).

10.5 CRS low-power modes

Table 82. Effect of low-power modes on CRS
Mode Description

Sleep No effect. CRS interrupts cause the device to exit the Sleep mode.
CRS registers are frozen. The CRS stops operating until the Stop mode is exited and the
Stop
HSI48 oscillator restarted.
Standby The CRS peripheral is powered down and must be reinitialized after exiting Standby mode.

10.6 CRS interrupts

Table 83. Interrupt control bits
Enable Clear
Interrupt event Event flag
control bit flag bit

Expected synchronization ESYNCF ESYNCIE ESYNCC

Synchronization OK SYNCOKF SYNCOKIE SYNCOKC
Synchronization warning SYNCWARNF SYNCWARNIE SYNCWARNC
Synchronization or trimming error
ERRF ERRIE ERRC
(TRIMOVF, SYNCMISS, SYNCERR)

432/2194 RM0438 Rev 7

RM0438 Clock recovery system (CRS)

10.7 CRS registers

Refer to Section 1.2 on page 76 for a list of abbreviations used in register descriptions.
The peripheral registers can be accessed only by words (32-bit).

10.7.1 CRS control register (CRS_CR)

Address offset: 0x00
Reset value: 0x0000 X000 (X=4 for products supporting 7-bit TRIM width, otherwise X=2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SW AUTO ESYNCI SYNC SYNC
Res. TRIM[6:0] CEN Res. ERRIE
SYNC TRIMEN E WARNIE OKIE
rw rw rw rw rw rw rw rt_w1 rw rw rw rw rw rw

Bits 31:15 Reserved, must be kept at reset value.

Bits 14:8 TRIM[6:0]: HSI48 oscillator smooth trimming
For product supporting the 7-bit TRIM width (see Section 10.3), the default value of the
HSI48 oscillator smooth trimming is 64, which corresponds to the middle of the trimming
interval.
For products supporting the 6-bit TRIM width (see Section 10.3) this bit is reserved, must be
kept at reset value.
Bit 7 SWSYNC: Generate software SYNC event
This bit is set by software in order to generate a software SYNC event. It is automatically
cleared by hardware.
0: No action
1: A software SYNC event is generated.
Bit 6 AUTOTRIMEN: Automatic trimming enable
This bit enables the automatic hardware adjustment of TRIM bits according to the measured
frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The
TRIM value can be adjusted by hardware by one or two steps at a time, depending on the
measured frequency error value. Refer to Section 10.4.4 for more details.
0: Automatic trimming disabled, TRIM bits can be adjusted by the user.
1: Automatic trimming enabled, TRIM bits are read-only and under hardware control.
Bit 5 CEN: Frequency error counter enable
This bit enables the oscillator clock for the frequency error counter.
0: Frequency error counter disabled
1: Frequency error counter enabled
When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
Bit 4 Reserved, must be kept at reset value.
Bit 3 ESYNCIE: Expected SYNC interrupt enable
0: Expected SYNC (ESYNCF) interrupt disabled
1: Expected SYNC (ESYNCF) interrupt enabled

RM0438 Rev 7 433/2194

438
Clock recovery system (CRS) RM0438

Bit 2 ERRIE: Synchronization or trimming error interrupt enable

0: Synchronization or trimming error (ERRF) interrupt disabled
1: Synchronization or trimming error (ERRF) interrupt enabled
Bit 1 SYNCWARNIE: SYNC warning interrupt enable
0: SYNC warning (SYNCWARNF) interrupt disabled
1: SYNC warning (SYNCWARNF) interrupt enabled
Bit 0 SYNCOKIE: SYNC event OK interrupt enable
0: SYNC event OK (SYNCOKF) interrupt disabled
1: SYNC event OK (SYNCOKF) interrupt enabled

10.7.2 CRS configuration register (CRS_CFGR)

This register can be written only when the frequency error counter is disabled (CEN bit is
cleared in CRS_CR). When the counter is enabled, this register is write-protected.
Address offset: 0x04
Reset value: 0x2022 BB7F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNCPOL Res. SYNCSRC[1:0] Res. SYNCDIV[2:0] FELIM[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RELOAD[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SYNCPOL: SYNC polarity selection

This bit is set and cleared by software to select the input polarity for the SYNC signal source.
0: SYNC active on rising edge (default)
1: SYNC active on falling edge
Bit 30 Reserved, must be kept at reset value.
Bits 29:28 SYNCSRC[1:0]: SYNC signal source selection
These bits are set and cleared by software to select the SYNC signal source.
00: GPIO selected as SYNC signal source
01: LSE selected as SYNC signal source
10: USB SOF selected as SYNC signal source (default).
11: Reserved
Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the
periodic USB SOF is not generated by the host. No SYNC signal is therefore provided
to the CRS to calibrate the HSI48 oscillator on the run. To guarantee the required clock
precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs
should be used as SYNC signal.
Bit 27 Reserved, must be kept at reset value.

434/2194 RM0438 Rev 7

RM0438 Clock recovery system (CRS)

Bits 26:24 SYNCDIV[2:0]: SYNC divider

These bits are set and cleared by software to control the division factor of the SYNC signal.
000: SYNC not divided (default)
001: SYNC divided by 2
010: SYNC divided by 4
011: SYNC divided by 8
100: SYNC divided by 16
101: SYNC divided by 32
110: SYNC divided by 64
111: SYNC divided by 128
Bits 23:16 FELIM[7:0]: Frequency error limit
FELIM contains the value to be used to evaluate the captured frequency error value latched
in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section 10.4.4 for more details
about FECAP evaluation.
Bits 15:0 RELOAD[15:0]: Counter reload value
RELOAD is the value to be loaded in the frequency error counter with each SYNC event.
Refer to Section 10.4.3 for more details about counter behavior.

10.7.3 CRS interrupt and status register (CRS_ISR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FECAP[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRIM SYNC SYNC SYNC SYNC
FEDIR Res. Res. Res. Res. Res. Res. Res. Res. ESYNCF ERRF
OVF MISS ERR WARNF OKF
r r r r r r r r

Bits 31:16 FECAP[15:0]: Frequency error capture

FECAP is the frequency error counter value latched in the time of the last SYNC event.
Refer to Section 10.4.4 for more details about FECAP usage.
Bit 15 FEDIR: Frequency error direction
FEDIR is the counting direction of the frequency error counter latched in the time of the last
SYNC event. It shows whether the actual frequency is below or above the target.
0: Upcounting direction, the actual frequency is above the target.
1: Downcounting direction, the actual frequency is below the target.
Bits 14:11 Reserved, must be kept at reset value.
Bit 10 TRIMOVF: Trimming overflow or underflow
This flag is set by hardware when the automatic trimming tries to over- or under-flow the
TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is
cleared by software by setting the ERRC bit in the CRS_ICR register.
0: No trimming error signalized
1: Trimming error signalized

RM0438 Rev 7 435/2194

438
Clock recovery system (CRS) RM0438

Bit 9 SYNCMISS: SYNC missed

This flag is set by hardware when the frequency error counter reached value FELIM * 128
and no SYNC was detected, meaning either that a SYNC pulse was missed or that the
frequency error is too big (internal frequency too high) to be compensated by adjusting the
TRIM value, and that some other action has to be taken. At this point, the frequency error
counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is
set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR
register.
0: No SYNC missed error signalized
1: SYNC missed error signalized
Bit 8 SYNCERR: SYNC error
This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the
measured frequency error is greater than or equal to FELIM * 128. This means that the
frequency error is too big (internal frequency too low) to be compensated by adjusting the
TRIM value, and that some other action has to be taken. An interrupt is generated if the
ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in
the CRS_ICR register.
0: No SYNC error signalized
1: SYNC error signalized
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ESYNCF: Expected SYNC flag
This flag is set by hardware when the frequency error counter reached a zero value. An
interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by
software by setting the ESYNCC bit in the CRS_ICR register.
0: No expected SYNC signalized
1: Expected SYNC signalized
Bit 2 ERRF: Error flag
This flag is set by hardware in case of any synchronization or trimming error. It is the logical
OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE
bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit
in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
0: No synchronization or trimming error signalized
1: Synchronization or trimming error signalized
Bit 1 SYNCWARNF: SYNC warning flag
This flag is set by hardware when the measured frequency error is greater than or equal to
FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency
error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the
SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCWARNC bit in the CRS_ICR register.
0: No SYNC warning signalized
1: SYNC warning signalized
Bit 0 SYNCOKF: SYNC event OK flag
This flag is set by hardware when the measured frequency error is smaller than FELIM * 3.
This means that either no adjustment of the TRIM value is needed or that an adjustment by
one trimming step is enough to compensate the frequency error. An interrupt is generated if
the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the
SYNCOKC bit in the CRS_ICR register.
0: No SYNC event OK signalized
1: SYNC event OK signalized

436/2194 RM0438 Rev 7

RM0438 Clock recovery system (CRS)

10.7.4 CRS interrupt flag clear register (CRS_ICR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC SYNC
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ESYNCC ERRC
WARNC OKC
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 ESYNCC: Expected SYNC clear flag
Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
Bit 2 ERRC: Error clear flag
Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
the ERRF flag in the CRS_ISR register.
Bit 1 SYNCWARNC: SYNC warning clear flag
Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
Bit 0 SYNCOKC: SYNC event OK clear flag
Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.

RM0438 Rev 7 437/2194

438
Clock recovery system (CRS) RM0438

10.7.5 CRS register map

Table 84. CRS register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SYNCWARNIE
AUTOTRIMEN

SYNCOKIE
ESYNCIE
SWSYNC
TRIM[6]

ERRIE
CEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
CRS_CR TRIM[5:0]
0x00

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYNCPOL

SYNC SYNC
Res.

Res.

CRS_CFGR SRC DIV FELIM[7:0] RELOAD[15:0]

0x04 [1:0] [2:0]

Reset value 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1

SYNCWARNF
SYNCMISS
SYNCERR

SYNCOKF
TRIMOVF

ESYNCF
FEDIR

ERRF
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
CRS_ISR FECAP[15:0]
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SYNCWARNC
SYNCOKC
ESYNCC
ERRC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRS_ICR
0x0C

Reset value 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

438/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

11 General-purpose I/Os (GPIO)

11.1 Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL) and a secure configuration register
(GPIOx_SECCFGR).

11.2 GPIO main features

• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
• Analog function
• Alternate function selection registers
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
• TrustZone security support

11.3 GPIO functional description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is

RM0438 Rev 7 439/2194

458
General-purpose I/Os (GPIO) RM0438

to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there
is no risk of an IRQ occurring between the read and the modify access.
Figure 37 and Figure 38 show the basic structures of a standard and a 5-Volt tolerant I/O
port bit, respectively. Table 85 gives the possible port bit configurations.

Figure 37. Basic structure of an I/O port bit

Analog
To on-chip
peripheral Alternate function input

on/off
Input data register

Read
VDDIOxVDDIOx
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Output data register

Write

Output driver VDDIOx on/off Protection

Pull
down diode
P-MOS
VSS
Output VSS
control
N-MOS
Read/write
VSS
Push-pull,
From on-chip open-drain or
peripheral Alternate function output
disabled
Analog

MS31476V1

Figure 38. Basic structure of a 5-Volt tolerant I/O port bit

To on-chip
peripheral
Alternate function input

on/off
Input data register

Read (1)
VDDIOx VDD_FT

TTL Schmitt
Bit set/reset registers

Protection
trigger on/off
Pull diode
up
Input driver I/O pin
Write
Output data register

Output driver VDDIOx on/off Pull Protection

down
diode
P-MOS
Output VSS
VSS
control
Read/write N-MOS

From on-chip VSS

Push-pull,
peripheral Alternate function output open-drain or
disabled

ai15939d

1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.

440/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

Table 85. Port bit configuration table(1)

MODE(i) OSPEED(i) PUPD(i)
OTYPER(i) I/O configuration
[1:0] [1:0] [1:0]

0 0 0 GP output PP
0 0 1 GP output PP + PU
0 1 0 GP output PP + PD
0 SPEED 1 1 Reserved
01
1 [1:0] 0 0 GP output OD
1 0 1 GP output OD + PU
1 1 0 GP output OD + PD
1 1 1 Reserved (GP output OD)
0 0 0 AF PP
0 0 1 AF PP + PU
0 1 0 AF PP + PD
0 SPEED 1 1 Reserved
10
1 [1:0] 0 0 AF OD
1 0 1 AF OD + PU
1 1 0 AF OD + PD
1 1 1 Reserved
x x x 0 0 Input Floating
x x x 0 1 Input PU
00
x x x 1 0 Input PD
x x x 1 1 Reserved (input floating)
x x x 0 0 Input/output Analog
x x x 0 1
11
x x x 1 0 Reserved
x x x 1 1
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.

RM0438 Rev 7 441/2194

458
General-purpose I/Os (GPIO) RM0438

11.3.1 General-purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in analog mode.
The debug pins are in AF pull-up/pull-down after reset:
• PA15: JTDI in pull-up
• PA14: JTCK/SWCLK in pull-down
• PA13: JTMS/SWDAT in pull-up
• PB4: NJTRST in pull-up
• PB3: JTDO in floating state no pull-up/pull-down
PH3/BOOT0 is in input mode during the reset until at least the end of the option byte loading
phase. See Section 11.3.15: Using PH3 as GPIO.
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.

11.3.2 I/O pin alternate function multiplexer and mapping

The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
• After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
• The specific alternate function assignments for each pin are detailed in the device
datasheet.
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
• Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
• GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
• Peripheral alternate function:
– Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
– Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.

442/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

– Configure the desired I/O as an alternate function in the GPIOx_MODER register.

• Additional functions:
– For the ADC, DAC and COMP, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC, DAC,
OPAMP and COMP registers.
As indicated above, for the additional functions (such as DAC or OPAMP), the
output is controlled by the corresponding peripheral. Care must be taken to select
the I/O port analog function before enabling the additional function output in the
peripheral control register.
– For the additional functions like RTC, WKUPx and oscillators, configure the
required function in the related RTC, PWR and RCC registers. These functions
have priority over the configuration in the standard GPIO registers.
Refer to the “Alternate function mapping” table in the device datasheet for the detailed
mapping of the alternate function I/O pins.

11.3.3 I/O port control registers

Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (push-
pull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pull-
up/pull-down whatever the I/O direction.

11.3.4 I/O port data registers

Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 11.6.5: GPIO port input data register (GPIOx_IDR) (x = A to H) and
Section 11.6.6: GPIO port output data register (GPIOx_ODR) (x = A to H) for the register
descriptions.

11.3.5 I/O data bitwise handling

The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.

RM0438 Rev 7 443/2194

458
General-purpose I/Os (GPIO) RM0438

There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.

11.3.6 GPIO locking mechanism

It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 11.6.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A to H)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details refer to LCKR register description in Section 11.6.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A to H).

11.3.7 I/O alternate function input/output

Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.

11.3.8 External interrupt/wakeup lines

All ports have external interrupt capability. To use external interrupt lines, the port can be
configured in input, output or alternate function mode (the port must not be configured in
analog mode).
Refer to Section 17: Extended interrupts and event controller (EXTI).

444/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

11.3.9 Input configuration

When the I/O port is programmed as input:
• The output buffer is disabled
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register provides the I/O state
Figure 39 shows the input configuration of the I/O port bit.

Figure 39. Input floating/pull up/pull down configurations

Input data register

on
Read
VDDIOx VDDIOx
Bit set/reset registers

TTL Schmitt on/off

trigger protection
pull diode
Write up
Output data register

input driver I/O pin

on/off
output driver
pull protection
down diode
VSS VSS
Read/write

MS31477V1

11.3.10 Output configuration

When the I/O port is programmed as output:
• The output buffer is enabled:
– Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
– Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
• The Schmitt trigger input is activated
• The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value
Figure 40 shows the output configuration of the I/O port bit.

RM0438 Rev 7 445/2194

458
General-purpose I/Os (GPIO) RM0438

Figure 40. Output configuration

Input data register

on
Read

TTL Schmitt VDDIOx VDDIOx

Bit set/reset registers

trigger
on/off
Write protection
Input driver diode

Output data register

pull
up
I/O pin
Output driver VDDIOx on/off

P-MOS pull protection

Output down diode
Read/write control VSS
N-MOS VSS
Push-pull or
VSS Open-drain
MS31478V1

11.3.11 Alternate function configuration

When the I/O port is programmed as alternate function:
• The output buffer can be configured in open-drain or push-pull mode
• The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
• A read access to the input data register gets the I/O state
Figure 41 shows the Alternate function configuration of the I/O port bit.

Figure 41. Alternate function configuration

To on-chip Alternate function input

peripheral
Input data register

on

Read
VDDIOxVDDIOx
TTL Schmitt on/off
Bit set/reset registers

trigger protection
Pull diode
Input driver up
Write
Output data register

I/O pin
Output driver VDD on/off

Pull protection
P-MOS down diode
Output
control VSS VSS
N-MOS
Read/write
VSS push-pull or
open-drain
From on-chip
peripheral Alternate function output

MSv34756V1

446/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

11.3.12 Analog configuration

When the I/O port is programmed as analog configuration:
• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled by hardware
• Read access to the input data register gets the value “0”
Figure 42 shows the high-impedance, analog-input configuration of the I/O port bits.

Figure 42. High impedance-analog configuration

Analog
To on-chip
peripheral
Input data register

Read off
0
VDDIOx
Bit set/reset registers

TTL Schmitt
trigger protection
Write diode
Output data register

Input driver
I/O pin

protection
diode

Read/write VSS

From on-chip Analog

peripheral MS31480V1

11.3.13 Using the HSE or LSE oscillator pins as GPIOs

When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the pin is reserved for
clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO.

11.3.14 Using the GPIO pins in the RTC supply domain

The PC13/PC14/PC15 GPIO functionality is lost when the core supply domain is powered
off (when the device enters Standby mode). In this case, if their GPIO configuration is not
bypassed by the RTC configuration, these pins are set in an analog input mode.
For details about I/O control by the RTC, refer to Section 41.3: RTC functional description.

RM0438 Rev 7 447/2194

458
General-purpose I/Os (GPIO) RM0438

11.3.15 Using PH3 as GPIO

PH3 may be used as boot pin (BOOT0) or as a GPIO. Depending on the nSWBOOT0 bit in
the user option byte, it switches from the input mode to the analog input mode:
• After the option byte loading phase if nSWBOOT0 = 1.
• After reset if nSWBOOT0 = 0.

11.4 TrustZone security

The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR. When the
TrustZone is active (TZEN=1), each I/O pin of GPIO port can be individually configured as
secure through the GPIOx_SECCFGR register.
When the selected I/O pin is configured as secure, its corresponding configuration bits for
alternate function, mode selection, I/O data are secure against a non-secure access. In
case of non-secure access, these bits are RAZ/WI.
The I/Os with peripherals functions are also conditioned by the peripheral security
configuration:
• For peripherals for which the I/O pin selection is done through alternate functions
registers: if the peripheral is configured as secure, it cannot be connected to a non-
secure I/O pin. If this is not respected, the input data to the secure peripheral is forced
to '0' (I/O input pin value is ignored) and the output pin value is forced to '0', thus
avoiding any secure information leak through non-secure I/Os.
• For I/Os with analog switches, directly controlled by peripherals (such as ADC for
instance): If the I/O is secure, the I/O analog switch cannot be controlled by a non-
secure peripheral. If this is not respected, the switch would remain open. This prevent
the redirection of secure data to a non-secure peripheral or I/O through analog path.
• Some of the paths between I/Os additional functions mainly and peripherals are not
blocked if the I/O is secure and the peripheral is non-secure. Therefore it is
recommended to configure those peripherals as secure even when not used by the
application. When the path has a security control, it follows the same rule as I/O
selection through alternate functions.
• Refer to the device pins definition table in datasheet for more information about
peripherals alternate functions and additional functions mapping.
After reset, all GPIO ports are secure.
Table 86 gives a summary of the I/O port secured bits following the security configuration bit
in the GPIO_SECCFGR register. When the I/O bit port is configured as secure:
• Secured bits: read and write operations are only allowed by a secure access. Non-
secure read or write accesses on secured bits are RAZ/WI. There is no illegal access
event generated.
• Non-secure bits: no restriction. Read and write operations are allowed by both secure
and non-secure accesses.
When the TrustZone security is disabled (TZEN = 0 in FLASH_OPTR register), all registers
bits are non-secure. The GPIOx_SECCFGR register is RAZ/WI.

448/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

Table 86. GPIO secured bits

Non-secure
Secure configuration bit Secured bit Register name access on secure
bits

MODEy[1:0] GPIOx_MODER
OTy GPIOx_OTYPER
OSPEEDy[1:0] GPIOx_OSPEEDR
PUPDy[1:0] GPIOx_PUPDR
IDy GPIOx_IDR
SECy = 1 in GPIOx_SECCFGR ODy GPIOx_ODR RAZ/WI
BSy GPIOx_BSRR
LCKy GPIOx_LCKR
AFSELy[3:0] GPIOx_AFRL
GPIOx_AFRH
BRy
GPIOx_BRR

Note: GPIOx, x= A..H , and y=0..15

11.5 Privileged and Unprivileged modes

All GPIO registers can be read and written by privileged and unprivileged accesses,
whatever the security state (secure or non-secure).

RM0438 Rev 7 449/2194

458
General-purpose I/Os (GPIO) RM0438

11.6 GPIO registers

This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 87.
The peripheral registers can be written in word, half word or byte mode.

11.6.1 GPIO port mode register (GPIOx_MODER)

(x =A to H)
Address offset:0x00
Reset value: 0xABFF FFFF (for port A)
Reset value: 0xFFFF FEBF (for port B)
Reset value: 0xFFFF FFFF (for ports C..G)
Reset value: 0x0000 000F (for port H)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MODE15[1:0] MODE14[1:0] MODE13[1:0] MODE12[1:0] MODE11[1:0] MODE10[1:0] MODE9[1:0] MODE8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MODE[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O mode.
00: Input mode
01: General purpose output mode
10: Alternate function mode
11: Analog mode (reset state)

11.6.2 GPIO port output type register (GPIOx_OTYPER)

(x = A to H)
Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

450/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OT[15:0]: Port x configuration I/O pin y (y = 15 to 0)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain

11.6.3 GPIO port output speed register (GPIOx_OSPEEDR)

(x = A to H)
Address offset: 0x08
Reset value: 0x0C00 0000 (for port A)
Reset value: 0x0000 0000 (for the other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OSPEED15 OSPEED14 OSPEED13 OSPEED12 OSPEED11 OSPEED10 OSPEED9 OSPEED8
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OSPEED7 OSPEED6 OSPEED5 OSPEED4 OSPEED3 OSPEED2 OSPEED1 OSPEED0
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 OSPEED[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed(1)
11: Very high speed(1)
Note: Refer to the device datasheet for the frequency specifications and the power supply
and load conditions for each speed..
1. Not available for FT_c IOs.

11.6.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR)

(x = A to H)
Address offset: 0x0C
Reset value: 0x6400 0000 (for port A)
Reset value: 0x0000 0100 (for port B)
Reset value: 0x0000 0000 (for other ports)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PUPD15[1:0] PUPD14[1:0] PUPD13[1:0] PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 451/2194

458
General-purpose I/Os (GPIO) RM0438

Bits 31:0 PUPD[15:0][1:0]: Port x configuration I/O pin y (y = 15 to 0)

These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved

11.6.5 GPIO port input data register (GPIOx_IDR)

(x = A to H)
Address offset: 0x10
Reset value: 0x0000 XXXX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 ID[15:0]: Port x input data I/O pin y (y = 15 to 0)
These bits are read-only. They contain the input value of the corresponding I/O port.

11.6.6 GPIO port output data register (GPIOx_ODR)

(x = A to H)
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port output data I/O pin y (y = 15 to 0)
These bits can be read and written by software.
Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the
GPIOx_BSRR register (x = A to H).

11.6.7 GPIO port bit set/reset register (GPIOx_BSRR)

(x = A to H)
Address offset: 0x18

452/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0
w w w w w w w w w w w w w w w w

Bits 31:16 BR[15:0]: Port x reset I/O pin y (y = 15 to 0)

These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Resets the corresponding ODx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BS[15:0]: Port x set I/O pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Sets the corresponding ODx bit

11.6.8 GPIO port configuration lock register (GPIOx_LCKR)

(x = A to H)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 453/2194

458
General-purpose I/Os (GPIO) RM0438

Bits 31:17 Reserved, must be kept at reset value.

Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit
returns ‘1’ until the next MCU reset or peripheral reset.

Bits 15:0 LCK[15:0]: Port x lock I/O pin y (y = 15 to 0)

These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked

11.6.9 GPIO alternate function low register (GPIOx_AFRL)

(x = A to H)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

454/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

Bits 31:0 AFSEL[7:0][3:0]: Alternate function selection for port x I/O pin y (y = 7 to 0)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

11.6.10 GPIO alternate function high register (GPIOx_AFRH)

(x = A to H)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 455/2194

458
General-purpose I/Os (GPIO) RM0438

Bits 31:0 AFSEL[15:8][3:0]: Alternate function selection for port x I/O pin y (y = 15 to 8)
These bits are written by software to configure alternate function I/Os.
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15

11.6.11 GPIO port bit reset register (GPIOx_BRR) (x = A to H)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 BR[15:0]: Port x reset IO pin y (y = 15 to 0)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODx bit
1: Reset the corresponding ODx bit

11.6.12 GPIO secure configuration register (GPIOx_SECCFGR) (x = A to H)

When the system is secure (TZEN = 1), this register provides write access security and can
be written only by a secure access. It is used to configure a selected I/O as secure. A non-
secure write access to this register is discarded. A non-secure read is possible, and thus
provides visibility on secured I/O pins on the GPIO port.
When the system is not secure (TZEN = 0), this register is WI and its content has no effect.
Address offset: 0x30
Reset value: 0x0000 FFFF (A to G) and 0x0000 000B (H)

456/2194 RM0438 Rev 7

RM0438 General-purpose I/Os (GPIO)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: Bits are “rw” when TZEN = 1.

Bits 31:16 Reserved

Bits 15:0 SEC[15:0]: I/O pin of Port x secure bit enable y (y= 0..15)
These bits are written by software to enable the security I/O port pin.
0: The I/O pin is non-secure
1: The I/O pin is secure. Refer to Table 86 for all corresponding secured bits.

RM0438 Rev 7 457/2194

458
 0x30
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04

0x1C

458/2194
11.6.13

H))

for H
for A...G
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

GPIOx_IDR

GPIOx_BRR
GPIOx_ODR

GPIOx_AFRL

GPIOx_AFRH
GPIOx_LCKR
GPIOx_BSRR
(where x = A..H)

(where x = A...H)
GPIOx_OTYPER

(where x = A to H)
(where x = A to H)
(where x = A to H)
(where x = A to H)
(where x = A to H)
(where x = A to H)
(where x = A to H)

GPIOx_SECCFGR
GPIOx_OSPEEDR

(where x = A..HA to
Offset Register name

0
0
0
0
Res. Res. Res. BR15 Res. Res. Res. 31
OSPEED15[1:0]

0
0
0
0
Res. Res. Res. BR14 Res. Res. Res. 30

0
0
0
0
Res. Res. Res. BR13 Res. Res. Res.

7[3:0]

15[3:0]
29
General-purpose I/Os (GPIO)

OSPEED14[1:0]

0
0
0
0
Res. Res. Res. BR12 Res. Res. Res. 28

0
0
0
0
Res. Res. Res. BR11 Res. Res. Res. 27
OSPEED13[1:0]
GPIO register map

0
0
0
0
Res. Res. Res. BR10 Res. Res. Res. 26

0
0
0
0
Res. Res. Res. BR9 Res. Res. Res.

6[3:0]

14[3:0]
OSPEED12[1:0] 25

0
0
0
0
Res. Res. Res. BR8 Res. Res. Res. 24

0
0
0
0
Res. Res. Res. BR7 Res. Res. Res. 23
OSPEED11[1:0]

0
0
0
Res. Res. Res. BR6 Res. Res. 0 Res. 22

0
0
0
0
Res. Res. Res. BR5 Res. Res. Res.

5[3:0]

13[3:0]
OSPEED10[1:0] 21

0
0
0
0

Res. Res. Res. BR4 Res. Res. Res. 20

0
0
0
0

Res. Res. Res. BR3 Res. Res. Res. 19

OSPEED9[1:0]

0
0
0
0

Res. Res. Res. BR2 Res. Res. Res. 18

RM0438 Rev 7
0
0
0
0

Res. Res. Res. BR1 Res. Res. Res.

4[3:0]

12[3:0]
OSPEED8[1:0] 17

0
0
0
0

0
Res. Res. LCKK BR0 Res. Res. Res. 16
x

0
0
0
0

0
1
0
0
0
0

SEC15 BR15 LCK15 BS15 OD15 ID15 OT15 15

OSPEED7[1:0]
x

0
0
0
0

0
1
0
0
0
0

SEC14 BR14 LCK14 BS14 OD14 ID14 OT14 14

x

0
0
0
0

0
1
0
0
0
0

SEC13 BR13 LCK13 BS13 OD13 ID13 OT13

3[3:0]

11[3:0]
OSPEED6[1:0] 13
x

0
0
0
0

0
1
0
0
0
0

SEC12 BR12 LCK12 BS12 OD12 ID12 OT12 12

x

0
0
0
0

0
1
0
0
0
0

SEC11 BR11 LCK11 BS11 OD11 ID11 OT11

Table 87. GPIO register map and reset values

OSPEED5[1:0]
11
x

0
0
0
0

0
1
0
0
0
0

SEC10 BR10 LCK10 BS10 OD10 ID10 OT10 10

The following table gives the GPIO register map and reset values.

0
0
0
0

0
1
0
0
0
0

SEC9 BR9 LCK9 BS9 OD9 ID9 OT9

2[3:0]

10[3:0]
9

Refer to Section 2.3 on page 87 for the register boundary addresses.

OSPEED4[1:0]
x

0
0
0
0

0
1
0
0
0
0

SEC8 BR8 LCK8 BS8 OD8 ID8 OT8 8

x

0
0
0
0

0
1
0
0
0
0

SEC7 BR7 LCK7 BS7 OD7 ID7 OT7 7

OSPEED3[1:0]
x

0
0
0
0

0
1
0
0
0
0

SEC6 BR6 LCK6 BS6 OD6 ID6 OT6 6

x

0
1
0
0
0
0

0
0
0
0

SEC5 BR5 LCK5 BS5 OD5 ID5 OT5

9[3:0]
1[3:0]

OSPEED2[1:0] 5
x

0
1
0
0
0
0

0
0
0
0

SEC4 BR4 LCK4 BS4 OD4 ID4 OT4 4

x

1
1
0
0
0
0

0
0
0
0

SEC3 BR3 LCK3 BS3 OD3 ID3 OT3 3

OSPEED1[1:0]
x

0
1
0
0
0
0

0
0
0
0

SEC2 BR2 LCK2 BS2 OD2 ID2 OT2 2

x

1
1
0
0
0
0

0
0
0
0

SEC1 BR1 LCK1 BS1 OD1 ID1 OT1

8[3:0]
0[3:0]

OSPEED0[1:0] 1
x

1
1
0
0
0
0

0
0
0
0

SEC0 BR0 LCK0 BS0 OD0 ID0 OT0 0

RM0438
RM0438 System configuration controller (SYSCFG)

12 System configuration controller (SYSCFG)

12.1 SYSCFG main features

The STM32L552xx and STM32L552xx devices feature a set of configuration registers. The
main purposes of the system configuration controller are the following:
• Managing robustness feature
• Setting SRAM2 write protection and software erase
• Configuring FPU interrupts
• Enabling/disabling the I2C fast-mode plus driving capability on some I/Os and voltage
booster for I/Os analog switches
• Configuring TrustZone security register access

12.2 SYSCFG TrustZone security and privilege

SYSCFG TrustZone security
When the TrustZone security is activated, the SYSCFG is able to secure registers from
being modified by non-secure accesses.
The TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
A non-secure read/write access to a secured register is RAZ/WI and generates an illegal
access event. An illegal access interrupt is generated if the SYSCFG illegal access event is
enabled in the GTZC_TZIC_IER register.

Privileged/unprivileged mode
The SYSCFG registers can be read and written by privileged and unprivileged accesses
except the SYSCFG registers for CPU configuration: SYSCFG_CSLCKR,
SYSCFG_FPUIMR and SYSCFG_CNSLCKR registers.
An unprivileged access to a privileged register is RAZ/WI.
Table 88 shows the register security overview.

Table 88. TrustZone security and privilege register accesses

SYSCFG register Privileged
Read/Write access
name /unprivileged access

TrustZone
TZEN=1 TZEN=0 NA
configuration(1)

Read: no restriction
Write: secure access only
SYSCFG_SECCFGR RAZ/WI No restriction
Write non-secure: is WI and
generates an illegal access event
Read/Write: secure access only
Read/Write non-secure: is RAZ/WI Privileged only
SYSCFG_CSLCKR RAZ/WI
and generates and an illegal access Unprivileged: RAZ/WI
event

RM0438 Rev 7 459/2194

471
System configuration controller (SYSCFG) RM0438

Table 88. TrustZone security and privilege register accesses (continued)

SYSCFG register Privileged
Read/Write access
name /unprivileged access

TrustZone
TZEN=1 TZEN=0 NA
configuration(1)

Read/Write secure access only if

FPUSEC bit is set
No Privileged only
SYSCFG_FPUIMR Read/Write non-secure: is RAZ/WI restriction Unprivileged: RAZ/WI
and generates an illegal access
event

No Privileged only
SYSCFG_CNSLCKR Read/write: no restriction
restriction Unprivileged: RAZ/WI
Read/Write: secure access only for
secure bits depending on peripheral
security bits in GTZSC_SECFGR
register No
SYSCFG_CFGR1 No restriction
restriction
Read/Write non-secure: only for
non-secure bits, otherwise is
RAZ/WI
– If SRAM2SEC bit is set:
Read/Write: secure access only
SYSCFG_SWPR,
Read/Write Non-secure: is RAZ/WI
SYSCFG_SWPR2, No
and generates an illegal access No restriction
SYSCFG_SKR, restriction
event
SYSCFG_SCSR
– If SRAM2SEC bit is reset:
Read/Write: no restriction
– If CLASSBSEC bit is set:
Read/Write: secure access only
Read/Write Non-secure: is RAZ/WI
No
SYSCFG_CFGR2 and generates an illegal access No restriction
restriction
event
– If CLASSBSEC bit is reset:
Read/Write: no restriction
RAZ/WI if register access is not
SYSCFG_RSSCMDR RAZ/WI No restriction
allowed(2)
1. TrustZone security is activated by the TZEN option bit in the FLASH_OPTR register.
2. Refer to register description for register access.

460/2194 RM0438 Rev 7

RM0438 System configuration controller (SYSCFG)

12.3 SYSCFG registers

12.3.1 SYSCFG secure configuration register (SYSCFG_SECCFGR)

When the system is secure (TZEN =1), this register provides write access security and can
be written only when the access is secure. It can be globally write-protected, or each bit of
this register can be individually write-protected.A non-secure write access is WI and
generates an illegal access event. There are no read restrictions.
When the system is not secure (TZEN=0), this register is RAZ/WI.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPUSE SRAM2 CLASS SYSCF
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
C SEC BSEC GSEC
rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 FPUSEC: FPU security.
0: SYSCFG_FPUIMR register can be written by secure and non-secure access
1: SYSCFG_FPUIMR register can be written by secure access only.
Bit 2 SRAM2SEC: SRAM2 security.
0: SYSCFG_SKR, SYSCFG_SCR and SYSCFG_SWPRx registers can be written by secure
and non-secure access
1: SYSCFG_SKR, SYSCFG_SCR and SYSCFG_SWPRx register can be written by secure
access only.
Bit 1 CLASSBSEC: ClassB security.
0: SYSCFG_CFGR2 register can be written by secure and non-secure access
1: SYSCFG_CFGR2 register can be written by secure access only.
Bit 0 SYSCFGSEC: SYSCFG clock control security.
0: SYSCFG configuration clock in RCC registers can be written by secure and non-secure
access
1: SYSCFG configuration clock in RCC registers can be written by secure access only.

12.3.2 SYSCFG configuration register 1 (SYSCFG_CFGR1)

When the system is secure (TZEN =1), this register can be a mix of secure and non-secure
bits depending on I2Cx, ADC security configuration bit in TZSC_SECCFGR register and
GPIO security bits. A non-secure read/write access on secured bits is RAZ/WI.
When the system is not secure (TZEN=0), there is no access restriction.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x04

RM0438 Rev 7 461/2194

471
System configuration controller (SYSCFG) RM0438

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2C_ I2C_ I2C_ I2C_
I2C4_ I2C3_ I2C2 I2C1
Res. Res. Res. Res. Res. Res. Res. Res. PB9_ PB8_ PB7_ PB6_
FMP FMP _FMP _FMP
FMP FMP FMP FMP
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ANAS BOOST
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
WVDD EN
rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bit 23 I2C4_FMP: I2C4 fast-mode plus (Fm+) driving capability activation.
This bit enables the Fm+ driving mode on I2C4 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C4 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C4 pins selected through AF selection bits.
Bit 22 I2C3_FMP: 12C3 fast-mode plus driving capability activation.
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C3 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C3 pins selected through AF selection bits.
Bit 21 I2C2_FMP: 12C2 fast-mode plus driving capability activation.
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C2 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C2 pins selected through AF selection bits.
Bit 20 I2C1_FMP: 12C1 fast-mode plus driving capability activation.
This bit enables the Fm+ driving mode on I2C3 pins selected through AF selection bits.
0: Fm+ mode is not enabled on I2C1 pins selected through AF selection bits
1: Fm+ mode is enabled on I2C1 pins selected through AF selection bits.
Bit 19 I2C_PB9_FMP: 12C1 fast-mode plus driving capability activation on PB9.
This bit enables the Fm+ driving mode for PB9.
0: PB9 pin operates in standard mode
1: Fm+ mode is enabled on PB9 pin, and the speed control is bypassed.
Bit 18 I2C_PB8_FMP: 12C1 fast-mode plus driving capability activation on PB8.
This bit enables the Fm+ driving mode for PB8.
0: PB8 pin operates in standard mode
1: Fm+ mode is enabled on PB8 pin, and the speed control is bypassed.
Bit 17 I2C_PB7_FMP: 12C1 fast-mode plus driving capability activation on PB7.
This bit enables the Fm+ driving mode for PB7.
0: PB7 pin operates in standard mode
1: Fm+ mode is enabled on PB7 pin, and the speed control is bypassed.
Bit 16 I2C_PB6_FMP: 12C1 fast-mode plus driving capability activation on PB6.
This bit enables the Fm+ driving mode for PB6.
0: PB6 pin operates in standard mode
1: Fm+ mode is enabled on PB6 pin, and the speed control is bypassed.
Bits 15:10 Reserved, must be kept at reset value.

462/2194 RM0438 Rev 7

RM0438 System configuration controller (SYSCFG)

Bit 9 ANASWVDD: GPIO analog switch control voltage selection.

0: I/O analog switches supplied by VDDA or booster when booster is ON
1: I/O analog switches supplied by VDD.
Note: Refer to Table 89: BOOSTEN and ANASWVDD set/reset for bit 9 setting.
Bit 8 BOOSTEN: I/O analog switch voltage booster enable.
0: I/O analog switches are supplied by VDDA voltage.
This is the recommended configuration when using the ADC in high VDDA voltage operation
1: I/O analog switches are supplied by a dedicated voltage booster (supplied by VDD).
This is the recommended configuration when using the ADC in low VDDA voltage operation.
Note: Refer to Table 89: BOOSTEN and ANASWVDD set/reset for bit 8setting.
Bits 7:0 Reserved, must be kept at reset value.

Table describes when the bit 8 (BOOSTEN) and the bit 9 (ANASWVDD) should be set or
reset depending on the voltage settings.

Table 89. BOOSTEN and ANASWVDD set/reset

VDD VDDA BOOSTEN ANASWVDD

- > 2.4 V 0
0
> 2.4 V 1
< 2.4 V
< 2.4 V 1 0

12.3.3 FPU interrupt mask register (SYSCFG_FPUIMR)

When the system is secure (TZEN =1), this register can be protected against non-secure
access by setting the FPUSEC bit in the SYSCFG_SECCFGR register. A non-secure
read/write access is RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register can be read and written by privileged access only. Unprivileged access is
RAZ/WI.
Address offset: 0x08
Reset value: 0x0000 001F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FPU_IE[5:0]
rw

RM0438 Rev 7 463/2194

471
System configuration controller (SYSCFG) RM0438

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 FPU_IE[5:0]: Floating point unit interrupts enable bits.
FPU_IE[5]: Inexact interrupt enable (interrupt disable at reset)
FPU_IE[4]: Input abnormal interrupt enable
FPU_IE[3]: Overflow interrupt enable
FPU_IE[2]: Underflow interrupt enable
FPU_IE[1]: Divide-by-zero interrupt enable
FPU_IE[0]: Invalid operation Interrupt enable

12.3.4 SYSCFG CPU non-secure lock register (SYSCFG_ CNSLCKR)

This register is used to lock the configuration of non-secure MPU and VTOR_NS registers.
This register can be read and written by privileged access only. Unprivileged access is
RAZ/WI.
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKN LOCKN
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SMPU SVTOR
rs rs

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 LOCKNSMPU: Non-secure MPU registers lock.
This bit is set by software and cleared only by a system reset. When is set, it disables write
access to non-secure MPU_CTRL_NS, MPU_RNR_NS and MPU_RBAR_NS registers.
0: Non-secure MPU registers write is enabled
1: Non-secure MPU registers write is disabled.
Bit 0 LOCKNSVTOR: VTOR_NS register lock.
This bit is set by software and cleared only by a system reset.
0: VTOR_NS register write is enabled
1: VTOR_NS register write is disabled.

12.3.5 SYSCFG CPU secure lock register (SYSCFG _CSLOCKR)

This register is used to lock the configuration of PRIS and BFHFNMINS bits in the AIRCR
register, SAU, secure MPU and VTOR_S registers.
When the system is secure (TZEN =1), this register can be written only when the access is
secure. A non-secure read/write access is RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), this register is RAZ/WI
This register can be read and written by privileged access only. Unprivileged access is
RAZ/WI.

464/2194 RM0438 Rev 7

RM0438 System configuration controller (SYSCFG)

Address offset: 0x10

Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LOCKS
LOCKS LOCKS
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VTAIR
AU MPU
CR
rs rs rs

Bits 31:3 Reserved, must be kept at reset value.

Bit 2 LOCKSAU: SAU registers lock.
This bit is set by software and cleared only by a system reset. When is set, it disables write
access to SAU_CTRL, SAU_RNR, SAU_RBAR and SAU_RLAR registers.
0: SAU registers write is enabled
1: SAU registers write is disabled.
Bit 1 LOCKSMPU: Secure MPU registers lock.
This bit is set by software and cleared only by a system reset. When is set, it disables write
access to secure MPU_CTRL, MPU_RNR and MPU_RBAR registers.
0: Secure MPU registers writes is enabled
1: Secure MPU registers writes is disabled.
Bit 0 LOCKSVTAIRCR: VTOR_S register and AIRCR register bits lock.
This bit is set by software and cleared only by a system reset. When is set, it disables write
access to VTOR_S register, PRIS and BFHFNMINS bits in the AIRCR register.
0: VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write is enabled
1: VTOR_S register PRIS and BFHFNMINS bits in the AIRCR register write is disabled.

12.3.6 SYSCFG configuration register 2 (SYSCFG_CFGR2)

When the system is secure (TZEN =1), this register can be protected against non-secure
access by setting the CLASSBSEC bit in the SYSCFG_SECCFGR register. When
CLASSBSEC bit is set, only secure access is allowed. A non-secure read/write access is
RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. SPF Res. Res. Res. Res. ECCL PVDL SPL CLL
rc_w1 rs rs rs rs

RM0438 Rev 7 465/2194

471
System configuration controller (SYSCFG) RM0438

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 SPF: SRAM2 parity error flag.
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by
writing ‘1’.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 ECCL: ECC lock.
This bit is set by software and cleared only by a system reset. It can be used to enable and lock
the Flash ECC error connection to TIM1/8/15/16/17 Break input.
0: ECC error disconnected from TIM1/8/15/16/17 Break input
1: ECC error connected to TIM1/8/15/16/17 Break input.
Bit 2 PVDL: PVD lock enable bit.
This bit is set by software and cleared only by a system reset. It can be used to enable and lock
the PVD connection to TIM1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the
PWR_CR2 register.
0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and PLS[2:0] bits
can be programmed by the application
1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0] bits are read
only.
Bit 1 SPL: SRAM2 parity lock bit.
This bit is set by software and cleared only by a system reset. It can be used to enable and lock
the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break inputs.
0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs
1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs.
Bit 0 CLL: Cortex®-M33 LOCKUP (hardfault) output enable bit.
This bit is set by software and cleared only by a system reset. It can be used to enable and lock
the connection of Cortex®-M33 LOCKUP (hardfault) output to TIM1/8/15/16/17 Break input.
0: Cortex®-M33 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs
1: Cortex®-M33 LOCKUP output connected to TIM1/8/15/16/17 Break inputs.

12.3.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)

When the system is secure (TZEN =1), this register can be protected against non-secure
access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When
SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is
RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), here is no access restriction.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x18
Reset value: 0x0000 0000

466/2194 RM0438 Rev 7

RM0438 System configuration controller (SYSCFG)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRAM2 SRAM2
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
BSY ER
r rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SRAM2BSY: SRAM2 busy by erase operation.
0: No SRAM2 erase operation is ongoing
1: SRAM2 erase operation is ongoing.
Bit 0 SRAM2ER: SRAM2 erase.
Setting this bit starts a hardware SRAM2 erase operation. This bit is automatically cleared at
the end of the SRAM2 erase operation
Note: This bit is write-protected: setting this bit is possible only after the correct key sequence
is written in the SYSCFG_SKR register.

12.3.8 SYSCFG SRAM2 key register (SYSCFG_SKR)

When the system is secure (TZEN =1), this register can be protected against non-secure
access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When
SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is
RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x1C
Reset value: 0x0000 0000
w

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. KEY[7:0]
w

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 KEY[7:0]: SRAM2 write protection key for software erase.
The following steps are required to unlock the write protection of the SRAM2ER bit in the
SYSCFG_CFGR2 register.
0: Write “0xCA” into Key[7:0]
1: Write “0x53” into Key[7:0]
Note: Writing a wrong key reactivates the write protection.

RM0438 Rev 7 467/2194

471
System configuration controller (SYSCFG) RM0438

12.3.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)

When the system is secure (TZEN =1), this register can be protected against non-secure
access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When
SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is
RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P31WP P30WP P29WP P28WP P27WP P26WP P25WP P24WP P23WP P22WP P21WP P20WP P19WP P18WP P17WP P16WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P15WP P14WP P13WP P12WP P11WP P10WP P9WP P8WP P7WP P6WP P5WP P4WP P3WP P2WP P1WP P0WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 PxWP (x = 0 to 31): SRAM2 1 Kbyte page x write protection.

These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 1 Kbyte page x is disabled
1: Write protection of SRAM2 1 Kbyte page x is enabled.

12.3.10 SYSCFG SRAM2 write protection register 2 (SYSCFG_SWPR2)

When the system is secure (TZEN =1), this register can be protected against non-secure
access by setting the SRAM2SEC bit in the SYSCFG_SECCFGR register. When
SRAM2SEC bit is set, only secure access is allowed. A non-secure read/write access is
RAZ/WI and generates an illegal access event.
When the system is not secure (TZEN=0), there is no access restriction.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P63WP P62WP P61WP P60WP P59WP P58WP P57WP P56WP P55WP P54WP P53WP P52WP P51WP P50WP P49WP P48WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
P47WP P46WP P45WP P44WP P43WP P42WP P41WP P40WP P39WP P38WP P37WP P36WP P35WP P34WP P33WP P32WP
rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs

Bits 31:0 PxWP (x = 32 to 63): SRAM2 1 Kbyte page x write protection.

These bits are set by software and cleared only by a system reset.
0: Write protection of SRAM2 1 Kbyte page x is disabled
1: Write protection of SRAM2 1 Kbyte page x is enabled.

468/2194 RM0438 Rev 7

RM0438 System configuration controller (SYSCFG)

12.3.11 SYSCFG RSS command register (SYSCFG_RSSCMDR)

When the system is secure (TZEN =1), this register can be read and written only when the
APB access is secure. Otherwise it is RAZ/WI.
When the system is not secure (TZEN=0), this register is RAZ/WI.
This register can be read and written by privileged and unprivileged access.
Address offset: 0x2C
Power-on reset value: 0x0000 0000
System reset: not affected

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSSCMD
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RSSCMD: RSS commands.
Defines a command to be executed by the RSS.
0x01C0: request boot from RSS with jump to bootloader when BOOT_LOCK bitfield from
FLASH_SECBOOTADD0R option byte register and FLASH_OPTR_nBOOT0
bitfield from FLASH_OPTR option byte register are cleared.

RM0438 Rev 7 469/2194

471
 0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x1C
0x0C
Offset

470/2194
12.3.12

R
R
R2
R1

MR
CFGR

SYSCFG
SYSCFG_
CNSLCKR
reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

_CSLOCKR
Register name

SYSCFG_SKR
SYSCFG_SEC

SYSCFG_SCS
SYSCFG_CFG
SYSCFG_CFG

SYSCFG_SWP
SYSCFG_FPUI
P31WP Res. Res. Res. Res. Res. Res. Res. Res. 31
P30WP Res. Res. Res. Res. Res. Res. Res. Res. 30
P29WP Res. Res. Res. Res. Res. Res. Res. Res. 29
P28WP Res. Res. Res. Res. Res. Res. Res. Res. 28
P27WP Res. Res. Res. Res. Res. Res. Res. Res. 27
P26WP Res. Res. Res. Res. Res. Res. Res. Res. 26
P25WP Res. Res. Res. Res. Res. Res. Res. Res. 25
SYSCFG register map

P24WP Res. Res. Res. Res. Res. Res. Res. Res. 24

P23WP Res. Res. Res. Res. Res. Res. I2C4_FMP Res. 23
System configuration controller (SYSCFG)

P22WP Res. Res. Res. Res. Res. Res. I2C3_FMP Res. 22

P21WP Res. Res. Res. Res. Res. Res. I2C2_FMP Res. 21
P20WP Res. Res. Res. Res. Res. Res. I2C1_FMP Res. 20
P19WP Res. Res. Res. Res. Res. Res. I2C_PB9_FMP Res. 19
P18WP Res. Res. Res. Res. Res. Res. I2C_PB8_FMP Res. 18

RM0438 Rev 7
P17WP Res. Res. Res. Res. Res. Res. I2C_PB7_FMP Res. 17
0 0 0 0 0 0 0 0

P16WP Res. Res. Res. Res. Res. Res. I2C_PB6_FMP Res. 16

P15WP Res. Res. Res. Res. Res. Res. Res. Res. 15
P14WP Res. Res. Res. Res. Res. Res. Res. Res. 14
P13WP Res. Res. Res. Res. Res. Res. Res. Res. 13
P12WP Res. Res. Res. Res. Res. Res. Res. Res. 12
P11WP Res. Res. Res. Res. Res. Res. Res. Res. 11
Table 90. SYSCFG register map and reset values

P10WP Res. Res. Res. Res. Res. Res. Res. Res. 10

P9WP Res. Res. Res. Res. Res. Res. ANASWVDD Res. 9
0 0

0
P8WP Res. Res. SSPF Res. Res. Res. BOOSTEN Res. 8
The following table gives the SYSCFG register map and the reset values.

P7WP Res. Res. Res. Res. Res. Res. Res. 7

P6WP Res. Res. Res. Res. Res. Res. Res. 6
P5WP Res. Res. Res. Res. Res. Res. 5
P4WP Res. Res. Res. Res. Res. Res. 4
P3WP Res. ECCL Res. Res. Res. FPUSEC 3

KEY [7:0]
P2WP Res. PVDL LOCKSAU Res. Res. SRAM2SEC 2
P1WP SRAM2BSY SPL LOCKSMPU LOCKNSMPU Res. CLASSBSEC 1
FPU_IE[5:0]

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0
0 0 0 0
0 0 0
0 0
1 1 1 1 1 1
0 0 0 0

P0WP SRAM2ER CLL. LOCKSVTAIRCR LOCKNSVTOR Res. SYSCFGSEC 0

RM0438
RM0438 System configuration controller (SYSCFG)

Table 90. SYSCFG register map and reset values (continued)

Register name
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
reset value

P63WP
P62WP
P61WP
P60WP
P59WP
P58WP
P57WP
P56WP
P55WP
P54WP
P53WP
P52WP
P51WP
P50WP
P49WP
P48WP
P47WP
P46WP
P45WP
P44WP
P43WP
P42WP
P41WP
P40WP
P39WP
P38WP
P37WP
P36WP
P35WP
P34WP
P33WP
P32WP
SYSCFG_SWP
0x24 R2
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SYSCFG_RSS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RSSCMD[15:0]
CMDR
Power-on reset
0x2C 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value
System reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
value

Refer to Section 2.3 on page 87 for the register boundary addresses.

RM0438 Rev 7 471/2194

471
Peripherals interconnect matrix RM0438

13 Peripherals interconnect matrix

13.1 Introduction
Several peripherals have direct connections between them.
This allows autonomous communication and or synchronization between peripherals,
saving CPU resources thus power supply consumption.
In addition, these hardware connections remove software latency and allow design of
predictable system.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run and sleep, Stop 0, Stop 1 and Stop 2 modes.

13.2 Connection summary

Table 91. STM32L552xx and STM32L562xx peripherals interconnect matrix(1) (2)
Destination

OPAMP1
OPAMP2
DFSDM1
Source

COMP1
COMP2
LPTIM1
LPTIM2
LPTIM3
TIM15
TIM16
TIM17

ADC1
ADC2

DAC1
DAC2

IRTIM
TIM1
TIM8
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7

TIM1 - 1 1 1 1 - - - 1 - - - - - 2 2 5 - - - - 9 - -
TIM8 - - 1 - 1 1 - - - - - - - - 2 2 5 - - 4 4 - 9 -
TIM2 1 1 - 1 1 1 - - - - - - - - 2 2 - - - 4 4 9 - -
TIM3 1 - 1 - 1 1 - - 1 - - - - - 2 2 5 - - - - 9 9 -
TIM4 1 1 1 1 - 1 - - - - - - - - 2 2 5 - - 4 4 - - -
TIM5 - 1 - - - - - - - - - - - - - - - - - 4 4 - - -
TIM6 - - - - - - - - - - - - - - 2 2 5 - - 4 4 - - -
TIM7 - - - - - - - - - - - - - - - - 5 - - 4 4 - - -
TIM15 1 - - 1 - - - - - - - - - - 2 2 - - - - - - 9 -
TIM16 - - - - - - - - 1 - - - - - - - 5 - - - - - - 15
TIM17 - - - - - - - - 1 - - - - - - - - - - - - - - 15
LPTIM1 - - - - - - - - - - - - - - - - 5 - - - - - - -
LPTIM2 - - - - - - - - - - - - - - - - - - - - - - - -
LPTIM3 - - - - - - - - - - - - - - - - - - - - - - - -
ADC1 3 - - - - - - - - - - - - - - - 16 - - - - - - -
ADC2 3 - - - - - - - - - - - - - - - 16 - - - - - - -
DFSDM1 6 6 - - - - - - 6 6 6 - - - - - - - - - - - - -
T. Sensor - - - - - - - - - - - - - - 12 12 - - - - - - - -
VBAT - - - - - - - - - - - - - - 12 12 - - - - - - - -
VREFINT - - - - - - - - - - - - - - 12 12 - - - - - - - -

472/2194 RM0438 Rev 7

RM0438 Peripherals interconnect matrix

Table 91. STM32L552xx and STM32L562xx peripherals interconnect matrix(1) (2) (continued)
Destination

OPAMP1
OPAMP2
DFSDM1
Source

COMP1
COMP2
LPTIM1
LPTIM2
LPTIM3
TIM15
TIM16
TIM17

IRTIM
ADC1
ADC2

DAC1
DAC2
TIM1
TIM8
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
OPAMP1 - - - - - - - - - - - - - - 12 12 - - - - - - - -
OPAMP2 - - - - - - - - - - - - - - 12 12 - - - - - - - -
DAC1 - - - - - - - - - - - - - - - - - 12 12 - - - - -
DAC2 - - - - - - - - - - - - - - - - - - - - - - - -
HSE - - - - - - - - - - 7 - - - - - - - - - - - - -
LSE - - 7 - - - - - 7 7 - - - - - - - - - - - - - -
MSI - - - - - - - - - - 7 - - - - - - - - - - - - -
LSI - - - - - - - - - 7 - - - - - - - - - - - - - -
MCO - - - - - - - - - - 7 - - - - - - - - - - - - -
EXTI - - - - - - - - - - - - - - 2 2 5 - - 4 4 - - -
RTC - - - - - - - - - 7 - 8 8 8 - - - - - - - - - -
COMP1 13 13 13 13 - - - - 13 13 13 8 8 8 - - - - - - - - - -
COMP2 13 13 13 13 - - - - 13 13 13 8 8 8 - - - - - - - - - -
SYST ERR 14 14 - - - - - - 14 14 14 - - - - - - - - - - - - -
USB - - 11 - - - - - - - - - - - - - - - - - - - - -
1. Numbers in table are links to corresponding detailed sub-section in Section 13.3: Interconnection details.
2. The “-” symbol in grayed cells means no interconnect.

13.3 Interconnection details

13.3.1 From timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15/TIM16/TIM17) to

timer (TIM1/TIM2/TIM3/TIM4/TIM5/TIM8/TIM15)
Purpose
Some of the TIMx timers are linked together internally for timer synchronization or chaining.
When one timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another timer configured in Slave Mode.
A description of the feature is provided in: Section 34.3.19: Timer synchronization.
The modes of synchronization are detailed in:
• Section 33.3.26: Timer synchronization for advanced-control timers (TIM1/TIM8)
• Section 34.3.18: Timers and external trigger synchronization for general-purpose
timers (TIM2/TIM3/TIM4/TIM5)
• Section 35.4.19: External trigger synchronization (TIM15 only) for general-purpose
timer (TIM15)

RM0438 Rev 7 473/2194

480
Peripherals interconnect matrix RM0438

Triggering signals
The output (from Master) is on signal TIMx_TRGO (and TIMx_TRGO2 for TIM1/TIM8)
following a configurable timer event.
The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3
The input and output signals for TIM1/TIM8 are shown in Figure 228: Advanced-control
timer block diagram.
The possible master/slave connections are given in:
• Table 270: TIMx internal trigger connection
• Table 275: TIMx internal trigger connection
• Table 279: TIMx Internal trigger connection

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.2 From timer (TIM1/TIM2/TIM3/TIM4/TIM6/TIM8/TIM15) and EXTI to ADC

(ADC1/ADC2)
Purpose
General-purpose timers (TIM2/TIM3/TIM4), basic timer (TIM6), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM15) and EXTI can be used to generate an ADC
triggering event.
TIMx synchronization is described in: Section 33.3.27: ADC synchronization (TIM1/TIM8).
ADC synchronization is described in: Section 21.4.18: Conversion on external trigger and
trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN).

Triggering signals
The output (from timer) is on signal TIMx_TRGO, TIMx_TRGO2 or TIMx_CCx event.
The input (to ADC) is on signal EXT[15:0], JEXT[15:0].
The connection between timers and ADC is provided in:

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.3 From ADC1/ADC2 to timer (TIM1/TIM8)

Purpose
ADC1/ADC2 can provide trigger event through watchdog signals to advanced-control timers
(TIM1/TIM8).
A description of the ADC analog watchdog setting is provided in: .
Trigger settings on the timer are provided in: Section 33.3.4: External trigger input.

474/2194 RM0438 Rev 7

RM0438 Peripherals interconnect matrix

Triggering signals
The output (from ADC) is on signals ADCn_AWDx_OUT n = 1 (for ADC1,2) x = 1, 2, 3 (3
watchdog per ADC) and the input (to timer) on signal TIMx_ETR (external trigger).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.4 From timer (TIM2/TIM4/TIM5/TIM6/TIM7/TIM8) and EXTI to DAC

(DAC1/DAC2)
Purpose
General-purpose timers (TIM2/TIM4/TIM5), basic timers (TIM6, TIM7), advanced-control
timers (TIM8) and EXTI can be used as triggering event to start a DAC conversion.

Triggering signals
The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC
inputs.
Selection of input triggers on DAC is provided in Section 22.4.6: DAC trigger selection
(single and dual mode).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.5 From timer (TIM1/TIM3/TIM4/TIM6/TIM7/TIM8/TIM16/LPTIM1)

and EXTI to DFSDM1
Purpose
General-purpose timers (TIM3/TIM4), basic timers (TIM6/TIM7), advanced-control timers
(TIM1/TIM8), general-purpose timer (TIM16), Low power timer (LPTIM1), EXTI11 and
EXTI15 can be used to generate a triggering event on DFSDM1 module (on each possible
data block DFSDM1_FLT0/DFSDM1_FLT1/DFSDM1_FLT2/DFSDM1_FLT3) and start an
ADC conversion.
DFSDM triggered conversion feature is described in: Section 26.4.15: Launching
conversions.

Triggering signals
The output (from timer) is on signal TIMx_TRGO/TIMx_TRGO2 or TIM16_OC1.
The input (on DFSDM1) is on signal DFSDM1_INTRG[0:8].
The connection between timers, EXTI and DFSDM1 is provided in Table 200: DFSDM
triggers connection.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

RM0438 Rev 7 475/2194

480
Peripherals interconnect matrix RM0438

13.3.6 From DFSDM1 to timer (TIM1/TIM8/TIM15/TIM16/TIM17)

Purpose
DFSDM1 can generate a timer break on advanced-control timers (TIM1/TIM8) and general-
purpose timers (TIM15/TIM16/TIM17) when a watchdog is activated (minimum or maximum
threshold value crossed by analog signal) or when a short-circuit detection is made.
DFSDM1 watchdog is described in Section 26.4.10: Analog watchdog.
DFSDM1 short-circuit detection is described in Section 26.4.11: Short-circuit detector.
Timer break is described in:
• Section 33.3.16: Using the break function (TIM1/TIM8)
• Section 35.4.13: Using the break function (TIM15/TIM16/TIM17)

Triggering signals
The output (from DFSDM1) is on signals dfsdm1_break[0:3] directly connected to timer and
‘Ored’ with other break input signals of the timer.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.7 From HSE, LSE, LSI, MSI, MCO, RTC to timer

(TIM2/TIM15/TIM16/TIM17)
Purpose
External clocks (HSE, LSE), internal clocks (LSI, MSI), microcontroller output clock (MCO),
GPIO and RTC wakeup interrupt can be used as input to general-purpose timer
(TIM15/16/17) channel 1.
This allows to calibrate the HSI16/MSI system clocks (with TIM15/TIM16 and LSE) or LSI
(with TIM16 and HSE). This is also used to precisely measure LSI (with TIM16 and HSI16)
or MSI (with TIM17 and HSI16) oscillator frequency.
When Low Speed External (LSE) oscillator is used, no additional hardware connections are
required.
This feature is described in Section 9.3.18: Internal/external clock measurement with
TIM15/TIM16/TIM17.
External clock LSE can be used as input to general-purpose timers (TIM2) on TIM2_ETR
pin, see Section 34.4.22: TIM2 option register 1 (TIM2_OR1).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

476/2194 RM0438 Rev 7

RM0438 Peripherals interconnect matrix

13.3.8 From RTC, COMP1, COMP2 to low-power timer

(LPTIM1/LPTIM2/LPTIM3)
Purpose
RTC alarm A/B, RTC_TAMP1/2/3 input detection, COMP1/2_OUT can be used as trigger to
start LPTIM counters (LPTIM1/2/3).

Triggering signals
This trigger feature is described in Section 37.4.7: Trigger multiplexer (and following
sections).
The input selection is described in Table 288: LPTIM1 external trigger connection.

Active power mode

Run, Sleep, Low-power run, Low-power sleep, Stop 0, Stop 1, Stop 2 (LPTIM1 only).

13.3.9 From timer (TIM1/TIM2/TIM3/TIM8/TIM15) to comparators

(COMP1/COMP2)
Purpose
Advanced-control timers (TIM1/TIM8), general-purpose timers (TIM2/TIM3) and general-
purpose timer (TIM15) can be used as blanking window input to COMP1/COMP2
The blanking function is described in Section 24.3.7: Comparator output blanking function.
The blanking sources are given in:
• Section 24.6.1: Comparator 1 control and status register (COMP1_CSR) bits 20:18
BLANKING[2:0]
• Section 24.6.2: Comparator 2 control and status register (COMP2_CSR) bits 20:18
BLANKING[2:0]

Triggering signals
Timer output signal TIMx_Ocx are the inputs to blanking source of COMP1/COMP2.

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.10 From ADC (ADC1) to ADC (ADC2)

Purpose
ADC1 can be used as a “master” to trigger ADC2 “slave” start of conversion.
In dual ADC mode, the converted data of the master and slave ADCs can be read in
parallel.

Triggering signals
Internal to the ADCs.

RM0438 Rev 7 477/2194

480
Peripherals interconnect matrix RM0438

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.11 From USB to timer (TIM2)

Purpose
USB (FS SOF) can generate a trigger to general-purpose timer (TIM2).
Connection of USB to TIM2 is described in Table 275: TIMx internal trigger connection.

Triggering signals
Internal signal generated by USB FS Start Of Frame.

Active power mode

Run, Sleep.

13.3.12 From internal analog source to ADC (ADC1/ADC2) and OPAMP

(OPAMP1/OPAM2)
Purpose
Internal temperature sensor (VTS) and VBAT monitoring channel are connected to ADC1
input channels.
Internal reference voltage (VREFINT) is connected to ADC1 input channels.
OPAMP1 and OPAMP2 outputs can be connected to ADC1 or ADC2 input channels through
the GPIO.
DAC1_OUT1 can be connected to OPAMP1_VINP.
DAC1_OUT2 can be connected to OPAMP2_VINP.
This is according:
• Section 21.2: ADC main features
• Section 21.4.11: Channel selection (SQRx, JSQRx)
• Section Figure 93.: ADC1 connectivity
• Table 193: Operational amplifier possible connections

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.13 From comparators (COMP1/COMP2) to timers

(TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17)
Purpose
Comparators (COMP1/COMP2) output values can be connected to timers
(TIM1/TIM2/TIM3/TIM8/TIM15/TIM16/TIM17) input captures or TIMx_ETR signals.
The connection to ETR is described in Section 33.3.4: External trigger input.

478/2194 RM0438 Rev 7

RM0438 Peripherals interconnect matrix

Comparators (COMP1/COMP2) output values can also generate break input signals for
timers (TIM1/TIM8) on input pins TIMx_BKIN or TIMx_BKIN2 through GPIO alternate
function selection using open drain connection of IO, see Section 33.3.17: Bidirectional
break inputs.
The possible connections are given in:
• Section 33.4.23: TIM1 option register 1 (TIM1_OR1)
• Section 33.4.24: TIM8 option register 1 (TIM8_OR1)
• Section 34.4.22: TIM2 option register 1 (TIM2_OR1)
• Section 34.4.23: TIM3 option register 1 (TIM3_OR1)
• Section 34.4.24: TIM2 option register 2 (TIM2_OR2)
• Section 34.4.25: TIM3 option register 2 (TIM3_OR2)
• Section 35.3: TIM16/TIM17 main features

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.14 From system errors to timers (TIM1/TIM8/TIM15/TIM16/TIM17)

Purpose
CSS, CPU hardfault, RAM parity error, FLASH ECC double error detection, PVD can
generate system errors in the form of timer break toward timers
(TIM1/TIM8/TIM15/TIM16/TIM17).
The purpose of the break function is to protect power switches driven by PWM signals
generated by the timers.
List of possible source of break are described in:
• Section 33.3.16: Using the break function (TIM1/TIM8)
• Section 35.4.13: Using the break function (TIM15/TIM16/TIM17)
• Figure 339: TIM15 block diagram
• Figure 340: TIM16/TIM17 block diagram

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

13.3.15 From timers (TIM16/TIM17) to IRTIM

Purpose
General-purpose timer (TIM16/TIM17) output channel TIMx_OC1 are used to generate the
waveform of infrared signal output.
The functionality is described in Section 38: Infrared interface (IRTIM).

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

RM0438 Rev 7 479/2194

480
Peripherals interconnect matrix RM0438

13.3.16 From ADC (ADC1/ADC2) to DFSDM

Purpose
Up to 3 internal ADC results can be directly connected through a parallel bus to DFSDM
input in order to use DFSDM filtering capabilities.
The feature is described as part of DFSDM peripheral description in Section 26.4.6: Parallel
data inputs - Input from internal ADC
The possible connections are given in:
• Section 26.7.1: DFSDM channel y configuration register (DFSDM_CHyCFGR1)
– Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
• Section 26.7.5: DFSDM channel y data input register (DFSDM_CHyDATINR)
– Bits 31:16 INDAT0[15:0]: Input data for channel y or channel y+1
– Bits 15:0 INDAT0[15:0]: Input data for channel y

Active power mode

Run, Sleep, Low-power run, Low-power sleep.

480/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

14 Direct memory access controller (DMA)

14.1 Introduction
The direct memory access (DMA) controller is a bus master and system peripheral.
The DMA is used to perform programmable data transfers between memory-mapped
peripherals and/or memories, upon the control of an off-loaded CPU.
The DMA controller features a single AHB master architecture.
There are two instances of DMA, DMA1 and DMA2.
Each channel is dedicated to managing memory access requests from one or more
peripherals. Each DMA includes an arbiter for handling the priority between DMA requests.

14.2 DMA main features

• Single AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as Flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (4 levels per channel:
very high, high, medium, low) and by hardware in case of equality (such as
request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
– Support of transfers from/to peripherals to/from memory with circular buffer
management
– Programmable number of data to be transferred: 0 to 218 - 1
• Generation of an interrupt request per channel. Each interrupt request is caused from
any of the three DMA events: transfer complete, half transfer, or transfer error.
• TrustZone support:
– Support for AHB secure and non-secure DMA transfers, independently of a first
channel level, and independently at a source and destination sub-level
– TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access
• Privileged/unprivileged support:
– Support for AHB privileged and unprivileged DMA transfers, independently of a
channel level
– Privileged-aware AHB slave port

RM0438 Rev 7 481/2194

508
Direct memory access controller (DMA) RM0438

14.3 DMA implementation

14.3.1 DMA1 and DMA2

DMA1 and DMA2 are implemented with the hardware configuration parameters shown
in Table 92.

Table 92. DMA1 and DMA2 implementation

Feature DMA1 DMA2

Number of channels (double-buffer) 8 8

TrustZone 1 (supported) 1 (supported)

14.3.2 DMA request mapping

The DMA controller is connected to DMA requests from the AHB/APB peripherals through
the DMAMUX peripheral.
For the mapping of the different requests, refer to the Section 15.3: DMAMUX
implementation.

482/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

14.4 DMA functional description

14.4.1 DMA block diagram

The DMA block diagram is shown in Figure 43.

Figure 43. DMA block diagram

DMA1

Ch 1

32-bit AHB bus

Ch 2
... AHB master interface

Ch 8

dma1_req [1..8] Arbiter

dma1_ack [1..8]

32-bit AHB bus

dma1_secm [1..8]
dma1_priv[1..8]
Interrupt AHB slave interface
interface

dma1_it[1..8] dma1_sec_ilac

DMA2
DMAMUX

Ch 1
32-bit AHB bus

Ch 2
AHB master interface
...

Ch 8

dma2_req [1..8] Arbiter

dma2_ack [1..8]
32-bit AHB bus

dma2_secm [1..8]
dma2_priv[1..8]
Interrupt AHB slave interface
interface

dma2_it[1..8] dma2_sec_ilac
MSv46688V1

RM0438 Rev 7 483/2194

508
Direct memory access controller (DMA) RM0438

The DMA controller performs direct memory transfer by sharing the AHB system bus with
other system masters. The bus matrix implements round-robin scheduling. DMA requests
may stop the CPU access to the system bus for a number of bus cycles, when CPU and
DMA target the same destination (memory or peripheral).
According to its configuration through the AHB slave interface, the DMA controller arbitrates
between the DMA channels and their associated received requests. The DMA controller
also schedules the DMA data transfers over the single AHB port master.
The DMA controller generates a secure bus and a privileged bus, to keep the DMAMUX
peripheral informed of the secure or non-secure state, and the privileged or unprivileged
state of each channel x.
The DMA controller generates an interrupt per channel to the interrupt controller.
The DMA controller also generates an illegal access event, as a pulse, to the TrustZone
interrupt controller, when a non-secure software attempts to access a secure DMA register
or register field.

14.4.2 DMA pins and internal signals

Table 93. DMA internal input/output signals

Signal name Signal type Description

dma_req[x] Input DMA channel x request

dma_ack[x] Output DMA channel x acknowledge
dma_it[x] Output DMA channel x interrupt
dma_secm[x] Output DMA channel x secure state
dma_priv[x] Output DMA channel x privileged state
dma_sec_ilac Output DMA global secure illegal access event

14.4.3 DMA transfers

The secure software configures the DMA controller at channel level, in order to perform a
block transfer, composed of a sequence of AHB secure or non-secure, privileged or
unprivileged bus transfers.
A DMA block transfer may be requested from a peripheral, or triggered by the software in
case of memory-to-memory transfer.
After an event, the following steps of a single DMA transfer occur:
1. The peripheral sends a single DMA request signal to the DMA controller.
2. The DMA controller serves the request, depending on the priority of the channel
associated to this peripheral request.
3. As soon as the DMA controller grants the peripheral, an acknowledge is sent to the
peripheral by the DMA controller.
4. The peripheral releases its request as soon as it gets the acknowledge from the DMA
controller.
5. Once the request is de-asserted by the peripheral, the DMA controller releases the
acknowledge.
The peripheral may order a further single request and initiate another single DMA transfer.

484/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

The request/acknowledge protocol is used when a peripheral is either the source or the
destination of the transfer. For example, in case of memory-to-peripheral transfer, the
peripheral initiates the transfer by driving its single request signal to the DMA controller. The
DMA controller reads then a single data in the memory and writes this data to the peripheral.
For a given channel x, a DMA block transfer consists of a repeated sequence of:
• a single DMA transfer, encapsulating two AHB transfers of a single data, over the DMA
AHB bus master:
– a single data read (byte, half-word or word) from the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first single transfer is the base address of the
peripheral or memory, and is programmed in the DMA_CPARx or
DMA_CM0/1ARx register.
– a single data write (byte, half-word or word) to the peripheral data register or a
location in the memory, addressed through an internal current peripheral/memory
address register.
The start address used for the first transfer is the base address of the peripheral or
memory, and is programmed in the DMA_CPARx or DMA_CM0/1ARx register.
• post-decrementing of the programmed DMA_CNDTRx register
This register contains the remaining number of data items to transfer (number of AHB
‘read followed by write’ transfers).
This sequence is repeated until DMA_CNDTRx is null.
Note: The AHB master bus source/destination address must be aligned with the programmed size
of the transferred single data to the source/destination.

14.4.4 DMA arbitration

The DMA arbiter manages the priority between the different channels.
When an active channel x is granted by the arbiter (hardware requested or software
triggered), a single DMA transfer is issued (such as a AHB ‘read followed by write’ transfer
of a single data). Then, the arbiter considers again the set of active channels and selects the
one with the highest priority.
The priorities are managed in two stages:
• software: priority of each channel is configured in the DMA_CCRx register, to one of
the four different levels:
– very high
– high
– medium
– low
• hardware: if two requests have the same software priority level, the channel with the
lowest index gets priority. For example, channel 2 gets priority over channel 4.
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.

RM0438 Rev 7 485/2194

508
Direct memory access controller (DMA) RM0438

14.4.5 DMA channels

Each channel may handle a DMA transfer between a peripheral register located at a fixed
address, and a memory address. The amount of data items to transfer is programmable.
The register that contains the amount of data items to transfer is decremented after each
transfer.
Each channel is either secure or non-secure.
A DMA channel is programmed at block transfer level.

Programmable data sizes

The transfer sizes of a single data (byte, half-word, or word) to the peripheral and memory
are programmable through, respectively, the PSIZE[1:0] and MSIZE[1:0] fields of the
DMA_CCRx register.

Pointer incrementation
The peripheral and memory pointers may be automatically incremented after each transfer,
depending on the PINC and MINC bits of the DMA_CCRx register.
If the incremented mode is enabled (PINC or MINC set to 1), the address of the next
transfer is the address of the previous one incremented by 1, 2 or 4, depending on the data
size defined in PSIZE[1:0] or MSIZE[1:0]. The first transfer address is the one programmed
in the DMA_CPARx or DMA_CM0/1ARx register. During transfers, these registers keep the
initially programmed value. The current transfer addresses (in the current internal
peripheral/memory address register) are not accessible by software.
If the channel x is configured in non-circular mode, no DMA request is served after the last
data transfer (once the number of single data to transfer reaches zero). The DMA channel
must be disabled in order to reload a new number of data items into the DMA_CNDTRx
register.
Note: If the channel x is disabled, the DMA registers are not reset. The DMA channel registers
(DMA_CCRx, DMA_CPARx and DMA_CM0ARx) retain the initial values programmed
during the channel configuration phase.
In circular mode, after the last data transfer, the DMA_CNDTRx register is automatically
reloaded with the initially programmed value. The current internal address registers are
reloaded with the base address values from the DMA_CPARx and DMA_CM0/1ARx
registers.

Security
The DMA controller is compliant with the TrustZone-M hardware architecture, partitioning all
its resources so that they exist in one of the two worlds: the secure world and the non-
secure world, at any given time.
A secure software is able to access any resource/register, whatever secure or non-secure.
A non-secure software is restricted to access any non-secure resource/register.
Any channel is in a secure or non-secure state, as securely configured by the
DMA_CCRx.SECM secure register bit.

486/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

When a channel x is configured in secure mode, the following access controls rules are
applied:
• A non-secure read access to a register field of this channel is forced to return 0, except
for both the secure state and the privileged state of this channel x (SECM and PRIV
bits of the DMA_CCRx register) which are readable by a non-secure software.
• A non-secure write access to a register field of this channel has no impact.
When a channel is configured in secure mode, a secure software can separately configure
as secure or non-secure the AHB DMA master transfer from the source (by the
DMA_CCRx.SSEC register bit), and as secure or non-secure the AHB DMA master transfer
to the destination (by the DMA_CCRx.DSEC register bit).
The DMA controller generates a secure bus, dma_secm[7:0], reflecting the
DMA_CCRx.SECM register, in order to keep the other hardware peripherals like the
DMAMUX, informed of the secure/non-secure state of each DMA channel x.
The DMA controller also generates a security illegal access pulse event, dma_sec_ilac, on
an illegal non-secure software access to a secure DMA register or register field. This event
is routed to the TrustZone interrupt controller.
The dma_sec_ilac event is generated in the configurations described below:
• If the channel x is in secure state (SECM bit of the DMA_CCRx register set), the
dma_sec_ilac is generated on one of the following accesses:
– a non-secure write access to a dedicated register of this channel x (DMA_CCRx,
DMA_CNDTRx, DMA_CPARx, DMA_CM0ARx and DMA_CM1ARx)
– a non-secure read access to a dedicated register of this channel x, except the
DMA_CxCR register (DMA_CNDTRx, DMA_CPARx, DMA_CM0ARx, and
DMA_CM1ARx).
• If the channel x is in non-secure state (SECM bit of the DMA_CCRx register cleared),
the dma_sec_ilac is generated on a non-secure write access to the DMA_CCRx
register which attempts to write 1 into any of the secure configuration bits SECM,
DSEC, SSEC.
When the software is switching from a secure state to a non-secure state (after the secure
transfer is completed), the secure software must disable the channel by a 32-bit write at the
DMA_CCRx address before switching. This operation is needed for the two below reasons:
• a non-secure software cannot do so
• the EN bit of the DMA_CCRx register must be cleared before the (non-secure)
software can reprogram the DMA_CCRx for a next transfer.
Note: A trusted application may require that the secure software does not only disable the
channel, but also reset the full DMA_CCRx word register to its reset value, as well as reset
any other DMA register corresponding to this channel x.

Privileged / unprivileged mode

Any channel x is a privileged or unprivileged hardware resource, as configured by a
privileged software via the PRIV bit of the DMA_CCRx register.
When a channel x is configured in privileged mode, the following access controls rules are
applied:
• An unprivileged read access to a register field of this channel is forced to return 0,
except for both the privileged state and the secure state of this channel x (PRIV and

RM0438 Rev 7 487/2194

508
Direct memory access controller (DMA) RM0438

SECM bits of the DMA_CCRx register) which are readable by an unprivileged

software.
• An unprivileged write access to a register field of this channel has no impact.
When a channel is configured in a privileged (or unprivileged) mode, the AHB master
transfers from the source and to the destination, are privileged (respectively unprivileged).
DMA generates a privileged bus, dma_priv[7:0], reflecting the PRIV bit of the DMA_CCRx
register, in order to keep the other hardware peripherals, like DMAMUX, informed of the
privileged / unprivileged state of each DMA channel x.

Channel configuration procedure

The following sequence is needed to configure a DMA channel x:
1. Set a channel x to secure or non-secure, by a secure write access to the secure SECM
bit of the DMA_CCRx register. Set a channel x to privileged or unprivileged, by a
privileged write access to the privileged PRIV bit of the DMA_CCRx register.
2. Set the peripheral register address in the DMA_CPARx register.
The data is moved from/to this address to/from the memory after the peripheral event,
or after the channel is enabled in memory-to-memory mode.
3. Set the memory address in the DMA_CM0ARx register.
The data is written to/read from the memory after the peripheral event or after the
channel is enabled in memory-to-memory mode.
4. Configure the total number of data to transfer in the DMA_CNDTRx register.
After each data transfer, this value is decremented.
5. Configure the parameters listed below in the DMA_CCRx register:
– the channel priority
– the data transfer direction
– the security level of the data transfers from source and to destination when the
channel is secure
– the circular mode
– the double-buffer mode
– the peripheral and memory incremented mode
– the peripheral and memory data size
– the interrupt enable at half and/or full transfer and/or transfer error
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
A channel, as soon as enabled, may serve any DMA request from the peripheral connected
to this channel, or may start a memory-to-memory block transfer.
Note: The two last steps of the channel configuration procedure may be merged into a single
access to the DMA_CCRx register, to configure and enable the channel.

Channel state and disabling a channel

A channel x in active state is an enabled channel (read DMA_CCRx.EN = 1). An active
channel x is a channel that must have been enabled by the software (DMA_CCRx.EN set
to 1) and afterwards with no occurred transfer error (DMA_ISR.TEIFx = 0). In case there is a
transfer error, the channel is automatically disabled by hardware (DMA_CCRx.EN = 0).

488/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

The three following use cases may happen:

• Suspend and resume a channel
This corresponds to the two following actions:
– An active channel is disabled by software (writing DMA_CCRx.EN = 0 whereas
DMA_CCRx.EN = 1).
– The software enables the channel again (DMA_CCRx.EN set to 1) without
reconfiguring the other channel registers (such as DMA_CNDTRx, DMA_CPARx
and DMA_CMARx).
This case is not supported by the DMA hardware, that does not guarantee that the
remaining data transfers are performed correctly.
• Stop and abort a channel
If the application does not need any more the channel, this active channel can be
disabled by software. The channel is stopped and aborted but the DMA_CNDTRx
register content may not correctly reflect the remaining data transfers versus the
aborted source and destination buffer/register.
• Abort and restart a channel
This corresponds to the software sequence: disable an active channel, then
reconfigure the channel and enable it again.
This is supported by the hardware if the following conditions are met:
– The application guarantees that, when the software is disabling the channel, a
DMA data transfer is not occurring at the same time over its master port. For
example, the application can first disable the peripheral in DMA mode, in order to
ensure that there is no pending hardware DMA request from this peripheral.
– The software must operate separated write accesses to the same DMA_CCRx
register: First disable the channel. Second reconfigure the channel for a next block
transfer including the DMA_CCRx if a configuration change is needed. There are
read-only DMA_CCRx register fields when DMA_CCRx.EN=1. Finally enable
again the channel.
When a channel transfer error occurs, the EN bit of the DMA_CCRx register is cleared by
hardware. This EN bit can not be set again by software to re-activate the channel x, until the
TEIFx bit of the DMA_ISR register is set.

Circular mode (in memory-to-peripheral/peripheral-to-memory transfers)

The circular mode is available to handle circular buffers and continuous data flows (such as
ADC scan mode). This feature is enabled using the CIRC bit in the DMA_CCRx register.
Note: The circular mode must not be used in memory-to-memory mode. Before enabling a
channel in circular mode (CIRC = 1), the software must clear the MEM2MEM bit of the
DMA_CCRx register. When the circular mode is activated, the amount of data to transfer is
automatically reloaded with the initial value programmed during the channel configuration
phase, and the DMA requests continue to be served.
In order to stop a circular transfer, the software needs to stop the peripheral from generating
DMA requests (such as quit the ADC scan mode), before disabling the DMA channel.
The software must explicitly program the DMA_CNDTRx value before starting/enabling a
transfer, and after having stopped a circular transfer.

RM0438 Rev 7 489/2194

508
Direct memory access controller (DMA) RM0438

Memory-to-memory mode
The DMA channels may operate without being triggered by a request from a peripheral. This
mode is called memory-to-memory mode, and is initiated by software.
If the MEM2MEM bit in the DMA_CCRx register is set, the channel, if enabled, initiates
transfers. The transfer stops once the DMA_CNDTRx register reaches zero.
Note: The memory-to-memory mode must not be used in circular mode. Before enabling a
channel in memory-to-memory mode (MEM2MEM = 1), the software must clear the CIRC
bit of the DMA_CCRx register.

Double-buffer mode (in memory-to-peripheral and peripheral-to memory

transfers)
The DMA channels can operate in double-buffer mode.
The difference compared to a regular operation is that the DMA controller toggles between
two memory address pointers at the end of each DMA transfer, thus accessing two memory
areas in an alternate way. This allows the software to access one of the two memory areas
while the DMA controller accesses the other one. The double-buffer mode transfer operates
in both directions, so the target memory can be either the source or the destination.
The double-buffer mode is configured by setting both the DBM and CIRC bits of the
DMA_CCRx register.
Note: The double-buffer mode must not be used in memory-to-memory mode. Before enabling a
channel in double-buffer mode (DBM = 1), the software has to configure appropriately the
MEM2MEM bit (MEM2MEM = 0).
The steps described below allow the configuration of a DMA channel x in double-buffer
mode:
• Set the DBM and CIRC bits and clear the MEM2MEM bit of the DMA_CCRx register.
The circular mode is then activated for the swap mechanism to occur.
• Configure the second memory address register DMA_CM1ARx.
• Continue with the regular channel configuration procedure, and lastly, activate the
channel by setting the EN bit of the DMA_CCRx register. The first DMA transfer target
memory of the corresponding DMA channel x, is given by the CT bit of the DMA_CCRx
register.
Note: Independently from the value of DBM bit of the DMA_CCRx register, if CT = 1, the memory
address pointer for the DMA transfer is defined by DMA_CM1ARx, and not by
DMA_CM0ARx.

Peripheral-to-peripheral mode
Any DMA channel can operate in peripheral-to-peripheral mode:
• when the hardware request from a peripheral is selected to trigger the DMA channel
This peripheral is the DMA initiator and paces the data transfer from/to this peripheral
to/from a register belonging to another memory-mapped peripheral (this one being not
configured in DMA mode).
• when no peripheral request is selected and connected to the DMA channel
The software configures a register-to-register transfer by setting the MEM2MEM bit of
the DMA_CCRx register.

490/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Programming transfer direction, assigning source/destination

The value of the DIR bit of the DMA_CCRx register sets the direction of the transfer, and
consequently, it identifies the source and the destination, regardless the source/destination
type (peripheral or memory):
• DIR = 1 defines typically a memory-to-peripheral transfer. More generally, if DIR = 1:
– The source attributes are defined by the DMA_MARx register, the MSIZE[1:0]
field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the source peripheral in peripheral-to-peripheral mode.
– The destination attributes are defined by the DMA_PARx register, the PSIZE[1:0]
field and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the destination memory in memory-to-memory mode.
• DIR = 0 defines typically a peripheral-to-memory transfer. More generally, if DIR = 0:
– The source attributes are defined by the DMA_PARx register, the PSIZE[1:0] field
and PINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘peripheral’ register, field and bit are used
to define the source memory in memory-to-memory mode
– The destination attributes are defined by the DMA_MARx register, the
MSIZE[1:0] field and MINC bit of the DMA_CCRx register.
Regardless of their usual naming, these ‘memory’ register, field and bit are used to
define the destination peripheral in peripheral-to-peripheral mode.

14.4.6 DMA data width, alignment and endianness

When PSIZE[1:0] and MSIZE[1:0] are not equal, the DMA controller performs some data
alignments as described in Table 94.

Table 94. Programmable data width and endian behavior (when PINC = MINC = 1)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (DMA_CM0/1ARx if DMA transfers
if if (DMA_CPARx if
transfer DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) DMA_CPARx)
else else DMA_CM0/1ARx)
PSIZE) MSIZE)

@0x0 / B0 1: read B0[7:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0

@0x1 / B1 2: read B1[7:0] @0x1 then write B1[7:0] @0x1 @0x1 / B1
8 8 8
@0x2 / B2 3: read B2[7:0] @0x2 then write B2[7:0] @0x2 @0x2 / B2
@0x3 / B3 4: read B3[7:0] @0x3 then write B3[7:0] @0x3 @0x3 / B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 00B0[15:0] @0x0 @0x0 / 00B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 00B1[15:0] @0x2 @0x2 / 00B1
8 16 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 00B2[15:0] @0x4 @0x4 / 00B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 00B3[15:0] @0x6 @0x6 / 00B3

@0x0 / B0 1: read B0[7:0] @0x0 then write 000000B0[31:0] @0x0 @0x0 / 000000B0
@0x1 / B1 2: read B1[7:0] @0x1 then write 000000B1[31:0] @0x4 @0x4 / 000000B1
8 32 4
@0x2 / B2 3: read B2[7:0] @0x2 then write 000000B2[31:0] @0x8 @0x8 / 000000B2
@0x3 / B3 4: read B3[7:0] @0x3 then write 000000B3[31:0] @0xC @0xC / 000000B3

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B2[7:0] @0x1 @0x1 / B2
16 8 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B4[7:0] @0x2 @0x2 / B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B6[7:0] @0x3 @0x3 / B6

RM0438 Rev 7 491/2194

508
Direct memory access controller (DMA) RM0438

Table 94. Programmable data width and endian behavior (when PINC = MINC = 1) (continued)
Source Destinat
port ion port Destination
Number Source content:
width width content:
of data address / data
(MSIZE (PSIZE address / data
items to (DMA_CM0/1ARx if DMA transfers
if if (DMA_CPARx if
transfer DIR = 1, else
DIR = 1, DIR = 1, DIR = 1, else
(NDT) DMA_CPARx)
else else DMA_CM0/1ARx)
PSIZE) MSIZE)

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write B3B2[15:0] @0x2 @0x2 / B3B2
16 16 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write B5B4[15:0] @0x4 @0x4 / B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write B7B6[15:0] @0x6 @0x6 / B7B6

@0x0 / B1B0 1: read B1B0[15:0] @0x0 then write 0000B1B0[31:0] @0x0 @0x0 / 0000B1B0
@0x2 / B3B2 2: read B3B2[15:0] @0x2 then write 0000B3B2[31:0] @0x4 @0x4 / 0000B3B2
16 32 4
@0x4 / B5B4 3: read B5B4[15:0] @0x4 then write 0000B5B4[31:0] @0x8 @0x8 / 0000B5B4
@0x6 / B7B6 4: read B7B6[15:0] @0x6 then write 0000B7B6[31:0] @0xC @0xC / 0000B7B6

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B0[7:0] @0x0 @0x0 / B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B4[7:0] @0x1 @0x1 / B4
32 8 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B8[7:0] @0x2 @0x2 / B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BC[7:0] @0x3 @0x3 / BC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B1B0[15:0] @0x0 @0x0 / B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B5B4[15:0] @0x2 @0x2 / B5B4
32 16 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write B9B8[15:0] @0x4 @0x4 / B9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BDBC[15:0] @0x6 @0x6 / BDBC

@0x0 / B3B2B1B0 1: read B3B2B1B0[31:0] @0x0 then write B3B2B1B0[31:0] @0x0 @0x0 / B3B2B1B0
@0x4 / B7B6B5B4 2: read B7B6B5B4[31:0] @0x4 then write B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4
32 32 4
@0x8 / BBBAB9B8 3: read BBBAB9B8[31:0] @0x8 then write BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8
@0xC / BFBEBDBC 4: read BFBEBDBC[31:0] @0xC then write BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC

Addressing AHB peripherals not supporting byte/half-word write transfers

When the DMA controller initiates an AHB byte or half-word write transfer, the data are
duplicated on the unused lanes of the AHB master 32-bit data bus (HWDATA[31:0]).
When the AHB slave peripheral does not support byte or half-word write transfers and does
not generate any error, the DMA controller writes the 32 HWDATA bits as shown in the two
examples below:
• To write the half-word 0xABCD, the DMA controller sets the HWDATA bus to
0xABCDABCD with a half-word data size (HSIZE = HalfWord in AHB master bus).
• To write the byte 0xAB, the DMA controller sets the HWDATA bus to 0xABABABAB
with a byte data size (HSIZE = Byte in the AHB master bus).
Assuming the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take into
account the HSIZE data, any AHB byte or half-word transfer is changed into a 32-bit APB
transfer as described below:
• An AHB byte write transfer of 0xB0 to one of the 0x0, 0x1, 0x2 or 0x3 addresses, is
converted to an APB word write transfer of 0xB0B0B0B0 to the 0x0 address.
• An AHB half-word write transfer of 0xB1B0 to the 0x0 or 0x2 addresses, is converted to
an APB word write transfer of 0xB1B0B1B0 to the 0x0 address.

14.4.7 DMA error management

A DMA transfer error is generated when reading from or writing to a reserved address
space. When a DMA transfer error occurs during a DMA read or write access, the faulty
channel x is automatically disabled through a hardware clear of its EN bit in the
corresponding DMA_CCRx register.

492/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

The TEIFx bit of the DMA_ISR register is set. An interrupt is then generated if the TEIE bit of
the DMA_CCRx register is set.
The EN bit of the DMA_CCRx register can not be set again by software (channel x re-
activated) until the TEIFx bit of the DMA_ISR register is cleared (by setting the CTEIFx bit of
the DMA_IFCR register).
When the software is notified with a transfer error over a channel which involves a
peripheral, the software has first to stop this peripheral in DMA mode, in order to disable any
pending or future DMA request. Then software may normally reconfigure both DMA and the
peripheral in DMA mode for a new transfer.
Additionally, a security illegal access pulse signal is generated on an illegal non-secure
software access to a secure DMA register. This signal is routed to the TrustZone interrupt
controller.

14.5 DMA interrupts

An interrupt can be generated on a half transfer, transfer complete or transfer error for each
DMA channel x (whatever the channel is secure or non-secure). Separate interrupt enable
bits are available for flexibility.

Table 95. DMA interrupt requests

Interrupt
Interrupt request Interrupt event Event flag
enable bit

Half transfer on channel x HTIFx HTIEx

Transfer complete on channel x TCIFx TCIEx
Channel x interrupt
Transfer error on channel x TEIFx TEIEx
Half transfer or transfer complete or transfer error on channel x GIFx -

14.6 DMA registers

Refer to Section 1.2 for a list of abbreviations used in register descriptions.
The DMA registers have to be accessed by words (32-bit).

14.6.1 DMA interrupt status register (DMA_ISR)

Address offset: 0x00
Reset value: 0x0000 0000
This register may mix secure and non secure information, depending on the secure mode of
each channel (SECM bit of the DMA_CCRx register). A secure software can read the full
interrupt status. A non-secure software is restricted to read the status of non-secure
channel(s), other secure bit fields returning zero.
This register may mix privileged and unprivileged information, depending on the privileged
mode of each channel (PRIV bit of the DMA_CCRx register). A privileged software can read

RM0438 Rev 7 493/2194

508
Direct memory access controller (DMA) RM0438

the full interrupt status. An unprivileged software is restricted to read the status of
unprivileged channel(s), other privileged bit fields returning zero.
Every status / flag bit is set by hardware, independently of the privileged and the secure
mode of the channel.
Every status bit is cleared by hardware when the software sets the corresponding clear bit
or the corresponding global clear bit CGIFx, in the DMA_IFCR register, provided that, if the
channel x is in privileged mode and/or in secure mode, then the software access to
DMA_IFCR is also privileged and/or secure.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TEIF8 HTIF8 TCIF8 GIF8 TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1
r r r r r r r r r r r r r r r r

Bit 31 TEIF8: transfer error (TE) flag for channel 8

0: no TE event
1: a TE event occurred
Bit 30 HTIF8: half transfer (HT) flag for channel 8
0: no HT event
1: a HT event occurred
Bit 29 TCIF8: transfer complete (TC) flag for channel 8
0: no TC event
1: a TC event occurred
Bit 28 GIF8: global interrupt flag for channel 8
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 27 TEIF7: transfer error (TE) flag for channel 7
0: no TE event
1: a TE event occurred
Bit 26 HTIF7: half transfer (HT) flag for channel 7
0: no HT event
1: a HT event occurred
Bit 25 TCIF7: transfer complete (TC) flag for channel 7
0: no TC event
1: a TC event occurred
Bit 24 GIF7: global interrupt flag for channel 7
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 23 TEIF6: transfer error (TE) flag for channel 6
0: no TE event
1: a TE event occurred
Bit 22 HTIF6: half transfer (HT) flag for channel 6
0: no HT event
1: a HT event occurred

494/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Bit 21 TCIF6: transfer complete (TC) flag for channel 6

0: no TC event
1: a TC event occurred
Bit 20 GIF6: global interrupt flag for channel 6
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 19 TEIF5: transfer error (TE) flag for channel 5
0: no TE event
1: a TE event occurred
Bit 18 HTIF5: half transfer (HT) flag for channel 5
0: no HT event
1: a HT event occurred
Bit 17 TCIF5: transfer complete (TC) flag for channel 5
0: no TC event
1: a TC event occurred
Bit 16 GIF5: global interrupt flag for channel 5
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 15 TEIF4: transfer error (TE) flag for channel 4
0: no TE event
1: a TE event occurred
Bit 14 HTIF4: half transfer (HT) flag for channel 4
0: no HT event
1: a HT event occurred
Bit 13 TCIF4: transfer complete (TC) flag for channel 4
0: no TC event
1: a TC event occurred
Bit 12 GIF4: global interrupt flag for channel 4
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 11 TEIF3: transfer error (TE) flag for channel 3
0: no TE event
1: a TE event occurred
Bit 10 HTIF3: half transfer (HT) flag for channel 3
0: no HT event
1: a HT event occurred
Bit 9 TCIF3: transfer complete (TC) flag for channel 3
0: no TC event
1: a TC event occurred
Bit 8 GIF3: global interrupt flag for channel 3
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 7 TEIF2: transfer error (TE) flag for channel 2
0: no TE event
1: a TE event occurred

RM0438 Rev 7 495/2194

508
Direct memory access controller (DMA) RM0438

Bit 6 HTIF2: half transfer (HT) flag for channel 2

0: no HT event
1: a HT event occurred
Bit 5 TCIF2: transfer complete (TC) flag for channel 2
0: no TC event
1: a TC event occurred
Bit 4 GIF2: global interrupt flag for channel 2
0: no TE, HT or TC event
1: a TE, HT or TC event occurred
Bit 3 TEIF1: transfer error (TE) flag for channel 1
0: no TE event
1: a TE event occurred
Bit 2 HTIF1: half transfer (HT) flag for channel 1
0: no HT event
1: a HT event occurred
Bit 1 TCIF1: transfer complete (TC) flag for channel 1
0: no TC event
1: a TC event occurred
Bit 0 GIF1: global interrupt flag for channel 1
0: no TE, HT or TC event
1: a TE, HT or TC event occurred

496/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

14.6.2 DMA interrupt flag clear register (DMA_IFCR)

Address offset: 0x04
Reset value: 0x0000 0000
This register may mix secure and non secure information, depending on the secure mode of
each channel (SECM bit of the DMA_CCRx register).
A secure software is able to set any flag clear bit of the DMA_IFCR, and order DMA
hardware to clear any corresponding flag(s) in the DMA_ISR register.
A non-secure software is restricted to order DMA hardware to clear the non-secure flag(s) in
the DMA_ISR, by setting any non-secure corresponding flag clear bit(s) of the DMA_IFCR
register.
This register may mix privileged and unprivileged information, depending on the privileged
mode of each channel (PRIV bit of the DMA_CCRx register).
A privileged software is able to set any flag clear bit of the DMA_IFCR, and order DMA
hardware to clear any corresponding flag(s) in the DMA_ISR register.
An unprivileged software is restricted to order DMA hardware to clear the unprivileged
flag(s) in the DMA_ISR, by setting any unprivileged corresponding flag clear bit(s) of the
DMA_IFCR register.
Setting the global clear bit CGIFx of the channel x in this DMA_IFCR register, causes the
DMA hardware to clear the corresponding GIFx bit and any individual flag among TEIFx,
HTIFx, TCIFx, in the DMA_ISR register.
Setting any individual clear bit among CTEIFx, CHTIFx, CTCIFx in this DMA_IFCR register,
causes the DMA hardware to clear the corresponding individual flag and the global flag
GIFx in the DMA_ISR register, provided that none of the two other individual flags is set.
Writing 0 into any flag clear bit has no effect.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CHTIF8

CTCIF8

CHTIF7

CTCIF7

CHTIF6

CTCIF6

CHTIF5

CTCIF5
CTEIF8

CTEIF7

CTEIF6

CTEIF5
CGIF8

CGIF7

CGIF6

CGIF5
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHTIF4

CTCIF4

CHTIF3

CTCIF3

CHTIF2

CTCIF2

CHTIF1

CTCIF1
CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF4

CGIF3

CGIF2

CGIF1

w w w w w w w w w w w w w w w w

Bit 31 CTEIF8: transfer error flag clear for channel 8

Bit 30 CHTIF8: half transfer flag clear for channel 8
Bit 29 CTCIF8: transfer complete flag clear for channel 8
Bit 28 CGIF8: global interrupt flag clear for channel 8
Bit 27 CTEIF7: transfer error flag clear for channel 7
Bit 26 CHTIF7: half transfer flag clear for channel 7
Bit 25 CTCIF7: transfer complete flag clear for channel 7
Bit 24 CGIF7: global interrupt flag clear for channel 7

RM0438 Rev 7 497/2194

508
Direct memory access controller (DMA) RM0438

Bit 23 CTEIF6: transfer error flag clear for channel 6

Bit 22 CHTIF6: half transfer flag clear for channel 6
Bit 21 CTCIF6: transfer complete flag clear for channel 6
Bit 20 CGIF6: global interrupt flag clear for channel 6
Bit 19 CTEIF5: transfer error flag clear for channel 5
Bit 18 CHTIF5: half transfer flag clear for channel 5
Bit 17 CTCIF5: transfer complete flag clear for channel 5
Bit 16 CGIF5: global interrupt flag clear for channel 5
Bit 15 CTEIF4: transfer error flag clear for channel 4
Bit 14 CHTIF4: half transfer flag clear for channel 4
Bit 13 CTCIF4: transfer complete flag clear for channel 4
Bit 12 CGIF4: global interrupt flag clear for channel 4
Bit 11 CTEIF3: transfer error flag clear for channel 3
Bit 10 CHTIF3: half transfer flag clear for channel 3
Bit 9 CTCIF3: transfer complete flag clear for channel 3
Bit 8 CGIF3: global interrupt flag clear for channel 3
Bit 7 CTEIF2: transfer error flag clear for channel 2
Bit 6 CHTIF2: half transfer flag clear for channel 2
Bit 5 CTCIF2: transfer complete flag clear for channel 2
Bit 4 CGIF2: global interrupt flag clear for channel 2
Bit 3 CTEIF1: transfer error flag clear for channel 1
Bit 2 CHTIF1: half transfer flag clear for channel 1
Bit 1 CTCIF1: transfer complete flag clear for channel 1
Bit 0 CGIF1: global interrupt flag clear for channel 1

14.6.3 DMA channel x configuration register (DMA_CCRx)

Address offset: 0x08 + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000
This register contains secure and privileged information: the secure state and the privileged
state of the channel x (SECM and PRIV control bits).
Modifying the SECM bit must be performed by a secure write access to this register.
Modifying the PRIV bit must be performed by a privileged write access to this register.

498/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Setting any of the DSEC or SSEC bits must be performed by a secure write access to this
register.
Except SECM and PRIV control bits, any other register field is non-readable by a
non-secure software if the SECM bit is set, and non-readable by an unprivileged software if
the PRIV bit is set.
The register fields/bits PRIV, DSEC, SSEC, SECM, CT, DBM, MEM2MEM, PL[1:0],
MSIZE[1:0], PSIZE[1:0], MINC, PINC, and DIR are read-only when EN = 1.
The states of MEM2MEM and CIRC bits must not be both high at the same time.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIV DSEC SSEC SECM CT
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEM2
DBM PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
MEM
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

Bit 20 PRIV: privileged mode
This bit can only be set and cleared by a privileged software.
0: disabled
1: enabled
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 19 DSEC: security of the DMA transfer to the destination
This bit can only be read, set or cleared by a secure software. It must be a privileged software
if the channel is in privileged mode.
This bit is cleared by hardware when the securely written data bit 17 is cleared (on a secure
reconfiguration of the channel as non -secure).
A non-secure read to this secure configuration bit returns 0.
A non-secure write of 1 to this secure configuration bit has no impact on the register setting
and an illegal access pulse is asserted.
Destination (peripheral or memory) of the DMA transfer is defined by the direction DIR
configuration bit.
0: non-secure DMA transfer to the destination
1: secure DMA transfer to the destination
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

RM0438 Rev 7 499/2194

508
Direct memory access controller (DMA) RM0438

Bit 18 SSEC: security of the DMA transfer from the source

This bit can only be accessed - read, set or cleared - by a secure software. It must be a
privileged software if the channel is in privileged mode.
This bit is cleared by hardware when the securely written data bit 17 is cleared (on a secure
reconfiguration of the channel as non -secure).
A non-secure read to this secure configuration bit returns 0.
A non-secure write of 1 to this secure configuration bit has no impact on the register setting
and an illegal access pulse is asserted.
Source (peripheral or memory) of the DMA transfer is defined by the direction DIR
configuration bit.
0: non-secure DMA transfer from the source
1: secure DMA transfer from the source
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 17 SECM: secure mode
This bit can only be set or cleared by a secure software.
0: non-secure channel
1: secure channel
This bit must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 16 CT: current target memory of DMA transfer in double-buffer mode
This bit is toggled by hardware at the end of each channel transfer in double-buffer mode.
0: memory 0 (addressed by the DMA_CM0AR pointer)
1: memory 1 (addressed by the DMA_CM1AR pointer)
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 15 DBM: double-buffer mode
This bit must be set only in memory-to-peripheral and peripheral-to-memory transfers
(MEM2MEM=0). The CIRC bit must also be set in double buffer mode.
0: disabled (no memory address switch at the end of the DMA transfer)
1: enabled (memory address switched at the end of the DMA transfer)
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 14 MEM2MEM: memory-to-memory mode
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

500/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Bits 13:12 PL[1:0]: priority level

00: low
01: medium
10: high
11: very high
Note: This field is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 11:10 MSIZE[1:0]: memory size
Defines the data size of each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: This field is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bits 9:8 PSIZE[1:0]: peripheral size
Defines the data size of each DMA transfer to the identified peripheral.
In memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved
Note: This field is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 7 MINC: memory increment mode
Defines the increment mode for each DMA transfer to the identified memory.
In memory-to-memory mode, this field identifies the memory source if DIR = 1 and the
memory destination if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral source if DIR = 1 and the
peripheral destination if DIR = 0.
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

RM0438 Rev 7 501/2194

508
Direct memory access controller (DMA) RM0438

Bit 6 PINC: peripheral increment mode

Defines the increment mode for each DMA transfer to the identified peripheral.
n memory-to-memory mode, this field identifies the memory destination if DIR = 1 and the
memory source if DIR = 0.
In peripheral-to-peripheral mode, this field identifies the peripheral destination if DIR = 1 and
the peripheral source if DIR = 0.
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 5 CIRC: circular mode
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 4 DIR: data transfer direction
This bit must be set only in memory-to-peripheral and peripheral-to-memory modes.
0: read from peripheral
– Source attributes are defined by PSIZE and PINC, plus the DMA_CPARx register.
This is still valid in a memory-to-memory mode.
– Destination attributes are defined by MSIZE and MINC, plus the DMA_CM0/1ARx
register. This is still valid in a peripheral-to-peripheral mode.
1: read from memory
– Destination attributes are defined by PSIZE and PINC, plus the DMA_CPARx
register. This is still valid in a memory-to-memory mode.
– Source attributes are defined by MSIZE and MINC, plus the DMA_CM0/1ARx
register. This is still valid in a peripheral-to-peripheral mode.
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).
Bit 3 TEIE: transfer error interrupt enable
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).

502/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Bit 2 HTIE: half transfer interrupt enable

0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 1 TCIE: transfer complete interrupt enable
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is not read-only when the channel is enabled (EN = 1).
Bit 0 EN: channel enable
When a channel transfer error occurs, this bit is cleared by hardware. It can not be set again
by software (channel x re-activated) until the TEIFx bit of the DMA_ISR register is cleared (by
setting the CTEIFx bit of the DMA_IFCR register).
0: disabled
1: enabled
Note: This bit is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode)

14.6.4 DMA channel x number of data to transfer register (DMA_CNDTRx)

Address offset: 0x0C + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. NDT[17:16]
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:18 Reserved, must be kept at reset value.

Bits 17:0 NDT[17:0]: number of data to transfer (0 to 218 - 1)
This field is updated by hardware when the channel is enabled:
– It is decremented after each single DMA ‘read followed by write’ transfer, indicating
the remaining amount of data items to transfer.
– It is kept at zero when the programmed amount of data to transfer is reached, if the
channel is not in circular mode (CIRC = 0 in the DMA_CCRx register).
– It is reloaded automatically by the previously programmed value, when the transfer
is complete, if the channel is in circular mode (CIRC = 1).
If this field is zero, no transfer can be served whatever the channel status (enabled or not).
Note: This field is set and cleared by software (privileged/secure software if the channel is in
privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

RM0438 Rev 7 503/2194

508
Direct memory access controller (DMA) RM0438

14.6.5 DMA channel x peripheral address register (DMA_CPARx)

Address offset: 0x10 + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PA[31:0]: peripheral address

It contains the base address of the peripheral data register from/to which the data is
read/written.
When PSIZE[1:0] = 01 (16 bits), bit 0 of PA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When PSIZE = 10 (32 bits), bits 1 and 0 of PA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory destination address if
DIR = 1 and the memory source address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral destination address
DIR = 1 and the peripheral source address if DIR = 0.
Note: This register is set and cleared by software (privileged/secure software if the channel is
in privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

14.6.6 DMA channel x memory 0 address register (DMA_CM0ARx)

Address offset: 0x14 + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

504/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data is read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: This register is set and cleared by software (privileged/secure software if the channel is
in privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

14.6.7 DMA channel x memory 1 address register (DMA_CM1ARx)

Address offset: 0x18 + 0x14 * (x - 1), (x = 1 to 8)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MA[31:0]: peripheral address

It contains the base address of the memory from/to which the data will be read/written.
When MSIZE[1:0] = 01 (16 bits), bit 0 of MA[31:0] is ignored. Access is automatically aligned
to a half-word address.
When MSIZE = 10 (32 bits), bits 1 and 0 of MA[31:0] are ignored. Access is automatically
aligned to a word address.
In memory-to-memory mode, this register identifies the memory source address if DIR = 1
and the memory destination address if DIR = 0.
In peripheral-to-peripheral mode, this register identifies the peripheral source address
DIR = 1 and the peripheral destination address if DIR = 0.
Note: This register is set and cleared by software (privileged/secure software if the channel is
in privileged/secure mode).
It must not be written when the channel is enabled (EN = 1).
It is read-only when the channel is enabled (EN = 1).

14.6.8 DMA register map

Table 96. DMA register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
HTIF8
TCIF8

HTIF7
TCIF7

HTIF6
TCIF6

HTIF5
TCIF5

HTIF4
TCIF4

HTIF3
TCIF3

HTIF2
TCIF2

HTIF1
TCIF1
TEIF8

TEIF7

TEIF6

TEIF5

TEIF4

TEIF3

TEIF2

TEIF1
GIF8

GIF7

GIF6

GIF5

GIF4

GIF3

GIF2

GIF1

DMA_ISR
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 505/2194

508
Direct memory access controller (DMA) RM0438

Table 96. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
CTCIF8

CTCIF7

CTCIF6

CTCIF5

CTCIF4

CTCIF3

CTCIF2

CTCIF1
CHTIF8

CHTIF7

CHTIF6

CHTIF5

CHTIF4

CHTIF3

CHTIF2

CHTIF1
CTEIF8

CTEIF7

CTEIF6

CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF8

CGIF7

CGIF6

CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
DMA_IFCR
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
DMA_CCR1
0x008

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR1 NDT[17:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR1 PA[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM0AR1 MA[31:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR1 MA[31:0]
0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
DMA_CCR2
0x01C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR2 NDT[17:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR2 PA[31:0]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM0AR2 MA[31:0]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR2 MA[31:0]
0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

DMA_CCR3
0x030

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR3 NDTR[17:0]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR3 PA[31:0]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM0AR3 MA[31:0]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR3 MA[31:0]
0x040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

DMA_CCR4
0x044

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR4 NDT[17:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR4 PA[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

506/2194 RM0438 Rev 7

RM0438 Direct memory access controller (DMA)

Table 96. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DMA_CM0AR4 MA[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR4 MA[31:0]
0x054
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
DBM

TEIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT
DMA_CCR5
0x058

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA_CNDTR5 NDT[17:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR5 PA[31:0]
0x060
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM0AR5 MA[31:0]
0x064
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR5 MA[31:0]
0x068
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
0x06C
DMA_CCR6 CT

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR6 NDT[17:0]
0x070
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR6 PA[31:0]
0x074
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM0AR6 MA[31:0]
0x078
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR6 MA[31:0]
0x07C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

DMA_CCR7
0x080

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR7 NDT[17:0]
0x084
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR7 PA[31:0]
0x088
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM0AR7 MA[31:0]
0x08C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR7 MA[31:0]
0x090
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

MSIZE[1:0]

PSIZE[1:0]
PL[1:0]
SECM
DSEC
SSEC

MINC

CIRC
PINC
PRIV

HTIE
TCIE
TEIE
DBM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DIR

EN
CT

DMA_CCR8
0x094

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

DMA_CNDTR8 NDT[17:0]
0x098
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CPAR8 PA[31:0]
0x09C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 507/2194

508
Direct memory access controller (DMA) RM0438

Table 96. DMA register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DMA_CM0AR8 MA[31:0]
0x0A0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_CM1AR8 MA[31:0]
0x0A4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

508/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

15 DMA request multiplexer (DMAMUX)

15.1 Introduction
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The
DMA request is pending until it is served by the DMA controller that generates a DMA
acknowledge signal, and the corresponding DMA request signal is deasserted.
In this document, the set of control signals required for the DMA request/acknowledge
protocol is not explicitly shown or described, and it is referred to as DMA request line.
The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controllers of the product. The routing function is ensured by a
programmable multi-channel DMA request line multiplexer. Each channel selects a unique
DMA request line, unconditionally or synchronously with events from its DMAMUX
synchronization inputs. The DMAMUX may also be used as a DMA request generator from
programmable events on its input trigger signals.
The number of DMAMUX instances and their main characteristics are specified in
Section 15.3.1.
The assignment of DMAMUX request multiplexer inputs to the DMA request lines from
peripherals and to the DMAMUX request generator outputs, the assignment of DMAMUX
request multiplexer outputs to DMA controller channels, and the assignment of DMAMUX
synchronizations and trigger inputs to internal and external signals depend on the product
implementation, and are detailed inSection 15.3.2.

RM0438 Rev 7 509/2194

528
DMA request multiplexer (DMAMUX) RM0438

15.2 DMAMUX main features

• 16-channel programmable DMA request line multiplexer output
• 4-channel DMA request generator
• 23 trigger inputs to DMA request generator
• 23 synchronization inputs
• Per DMA request generator channel:
– DMA request trigger input selector
– DMA request counter
– Event overrun flag for selected DMA request trigger input
• Per DMA request line multiplexer channel output:
– 90 input DMA request lines from peripherals
– One DMA request line output
– Synchronization input selector
– DMA request counter
– Event overrun flag for selected synchronization input
– One event output, for DMA request chaining
• TrustZone support:
– Support for AHB secure and non-secure DMA transfers, independently at a
channel level.
– TrustZone-aware AHB slave port, protecting any secure resource (register,
register field) from a non-secure software access, with configurable interrupt
event.
– Two secure and non-secure interrupt requests, resulting from any of the
respectively secure and non-secure channels. Each channel event being caused
from any of the two DMAMUX input events: trigger or synchronization overrun,
associated with a respectively secure and non-secure channels.
• Privileged / Unprivileged support:
– Support for AHB privileged and unprivileged DMA transfers, independently, at a
channel level.
– Privileged-aware AHB slave port.

15.3 DMAMUX implementation

15.3.1 DMAMUX instantiation

DMAMUX is instantiated with the hardware configuration parameters listed in the following
table.

Table 97. DMAMUX instantiation

Feature DMAMUX

Number of DMAMUX output request channels 16

Number of DMAMUX request generator channels 4
Number of DMAMUX request trigger inputs 23

510/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

Table 97. DMAMUX instantiation (continued)

Feature DMAMUX

Number of DMAMUX synchronization inputs 23

Number of DMAMUX peripheral request inputs 90
DMAMUX TrustZone support 1

15.3.2 DMAMUX mapping

The mapping of resources to DMAMUX is hardwired.
DMAMUX is used with DMA1 and DMA2:
• DMAMUX channels 0 to 7 are connected to DMA1 channels 0 to 7
• DMAMUX channels 8 to 15 are connected to DMA2 channels 0 to 7

Table 98. DMAMUX: assignment of multiplexer inputs to resources

DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

1 dmamux_req_gen0 44 TIM1_CH3 87 DFSDM1_FLT1

2 dmamux_req_gen1 45 TIM1_CH4 88 DFSDM1_FLT2
3 dmamux_req_gen2 46 TIM1_UP 89 DFSDM1_FLT3
4 dmamux_req_gen3 47 TIM1_TRIG 90 AES_IN
5 ADC1 48 TIM1_COM 91 AES_OUT
6 ADC2 49 TIM8_CH1 92 HASH_IN
7 DAC1 50 TIM8_CH2 93 USBPD_TX
8 DAC2 51 TIM8_CH3 94 USBPD_RX
9 TIM6_UP 52 TIM8_CH4 95 Reserved
10 TIM7_UP 53 TIM8_UP 96 Reserved
11 SPI1_RX 54 TIM8_TRIG 97 Reserved
12 SPI1_TX 55 TIM8_COM 98 Reserved
13 SPI2_RX 56 TIM2_CH1 99 Reserved
14 SPI2_TX 57 TIM2_CH2 100 Reserved
15 SPI3_RX 58 TIM2_CH3 101 Reserved
16 SPI3_TX 59 TIM2_CH4 102 Reserved
17 I2C1_RX 60 TIM2_UP 103 Reserved
18 I2C1_TX 61 TIM3_CH1 104 Reserved
19 I2C2_RX 62 TIM3_CH2 105 Reserved
20 I2C2_TX 63 TIM3_CH3 106 Reserved
21 I2C3_RX 64 TIM3_CH4 107 Reserved
22 I2C3_TX 65 TIM3_UP 108 Reserved
23 I2C4_RX 66 TIM3_TRIG 109 Reserved

RM0438 Rev 7 511/2194

528
DMA request multiplexer (DMAMUX) RM0438

Table 98. DMAMUX: assignment of multiplexer inputs to resources (continued)

DMA DMA DMA
request Resource request Resource request Resource
MUX input MUX input MUX input

24 I2C4_TX 67 TIM4_CH1 110 Reserved

25 USART1_RX 68 TIM4_CH2 111 Reserved
26 USART1_TX 69 TIM4_CH3 112 Reserved
27 USART2_RX 70 TIM4_CH4 113 Reserved
28 USART2_TX 71 TIM4_UP 114 Reserved
29 USART3_RX 72 TIM5_CH1 115 Reserved
30 USART3_TX 73 TIM5_CH2 116 Reserved
31 UART4_RX 74 TIM5_CH3 117 Reserved
32 UART4_TX 75 TIM5_CH4 118 Reserved
33 UART5_RX 76 TIM5_UP 119 Reserved
34 UART5_TX 77 TIM5_TRIG 120 Reserved
35 LPUART1_RX 78 TIM15_CH1 121 Reserved
36 LPUART1_TX 79 TIM15_UP 122 Reserved
37 SAI1_A 80 TIM15_TRIG 123 Reserved
38 SAI1_B 81 TIM15_COM 124 Reserved
39 SAI2_A 82 TIM16_CH1 125 Reserved
40 SAI2_B 83 TIM16_UP 126 Reserved
41 OCTOSPI1 84 TIM17_CH1 127 Reserved
42 TIM1_CH1 85 TIM17_UP - -
43 TIM1_CH2 86 DFSDM1_FLT0 - -

Table 99. DMAMUX: assignment of trigger inputs to resources

Trigger input Resource Trigger input Resource

0 EXTI LINE0 16 dmamux_evt0

1 EXTI LINE1 17 dmamux_evt1
2 EXTI LINE2 18 dmamux_evt2
3 EXTI LINE3 19 dmamux_evt3
4 EXTI LINE4 20 LPTIM1_OUT
5 EXTI LINE5 21 LPTIM2_OUT
6 EXTI LINE6 22 LPTIM3_OUT
7 EXTI LINE7 23 Reserved
8 EXTI LINE8 24 Reserved
9 EXTI LINE9 25 Reserved
10 EXTI LINE10 26 Reserved
11 EXTI LINE11 27 Reserved
12 EXTI LINE12 28 Reserved

512/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

Table 99. DMAMUX: assignment of trigger inputs to resources (continued)

Trigger input Resource Trigger input Resource

13 EXTI LINE13 29 Reserved

14 EXTI LINE14 30 Reserved
15 EXTI LINE15 31 Reserved

Table 100. DMAMUX: assignment of synchronization inputs to resources

Sync. input Resource Sync. input Resource

0 EXTI LINE0 16 dmamux_evt0

1 EXTI LINE1 17 dmamux_evt1
2 EXTI LINE2 18 dmamux_evt2
3 EXTI LINE3 19 dmamux_evt3
4 EXTI LINE4 20 LPTIM1_OUT
5 EXTI LINE5 21 LPTIM2_OUT
6 EXTI LINE6 22 LPTIM3_OUT
7 EXTI LINE7 23 Reserved
8 EXTI LINE8 24 Reserved
9 EXTI LINE9 25 Reserved
10 EXTI LINE10 26 Reserved
11 EXTI LINE11 27 Reserved
12 EXTI LINE12 28 Reserved
13 EXTI LINE13 29 Reserved
14 EXTI LINE14 30 Reserved
15 EXTI LINE15 31 Reserved

RM0438 Rev 7 513/2194

528
DMA request multiplexer (DMAMUX) RM0438

15.4 DMAMUX functional description

15.4.1 DMAMUX block diagram

Figure 44 shows the DMAMUX block diagram.

Figure 44. DMAMUX block diagram

32-bit AHB bus

dmamux_hclk

To TrustZone DMAMUX Request multiplexer

AHB slave
interrupt controller: Channel m
dmamux_sec_ilac interface
DMAMUX_CmCR

p Channel 1 Secure and

x
eq
_r Channel 0 m privileged state of
DMA requests the DMA channels:
ux
1
from peripherals: DMAMUX_C0CR
am

1 0 dma_secmx
dmamux_req_inx
dm

Channel Ctrl dma_privx

0 select
n+p+2 m DMA requests
Request 1 to DMA controllers:
dmamux_req_genx

0
generator dmamux_req_outx
n n+3
Channel n
DMAMUX_RGCnCR n+2 Sync m
1 DMA channels events:
n+1 0 dmamux_evtx
s 1 0
Channel 1 1 2
DMAMUX_RGC1CR
1
Channel 0 0
DMAMUX_RGC0CR

Interrupt
interface
t 1 0 s 1 0

Trigger inputs: Synchronization inputs:

dmamux_trgx Interrupts: dmamux_syncx
Control registers dmamux_sec_ovr_it,
dmamux_nonsec_ovr_it
MS45425V2

DMAMUX features two main sub-blocks: the request line multiplexer and the request line
generator.
The implementation assigns:
• DMAMUX request multiplexer sub-block inputs (dmamux_reqx) from peripherals
(dmamux_req_inx) and from channels of the DMAMUX request generator sub-block
(dmamux_req_genx)
• DMAMUX request outputs to channels of DMA controllers (dmamux_req_outx)
• Internal or external signals to DMA request trigger inputs (dmamux_trgx)
• Internal or external signals to synchronization inputs (dmamux_syncx)

514/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

15.4.2 DMAMUX signals

Table 101 lists the DMAMUX signals.

Table 101. DMAMUX signals

Signal name Description

dmamux_hclk DMAMUX AHB clock

dmamux_req_inx DMAMUX DMA request line inputs from peripherals
dmamux_trgx DMAMUX DMA request triggers inputs (to request generator sub-block)
dmamux_req_genx DMAMUX request generator sub-block channels outputs
DMAMUX request multiplexer sub-block inputs (from peripheral
dmamux_reqx
requests and request generator channels)
dmamux_syncx DMAMUX synchronization inputs (to request multiplexer sub-block)
dmamux_req_outx DMAMUX requests outputs (to DMA controllers)
dma_secmx Secure mode of each DMA controller request channel
dma_privx Privileged mode of each DMA controller request channel
dmamux_evtx DMAMUX events outputs
dmamux_non_sec_ovr_it DMAMUX non-secure overrun interrupts
dmamux_sec_ovr_it DMAMUX secure overrun interrupts
DMAMUX security illegal access output (to TrustZone interrupt
dmamux_illegal_access_it
controller)

15.4.3 DMAMUX channels

A DMAMUX channel is a DMAMUX request multiplexer channel that may include,
depending on the selected input of the request multiplexer, an additional DMAMUX request
generator channel.
A DMAMUX request multiplexer channel is connected and dedicated to one single channel
of DMA controller(s).

Channel configuration procedure

Follow the sequence below to configure both a DMAMUX x channel and the related DMA
channel y:
1. Set to secure or non-secure the DMA channel y by a secure write access to the secure
control bit of the DMA channel y configuration register, and set to privileged or
unprivileged the DMA channel y by a privileged write access to the privileged control bit
of the DMA channel y configuration register.
2. Set and configure completely the DMA channel y, except enabling the channel y.
3. Set and configure completely the related DMAMUX y channel.
4. Last, activate the DMA channel y by setting the EN bit in the DMA y channel register.

RM0438 Rev 7 515/2194

528
DMA request multiplexer (DMAMUX) RM0438

15.4.4 DMAMUX secure/non-secure channels

The DMAMUX is a security-aware peripheral compliant with the TrustZone hardware
architecture, partitioning all its resources so that they exist in one of the two worlds: the
secure world and the normal/non-secure world, at any given time.
The DMAMUX security is controlled by software at channel level. Any DMAMUX channel is
in secure or non-secure state, as configured by the secure register bit of the associated
channel of the DMA controller(s).
Note: A DMA controller(s) channel must be first configured as secure or non-secure, before the
configuration of the connected DMAMUX channel.
Note: A secure software is able to access any DMAMUX register, whatever secure or non-secure.
A non-secure software is restricted to access only non-secure DMAMUX register or
non-secure register fields.
A secure read/write access is a read/write transaction on AHB slave with the signal
HNONSEC = 0 (at the clock cycle of the address sampling). On the contrary, a non-secure
read/write access is a read/write transaction on AHB slave with the signal HNONSEC = 1.
When a channel is configured in secure mode, its configuration register fields become
secure resources, meaning that:
• A non-secure read access to a (secure register) field is forced to return 0.
• A non-secure write access to a (secure register) field has no impact.
Additionally, an illegal access signal is generated, as a pulse, to the TrustZone interrupt
controller, when a non-secure software attempts to access a secure DMAMUX register:
• DMAMUX_CxCR if the request multiplexer channel x is secure.
• DMAMUX_RGxCR if the request generator channel x is secure.
Note: The secure illegal access signal is never asserted on a non-secure access to the global
interrupt status and clear registers, even despite all the DMAMUX channels are set as
secure.

15.4.5 DMAMUX privileged / unprivileged channels

The DMAMUX is aware of the privileged or unprivileged state of a given DMA connected
channel, and manages consequently its DMAMUX requested channel.
Note: A DMA controller(s) channel must be first configured as privileged or unprivileged, before
the configuration of the connected DMAMUX channel.
Note: A privileged software is able to access any DMAMUX register, privileged or unprivileged. An
unprivileged software is restricted to access only unprivileged DMAMUX register or register
fields.
When a privileged software configures a DMA channel x either as privileged, an
unprivileged software is not able to access (write is ignored, read returns zero) the related
DMAMUX channel registers or register fields.

15.4.6 DMAMUX request line multiplexer

The DMAMUX request multiplexer with its multiple channels ensures the actual routing of
DMA request/acknowledge control signals, named DMA request lines.
Each DMA request line is connected in parallel to all the channels of the DMAMUX request
line multiplexer.

516/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

A DMA request is sourced either from the peripherals or from the DMAMUX request
generator.
The DMAMUX request line multiplexer channel x selects the DMA request line number as
configured by the DMAREQ_ID field in the DMAMUX_CxCR register.
Note: The null value in the field DMAREQ_ID corresponds to no DMA request line selected.
Caution: A same non-null DMAREQ_ID can be assigned to two different channels only if the
application ensures that these channels are not requested to be served at the same time. In
other words, if two different channels receive a same asserted hardware request at the
same time, an unpredictable DMA hardware behavior occurs.
On top of the DMA request selection, the synchronization mode and/or the event generation
may be configured and enabled, if required.

Synchronization mode and channel event generation

Each DMAMUX request line multiplexer channel x can be individually synchronized by
setting the synchronization enable (SE) bit in the DMAMUX_CxCR register.
DMAMUX has multiple synchronization inputs. The synchronization inputs are connected in
parallel to all the channels of the request multiplexer.
The synchronization input is selected via the SYNC_ID field in the DMAMUX_CxCR register
of a given channel x.
When a channel is in this synchronization mode, the selected input DMA request line is
propagated to the multiplexer channel output, once is detected a programmable
rising/falling edge on the selected input synchronization signal, via the SPOL[1:0] field of the
DMAMUX_CxCR register.
Additionally, there is a programmable DMA request counter, internally to the DMAMUX
request multiplexer, which may be used for the channel request output generation and also
possibly for an event generation. An event generation on the channel x output is enabled
through the EGE bit (event generation enable) of the DMAMUX_CxCR register.
As shown in Figure 46, upon the detected edge of the synchronization input, the pending
selected input DMA request line is connected to the DMAMUX multiplexer channel x output.
Note: If a synchronization event occurs while there is no pending selected input DMA request line,
it is discarded. The following asserted input request lines is not connected to the DMAMUX
multiplexer channel output until a synchronization event occurs again.
From this point on, each time the connected DMAMUX request is served by the DMA
controller (a served request is deasserted), the DMAMUX request counter is decremented.
At its underrun, the DMA request counter is automatically loaded with the value in NBREQ
field of the DMAMUX_CxCR register and the input DMA request line is disconnected from
the multiplexer channel x output.
Thus, the number of DMA requests transferred to the multiplexer channel x output following
a detected synchronization event, is equal to the value in NBREQ field, plus one.
Note: The NBREQ field value shall only be written by software when both synchronization enable
bit SE and event generation enable EGE bit of the corresponding multiplexer channel x are
disabled.

RM0438 Rev 7 517/2194

528
DMA request multiplexer (DMAMUX) RM0438

Figure 45. Synchronization mode of the DMAMUX request line multiplexer channel

Selected DMA request line transferred to the output

DMA requests served

DMA request pending

Selected
dmamux_reqx
Not pending

dmamux_syncx

dmamux_req_outx

DMA request counter 4 3 2 1 0 4

dmamux_evtx

DMA request counter underrun

Synchronization event
DMA request counter auto-reload to NBREQ
Input DMA request line connected to output
Input DMA request line disconnected from output

Example: DMAMUX_CCRx configured with: NBREQ=4, SE=1, EGE=1, SPOL=01 (rising edge)

MSv41974V1

Figure 46. Event generation of the DMA request line multiplexer channel

Selected DMA request line transferred to the output

DMA request pending

Selected
dmamux_reqx Not pending

dmamux_req_outx

DMA request counter 3 2 1 0 3 2 1 0 3 2 1 0

SE

EGE

dmamux_evtx

DMA request counter reaches zero

Event is generated on the output
DMA request counter auto-reloads with NBREQ value

Example with: DMAMUX_CCRx configured with: NBREQ=3, SE=0, EGE=1

MSv41975V1

If EGE is enabled, the multiplexer channel generates a channel event, as a pulse of one
AHB clock cycle, when its DMA request counter is automatically reloaded with the value of
the programmed NBREQ field, as shown in Figure 45 and Figure 46.

518/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

Note: If EGE is enabled and NBREQ = 0, an event is generated after each served DMA request.
Note: A synchronization event (edge) is detected if the state following the edge remains stable for
more than two AHB clock cycles.
Upon writing into DMAMUX_CxCR register, the synchronization events are masked during
three AHB clock cycles.

Synchronization overrun and interrupt

If a new synchronization event occurs before the request counter underrun (the internal
request counter programmed via the NBREQ field of the DMAMUX_CxCR register), the
synchronization overrun flag bit SOFx is set in the DMAMUX_CSR status register.
Note: The request multiplexer channel x synchronization must be disabled
(DMAMUX_CxCR.SE = 0) at the completion of the use of the related channel of the DMA
controller. Else, upon a new detected synchronization event, there is a synchronization
overrun due to the absence of a DMA acknowledge (that is, no served request) received
from the DMA controller.
The overrun flag SOFx is reset by setting the associated clear synchronization overrun flag
bit CSOFx in the DMAMUX_CCFR register.
Setting the synchronization overrun flag generates an interrupt if the synchronization
overrun interrupt enable bit SOIE is set in the DMAMUX_CxCR register.

15.4.7 DMAMUX request generator

The DMAMUX request generator produces DMA requests following trigger events on its
DMA request trigger inputs.
The DMAMUX request generator has multiple channels. DMA request trigger inputs are
connected in parallel to all channels.
The outputs of DMAMUX request generator channels are inputs to the DMAMUX request
line multiplexer.
Each DMAMUX request generator channel x has an enable bit GE (generator enable) in the
corresponding DMAMUX_RGxCR register.
The DMA request trigger input for the DMAMUX request generator channel x is selected
through the SIG_ID (trigger signal ID) field in the corresponding DMAMUX_RGxCR register.
Trigger events on a DMA request trigger input can be rising edge, falling edge or either
edge. The active edge is selected through the GPOL (generator polarity) field in the
corresponding DMAMUX_RGxCR register.
Upon the trigger event, the corresponding generator channel starts generating DMA
requests on its output. Each time the DMAMUX generated request is served by the
connected DMA controller (a served request is deasserted), a built-in (inside the DMAMUX
request generator) DMA request counter is decremented. At its underrun, the request
generator channel stops generating DMA requests and the DMA request counter is
automatically reloaded to its programmed value upon the next trigger event.
Thus, the number of DMA requests generated after the trigger event is GNBREQ + 1.

RM0438 Rev 7 519/2194

528
DMA request multiplexer (DMAMUX) RM0438

Note: The GNBREQ field value must be written by software only when the enable GE bit of the
corresponding generator channel x is disabled.
A trigger event (edge) is detected if the state following the edge remains stable for more
than two AHB clock cycles.
Upon writing into DMAMUX_RGxCR register, the trigger events are masked during three
AHB clock cycles.

Trigger overrun and interrupt

If a new DMA request trigger event occurs before the DMAMUX request generator counter
underrun (the internal counter programmed via the GNBREQ field of the DMAMUX_RGxCR
register), and if the request generator channel x was enabled via GE, then the request
trigger event overrun flag bit OFx is asserted by the hardware in the status
DMAMUX_RGSR register.
Note: The request generator channel x must be disabled (DMAMUX_RGxCR.GE = 0) at the
completion of the usage of the related channel of the DMA controller. Else, upon a new
detected trigger event, there is a trigger overrun due to the absence of an acknowledge (that
is, no served request) received from the DMA.
The overrun flag OFx is reset by setting the associated clear overrun flag bit COFx in the
DMAMUX_RGCFR register.
Setting the DMAMUX request trigger overrun flag generates an interrupt if the DMA request
trigger event overrun interrupt enable bit OIE is set in the DMAMUX_RGxCR register.

15.5 DMAMUX interrupts

An interrupt can be generated upon:
• a synchronization event overrun in each DMA request line multiplexer channel
• a trigger event overrun in each DMA request generator channel
For each case, per-channel individual interrupt enable, status and clear flag register bits are
available. As a consequence, there are mixed secure and non-secure status and clear flag
bit fields inside a same global status and clear flag interrupt register, depending on the
security of the considered DMAMUX channel.
There are two different secure and non-secure interrupt signals that may be generated,
depending on the security of the DMAMUX channel.

Table 102. DMAMUX interrupts

Interrupt signal Interrupt event Event flag Clear bit Enable bit

Synchronization event overrun

on a non-secure channel x of the SOFx CSOFx SOIE
DMAMUX request line multiplexer
dmamux_nonsec_ovr_it
Trigger event overrun
on a non-secure channel x of the OFx COFx OIE
DMAMUX request generator

520/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

Table 102. DMAMUX interrupts (continued)

Interrupt signal Interrupt event Event flag Clear bit Enable bit

Synchronization event overrun

on a secure channel x of the SOFx CSOFx SOIE
DMAMUX request line multiplexer
dmamux_sec_ovr_it
Trigger event overrun
on a secure channel x of the OFx COFx OIE
DMAMUX request generator

RM0438 Rev 7 521/2194

528
DMA request multiplexer (DMAMUX) RM0438

15.6 DMAMUX registers

Refer to the table containing register boundary addresses for the DMAMUX base address.
DMAMUX registers may be accessed per (8-bit) byte, (16-bit) half-word, or (32-bit) word.
The address must be aligned with the data size.

15.6.1 DMAMUX request line multiplexer channel x configuration register

(DMAMUX_CxCR)
Address offset: 0x000 + 0x04 * x (x = 0 to 15)
Reset value: 0x0000 0000
This register shall be written by a non-secure or secure write, according to the secure mode
of the considered DMAMUX request line multiplexer channel x, depending on the secure
mode bit of the connected DMA controller channel y. This assumes that the DMAMUX
x channel output is connected to the y channel of the DMA (refer to the DMAMUX mapping
implementation section).
This register shall be accessed by a privileged or unprivileged read/write, according to the
privileged mode of the considered DMAMUX request line multiplexer channel x, depending
on the privileged control bit of the connected of the connected DMA controller channel y.
This assumes that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMUX mapping implementation section).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SYNC_ID[4:0] NBREQ[4:0] SPOL[1:0] SE
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. EGE SOIE Res. DMAREQ_ID[6:0]
rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SYNC_ID[4:0]: Synchronization identification
Selects the synchronization input (see Table 100: DMAMUX: assignment of synchronization
inputs to resources).
Bits 23:19 NBREQ[4:0]: Number of DMA requests minus 1 to forward
Defines the number of DMA requests to forward to the DMA controller after a synchronization
event, and/or the number of DMA requests before an output event is generated.
This field shall only be written when both SE and EGE bits are low.
Bits 18:17 SPOL[1:0]: Synchronization polarity
Defines the edge polarity of the selected synchronization input:
00: No event, i.e. no synchronization nor detection.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 SE: Synchronization enable
0: synchronization disabled
1: synchronization enabled
Bits 15:10 Reserved, must be kept at reset value.

522/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

Bit 9 EGE: Event generation enable

0: event generation disabled
1: event generation enabled
Bit 8 SOIE: Synchronization overrun interrupt enable
0: interrupt disabled
1: interrupt enabled
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 DMAREQ_ID[6:0]: DMA request identification
Selects the input DMA request. See the DMAMUX table about assignments of multiplexer
inputs to resources.

15.6.2 DMAMUX request line multiplexer interrupt channel status register

(DMAMUX_CSR)
Address offset: 0x080
Reset value: 0x0000 0000
This register must be accessed at bit level by a non-secure or secure read, according to the
secure mode of the considered DMAMUX request line multiplexer channel x, depending on
the secure mode bit of the connected DMA controller channel y, and considering that the
DMAMUX x channel output is connected to the y channel of the DMA (refer to the DMAMUX
mapping implementation section).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOF15 SOF14 SOF13 SOF12 SOF11 SOF10 SOF9 SOF8 SOF7 SOF6 SOF5 SOF4 SOF3 SOF2 SOF1 SOF0
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 SOF[15:0]: Synchronization overrun event flag
The flag is set when a synchronization event occurs on a DMA request line multiplexer
channel x, while the DMA request counter value is lower than NBREQ.
The flag is cleared by writing 1 to the corresponding CSOFx bit in DMAMUX_CCFR register.

15.6.3 DMAMUX request line multiplexer interrupt channel clear flag register
(DMAMUX_CCFR)
Address offset: 0x084
Reset value: 0x0000 0000
This register must be written at bit level by a non-secure or secure write, according to the
secure mode of the considered DMAMUX request line multiplexer channel x, depending on
the secure control bit of the connected DMA controller channel y, and considering that the
DMAMUX x channel output is connected to the y channel of the DMA (refer to the
DMAMXUX mapping implementation section).
This register must be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel x,

RM0438 Rev 7 523/2194

528
DMA request multiplexer (DMAMUX) RM0438

depending on the privileged control bit of the connected DMA controller channel y, and
considering that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMXUX mapping implementation section).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF CSOF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
w w w w w w w w w w w w w w w w

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 CSOF[15:0]: Clear synchronization overrun event flag
Writing 1 in each bit clears the corresponding overrun flag SOFx in the DMAMUX_CSR
register.

15.6.4 DMAMUX request generator channel x configuration register

(DMAMUX_RGxCR)
Address offset: 0x100 + 0x04 * x (x = 0 to 3)
Reset value: 0x0000 0000
This register shall be written by a non-secure or secure write, according to the secure mode
of the considered DMAMUX request line multiplexer channel y it is assigned to, and
considering that the DMAMUX request generator x channel output is selected by the y
channel of the DMAMUX request line channel (refer to DMAMUX_CyCR.DMAREQ_ID[7:0]
and to the DMAMXUX mapping implementation section).
This register shall be written by an unprivileged or privileged write, according to the
privileged mode of the considered DMAMUX request line multiplexer channel y it is
assigned to, and considering that the DMAMUX request generator x channel output is
selected by the y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. GNBREQ[4:0] GPOL[1:0] GE
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. OIE Res. Res. Res. SIG_ID[4:0]
rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:19 GNBREQ[4:0]: Number of DMA requests to be generated (minus 1)
Defines the number of DMA requests to be generated after a trigger event. The actual
number of generated DMA requests is GNBREQ +1.
Note: This field must be written only when GE bit is disabled.

524/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

Bits 18:17 GPOL[1:0]: DMA request generator trigger polarity

Defines the edge polarity of the selected trigger input
00: No event, i.e. no trigger detection nor generation.
01: Rising edge
10: Falling edge
11: Rising and falling edges
Bit 16 GE: DMA request generator channel x enable
0: DMA request generator channel x disabled
1: DMA request generator channel x enabled
Bits 15:9 Reserved, must be kept at reset value.
Bit 8 OIE: Trigger overrun interrupt enable
0: Interrupt on a trigger overrun event occurrence is disabled
1: Interrupt on a trigger overrun event occurrence is enabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 SIG_ID[4:0]: Signal identification
Selects the DMA request trigger input used for the channel x of the DMA request generator

15.6.5 DMAMUX request generator interrupt status register

(DMAMUX_RGSR)
Address offset: 0x140
Reset value: 0x0000 0000
This register shall be accessed at bit level by a non-secure or secure read, according to the
secure mode of the considered DMAMUX request line multiplexer channel x, depending on
the secure mode bit of the connected DMA controller channel y, and considering that the
DMAMUX x channel output is connected to the y channel of the DMA (refer to the
DMAMXUX mapping implementation section).
This register shall be accessed at bit level by an unprivileged or privileged read, according
to the privileged mode of the considered DMAMUX request line multiplexer channel x,
depending on the privileged control bit of the connected DMA controller channel y, and
considering that the DMAMUX x channel output is connected to the y channel of the DMA
(refer to the DMAMXUX mapping implementation section).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OF3 OF2 OF1 OF0
r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 OF[3:0]: Trigger overrun event flag
The flag is set when a new trigger event occurs on DMA request generator channel x, before
the request counter underrun (the internal request counter programmed via the GNBREQ
field of the DMAMUX_RGxCR register).
The flag is cleared by writing 1 to the corresponding COFx bit in the DMAMUX_RGCFR
register.

RM0438 Rev 7 525/2194

528
DMA request multiplexer (DMAMUX) RM0438

15.6.6 DMAMUX request generator interrupt clear flag register

(DMAMUX_RGCFR)
Address offset: 0x144
Reset value: 0x0000 0000
This register shall be written at bit level by a non-secure or secure write, according to the
secure mode of the considered DMAMUX request line multiplexer channel y it is assigned
to, and considering that the DMAMUX request generator x channel output is selected by the
y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).
This register shall be written at bit level by an unprivileged or privileged write, according to
the privileged mode of the considered DMAMUX request line multiplexer channel y it is
assigned to, and considering that the DMAMUX request generator x channel output is
selected by the y channel of the DMAMUX request line channel (refer to
DMAMUX_CyCR.DMAREQ_ID[7:0] and to the DMAMXUX mapping implementation
section).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COF3 COF2 COF1 COF0
w w w w

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 COF[3:0]: Clear trigger overrun event flag
Writing 1 in each bit clears the corresponding overrun flag OFx in the DMAMUX_RGSR
register.

526/2194 RM0438 Rev 7

RM0438 DMA request multiplexer (DMAMUX)

15.6.7 DMAMUX register map

The following table summarizes the DMAMUX registers and reset values. Refer to the
register boundary address table for the DMAMUX register base address.

Table 103. DMAMUX register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C0CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x000
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C1CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x004
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C2CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x008
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
DMAMUX_C3CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C4CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE
DMAMUX_C5CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C6CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C7CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x01C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C8CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]

DMAMUX_C9CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

SE

0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C10CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C11CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C12CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x030
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C13CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C14CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPOL

SOIE
EGE
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
[1:0]
SE

DMAMUX_C15CR SYNC_ID[4:0] NBREQ[4:0] DMAREQ_ID[6:0]

0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x040 -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x07C

RM0438 Rev 7 527/2194

528
 0x144
0x140
0x108
0x104
0x100
0x084
0x080

0x13C
0x10C

0x3FC
0x0FC

0x110 -
Offset

0x148 -
0x088 -

528/2194
Reserved
Reserved
Reserved
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
DMAMUX_CSR

DMAMUX_CCFR

DMAMUX_RGSR
DMAMUX_RG3CR
DMAMUX_RG2CR
DMAMUX_RG1CR
DMAMUX_RG0CR

DMAMUX_RGCFR
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
DMA request multiplexer (DMAMUX)

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 20

GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]
GNBREQ[4:0]

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0

Res. Res. Res. Res. GPOL GPOL GPOL GPOL Res. Res. Res. 18

RM0438 Rev 7
[1:0] [1:0] [1:0]

0
0
0
0

Res. Res. Res. Res. [1:0] Res. Res. Res. 17

0
0
0
0

Res. Res. Res. Res. GE GE GE GE Res. Res. Res. 16

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF15 SOF15 15
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF14 SOF14 14
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF13 SOF13 13
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF12 SOF12 12
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF11 SOF11 11
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF10 SOF10 10
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF9 SOF9 9

Refer to Section 2.3 on page 87 for the register boundary addresses.

0
0
0
0
0
0

Res. Res. Res. Res. OIE OIE OIE OIE Res. CSOF8 SOF8 8
Table 103. DMAMUX register map and reset values (continued)

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF7 SOF7 7
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF6 SOF6 6
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CSOF5 SOF5 5
0
0
0
0
0
0

Res. Res. Res. Res. Res. CSOF4 SOF4 4

0
0
0
0
0
0

0
0

Res. COF3 OF3 Res. Res. CSOF3 SOF3 3

0
0
0
0
0
0

0
0

Res. COF2 OF2 Res. Res. CSOF2 SOF2 2

0
0
0
0
0
0

0
0

Res. COF1 OF1 Res. Res. CSOF1 SOF1 1

SIG_ID[4:0]
SIG_ID[4:0]
SIG_ID[4:0]
SIG_ID[4:0]

0
0
0
0
0
0

0
0

Res. COF0 OF0 Res. Res. CSOF0 SOF0 0

RM0438
RM0438 Nested vectored interrupt controller (NVIC)

16 Nested vectored interrupt controller (NVIC)

16.1 NVIC main features

• 109 maskable interrupt channels (not including the 16 Cortex®-M33 with FPU interrupt
lines)
• 8 programmable priority levels (3 bits of interrupt priority are used)
• Low-latency exception and interrupt handling
• Power management control
• Implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
The NVIC registers are banked across secure and non-secure states.
All interrupts including the core exceptions are managed by the NVIC.

16.2 SysTick calibration value register

The Cortex®-M33 with TrustZone mainline security extension embeds two SysTick timers.
When TrustZone is activated, two SysTick timer are available:
• SysTick, secure instance.
• SysTick, non-secure instance.
When TrustZone is disabeld, only one SysTick timer is available.
The SysTick timer calibration value (STCALIB) is 0x3E8. It gives a reference time base of
1 ms based on a SysTick clock frequency of 1 MHz. In order to match the 1 ms time base
for an application Running at a given frequency, the SysTick reload value must be
programmed as follows in the SYST_RVR register:
• SysTick clock source is CPU clock HCLK: reload value = (HCLK x STCALIB)-1
• SysTick clock source is external clock (HCLK/8): reload value =
((HCLK/8) x STCALIB)-1
The HCLK refers to AHB frequency value in MHz.
Example: SysTick clock source is CPU clock HCLK of 100 MHz, to match a time base of
1 ms:
• SysTick reload value = (100 x STCALIB) -1 = 0x1869F

RM0438 Rev 7 529/2194

563
Nested vectored interrupt controller (NVIC) RM0438

16.3 Interrupt and exception vectors

The grey rows in Table 104 describe the vectors without specific position.

Table 104. STM32L552xx and STM32L562xx vector table

Position

Priority

Type of
Acronym Description Address
priority

- - - - Reserved 0x0000 0000

- -4 Fixed Reset Reset 0x0000 0004
Non maskable interrupt. SRAM parity err +
- -2 Fixed NMI 0x0000 0008
FLASH ECC err + HSE CSS
-3 or
- Fixed Secure HardFault Secure hard fault 0x0000 000C
-1
Non-secure
- -1 Fixed Non-secure hard fault. All classes of fault 0x0000 000C
HardFault
- 0 Settable MemManage Memory management 0x0000 0010
- 1 Settable BusFault Pre-fetch fault, memory access fault 0x0000 0014
- 2 Settable UsageFault Undefined instruction or illegal state 0x0000 0018
- 3 Settable SecureFault Secure fault 0x0000 001C
0x0000 0020 -
- - - - Reserved
0x0000 0028
- 4 - SVC System service call via SWI instruction 0x0000 002C
- 5 - Debug Monitor Debug monitor 0x0000 0030
- - - - Reserved 0x0000 0034
- 6 Settable PendSV Pendable request for system service 0x0000 0038
- 7 Settable SysTick System tick timer 0x0000 003C
0 8 Settable WWDG Window watchdog interrupt 0x0000 0040
PVD/PVM1/PVM2/PVM3/PVM4 through EXTI
1 9 Settable PDV_PVM 0x0000 0044
lines 16/35/36/37/38 interrupts
2 10 Settable RTC RTC global interrupts (EXTI line 17) 0x0000 0048
3 11 Settable RTC_S RTC secure global interrupts (EXTI line 18) 0x0000 004C
4 12 Settable TAMP Tamper global interrupt (EXTI line 19) 0x0000 0050
5 13 Settable TAMP_S Tamper secure global interrupt (EXTI line 20) 0x0000 0054
6 14 Settable FLASH Flash memory global interrupt 0x0000 0058
7 15 Settable FLASH_S Flash memory secure global interrupt 0x0000 005C
8 16 Settable GTZC TZIC secure global interrupt 0x0000 0060
9 17 Settable RCC RCC global interrupt 0x0000 0064
10 18 Settable RCC_S RCC secure global interrupt 0x0000 0068

530/2194 RM0438 Rev 7

RM0438 Nested vectored interrupt controller (NVIC)

Table 104. STM32L552xx and STM32L562xx vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

11 19 Settable EXTI0 EXTI Line0 interrupt 0x0000 006C

12 20 Settable EXTI1 EXTI Line1 interrupt 0x0000 0070
13 21 Settable EXTI2 EXTI Line2 interrupt 0x0000 0074
14 22 Settable EXTI3 EXTI Line3 interrupt 0x0000 0078
15 23 Settable EXTI4 EXTI Line4 interrupt 0x0000 007C
16 24 Settable EXTI5 EXTI Line5 interrupt 0x0000 0080
17 25 Settable EXTI6 EXTI Line6 interrupt 0x0000 0084
18 26 Settable EXTI7 EXTI Line7 interrupt 0x0000 0088
19 27 Settable EXTI8 EXTI Line8 interrupt 0x0000 008C
20 28 Settable EXTI9 EXTI Line9 interrupt 0x0000 0090
21 29 Settable EXTI10 EXTI Line10 interrupt 0x0000 0094
22 30 Settable EXTI11 EXTI Line11 interrupt 0x0000 0098
23 31 Settable EXTI12 EXTI Line12 interrupt 0x0000 009C
24 32 Settable EXTI13 EXTI Line13 interrupt 0x0000 00E4
25 33 Settable EXTI14 EXTI Line14 interrupt 0x0000 00A0
26 34 Settable EXTI15 EXTI Line15 interrupt 0x0000 00A4
27 35 Settable DMAMUX1_OVR DMAMUX1 overRun interrupt 0x0000 00A8
28 36 Settable DMAMUX1_OVR_S DMAMUX1 secure overRun interrupt 0x0000 00AC
29 37 Settable DMA1_CH1 DMA1 channel 1 interrupt 0x0000 00B0
30 38 Settable DMA1_CH2 DMA1 channel 2 interrupt 0x0000 00B4
31 39 Settable DMA1_CH3 DMA1 channel 3 interrupt 0x0000 00B8
32 40 Settable DMA1_CH4 DMA1 channel 4 interrupt 0x0000 00C0
33 41 Settable DMA1_CH5 DMA1 channel 5 interrupt 0x0000 00C4
34 42 Settable DMA1_CH6 DMA1 channel 6 interrupt 0x0000 00C8
35 43 Settable DMA1_CH7 DMA1 channel 7 interrupt 0x0000 00CC
36 44 Settable DMA1_CH8 DMA1 channel 8 interrupt 0x0000 00D0
37 45 Settable ADC1_2 ADC1_2 global interrupt 0x0000 00D4
38 46 Settable DAC DAC global interrupt 0x0000 00D8
39 47 Settable FDCAN1_IT0 FDCAN1 Interrupt 0 0x0000 00DC
40 48 Settable FDCAN1_IT1 FDCAN1 Interrupt 1 0x0000 00E0
41 49 Settable TIM1_BRK TIM1 break 0x0000 00E4
42 50 Settable TIM1_UP TIM1 update 0x0000 00E8
43 51 Settable TIM1_TRG_COM TIM1 trigger and commutation 0x0000 00EC

RM0438 Rev 7 531/2194

563
Nested vectored interrupt controller (NVIC) RM0438

Table 104. STM32L552xx and STM32L562xx vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

44 52 Settable TIM1_CC TIM1 capture compare interrupt 0x0000 00F0

45 53 Settable TIM2 TIM2 global interrupt 0x0000 00F4
46 54 Settable TIM2 TIM3 global interrupt 0x0000 00F8
47 55 Settable TIM2 TIM4 global interrupt 0x0000 00FC
48 56 Settable TIM2 TIM5 global interrupt 0x0000 0100
49 57 Settable TIM2 TIM6 global interrupt 0x0000 0104
50 58 Settable TIM2 TIM7 global interrupt 0x0000 0108
51 59 Settable TIM8_BRK TIM8 break interrupt 0x0000 010C
52 60 Settable TIM8_UP TIM8 update interrupt 0x0000 0110
53 61 Settable TIM8_TRG_COM TIM8 trigger and commutation interrupt 0x0000 0114
54 62 Settable TIM8_CC TIM8 capture compare interrupt 0x0000 0118
55 63 Settable I2C1_EV I2C1 event interrupt 0x0000 011C
56 64 Settable I2C1_ER I2C1 error interrupt 0x0000 0120
57 65 Settable I2C2_EV I2C2 event interrupt 0x0000 0124
58 66 Settable I2C2_ER I2C2 error interrupt 0x0000 0128
59 67 Settable SPI1 SPI1 global interrupt 0x0000 012C
60 68 Settable SPI2 SPI2 global interrupt 0x0000 0130
61 69 Settable USART1 USART1 global interrupt 0x0000 0134
62 70 Settable USART2 USART2 global interrupt 0x0000 0138
63 71 Settable USART3 USART3 global interrupt 0x0000 013C
64 72 Settable UART4 UART4 global interrupt 0x0000 0140
65 73 Settable UART5 UART5 global interrupt 0x0000 0144
66 74 Settable LPUART1 LPUART1 global interrupt 0x0000 0148
67 75 Settable LPTIM1 LPTIM1 global interrupt 0x0000 014C
68 76 Settable LPTIM2 LPTIM2 global interrupt 0x0000 0150
69 77 Settable TIM15 TIM15 global interrupt 0x0000 0154
70 78 Settable TIM16 TIM16 global interrupt 0x0000 0158
71 79 Settable TIM17 TIM16 global interrupt 0x0000 015C
COMP1/COMP2 through EXTI lines 21/22
72 80 Settable COMP 0x0000 0160
interrupts
73 81 Settable USB_FS USB FS global interrupt 0x0000 0164
74 82 Settable CRS Clock recovery system global interrupt 0x0000 0168
75 83 Settable FMC FMC global interrupt 0x0000 016C

532/2194 RM0438 Rev 7

RM0438 Nested vectored interrupt controller (NVIC)

Table 104. STM32L552xx and STM32L562xx vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

76 84 Settable OCTOSPI1 OCTOSPI1 global interrupt 0x0000 0170

77 85 Settable - Reserved 0x0000 0174
78 86 Settable SDMMC1 SDMMC1 global interrupt 0x0000 0178
79 87 Settable - Reserved 0x0000 017C
80 88 Settable DMA2_CH1 DMA2 channel 1 interrupt 0x0000 0180
81 89 Settable DMA2_CH2 DMA2 channel 2 interrupt 0x0000 0184
82 90 Settable DMA2_CH3 DMA2 channel 3 interrupt 0x0000_0188
83 91 Settable DMA2_CH4 DMA2 channel 4 interrupt 0x0000 0174
84 92 Settable DMA2_CH5 DMA2 channel 5 interrupt 0x0000 0178
85 93 Settable DMA2_CH6 DMA2 channel 6 interrupt 0x0000 017C
86 94 Settable DMA2_CH7 DMA2 channel 7 interrupt 0x0000 0180
87 95 Settable DMA2_CH8 DMA2 channel 8 interrupt 0x0000 0184
88 96 Settable I2C3_EV I2C3 event interrupt 0x0000 0188
89 97 Settable I2C3_ER I2C3 error interrupt 0x0000 018C
90 98 Settable SAI1 SAI1 global interrupt 0x0000 0190
91 99 Settable SAI2 SAI2 global interrupt 0x0000 0194
92 100 Settable TSC TSC global interrupt 0x0000 0198
93 101 Settable AES AES global interrupt 0x0000 019C
94 102 Settable RNG RNG global interrupt 0x0000 01A0
95 103 Settable FPU Floating point interrupt 0x0000 01A4
96 104 Settable HASH HASH interrupt 0x0000 01A8
97 105 Settable PKA PKA global interrupt 0x0000 01AC
98 106 Settable LPTIM3 LPTIM3 global interrupt 0x0000 01A0
99 107 Settable SPI3 SPI3 global interrupt 0x0000 01A4
100 108 Settable I2C4_ER I2C4 error interrupt 0x0000 01A8
101 109 Settable I2C4_EV I2C4 event interrupt 0x0000 01AC
102 110 Settable DFSDM1_FLT0 DFSDM1 filter 0 global interrupt 0x0000 01B0
103 111 Settable DFSDM1_FLT1 DFSDM1 filter 0 global interrupt 0x0000 01B4
104 112 Settable DFSDM1_FLT2 DFSDM1 filter 0 global interrupt 0x0000 01B8
105 113 Settable DFSDM1_FLT3 DFSDM1 filter 0 global interrupt 0x0000 01BC
106 114 Settable UCPD1 UCPD1 global interrupt 0x0000 01C0
107 115 Settable ICACHE Instruction cache global interrupt 0x0000 01C4
108 116 Settable OTFDEC1 OTFDEC1 secure global interrupt 0x0000 01C8

RM0438 Rev 7 533/2194

563
Extended interrupts and event controller (EXTI) RM0438

17 Extended interrupts and event controller (EXTI)

The extended interrupts and event controller (EXTI) manages the individual CPU and
system wakeup through configurable and direct event inputs. It provides wakeup requests to
the power control, and generates an interrupt request to the CPU NVIC and events to the
CPU event input. For the CPU an additional event generation block (EVG) is needed to
generate the CPU event signal.
The EXTI wakeup requests allow the system to be woken up from Stop modes.
The interrupt request and event request generation can be used also in Run modes.
The EXTI also includes the EXTI mux IOport selection.

17.1 EXTI main features

The EXTI main features are the following:
• 43 input events supported.
• All event inputs allow the possibility to wake up the system.
• Events which do not have an associated wakeup flag in the peripheral, have a flag in
the EXTI and generate an interrupt to the CPU from the EXTI.
• Events can be used to generate a CPU wakeup event.
The asynchronous event inputs are classified in two groups:
• Configurable events (signals from I/Os or peripherals able to generate a pulse).
The configurable events have the following features:
– Selectable active trigger edge
– Interrupt pending status register bits independent for the rising and falling edge
– Individual interrupt and event generation mask, used for conditioning the CPU
wakeup, interrupt and event generation
– SW trigger possibility
• Direct events (interrupt and wakeup sources from peripherals having an associated
flag which requires to be cleared in the peripheral).
The direct events have the following features:
– Fixed rising edge active trigger
– No interrupt pending status register bit in the EXTI. (The interrupt pending status
flag is provided by the peripheral generating the event.)
– Individual interrupt and event generation mask, used for conditioning the CPU
wakeup and event generation
– No SW trigger possibility
• Secure events
– The access to control and configuration bits of secure input events can be made
secure and or privilege.
• EXTI IO port selection.

534/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

17.2 EXTI block diagram

The EXTI consists of a register block accessed via an AHB interface, the event input trigger
block, the masking block, and EXTI mux as shown in Figure 47.
The register block contains all the EXTI registers.
The event input trigger block provides event input edge trigger logic.
The masking block provides the event input distribution to the different wakeup, interrupt
and event outputs, and their masking.
The EXTI mux provides the IO port selection on to the EXTI event signal.

Figure 47. EXTI block diagram

AHB interface exti_ilac

Registers
hclk
exti[15:0]
To interconnect
EXTImux
GPIO

IOPort sys_wakeup
c_wakeup PWR
Configurable event(15:0)
it_exti_per(y)*
Direct event(x)
orconfigurable event(y)
Event
Peripherals

Wakeup
c_evt_exti c_event
Trigger events Masking Pulse rxev
c_evt_rst
c_fclk nvic(x) CPU
Interrupt Direct event(x) EVG nvic(y)

EXTI
* it_exti_per(y) are only available for configurable events (y)
MSv49347V1

Table 105. EXTI pin overview

Pin name I/O Description

EXTI register bus interface. When one event is configured to enable

AHB interface I/O
security, the AHB interface supports secure accesses
hclk I AHB bus clock and EXTI system clock
Configurable Asynchronous wakeup events from peripherals which do not have an
I
event(y) associated interrupt and flag in the peripheral
exti_ilac O Illegal access event
Synchronous and asynchronous wakeup events from peripherals which
Direct event(x) I
have an associated interrupt and flag in the peripheral
IOPort(n) I GPIOs block IO ports[15:0]
exti[15:0] O EXTI GPIO output port to trigger other IPs
it_exti_per (y) O Interrupts to the CPU associated with Configurable event (y)
c_evt_exti O High level sensitive event output for CPU synchronous to hclk

RM0438 Rev 7 535/2194

563
Extended interrupts and event controller (EXTI) RM0438

Table 105. EXTI pin overview (continued)

Pin name I/O Description

c_evt_rst I Asynchronous reset input to clear c_evt_exti

sys_wakeup O Asynchronous system wakeup request to PWR for ck_sys and hclk
c_wakeup O Wakeup request to PWR for CPU, synchronous to hclk

Table 106. EVG pin overview

Pin name I/O Description

c_fclk I CPU free Running clock

c_evt_in I High level sensitive events input from EXTI, asynchronous to CPU clock
c_event O Event pulse, synchronous to CPU clock
c_evt_rst O Event reset signal, synchronous to CPU clock

17.2.1 EXTI connections between peripherals and CPU

The peripherals able to generate wakeup or interrupt events when the system is in Stop
mode are connected to the EXTI.
• Peripheral wakeup signals which generate a pulse or which do not have an interrupt
status bits in the peripheral, are connected to an EXTI configurable event input. For
these events the EXTI provides a status pending bit which requires to be cleared. It is
the EXTI interrupt associated with the status bit that will interrupt the CPU.
• Peripheral interrupt and wakeup signals that have a status bit in the peripheral which
requires to be cleared in the peripheral, are connected to an EXTI direct event input.
There is no status pending bit within the EXTI. The interrupt or wakeup is cleared by
the CPU in the peripheral. It is the peripheral interrupt that interrupts the CPU directly.
• All GPIO ports input to the EXTI multiplexer, allowing the selection of a port pin to wake
up the system via a configurable event.
The EXTI configurable event interrupts are connected to the NVIC of the CPU.
The dedicated EXTI/EVG CPU event is connected to the CPU rxev input.
The EXTI CPU wakeup signals are connected to the PWR block, and are used to wake up
the system and CPU sub-system bus clocks.

17.2.2 EXTI interrupt/event mapping

The EXTI lines are connected as shown in Table 107: EXTI line connections.

Table 107. EXTI line connections

EXTI line Line source Line type

0-15 GPIO Configurable

16 PVD output Configurable
17 RTC Direct
18 RTC secure Direct
19 TAMP Direct

536/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Table 107. EXTI line connections (continued)

EXTI line Line source Line type

20 TAMP secure Direct

21 COMP1 output Configurable
22 COMP2 output Configurable
23 I2C1 wakeup Direct
24 I2C2 wakeup Direct
25 I2C3 wakeup Direct
26 USART1 wakeup Direct
27 USART2 wakeup Direct
28 USART3 wakeup Direct
29 USART4 wakeup Direct
30 USART5 wakeup Direct
31 LPUART1 wakeup Direct
32 LPTIM1 Direct
33 LPTIM2 Direct
34 USB FS wakeup Direct
35 PVM1 wakeup Configurable
36 PVM2 wakeup Configurable
37 PVM3 wakeup Configurable
38 PVM4 wakeup Configurable
39 reserved Direct
40 I2C4 wakeup Direct
41 UCPD1 wakeup Direct
42 LPTIM3 wakeup Direct

RM0438 Rev 7 537/2194

563
Extended interrupts and event controller (EXTI) RM0438

17.3 EXTI functional description

Depending on the EXTI event input type and wakeup target(s), different logic
implementations are used. The applicable features are controlled from register bits:
• Active trigger edge enable, by rising edge selection
EXTI rising trigger selection register (EXTI_RTSR1),
EXTI rising trigger selection register (EXTI_RTSR2),
and falling edge selection
EXTI falling trigger selection register (EXTI_FTSR1),
EXTI falling trigger selection register (EXTI_FTSR2).
• Software trigger, by
EXTI software interrupt event register (EXTI_SWIER1),
EXTI software interrupt event register (EXTI_SWIER2).
• Interrupt pending flag, by
EXTI rising edge pending register (EXTI_RPR1),
EXTI falling edge pending register (EXTI_FPR1),
EXTI rising edge pending register (EXTI_RPR2),
EXTI falling edge pending register (EXTI_FPR2).
• CPU wakeup and interrupt enable, by
EXTI CPU wakeup with interrupt mask register (EXTI_IMR1),
EXTI CPU wakeup with interrupt mask register (EXTI_IMR2).
• CPU wakeup and event enable, by
EXTI CPU wakeup with interrupt mask register (EXTI_IMR1),
EXTI CPU wakeup with event mask register (EXTI_EMR2).

Table 108. EXTI event input configurations and register control

EXTI_SWIER

EXTI_EMR(1)
EXTI_R/FPR
EXTI_RTSR

EXTI_FTSR

EXTI_IMR
Event input
Logic implementation
type

Configurable Configurable event input wakeup logic x x x x x x

Direct Direct event input wakeup logic - - - - x x
1. Only for input events with configuration “rxev generation” enabled.

17.3.1 EXTI configurable event input wakeup

Figure 48 is a detailed representation of the logic associated with configurable event inputs
which wakeup the CPU sub-system bus clocks and generated an EXTI pending flag and
interrupt to the CPU and or a CPU wakeup event.

538/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Figure 48. Configurable event trigger logic CPU wakeup

AHB Peripheral interface

interface Falling Rising Software CPU CPU
interrupt Pending
trigger trigger Event Interrupt request
selection selection event mask mask register
hclk register register register register register
it_exti_per(y)
hclk
Same circuit for Configurable
and Direct events EVG

Delay
Configurable Asynchronous Edge Rising Edge
detect Pulse ck_fclk_c
Event input(y) detection circuit hclk
generator
rst (1) c_evt_rst
CPU Event(y) Rising CPU
Rising Edge
c_event
Other CPU Events(x,y) Edge c_evt_exti
detect rst detect Pulse
generator
hclk

Synch
Other CPU Wakeups c_wakeup
CPU Wakeup(y)

Other Wakeups sys_wakeup

Wakeup(y)
EXTI
MS46537V1

1. Only for the input events that support CPU rxev generation c_event.
The software interrupt event register allows to trigger configurable events by software,
writing the corresponding register bit, irrespective of the edge selection setting.
The rising edge and falling edge selection registers allow the enabling and selection of the
configurable event active trigger edge or both edges.
The CPU has its dedicated wakeup (interrupt) mask register and a dedicated event mask
registers. The enabled event make it possible to generate an event on the CPU. All events
for a CPU are ordered together into a single CPU event signal. The event pending registers
(EXTI_RPR and EXTI_FPR) is not set for an unmasked CPU event.
The configurable events have unique interrupt pending request registers, shared by the
CPU. The pending register is only set for an unmasked interrupt. Each configurable event
provides a common interrupt to the CPU. The configurable event interrupts need to be
acknowledged by software in the EXTI_RPR and/or EXTI_FPR registers.
When a CPU wakeup (interrupt) or CPU event is enabled the asynchronous edge detection
circuit is reset by the clocked delay and rising edge detect pulse generator. This guarantees
that the EXTI hclk clock is woken up before the asynchronous edge detection circuit is reset.
Note: A detected configurable event interrupt pending request, may be cleared by any CPU with
the correct access permission. The system is not able to enter into low-power modes as
long as an interrupt pending request is active.

RM0438 Rev 7 539/2194

563
Extended interrupts and event controller (EXTI) RM0438

17.3.2 EXTI direct event input wakeup

Figure 49 is a detailed representation of the logic associated with direct event inputs waking
up the system.
The direct events do not have an associated EXTI interrupt. The EXTI only wakes up the
system and CPU sub-system clocks and may generate a CPU wakeup event. The
peripheral synchronous interrupt, associated with the direct wakeup event wakes up the
CPU.
The EXTI direct event is able to generate a CPU event. This CPU event wakes up the CPU.
The CPU event may occur before the associated peripheral interrupt flag is set.

Figure 49. Direct event trigger logic CPU wakeup

AHB interface Peripheral interface

hclk CPU CPU
Interrupt Event
Same circuit for Configurable
hclk
mask mask and Direct events EVG
register register ck_fclk_c
hclk
(1) Rising
c_evt_rst
CPU
Delay

CPU Event(x) c_event

Edge Rising Edge
Other CPU Events(x,y) detect c_evt_exti detect Pulse
rst
Direct generator
Event
Asynchronous
input(x) hclk
Rising Edge
detect circuit
Synch

rst CPU Wakeup(x) c_wakeup

Other CPU Wakeups

Falling Edge
detect sys_wakeup
Pulse Other Wakeups
generator Wakeup(x)

EXTI hclk

MS46536V1

1. Only for the input events that support CPU rxev generation c_event.

17.3.3 EXTI mux selection

The EXTI mux allow the selection of GPIOs as interrupts and wakeup. The GPIOs are
connected via 16 EXTI mux lines to the first 16 EXTI events as configurable event. The
selection of GPIO port as EXTI mux output, is controlled by registers: EXTI external interrupt
selection register (EXTI_EXTICRn).

540/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Figure 50. EXTI mux GPIO selection

EXTI_EXTICR1.EXTI0 EXTI_EXTICR1.EXTI1 EXTI_EXTICR4.EXTI15

PA0 PA1 PA15

PB0 PB1 PB15

PC0 PC1 PC15

EXTI0 EXTI1 EXTI15

Px0 Px1 Px15

MS44726V1

The EXTIs mux outputs are available as output signals from the EXTI to trigger other IPs.
The EXTI mux outputs are available independent from any masking in EXTI_IMRx and
EXTI_EMRx.

17.4 EXTI functional behavior

The direct event inputs are enabled in the respective peripheral generating the wakeup
event. The configurable events are enabled by enabling at least one of the trigger edges.
Once an event input is enabled, the generation of a CPU wakeup is conditioned by the CPU
interrupt mask and CPU event mask.

Table 109. Masking functionality

Configurable
CPU interrupt
CPU event enable event inputs exti(n) CPU
enable CPU wakeup
EXTI_EMR.EMn EXTI_RPR.RPIFn interrupt(1) event
EXTI_IMR.IMn
EXTI_FPR.FPIFn

0 no masked masked masked

0
1 no masked yes yes
0 status latched yes masked yes(2)
1
1 status latched yes yes yes
1. The single exti(n) interrupt will go to the CPU. If no interrupt is required for CPU, the exti(n) interrupt shall be masked in the
CPU NVIC.
2. Only if CPU interrupt is enabled in EXTI_IMR.IMn.

For configurable event inputs, when the enabled edge(s) occur on the event input, an event
request is generated. When the associated CPU interrupt is unmasked the corresponding
pending bit EXTI_RPR.RPIFn and/or EXTI_FPR.FPIFn is/are set and the CPU sub-system
is woken up and CPU interrupt signal is activated. The EXTI_RPR.RPIFn and/or
EXTI_FPR.FPIFn pending bit shall be cleared by software writing it to ‘1’. This action clears
the CPU interrupt.
For direct event inputs, when enabled in the associated peripheral, an event request is
generated on the rising edge only. There is no corresponding CPU pending bit in the EXTI.

RM0438 Rev 7 541/2194

563
Extended interrupts and event controller (EXTI) RM0438

When the associated CPU interrupt is unmasked, the corresponding CPU sub-system is
woken up. The CPU is woken up (interrupted) by the peripheral synchronous interrupt.
The CPU event has to be unmasked to generate an event. When the enabled edge(s) occur
on the event input a CPU event pulse is generated. There is no event pending bit.
For the configurable event inputs an event request can be generated by software when
writing a ‘1’ in the software interrupt/event register EXTI_SWIER, allowing the generation of
a rising edge on the event. The rising edge event pending bit is set in EXTI_RPR,
irrespective of the setting in EXTI_RTSR.

17.5 EXTI event protection

The EXTI is able to protect event register bits from being modified by non-secure and
unprivileged accesses. The protection can individually be activated per input event via the
register bits in EXTI_SECCFGR and EXTI_PRIVCFGR. At EXTI level the protection
consists in preventing unauthorized write access to:
• Change the settings of the secure and/or privileged configurable events.
• Change the masking of the secure and/or privileged input events.
• Clear pending status of the secure and/or privileged input events.

Table 110. Register protection overview

Register name Access type Protection(1)(2)

EXTI_RTSR RW
EXTI_FTSR RW
Security and privilege can be bit wise enabled in
EXTI_SWIER RW
EXTI_SECCFGR and EXTI_PRIVCFGR
EXTI_RPR RW
EXTI_FPR RW

EXTI_SECCFGR RW Always secure, and privilege can be bit wise enabled in

EXTI_PRIVCFGR
Always privilege, and security can be bit wise enabled in
EXTI_PRIVCFGR RW
EXTI_SECCFGR
Security and privilege can be bit wise enabled in
EXTI_EXTICRn RW
EXTI_SECCFGR and EXTI_PRIVCFGR
EXTI_LOCKR RW Always secure.
EXTI_IM RW Security and privilege can be bit wise enabled in
RW EXTI_SECCFGR and EXTI_PRIVCFGR
EXTI_EMR
1. Security is enabled with the individual Input event. EXTI_SECCFG registers.
2. Privilege is enabled with the individual Input event EXTI_PRIVCFGRn registers.

17.5.1 EXTI security protection

When security is enabled for an input event, the associated input event configuration and
control bits can only be modified and read by a secure access, a non-secure write access is
discarded and a read returns 0.

542/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

When input events are non-secure, the security is disabled. The associated input event
configuration and control bits can be modified and read by a secure access and non-secure
access.
The security configuration in registers EXTI_SECCFGR can be globally locked after reset
by EXTI_LOCKR.LOCK.

17.5.2 EXTI privilege protection

When privilege is enabled for an input event, the associated input event configuration and
control bits can only be modified and read by a privilege access, an unprivileged write
access is discarded and a read returns 0.
When input events are unprivileged, the privilege is disabled. The associated input event
configuration and control bits can be modified and read by a privilege access and
unprivileged access.
The privilege configuration in registers EXTI_PRIVCFGRn can be globally locked after reset
by EXTI_LOCKR.LOCK.

RM0438 Rev 7 543/2194

563
Extended interrupts and event controller (EXTI) RM0438

17.6 EXTI registers

The EXTI register map is divided in the following sections:

Table 111. EXTI register map sections

Address offset Description

0x000 - 0x01C General configurable event [31:0] configuration

0x020 - 0x03C General configurable event [63:32] configuration
0x060 - 0x06C EXTI IOport mux selection
0x070 EXTI protection lock configuration
0x080 - 0x0BC CPU input event configuration

All the registers can be accessed with word (32-bit), half-word (16-bit) and byte (8-bit)
access.

17.6.1 EXTI rising trigger selection register (EXTI_RTSR1)

Address offset: 0x000
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 Res. Res. Res. Res. RT16

rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

544/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Bits 22:21 RT[22:21]: Rising trigger event configuration bit of configurable event input x(1) (where x = 18
to 22)
When SECx is disabled, RTx can be accessed with non-secure and secure access.
When SECx is enabled, RTx can only be accessed with secure access. Non-secure write to
this bit x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGRn.PRIVx is disabled, RTx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGRn.PRIVx is enabled, RTx can only be accessed with privilege access.
Unprivileged write to this bit x is discarded, unprivileged read returns 0.
0: Rising trigger disabled (for event and Interrupt) for input line
1: Rising trigger enabled (for event and Interrupt) for input line
Bits 20:17 Reserved, must be kept at reset value.
Bits 16:0 RT[16:0]: Rising trigger event configuration bit of configurable event input x(1) (where x = 0 to
16)
When EXTI_SECCFGR SECx is disabled, RTx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR SECx is enabled, RTx can only be accessed with secure access. Non-
secure write to this bit x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR PRIVx is disabled, RTx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR PRIVx is enabled, RTx can only be accessed with privilege access.
Unprivileged write to this bit x is discarded, unprivileged read returns 0.
0: Rising trigger disabled (for event and Interrupt) for input line
1: Rising trigger enabled (for event and Interrupt) for input line
1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a rising edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a
trigger.

17.6.2 EXTI falling trigger selection register (EXTI_FTSR1)

Address offset: 0x004
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 Res. Res. Res. Res. FT16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 545/2194

563
Extended interrupts and event controller (EXTI) RM0438

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 FT[22:21]: Falling trigger event configuration bit of configurable event input x (1) (where x = 18
to 22).
When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-
secure write to this FTx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privilege access.
Unprivileged write to this FTx is discarded, unprivileged read returns 0.
0: Falling trigger disabled (for event and Interrupt) for input line
1: Falling trigger enabled (for event and Interrupt) for input line.
Bit 20:17 Reserved, must be kept at reset value.
Bits 16:0 FT[16:0]: Falling trigger event configuration bit of configurable event input x (1) (where x = 0 to
16).
When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-
secure write to this FTx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privilege access.
Unprivileged write to this FTx is discarded, unprivileged read returns 0.
0: Falling trigger disabled (for event and Interrupt) for input line
1: Falling trigger enabled (for event and Interrupt) for input line.
1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a
trigger.

17.6.3 EXTI software interrupt event register (EXTI_SWIER1)

Address offset: 0x008
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI22 SWI21 Res. Res. Res. Res. SWI16
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

546/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 SWI[22:21]: Software interrupt on event x (where x = 18 to 22)
When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access.
Non-secure write to this SWI x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privilege access.
Unprivileged write to this SWIx is discarded, unprivileged read returns 0.
A software interrupt is generated independent from the setting in EXTI_RTSR and
EXTI_FTSR. It always returns 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit triggers a rising edge event on event x. This bit is auto cleared by
HW.
Bit 20:17 Reserved, must be kept at reset value.
Bits 16:0 SWI[16:0]: Software interrupt on event x (where x = 18 to 22)
When EXTI_SECFGR.SECx is disabled, SWIx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access.
Non-secure write to this SWI x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privilege access.
Unprivileged write to this SWIx is discarded, unprivileged read returns 0.
A software interrupt is generated independent from the setting in EXTI_RTSR and
EXTI_FTSR. It always returns 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit triggers a rising edge event on event x. This bit is auto cleared by
HW.

17.6.4 EXTI rising edge pending register (EXTI_RPR1)

Address offset: 0x00C
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. RPIF22 RPIF21 Res. Res. Res. Res. RPIF16
rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RPIF15 RPIF14 RPIF13 RPIF12 RPIF11 RPIF10 RPIF9 RPIF8 RPIF7 RPIF6 RPIF5 RPIF4 RPIF3 RPIF2 RPIF1 RPIF0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

RM0438 Rev 7 547/2194

563
Extended interrupts and event controller (EXTI) RM0438

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 RPIF[22:21]: configurable event inputs x rising edge pending bit (where x = 18 to 22).
When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access.
Non-secure write to this RPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privilege access.
Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred
This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the
configurable event line. This bit is cleared by writing a 1 into the bit.
Bit 20:17 Reserved, must be kept at reset value.
Bits 16:0 RPIF[16:0]: configurable event inputs x rising edge pending bit (where x = 0 to 16).
When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access.
Non-secure write to this RPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RPIFx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privilege access.
Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred
This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the
configurable event line. This bit is cleared by writing a 1 into the bit.

17.6.5 EXTI falling edge pending register (EXTI_FPR1)

Address offset: 0x010
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. FPIF22 FPIF21 Res. Res. Res. Res. FPIF16
rc_w1 rc_w1 rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FPIF15 FPIF14 FPIF13 FPIF12 FPIF11 FPIF10 FPIF9 FPIF8 FPIF7 FPIF6 FPIF5 FPIF4 FPIF3 FPIF2 FPIF1 FPIF0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

548/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:21 FPIF[22:21]: configurable event inputs x falling edge pending bit (where x = 22 to 18)
When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access.
Non-secure write to this FPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privilege access.
Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.
0: No falling edge trigger request occurred
1: Rising edge trigger request occurred
This bit is set when the falling edge event arrives on the configurable event line. This bit is
cleared by writing a 1 into the bit.
Bit 20:17 Reserved, must be kept at reset value.
Bits 16:0 FPIF[16:0]: configurable event inputs x falling edge pending bit (where x = 0 to 16)
When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access.
Non-secure write to this FPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privilege access.
Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.
0: No falling edge trigger request occurred
1: Rising edge trigger request occurred
This bit is set when the falling edge event arrives on the configurable event line. This bit is
cleared by writing a 1 into the bit.

17.6.6 EXTI security configuration register (EXTI_SECCFGR1)

Address offset: 0x014
Reset value: 0x0000 0000
This register provides write access security, a non-secure write access is ignored and
causes the generation of an illegal access event. A non-secure read returns the register
data.
Contains only register bits for security capable input events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SEC31 SEC30 SEC29 SEC28 SEC27 SEC26 SEC25 SEC24 SEC23 SEC22 SEC21 SEC20 SEC19 SEC18 SEC17 SEC16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 549/2194

563
Extended interrupts and event controller (EXTI) RM0438

Bits 31:0 SEC[31:0]: Security enable on event input x (where x = 0 to 31)

When EXTI_PRIVCFGRn.PRIVx is disabled, SECx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGRn.PRIVx is enabled, SECx can only be written with privilege access.
Unprivileged write to this SECx is discarded.
0: Event security disabled (non-secure)
1: Event security enabled (secure)

17.6.7 EXTI privilege configuration register (EXTI_PRIVCFGR1)

Address offset: 0x018
Reset value: 0x0000 0000
This register provides privileged write access protection. An unprivileged read returns the
register data.
Contains only register bits for security capable input events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PRIV31 PRIV30 PRIV29 PRIV28 PRIV27 PRIV26 PRIV25 PRIV24 PRIV23 PRIV22 PRIV21 PRIV20 PRIV19 PRIV18 PRIV17 PRIV16
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRIV15 PRIV14 PRIV13 PRIV12 PRIV11 PRIV10 PRIV9 PRIV8 PRIV7 PRIV6 PRIV5 PRIV4 PRIV3 PRIV2 PRIV1 PRIV0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 PRIV[31:0]: Security enable on event input x (where x = 0 to 31)

When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-
secure access.
When EXTI_SECCFGR.SECx is enabled, PRIVx can only be written with secure access.
Non-secure write to this PRIVx is discarded.
0: Event privilege disabled (unprivileged)
1: Event privilege enabled (privileged)

17.6.8 EXTI rising trigger selection register (EXTI_RTSR2)

Address offset: 0x020
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. RT38 RT37 RT36 RT35 Res. Res. Res.

rw rw rw rw

550/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 RT[38:35]: Rising trigger event configuration bit of configurable event input x(1) (where x = 35
to 38).
When EXTI_SECCFGR.SECx is disabled, RTx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, RTx can only be accessed with secure access.
Non-secure write to this RTx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RTx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, RTx can only be accessed with privilege access.
Unprivileged write to this RTx is discarded, unprivileged read returns 0.
0: Rising trigger disabled (for event and interrupt) for input line
1: Rising trigger enabled (for event and interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.
1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs. If a falling edge on the
configurable event input occurs during writing of the register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a
trigger.

17.6.9 EXTI falling trigger selection register (EXTI_FTSR2)

Address offset: 0x024
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. FT38 FT37 FT36 FT35 Res. Res. Res.

rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 FT[38:35]: Falling trigger event configuration bit of configurable event input x(1) (where x = 35
to 38)
When EXTI_SECCFGR.SECx is disabled, FTx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, FTx can only be accessed with secure access. Non-
secure write to this FTx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, FTx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, FTx can only be accessed with privilege access.
Unprivileged write to this FTx is discarded, unprivileged read returns 0.
0: Falling trigger disabled (for event and interrupt) for input line
1: Falling trigger enabled (for event and interrupt) for input line
Bits 2:0 Reserved, must be kept at reset value.

RM0438 Rev 7 551/2194

563
Extended interrupts and event controller (EXTI) RM0438

1. The configurable event inputs are edge triggered, no glitch must be generated on these inputs.
If a falling edge on the configurable event input occurs during writing of the register, the associated pending bit is not set.
Rising and falling edge triggers can be set for the same configurable event input. In this case, both edges generate a
trigger.

17.6.10 EXTI software interrupt event register (EXTI_SWIER2)

Address offset: 0x028
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI38 SWI37 SWI36 SWI35 Res. Res. Res.

rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 SWI[38:35]: Software interrupt on event x (where x = 35 to 38)
When EXTI_SECCFGR.SECx is disabled, SWIx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, SWIx can only be accessed with secure access.
Non-secure write to this SWIx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, SWIx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, SWIx can only be accessed with privilege access.
Unprivileged write to this SWIx is discarded, unprivileged read returns 0.
A software interrupt is generated independent from the setting in EXTI_RTSR and
EXTI_FTSR. It always return 0 when read.
0: Writing 0 has no effect.
1: Writing a 1 to this bit triggers a rising edge event on event x+32. This bit is auto cleared by
HW.
Bits 2:0 Reserved, must be kept at reset value.

17.6.11 EXTI rising edge pending register (EXTI_RPR2)

Address offset: 0x02C
Reset value: 0x0000 0000
Contains only register bits for configurable events.

552/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. RPIF38 RPIF37 RPIF36 RPIF35 Res. Res. Res.

rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 RPIF[38:35]: configurable event inputs x rising edge pending bit (where x = 35 to 38).
When EXTI_SECCFGR.SECx is disabled, RPIFx can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SECx is enabled, RPIFx can only be accessed with secure access.
Non-secure write to this RPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, RPIF can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, RPIFx can only be accessed with privilege access.
Unprivileged write to this RPIFx is discarded, unprivileged read returns 0.
0: No rising edge trigger request occurred
1: Rising edge trigger request occurred
This bit is set when the rising edge event or an EXTI_SWIER software trigger arrives on the
configurable event line. This bit is cleared by writing a 1 into the bit.
Bits 2:0 Reserved, must be kept at reset value.

17.6.12 EXTI falling edge pending register (EXTI_FPR2)

Address offset: 0x030
Reset value: 0x0000 0000
Contains only register bits for configurable events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. FPIF38 FPIF37 FPIF36 FPIF35 Res. Res. Res.

rc_w1 rc_w1 rc_w1 rc_w1

RM0438 Rev 7 553/2194

563
Extended interrupts and event controller (EXTI) RM0438

Bits 31:7 Reserved, must be kept at reset value.

Bits 6:3 FPIF[38:35]: configurable event inputs x pending bit (where x = 35 to 38).
When EXTI_SECCFGR.SECx is disabled, FPIFx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, FPIFx can only be accessed with secure access.
Non-secure write to this FPIFx is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, FPIFx can be accessed with unprivileged and
privilege access.
When EXTI_PRIVCFGR.PRIVx is enabled, FPIFx can only be accessed with privilege access.
Unprivileged write to this FPIFx is discarded, unprivileged read returns 0.
0: No fallling edge trigger request occurred
1: Rising edge trigger request occurred
This bit is set when the falling edge event arrives on the configurable event line. This bit is
cleared by writing a 1 into the bit.
Bits 2:0 Reserved, must be kept at reset value.

17.6.13 EXTI security enable register (EXTI_SECCFGR2)

Address offset: 0x034
Reset value: 0x0000 0000
This register provides write access security, a non-secure write access is ignored and
causes the generation of an illegal access event. A non-secure read returns the register
data.
Contains only register bits for security capable Input events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. SEC42 SEC41 SEC40 SEC39 SEC38 SEC37 SEC36 SEC35 SEC34 SEC33 SEC32

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 SEC[42:32]: Security enable on event input x (where x = 32 to 42)
When EXTI_PRIVCFGRn.PRIVx is disabled, SECx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGRn.PRIVx is enabled, SECx can only be written with privilege access.
Unprivileged write to this SECx is discarded
0: Event security disabled (non-secure)
1: Event security enabled (secure)

17.6.14 EXTI privilege enable register (EXTI_PRIVCFGR2)

Address offset: 0x038
Reset value: 0x0000 0000

554/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

This register provides privileged write access protection, an unprivileged write access is
discarded and causes the generation of an illegal access event. An unprivileged read
returns the register data.
Contains only register bits for security capable Input events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. PRIV42 PRIV41 PRIV40 PRIV39 PRIV38 PRIV37 PRIV36 PRIV35 PRIV34 PRIV33 PRIV32

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 PRIV[42:32]: Privilege enable on event input x (where x = 32 to 42)
When EXTI_SECCFGR.SECx is disabled, PRIVx can be accessed with secure and non-
secure access.
When EXTI_SECCFGR.SECx is enabled, PRIVx can only be accessed with secure access.
Non-secure write to this PRIVx is discarded.
0: Event privilege disabled (unprivileged)
1: Event security enabled (privileged)

17.6.15 EXTI external interrupt selection register (EXTI_EXTICRn)

Address offset: 0x060 (EXTI_EXTICR1) EXTI mux 0, 1, 2, 3 (m =0)
Address offset: 0x064 (EXTI_EXTICR2) EXTI mux 4, 5, 6, 7 (m = 4)
Address offset: 0x068 (EXTI_EXTICR3) EXTI mux 8, 9, 10, 11 (m = 8)
Address offset: 0x06C (EXTI_EXTICR4) EXTI mux 12, 13, 14, 15 (m = 12)
Reset value: 0x0000 0000
EXTIm fields contain only the number of bits in line with the nb_ioport configuration.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXTIm+3[7:0] EXTIm+2[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTIm+1[7:0] EXTIm[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 555/2194

563
Extended interrupts and event controller (EXTI) RM0438

Bits 31:24 EXTIm+3[7:0]: EXTIm+3 GPIO port selection (where m = 0, 4, 8, or 12 for respectively
EXTI_EXTICR[1:4]).
These bits are written by software to select the source input for EXTIm+3 external interrupt.
When EXTI_SECCFGR.SEC(m+3) is disabled, EXTI(m+3) can be accessed with non-secure
and secure access.
When EXTI_SECCFGR.SEC(m+3) is enabled, EXTI(m+3) can only be accessed with secure
access. Non-secure write is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIV(m+3) is disabled, EXTI(m+3) can be accessed with privilege
and unprivileged access.
When EXTI_PRIVCFGR.PRIV(m+3) is enabled, EXTI(m+3) can only be accessed with
privilege access. Unprivileged write to this bit is discarded.
0x00: PA[m+3] pin
0x01: PB[m+3] pin
0x02: PC[m+3] pin
0x03: PD[m+3] pin
0x04: PE[m+3] pin
0x05: PF[m+3] pin
0x06: PG[m+3] pin
0x07: PH[m+3] pin
Others reserved

556/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Bits 23:1 EXTIm+2[7:0]: EXTIm+2 GPIO port selection (where m = 0, 4, 8, or 12 for respectively
EXTI_EXTICR[1:4])(where m = 0, 4, 8, or 12 for respectively EXTI_EXTICR[1:4]).
These bits are written by software to select the source input for EXTIm+2 external interrupt.
When EXTI_SECCFGR.SEC(m+2) is disabled, EXTI(m+2) can be accessed with non-secure
and secure access.
When EXTI_SECCFGR.SEC(m+2) is enabled, EXTI(m+2) can only be accessed with secure
access. Non-secure write is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIV(m+2) is disabled, EXTI(m+2) can be accessed with privilege
and unprivileged access.
When EXTI_PRIVCFGR.PRIV(m+2) is enabled, EXTI(m+2) can only be accessed with
privilege access. Unprivileged write to this bit is discarded.
0x00: PA[m+2] pin
0x01: PB[m+2] pin
0x02: PC[m+2] pin
0x03: PD[m+2] pin
0x04: PE[m+2] pin
0x05: PF[m+2] pin
0x06: PG[m+2] pin
0x07: PH[m+2] pin
Others reserved
Bits 15:8 EXTIm+1[7:0]: EXTIm+1 GPIO port selection (where m = 0, 4, 8, or 12 for respectively
EXTI_EXTICR[1:4]).
These bits are written by software to select the source input for EXTIm+1 external interrupt.
When EXTI_SECCFGR.SEC(m+1) is disabled, EXTI(m+1) can be accessed with non-secure
and secure access.
When EXTI_SECCFGR.SEC(m+1) is enabled, EXTI(m+1) can only be accessed with secure
access. Non-secure write is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVm+1 is disabled, EXTI(m+1) can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVm+1 is enabled, EXTI(m+1) can only be accessed with privilege
access. Unprivileged write to this bit is discarded.
0x00: PA[m+1] pin
0x01: PB[m+1] pin
0x02: PC[m+1] pin
0x03: PD[m+1] pin
0x04: PE[m+1] pin
0x05: PF[m+1] pin
0x06: PG[m+1] pin
0x07: PH[m+1] pin
Others reserved

RM0438 Rev 7 557/2194

563
Extended interrupts and event controller (EXTI) RM0438

Bits 7:0 EXTIm[7:0]: EXTIm GPIO port selection (where m = 0, 4, 8, or 12 for respectively
EXTI_EXTICR[1:4]).
These bits are written by software to select the source input for EXTIm external interrupt.
When EXTI_SECCFGR.SEC(m) is disabled, EXTI(m) can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SEC(m) is enabled, EXTI(m) can only be accessed with secure
access. Non-secure write is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIV(m) is disabled, EXTI(m) can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIV(m) is enabled, EXTI(m) can only be accessed with privilege
access. Unprivileged write to this bit is discarded
0x00: PA[m] pin
0x01: PB[m] pin
0x02: PC[m] pin
0x03: PD[m] pin
0x04: PE[m] pin
0x05: PF[m] pin
0x06: PG[m] pin
0x07: PH[m] pin
Others reserved

17.6.16 EXTI lock register (EXTI_LOCKR)

Address offset: 0x070
Reset value: 0x0000 0000
This register provides both write access security, a non-secure write access is ignored and a
read access returns zero data, and generate an illegal access event.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LOCK

rs

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 LOCK: Global security and privilege configuration registers EXTI_SECCFGR and
EXTI_PRIVCFGR lock.
This register bit is write once after reset.
0: Security and privilege configuration open, can be modified.
1: Security and privilege configuration locked, can no longer be modified.

17.6.17 EXTI CPU wakeup with interrupt mask register (EXTI_IMR1)

Address offset: 0x080
Reset value: 0xFF9E 0000

558/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

Contains register bits for configurable events and direct events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IM31 IM30 IM29 IM28 IM27 IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IM[31:0]: CPU wakeup with interrupt mask on event input x (1) (where x = 0 to 31).
When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-
secure write to this bit is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.
0: Wakeup with interrupt request from input event x is masked
1: Wakeup with interrupt request from input event x is unmasked
1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

17.6.18 EXTI CPU wakeup with event mask register (EXTI_EMR1)

Address offset: 0x084
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EM31 EM30 EM29 EM28 EM27 EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 EM18 EM17 EM16

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 EM[31:0]: CPU wakeup with event generation mask on event input x (where x = 0 to 31).
When EXTI_SECCFGR.SECENx is disabled, EMx can be accessed with non-secure and
secure access.
When EXTI_SECCFGR.SECENx is enabled, EMx can only be accessed with secure access.
Non-secure write to this bit x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.
0: Wakeup with event generation from Line x is masked
1: Wakeup with event generation from Line x is unmasked

RM0438 Rev 7 559/2194

563
Extended interrupts and event controller (EXTI) RM0438

17.6.19 EXTI CPU wakeup with interrupt mask register (EXTI_IMR2)

Address offset: 0x090
Reset value: 0x0000 0787
Contains register bits for configurable events and direct events.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. IM42 IM41 IM40 Res. IM38 IM37 IM36 IM35 IM34 IM33 IM32

rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 IM[42:40]: CPU wakeup with interrupt mask on event input x (1) (where x = 40 to 42).
When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-
secure write to this bit is discarded, non-secure read returns 0..
When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.
0: Wakeup with interrupt request from input event x is masked
1: Wakeup with interrupt request from input event x is unmasked
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 IM[38:32]: CPU wakeup with interrupt mask on event input x(1) (where x = 32 to 38).
When EXTI_SECCFGR.SECx is disabled, IMx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, IMx can only be accessed with secure access. Non-
secure write to this bit is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, IMx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, IMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.
0: Wakeup with interrupt request from input event x is masked
1: Wakeup with interrupt request from input event x is unmasked
1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

17.6.20 EXTI CPU wakeup with event mask register (EXTI_EMR2)

Address offset: 0x094
Reset value: 0x0000 0000

560/2194 RM0438 Rev 7

RM0438 Extended interrupts and event controller (EXTI)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. EM42 EM41 EM40 Res. EM38 EM37 EM36 EM35 EM34 EM33 EM32

rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:0 EM[42:40]: CPU wakeup with event generation mask on event input(1) (where x = 40 to 42).
When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access.
Non-secure write to this bit x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.
0: Wakeup with event generation from line x is masked
1: Wakeup with event generation from line x is unmasked
Bit 7 Reserved, must be kept at reset value.
Bits 6:0 EM[38:32]: CPU wakeup with event generation mask on event input x(1) (where x = 32 to 38).
When EXTI_SECCFGR.SECx is disabled, EMx can be accessed with non-secure and secure
access.
When EXTI_SECCFGR.SECx is enabled, EMx can only be accessed with secure access.
Non-secure write to this bit x is discarded, non-secure read returns 0.
When EXTI_PRIVCFGR.PRIVx is disabled, EMx can be accessed with privilege and
unprivileged access.
When EXTI_PRIVCFGR.PRIVx is enabled, EMx can only be accessed with privilege access.
Unprivileged write to this bit is discarded.
0: Wakeup with event generation from line x is masked
1: Wakeup with event generation from line x is unmasked
1. The reset value for configurable event inputs is set to ‘0’ in order to disable the interrupt by default.

17.6.21 EXTI register map

The following table gives the EXTI register map and the reset values.

Table 112. Extended interrupt/event controller register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
RT[22:21]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

EXTI_RTSR1 RT[16:0]
0x000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 561/2194

563
 0x034
0x014

0x038
0x030
0x028
0x024
0x020
0x018
0x010
0x008
0x004

0x02C
0x00C
Offset

562/2194
1
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

EXTI_FPR2
EXTI_FPR1

EXTI_RPR2
EXTI_RPR1

EXTI_FTSR2
EXTI_FTSR1

EXTI_RTSR2

EXTI_SWIER2
EXTI_SWIER1

EXTI_SECCFG2
EXTI_SECCFGR

EXTI_PRIVCFG2
EXTI_PRIVCFG1

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 22

FPIF[22:21] RPIF[22:21] SWI[22:21] FT[22:21]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 21

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
Extended interrupts and event controller (EXTI)

20

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 18

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

RM0438 Rev 7
17

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 15

SEC[31:0]

PRIV[31:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 14

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 13

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 12

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res. 10

0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res. 9
0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res. 8
FT[16:0]

0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res.
SWi[16:0]

FPIF[16:0]

7
RPIF[16:0]

0
0
0
0
0
0

0
0
0
0
0
0
0
6
0
0
0
0
0
0

0
0
0
0
0
0
0 5
FT
RT

SWI

FPIF
0
0
0
0
0
0

0
0
0
0
0
0
0

RPIF

[38:35]
[38:35]
[38:35]
[38:35]
[38:35]

SEC[42:32]

PRIV[42:32]
0
0
0
0
0
0

0
0
0
0
0
0
0

3
0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res. 2
Table 112. Extended interrupt/event controller register map and reset values (continued)

0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res. 1
0
0
0
0
0
0

0
0
Res. Res. Res. Res. Res. 0
RM0438
RM0438 Extended interrupts and event controller (EXTI)

Table 112. Extended interrupt/event controller register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EXTI_EXTICR1 EXTI3[7:0] EXTI2[7:0] EXTI1[7:0] EXTI0[7:0]
0x060

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR2 EXTI7[7:0] EXTI6[7:0] EXTI5[7:0] EXTI4[7:0]

0x064

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR3 EXTI11[7:0] EXTI10[7:0] EXTI9[7:0] EXTI8[7:0]

0x068

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EXTICR4 EXTI15[7:0] EXTI14[7:0] EXTI13[7:0] EXTI2[7:0]

0x06C

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOCK
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_LOCKR
0x070

Reset value 0

EXTI_IMR1 IM[31:0]
0x080

Reset value 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EMR1 EM[31:0]
0x084

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x088-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
0x08C

EXTI_IMR2 IM[42:32]
0x090

Reset value 1 1 1 1 0 0 0 0 1 1 1

EXTI_EMR2 EM[42:32]
0x094

Reset value 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

RM0438 Rev 7 563/2194

563
Cyclic redundancy check calculation unit (CRC) RM0438

18 Cyclic redundancy check calculation unit (CRC)

18.1 Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16-
or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.

18.2 CRC main features

• Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +X8 + X7 + X5 + X4 + X2+ X +1
• Alternatively, uses fully programmable polynomial with programmable size (7, 8, 16, 32
bits)
• Handles 8-,16-, 32-bit data size
• Programmable CRC initial value
• Single input/output 32-bit data register
• Input buffer to avoid bus stall during calculation
• CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
• General-purpose 8-bit register (can be used for temporary storage)
• Reversibility option on I/O data

564/2194 RM0438 Rev 7

RM0438 Cyclic redundancy check calculation unit (CRC)

18.3 CRC functional description

18.3.1 CRC block diagram

Figure 51. CRC calculation unit block diagram

32-bit AHB bus

32-bit (read access)

Data register (output)
crc_hclk

CRC computation

32-bit (write access)

Data register (input)

MS19882V2

18.3.2 CRC internal signals

Table 113. CRC internal input/output signals

Signal name Signal type Description

crc_hclk Digital input AHB clock

18.3.3 CRC operation

The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
• 4 AHB clock cycles for 32-bit
• 2 AHB clock cycles for 16-bit
• 1 AHB clock cycles for 8-bit
An input buffer allows a second data to be immediately written without waiting for any wait
states due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.

RM0438 Rev 7 565/2194

570
Cyclic redundancy check calculation unit (CRC) RM0438

The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
• 0x58D43CB2 with bit-reversal done by byte
• 0xD458B23C with bit-reversal done by half-word
• 0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.

Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.

566/2194 RM0438 Rev 7

RM0438 Cyclic redundancy check calculation unit (CRC)

18.4 CRC registers

18.4.1 CRC data register (CRC_DR)

Address offset: 0x00
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DR[31:0]: Data register bits

This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the correct
value.

18.4.2 CRC independent data register (CRC_IDR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

IDR[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IDR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IDR[31:0]: General-purpose 32-bit data register bits

These bits can be used as a temporary storage location for four bytes.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR
register

RM0438 Rev 7 567/2194

570
Cyclic redundancy check calculation unit (CRC) RM0438

18.4.3 CRC control register (CRC_CR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REV_
Res. Res. Res. Res. Res. Res. Res. Res. REV_IN[1:0] POLYSIZE[1:0] Res. Res. RESET
OUT
rw rw rw rw rw rs

Bits 31:8 Reserved, must be kept at reset value.

Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept at reset value.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the
value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by
hardware

568/2194 RM0438 Rev 7

RM0438 Cyclic redundancy check calculation unit (CRC)

18.4.4 CRC initial value (CRC_INIT)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CRC_INIT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC_INIT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CRC_INIT[31:0]: Programmable initial CRC value

This register is used to write the CRC initial value.

18.4.5 CRC polynomial (CRC_POL)

Address offset: 0x14
Reset value: 0x04C1 1DB7

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

POL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

POL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 POL[31:0]: Programmable polynomial

This register is used to write the coefficients of the polynomial to be used for CRC
calculation.
If the polynomial size is less than 32 bits, the least significant bits have to be used to program
the correct value.

RM0438 Rev 7 569/2194

570
Cyclic redundancy check calculation unit (CRC) RM0438

18.4.6 CRC register map

Table 114. CRC register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

CRC_DR DR[31:0]
0x00
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_IDR IDR[31:0]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

POLYSIZE[1:0]
REV_IN[1:0]
REV_OUT

RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
CRC_CR
0x08

Reset value 0 0 0 0 0 0

CRC_INIT CRC_INIT[31:0]
0x10
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CRC_POL POL[31:0]
0x14
Reset value 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1

Refer to Section 2.3 on page 87 for the register boundary addresses.

570/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

19 Flexible static memory controller (FSMC)

19.1 Introduction
The flexible static memory controller (FSMC) includes two memory controllers:
• The NOR/PSRAM memory controller
• The NAND memory controller
This memory controller is also named flexible memory controller (FMC).

19.2 FMC main features

The FMC functional block makes the interface with: synchronous and asynchronous static
memories, and NAND Flash memory. Its main purposes are:
• to translate AHB transactions into the appropriate external device protocol
• to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique chip select. The FMC performs only
one access at a time to an external device.
The main features of the FMC controller are the following:
• Interface with static-memory mapped devices including:
– Static random access memory (SRAM)
– NOR Flash memory/OneNAND Flash memory
– PSRAM (4 memory banks)
– Ferroelectric RAM (FRAM)
– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
• Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
• Burst mode support for faster access to synchronous devices such as NOR Flash
memory, PSRAM)
• Programmable continuous clock output for asynchronous and synchronous accesses
• 8-,16-bit wide data bus
• Independent chip select control for each memory bank
• Independent configuration for each memory bank
• Write enable and byte lane select outputs for use with PSRAM, SRAM devices
• External asynchronous wait control
• Write FIFO with 16 x32-bit depth
The Write FIFO is common to all memory controllers and consists of:
• a Write Data FIFO which stores the AHB data to be written to the memory (up to 32
bits) plus one bit for the AHB transfer (burst or not sequential mode)
• a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data
size (up to 2 bits). When operating in burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM). In this case, the AHB burst is
broken into two FIFO entries.

RM0438 Rev 7 571/2194

628
Flexible static memory controller (FSMC) RM0438

At startup the FMC pins must be configured by the user application. The FMC I/O pins which
are not used by the application can be used for other purposes.
The FMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, the
settings can be changed at any time.

19.3 FMC block diagram

The FMC consists of the following main blocks:
• The AHB interface (including the FMC configuration registers)
• The NOR Flash/PSRAM/SRAM controller
The block diagram is shown in the figure below.

Figure 52. FMC block diagram

FMC interrupts to NVIC

NOR/PSRAM
FMC_NL (or NADV)
signals
FMC_CLK
From clock NOR/PSRAM
controller NOR / PSRAM / SRAM
memory FMC_NBL[1:0]
HCLK shared signals
controller
FMC_A[25:0]
Shared signals
FMC_D[15:0]

FMC_NE[4:1]
Configuration
FMC_NOE NOR / PSRAM / SRAM
registers
NAND FMC_NWE shared signals
memory FMC_NWAIT
controller
FMC_NCE
NAND signals
FMC_INT

MS34473V3

572/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

19.4 AHB interface

The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FMC chip select (FMC_NEx) does not toggle
between the consecutive accesses except in case of Access mode D when the Extended
mode is enabled.
The FMC generates an AHB error in the following conditions:
• When reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.
• When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the
FMC_BCRx register.
The effect of an AHB error depends on the AHB master which has attempted the R/W
access:
• If the access has been attempted by the Cortex®-M33 CPU, a hard fault interrupt is
generated.
• If the access has been performed by a DMA controller, a DMA transfer error is
generated and the corresponding DMA channel is automatically disabled.
The AHB clock (HCLK) is the reference clock for the FMC.

19.4.1 Supported memories and transactions

General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
Therefore, some simple transaction rules must be followed:
• AHB transaction size and memory data size are equal
There is no issue in this case.
• AHB transaction size is greater than the memory size:
In this case, the FMC splits the AHB transaction into smaller consecutive memory
accesses to meet the external data width. The FMC chip select (FMC_NEx) does not
toggle between the consecutive accesses. If the bus turnaround timings is configured

RM0438 Rev 7 573/2194

628
Flexible static memory controller (FSMC) RM0438

to any other value than 0, the FMC chip select (FMC_NEx) toggles between the
consecutive accesses. This feature is required when interfacing with FRAM memory.
• AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
– Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM)
In this case, the FMC allows read/write transactions and accesses the right data
through its byte lanes NBL[1:0].
Bytes to be written are addressed by NBL[1:0].
All memory bytes are read (NBL[1:0] are driven low during read transaction) and
the useless ones are discarded.
– Accesses to devices that do not have the byte select feature (NOR and NAND
Flash memories)
This situation occurs when a byte access is requested to a 16-bit wide Flash
memory. Since the device cannot be accessed in Byte mode (only 16-bit words
can be read/written from/to the Flash memory), Write transactions and Read
transactions are allowed (the controller reads the entire 16-bit memory word and
uses only the required byte).

Wrap support for NOR Flash/PSRAM

Wrap burst mode for synchronous memories is not supported. The memories must be
configured in Linear burst mode of undefined length.

Configuration registers
The FMC can be configured through a set of registers. Refer to Section 19.6.6, for a
detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 19.7.7,
for a detailed description of the NAND Flash registers.

19.5 External device address mapping

From the FMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see Figure 53):
• Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated chip selects, as follows:
– Bank 1 - NOR/PSRAM 1
– Bank 1 - NOR/PSRAM 2
– Bank 1 - NOR/PSRAM 3
– Bank 1 - NOR/PSRAM 4
• Bank 3 used to address NAND Flash memory devices.The MPU memory attribute for
this space must be reconfigured by software to Device.
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.

574/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Figure 53. FMC memory banks

Address Bank Supported memory type

0x6000 0000
Bank 1 NOR/PSRAM/SRAM
4 x 64 Mbyte

0x6FFF FFFF
0x7000 0000

Not used

0x7FFF FFFF
0x8000 0000

Bank 3
NAND Flash memory
4 x 64 Mbyte

0x8FFF FFFF
0x9000 0000

Not used

0x9FFF FFFF
MSv34475V2

19.5.1 NOR/PSRAM address mapping

HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 115.

Table 115. NOR/PSRAM bank selection

HADDR[27:26](1) Selected bank

00 Bank 1 - NOR/PSRAM 1
01 Bank 1 - NOR/PSRAM 2
10 Bank 1 - NOR/PSRAM 3
11 Bank 1 - NOR/PSRAM 4
1. HADDR are internal AHB address lines that are translated to external memory.

The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.

Table 116. NOR/PSRAM External memory address

Memory width(1) Data address issued to the memory Maximum memory capacity (bits)

8-bit HADDR[25:0] 64 Mbytes x 8 = 512 Mbit

16-bit HADDR[25:1] >> 1 64 Mbytes/2 x 16 = 512 Mbit
1. In case of a 16-bit external memory width, the FMC internally uses HADDR[25:1] to generate the address
for external memory FMC_A[24:0].
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].

RM0438 Rev 7 575/2194

628
Flexible static memory controller (FSMC) RM0438

19.5.2 NAND Flash memory address mapping

The NAND bank is divided into memory areas as indicated in Table 117.

Table 117. NAND memory mapping and timing registers

Start address End address FMC bank Memory space Timing register

0x8800 0000 0x8BFF FFFF Attribute FMC_PATT (0x8C)

Bank 3 - NAND Flash
0x8000 0000 0x83FF FFFF Common FMC_PMEM (0x88)

For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in Table 118 below) located in the lower 256 Kbytes:
• Data section (first 64 Kbytes in the common/attribute memory space)
• Command section (second 64 Kbytes in the common / attribute memory space)
• Address section (next 128 Kbytes in the common / attribute memory space)

Table 118. NAND bank selection

Section name HADDR[17:16] Address range

Address section 1X 0x020000-0x03FFFF

Command section 01 0x010000-0x01FFFF
Data section 00 0x000000-0x0FFFF

The application software uses the 3 sections to access the NAND Flash memory:
• To sending a command to NAND Flash memory, the software must write the
command value to any memory location in the command section.
• To specify the NAND Flash address that must be read or written, the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
• To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.

576/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

19.6 NOR Flash/PSRAM controller

The FMC generates the appropriate signal timings to drive the following types of memories:
• Asynchronous SRAM, FRAM and ROM
– 8 bits
– 16 bits
• PSRAM (CellularRAM™)
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
• NOR Flash memory
– Asynchronous mode
– Burst mode for synchronous accesses
– Multiplexed or non-multiplexed
The FMC outputs a unique chip select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
The FMC supports a wide range of devices through a programmable timings among which:
• Programmable wait states (up to 15)
• Programmable bus turnaround cycles (up to 15)
• Programmable output enable and write enable delays (up to 15)
• Independent read and write timings and protocol to support the widest variety of
memories and timings
• Programmable continuous clock (FMC_CLK) output.
The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1
register:
• If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during
synchronous accesses (Read/write transactions).
• If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must
be configured in Synchronous mode (see Section 19.6.6: NOR/PSRAM controller
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AHB data size has to be the same as the memory data width (MWID) otherwise the
FMC_CLK frequency is changed depending on AHB data transaction (refer to
Section 19.6.5: Synchronous transactions for FMC_CLK divider ratio formula).
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see Section 19.6.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 119) and support
for wait management (for PSRAM and NOR Flash accessed in Burst mode).

RM0438 Rev 7 577/2194

628
Flexible static memory controller (FSMC) RM0438

Table 119. Programmable NOR/PSRAM access parameters

Parameter Function Access mode Unit Min. Max.

Address Duration of the address AHB clock cycle

Asynchronous 0 15
setup setup phase (HCLK)
Duration of the address hold Asynchronous, AHB clock cycle
Address hold 1 15
phase muxed I/Os (HCLK)
Duration of the byte lanes AHB clock cycle
NBL setup Asynchronous 0 3
setup phase (HCLK)
Duration of the data setup AHB clock cycle
Data setup Asynchronous 1 256
phase (HCLK)
Duration of the data hold AHB clock cycle
Data hold Asynchronous 0 3
phase (HCLK)
Asynchronous and
Duration of the bus AHB clock cycle
Bust turn synchronous read 0 15
turnaround phase (HCLK)
/ write
Number of AHB clock cycles
Clock divide AHB clock cycle
(HCLK) to build one memory Synchronous 2 16
ratio (HCLK)
clock cycle (CLK)
Number of clock cycles to
Memory clock
Data latency issue to the memory before Synchronous 2 17
cycle (CLK)
the first data of the burst

19.6.1 External memory interface signals

Table 120, Table 121 and Table 122 list the signals that are typically used to interface with
NOR Flash memory, SRAM and PSRAM.
Note: The prefix “N” identifies the signals that are active low.

NOR Flash memory, non-multiplexed I/Os

Table 120. Non-multiplexed I/O NOR Flash memory

FMC signal name I/O Function

CLK O Clock (for synchronous access)

A[25:0] O Address bus
D[15:0] I/O Bidirectional data bus
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
Latch enable (this signal is called address
NL(=NADV) O
valid, NADV, by some NOR Flash devices)
NWAIT I NOR Flash wait input signal to the FMC

The maximum capacity is 512 Mbits (26 address lines).

578/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

NOR Flash memory, 16-bit multiplexed I/Os

Table 121. 16-bit multiplexed I/O NOR Flash memory

FMC signal name I/O Function

CLK O Clock (for synchronous access)

A[25:16] O Address bus
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
AD[15:0] I/O
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x] O Chip select, x = 1..4
NOE O Output enable
NWE O Write enable
Latch enable (this signal is called address valid, NADV, by some NOR
NL(=NADV) O
Flash devices)
NWAIT I NOR Flash wait input signal to the FMC

The maximum capacity is 512 Mbits.

PSRAM/FRAM/SRAM, non-multiplexed I/Os

Table 122. Non-multiplexed I/Os PSRAM/SRAM

FMC signal name I/O Function

CLK O Clock (only for PSRAM synchronous access)

A[25:0] O Address bus
D[15:0] I/O Data bidirectional bus
NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid only for PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits.

PSRAM, 16-bit multiplexed I/Os

Table 123. 16-Bit multiplexed I/O PSRAM

FMC signal name I/O Function

CLK O Clock (for synchronous access)

A[25:16] O Address bus
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
AD[15:0] I/O
A[15:0] and data D[15:0] are multiplexed on the databus)

RM0438 Rev 7 579/2194

628
Flexible static memory controller (FSMC) RM0438

Table 123. 16-Bit multiplexed I/O PSRAM (continued)

FMC signal name I/O Function

NE[x] O Chip select, x = 1..4 (called NCE by PSRAM (CellularRAM™ i.e. CRAM))
NOE O Output enable
NWE O Write enable
NL(= NADV) O Address valid PSRAM input (memory signal name: NADV)
NWAIT I PSRAM wait input signal to the FMC
NBL[1:0] O Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)

The maximum capacity is 512 Mbits (26 address lines).

19.6.2 Supported memories and transactions

Table 124 below shows an example of the supported devices, access modes and
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.

Table 124. NOR Flash/PSRAM: example of supported memories

and transactions
AHB Allowed/
Memory
Device Mode R/W data not Comments
data size
size allowed

Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
NOR Flash Asynchronous R 32 16 Y Split into 2 FMC accesses
(muxed I/Os
and nonmuxed Asynchronous W 32 16 Y Split into 2 FMC accesses
I/Os) Asynchronous
R - 16 N Mode is not supported
page
Synchronous R 8 16 N -
Synchronous R 16 16 Y -
Synchronous R 32 16 Y -

580/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 124. NOR Flash/PSRAM: example of supported memories

and transactions (continued)
AHB Allowed/
Memory
Device Mode R/W data not Comments
data size
size allowed

Asynchronous R 8 16 Y -
Asynchronous W 8 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 16 16 Y -
Asynchronous W 16 16 Y -
Asynchronous R 32 16 Y Split into 2 FMC accesses
PSRAM
(multiplexed Asynchronous W 32 16 Y Split into 2 FMC accesses
I/Os and non- Asynchronous
multiplexed R - 16 N Mode is not supported
page
I/Os)
Synchronous R 8 16 N -
Synchronous R 16 16 Y -
Synchronous R 32 16 Y -
Synchronous W 8 16 Y Use of byte lanes NBL[1:0]
Synchronous W 16/32 16 Y -
Asynchronous R 8 / 16 16 Y -
Asynchronous W 8 / 16 16 Y Use of byte lanes NBL[1:0]
SRAM and
ROM Asynchronous R 32 16 Y Split into 2 FMC accesses
Split into 2 FMC accesses
Asynchronous W 32 16 Y
Use of byte lanes NBL[1:0]

19.6.3 General timing rules

Signals synchronization
• All controller output signals change on the rising edge of the internal clock (HCLK)
• In Synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
– NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FMC_CLK clock.
– NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FMC_CLK clock.

RM0438 Rev 7 581/2194

628
Flexible static memory controller (FSMC) RM0438

19.6.4 NOR Flash/PSRAM controller asynchronous transactions

Asynchronous static memories (NOR Flash, PSRAM, SRAM, FRAM)
• Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
• The FMC always samples the data before de-asserting the NOE signal. This
guarantees that the memory data hold timing constraint is met (minimum Chip Enable
high to data transition is usually 0 ns)
• If the Extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to
four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D
modes for read and write operations. For example, read operation can be performed in
mode A and write in mode B.
• If the Extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the
FMC can operate in mode 1 or mode 2 as follows:
– Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP
= 0x0 or 0x01 in the FMC_BCRx register)
– Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in
the FMC_BCRx register).

Mode 1 - SRAM/FRAM/PSRAM (CRAM)

The next figures show the read and write transactions for the supported modes followed by
the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.

Figure 54. Mode 1 read access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE High

Data bus Data driven by memory

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK HCLK cycles
cycles
MSv41664V1

582/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Figure 55. Mode 1 write access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE

Data bus Data driven by controller

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles
cycles
MSv41665V1

The DATAHLD time at the end of the read and write transactions guarantee the address and
data hold time after the NOE/NWE rising edge. The DATAST value must be greater than
zero (DATAST > 0).

Table 125. FMC_BCRx bitfields (mode 1)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5:4 MWID As needed

RM0438 Rev 7 583/2194

628
Flexible static memory controller (FSMC) RM0438

Table 125. FMC_BCRx bitfields (mode 1) (continued)

Bit number Bit name Value to set

3:2 MTYP As needed, exclude 0x2 (NOR Flash memory)

1 MUXE 0x0
0 MBKEN 0x1

Table 126. FMC_BTRx bitfields (mode 1)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses, DATAHLD+1 HCLK cycles for write accesses).
29:28 ACCMOD Don’t care
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles).
3:0 ADDSET
Minimum value for ADDSET is 0.

Mode A - SRAM/FRAM/PSRAM (CRAM) OE toggling

Figure 56. Mode A read access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE High

Data bus Data driven by memory

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK HCLK cycles
cycles
MSv41681V1

1. NBL[1:0] are driven low during the read access

584/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Figure 57. Mode A write access waveforms

Memory transaction

A[25:0]

NBL[x:0]

NEx

NOE

NWE

Data bus Data driven by controller

NBLSET ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles
cycles
MSv41665V1

The differences compared with Mode 1 are the toggling of NOE and the independent read
and write timings.

Table 127. FMC_BCRx bitfields (mode A)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN Don’t care
5:4 MWID As needed

RM0438 Rev 7 585/2194

628
Flexible static memory controller (FSMC) RM0438

Table 127. FMC_BCRx bitfields (mode A) (continued)

Bit number Bit name Value to set

3:2 MTYP As needed, exclude 0x2 (NOR Flash memory)

1 MUXEN 0x0
0 MBKEN 0x1

Table 128. FMC_BTRx bitfields (mode A)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
15:8 DATAST
accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for read
3:0 ADDSET accesses.
Minimum value for ADDSET is 0.

Table 129. FMC_BWTRx bitfields (mode A)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for write
15:8 DATAST
accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for write
3:0 ADDSET accesses.
Minimum value for ADDSET is 0.

586/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Mode 2/B - NOR Flash

Figure 58. Mode 2 and mode B read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE High

D[15:0] Data driven by memory

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK cycles

MSv41678V1

Figure 59. Mode 2 write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

Data bus Data driven by controller

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK cycles

MSv41679V1

RM0438 Rev 7 587/2194

628
Flexible static memory controller (FSMC) RM0438

Figure 60. Mode B write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

Data bus Data driven by controller

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK cycles

MSv41680V1

The differences with mode 1 are the toggling of NWE and the independent read and write
timings when extended mode is set (mode B).

Table 130. FMC_BCRx bitfields (mode 2/B)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1 for mode B, 0x0 for mode 2
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed

588/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 130. FMC_BCRx bitfields (mode 2/B) (continued)

Bit number Bit name Value to set

3:2 MTYP 0x2 (NOR Flash memory)

1 MUXEN 0x0
0 MBKEN 0x1

Table 131. FMC_BTRx bitfields (mode 2/B)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD accesses and DATAHLD+1 HCLK cycles for write accesses when
Extended mode is disabled).
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
15:8 DATAST
read accesses.
7:4 ADDHLD Don’t care
Duration of the access first phase (ADDSET HCLK cycles) for read
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

Table 132. FMC_BWTRx bitfields (mode 2/B)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x1 if Extended mode is set
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the access second phase (DATAST HCLK cycles) for
15:8 DATAST
write accesses.
7:4 ADDHLD Don’t care
Duration of the access first phase (ADDSET HCLK cycles) for write
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

Note: The FMC_BWTRx register is valid only if the Extended mode is set (mode B), otherwise its
content is don’t care.

RM0438 Rev 7 589/2194

628
Flexible static memory controller (FSMC) RM0438

Mode C - NOR Flash - OE toggling

Figure 61. Mode C read access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE High

D[15:0] Data driven by memory

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD

HCLK cycles

MSv41682V1

Figure 62. Mode C write access waveforms

Memory transaction

A[25:0]

NADV

NEx

NOE

NWE

Data bus Data driven by controller

ADDSET HCLK cycles DATAST HCLK cycles DATAHLD +1

HCLK cycles

MSv41679V1

The differences compared with mode 1 are the toggling of NOE and the independent read
and write timings.

590/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 133. FMC_BCRx bitfields (mode C)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5:4 MWID As needed
3:2 MTYP 0x02 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1

Table 134. FMC_BTRx bitfields (mode C)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x2
27:24 DATLAT 0x0
23:20 CLKDIV 0x0
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
15:8 DATAST
read accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for read
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

RM0438 Rev 7 591/2194

628
Flexible static memory controller (FSMC) RM0438

Table 135. FMC_BWTRx bitfields (mode C)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x2
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for
15:8 DATAST
write accesses.
7:4 ADDHLD Don’t care
Duration of the first access phase (ADDSET HCLK cycles) for write
3:0 ADDSET
accesses. Minimum value for ADDSET is 0.

Mode D - asynchronous access with extended address

Figure 63. Mode D read access waveforms

Memory transaction

A[25:0]

NADV

NBL[x:0]

NEx

NOE

NWE High

Data bus Data driven by memory

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD

HCLK HCLK HCLK cycles
cycles cycles
MSv41683V1

592/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Figure 64. Mode D write access waveforms

Memory transaction

A[25:0]

NADV

NBL[x:0]

NEx

NOE

NWE

Data bus Data driven by controller

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles HCLK cycles
cycles
MSv41684V1

The differences with mode 1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.

Table 136. FMC_BCRx bitfields (mode D)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x1
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1

RM0438 Rev 7 593/2194

628
Flexible static memory controller (FSMC) RM0438

Table 136. FMC_BCRx bitfields (mode D) (continued)

Bit number Bit name Value to set

6 FACCEN Set according to memory support

5:4 MWID As needed
3:2 MTYP As needed
1 MUXEN 0x0
0 MBKEN 0x1

Table 137. FMC_BTRx bitfields (mode D)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
Duration of the second access phase (DATAST HCLK cycles) for read
15:8 DATAST
accesses.
Duration of the middle phase of the read access (ADDHLD HCLK
7:4 ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for read
3:0 ADDSET
accesses. Minimum value for ADDSET is 1.

Table 138. FMC_BWTRx bitfields (mode D)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD+1 HCLK cycles for write
31:30 DATAHLD
accesses).
29:28 ACCMOD 0x3
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
Duration of the middle phase of the write access (ADDHLD HCLK
7:4 ADDHLD
cycles)
Duration of the first access phase (ADDSET HCLK cycles) for write
3:0 ADDSET
accesses. Minimum value for ADDSET is 1.

594/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Muxed mode - multiplexed asynchronous access to NOR Flash memory

Figure 65. Muxed read access waveforms

Memory transaction

A[25:16]

NADV

NBL[x:0]

NEx

NOE

NWE High

AD[15:0] Lower address Data driven by memory

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD

HCLK HCLK HCLK cycles
cycles cycles
MSv41685V1

RM0438 Rev 7 595/2194

628
Flexible static memory controller (FSMC) RM0438

Figure 66. Muxed write access waveforms

Memory transaction

A[25:16]

NADV

NBL[x:0]

NEx

NOE

NWE

AD[15:0] Lower address Data driven by controller

NBLSET ADDSET HCLK cycles ADDHLD DATAST HCLK cycles DATAHLD +1

HCLK HCLK cycles HCLK cycles
cycles
MSv41686V1

The difference with mode D is the drive of the lower address byte(s) on the data bus.

Table 139. FMC_BCRx bitfields (Muxed mode)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] As needed
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in Asynchronous mode)
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect in Asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 Reserved 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1

596/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 139. FMC_BCRx bitfields (Muxed mode) (continued)

Bit number Bit name Value to set

5:4 MWID As needed

3:2 MTYP 0x2 (NOR Flash memory) or 0x1(PSRAM)
1 MUXEN 0x1
0 MBKEN 0x1

Table 140. FMC_BTRx bitfields (Muxed mode)

Bit number Bit name Value to set

Duration of the data hold phase (DATAHLD HCLK cycles for read
31:30 DATAHLD
accesses, DATAHLD+1 HCLK cycles for write accesses).
29:28 ACCMOD 0x0
27:24 DATLAT Don’t care
23:20 CLKDIV Don’t care
19:16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15:8 DATAST Duration of the second access phase (DATAST HCLK cycles).
7:4 ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
Duration of the first access phase (ADDSET HCLK cycles). Minimum
3:0 ADDSET
value for ADDSET is 1.

WAIT management in asynchronous accesses

If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:

RM0438 Rev 7 597/2194

628
Flexible static memory controller (FSMC) RM0438

1. The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
DATAST ≥ ( 4 × HCLK ) + max_wait_assertion_time

2. The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
max_wait_assertion_time > address_phase + hold_phase

then:

DATAST ≥ ( 4 × HCLK ) + ( max_wait_assertion_time – address_phase – hold_phase )

otherwise
DATAST ≥ 4 × HCLK

where max_wait_assertion_time is the maximum time taken by the memory to assert

the WAIT signal once NEx/NOE/NWE is low.
Figure 67 and Figure 68 show the number of HCLK clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).

Figure 67. Asynchronous wait during a read access waveforms

Memory transaction

A[25:0]

address phase data setup phase

NEx

NWAIT don’t care don’t care

NOE

D[15:0] data driven by memory

4HCLK

MS30463V2

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

598/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Figure 68. Asynchronous wait during a write access waveforms

Memory transaction

A[25:0]

address phase data setup phase

NEx

NWAIT don’t care don’t care

1HCLK

NWE

D[15:0] data driven by FMC

3HCLK

MSv40168V1

1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.

CellularRAM™ (PSRAM) refresh management

The CellularRAM™ does not allow maintaining the chip select signal (NE) low for longer
than the tCEM timing specified for the memory device. This timing can be programmed in the
FMC_PCSCNTR register. It defines the maximum duration of the NE low pulse in HCLK
cycles for asynchronous accesses and FMC_CLK cycles for synchronous accesses

19.6.5 Synchronous transactions

The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of
CLKDIV and the MWID/ AHB data size, following the formula given below:
Whatever MWID size: 16 or 8-bit, the FMC_CLK divider ratio is always defined by the
programmed CLKDIV value.
Example:
• If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.
NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet
this constraint, the FMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.

Data latency versus NOR memory latency

The data latency is the number of cycles to wait before sampling the data. The DATLAT
value must be consistent with the latency value specified in the NOR Flash configuration

RM0438 Rev 7 599/2194

628
Flexible static memory controller (FSMC) RM0438

register. The FMC does not include the clock cycle when NADV is low in the data latency
count.
Caution: Some NOR Flash memories include the NADV Low cycle in the data latency count, so that
the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be
either:
• NOR Flash latency = (DATLAT + 2) CLK clock cycles
• or NOR Flash latency = (DATLAT + 3) CLK clock cycles
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can
be set to its minimum value. As a result, the FMC samples the data and waits long enough
to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and
real data are processed.
Other memories do not assert NWAIT during latency. In this case the latency must be set
correctly for both the FMC and the memory, otherwise invalid data are mistaken for good
data, or valid data are lost in the initial phase of the memory access.

Single-burst transfer
When the selected bank is configured in Burst mode for synchronous accesses, if for
example an AHB single-burst transaction is requested on 16-bit memories, the FMC
performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the
AHB transfer is 32 bits) and de-assert the chip select signal when the last data is strobed.
Such transfers are not the most efficient in terms of cycles compared to asynchronous read
operations. Nevertheless, a random asynchronous access would first require to re-program
the memory access mode, which would altogether last longer.

Cross boundary page for CellularRAM™ 1.5

CellularRAM™ 1.5 does not allow burst access to cross the page boundary. The FMC
controller allows to split automatically the burst access when the memory page size is
reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory
page size.

Wait management
For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency
period, which corresponds to (DATLAT+2) CLK clock cycles.
If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait
states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when
WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the chip select and output enable signals valid. It does not
consider the data as valid.
In Burst mode, there are two timing configurations for the NOR Flash NWAIT signal:
• The Flash memory asserts the NWAIT signal one data cycle before the wait state
(default after reset).
• The Flash memory asserts the NWAIT signal during the wait state

600/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to
the WAITCFG bit in the FMC_BCRx registers (x = 0..3).

Figure 69. Wait configuration waveforms

Memory transaction = burst of 4 half words

HCLK

CLK

A[25:16] addr[25:16]

NADV

NWAIT
(WAITCFG = 0)

NWAIT
(WAITCFG = 1)
inserted wait state

A/D[15:0] addr[15:0] data data data

ai15798c

RM0438 Rev 7 601/2194

628
Flexible static memory controller (FSMC) RM0438

Figure 70. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)

Memory transaction = burst of 4 half words

HCLK

CLK

A[25:16] addr[25:16]

NEx

NOE

High
NWE

NADV

NWAIT
(WAITCFG=
0)
(DATLAT + 2) inserted wait state
CLK cycles
A/D[15:0] Addr[15:0] data data data data

1 clock 1 clock
cycle cycle
Data strobes Data strobes
ai17723f

1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.

Table 141. FMC_BCRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
20 CCLKEN As needed
19 CBURSTRW No effect on synchronous read
18:16 CPSIZE 0x0 (no effect in Asynchronous mode)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
To be set to 1 if the memory supports this feature, to be kept at 0
13 WAITEN
otherwise
12 WREN No effect on synchronous read
11 WAITCFG To be set according to memory
10 Reserved 0x0

602/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 141. FMC_BCRx bitfields (Synchronous multiplexed read mode) (continued)

Bit number Bit name Value to set

9 WAITPOL To be set according to memory

8 BURSTEN 0x1
7 Reserved 0x1
6 FACCEN Set according to memory support (NOR Flash memory)
5-4 MWID As needed
3-2 MTYP 0x1 or 0x2
1 MUXEN As needed
0 MBKEN 0x1

Table 142. FMC_BTRx bitfields (Synchronous multiplexed read mode)

Bit number Bit name Value to set

31:30 DATAHLD Don’t care

29:28 ACCMOD 0x0
27-24 DATLAT Data latency
27-24 DATLAT Data latency
0x0 to get CLK = HCLK
23-20 CLKDIV 0x1 to get CLK = 2 × HCLK
..
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET Don’t care

RM0438 Rev 7 603/2194

628
Flexible static memory controller (FSMC) RM0438

Figure 71. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

Memory transaction = burst of 2 half words

HCLK

CLK

A[25:16] addr[25:16]

NEx

Hi-Z
NOE

NWE

NADV

NWAIT
(WAITCFG = 0)

(DATLAT + 2) inserted wait state

CLK cycles
A/D[15:0] Addr[15:0] data data

1 clock 1 clock ai14731f

1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.

Table 143. FMC_BCRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31:24 Reserved 0x000

23:22 NBLSET[1:0] Don’t care
20 CCLKEN As needed
19 CBURSTRW 0x1
18:16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASYNCWAIT 0x0
14 EXTMOD 0x0
To be set to 1 if the memory supports this feature, to be kept at 0
13 WAITEN
otherwise.

604/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 143. FMC_BCRx bitfields (Synchronous multiplexed write mode) (continued)

Bit number Bit name Value to set

12 WREN 0x1
11 WAITCFG 0x0
10 Reserved 0x0
9 WAITPOL to be set according to memory
8 BURSTEN no effect on synchronous write
7 Reserved 0x1
6 FACCEN Set according to memory support
5-4 MWID As needed
3-2 MTYP 0x1
1 MUXEN As needed
0 MBKEN 0x1

Table 144. FMC_BTRx bitfields (Synchronous multiplexed write mode)

Bit number Bit name Value to set

31-30 DATAHLD Don’t care

29:28 ACCMOD 0x0
27-24 DATLAT Data latency
0x0 to get CLK = HCLK
23-20 CLKDIV
0x1 to get CLK = 2 × HCLK
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK).
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET Don’t care

RM0438 Rev 7 605/2194

628
Flexible static memory controller (FSMC) RM0438

19.6.6 NOR/PSRAM controller registers

SRAM/NOR-Flash chip-select control register for bank x
(FMC_BCRx) (x = 1 to 4)
Address offset: 8 * (x – 1), (x = 1 to 4)
Reset value: Bank 1: 0x0000 30DB
Reset value: Bank 2: 0x0000 30D2
Reset value: Bank 3: 0x0000 30D2
Reset value: Bank 4: 0x0000 30D2
This register contains the control information of each memory bank, used for SRAMs,
PSRAM, FRAM and NOR Flash memories.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CCLK CBURST
Res. Res. Res. Res. Res. Res. Res. Res. NBLSET[1:0] WFDIS CPSIZE[2:0]
EN RW

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ASYNC EXT WAIT WAIT WAIT BURST FACC MUX MBK
WREN Res. Res. MWID[1:0] MTYP[1:0]
WAIT MOD EN CFG POL EN EN EN EN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 NBLSET[1:0]: Byte lane (NBL) setup
These bits configure the NBL setup timing from NBLx low to chip select NEx low.
00: NBL setup time is 0 AHB clock cycle
01: NBL setup time is 1 AHB clock cycle
10: NBL setup time is 2 AHB clock cycles
11: NBL setup time is 3 AHB clock cycles
Bit 21 WFDIS: Write FIFO disable
This bit disables the Write FIFO used by the FMC controller.
0: Write FIFO enabled (Default after reset)
1: Write FIFO disabled
Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the
FMC_BCR1 register.

606/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Bit 20 CCLKEN: Continuous clock enable

This bit enables the FMC_CLK clock output to external memory devices.
0: The FMC_CLK is only generated during the synchronous memory access (read/write
transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the
FMC_BCRx register (default after reset).
1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The
FMC_CLK clock is activated when the CCLKEN is set.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the
FMC_BCR1 register. Bank 1 must be configured in Synchronous mode to generate the
FMC_CLK continuous clock.
Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1
register. CLKDIV in FMC_BWTR1 is don’t care.
Note: If the Synchronous mode is used and CCLKEN bit is set, the synchronous memories
connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the
FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)
Bit 19 CBURSTRW: Write burst enable
For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write
operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx
register.
0: Write operations are always performed in Asynchronous mode.
1: Write operations are performed in Synchronous mode.
Bits 18:16 CPSIZE[2:0]: CRAM page size
These are used for CellularRAM™ 1.5 which does not allow burst access to cross the address
boundaries between pages. When these bits are configured, the FMC controller splits automatically
the burst access when the memory page size is reached (refer to memory datasheet for page size).
000: No burst split when crossing page boundary (default after reset)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
Others: reserved
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after
reset).
1: NWAIT signal is taken in to account when running an asynchronous protocol.
Bit 14 EXTMOD: Extended mode enable
This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses
inside the FMC_BWTR register, thus resulting in different timings for read and write operations.
0: values inside FMC_BWTR register are not taken into account (default after reset)
1: values inside FMC_BWTR register are taken into account
Note: When the Extended mode is disabled, the FMC can operate in mode 1 or mode 2 as follows:
– Mode 1 is the default mode when the SRAM/PSRAM memory type is selected
(MTYP = 0x0 or 0x01)
– Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).

RM0438 Rev 7 607/2194

628
Flexible static memory controller (FSMC) RM0438

Bit 13 WAITEN: Wait enable bit

This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in
Synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed Flash latency period).
1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to
insert wait states if asserted) (default after reset).
Bit 12 WREN: Write enable bit
This bit indicates whether write operations are enabled/disabled in the bank by the FMC.
0: Write operations are disabled in the bank by the FMC, an AHB error is reported.
1: Write operations are enabled for the bank by the FMC (default after reset).
Bit 11 WAITCFG: Wait timing configuration
The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be
inserted when accessing the memory in Synchronous mode. This configuration bit determines if
NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset).
1: NWAIT signal is active during wait state (not used for PSRAM).
Bit 10 Reserved, must be kept at reset value.
Bit 9 WAITPOL: Wait signal polarity bit
Defines the polarity of the wait signal from memory used for either in Synchronous or Asynchronous
mode.
0: NWAIT active low (default after reset)
1: NWAIT active high
Bit 8 BURSTEN: Burst enable bit
This bit enables/disables synchronous accesses during read operations. It is valid only for
synchronous memories operating in Burst mode.
0: Burst mode disabled (default after reset). Read accesses are performed in Asynchronous mode.
1: Burst mode enable. Read accesses are performed in Synchronous mode.
Bit 7 Reserved, must be kept at reset value.
Bit 6 FACCEN: Flash access enable
Enables NOR Flash memory access operations.
0: Corresponding NOR Flash memory access is disabled.
1: Corresponding NOR Flash memory access is enabled (default after reset).
Bits 5:4 MWID[1:0]: Memory data bus width
Defines the external memory device width, valid for all type of memories.
00: 8 bits
01: 16 bits (default after reset)
10: reserved
11: reserved

608/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Bits 3:2 MTYP[1:0]: Memory type

Defines the type of external memory attached to the corresponding memory bank.
00: SRAM/FRAM (default after reset for Bank 2...4)
01: PSRAM (CRAM) / FRAM
10: NOR Flash/OneNAND Flash (default after reset for Bank 1)
11: reserved
Bit 1 MUXEN: Address/data multiplexing enable bit
When this bit is set, the address and data values are multiplexed on the data bus, valid only with
NOR and PSRAM memories:
0: Address/data non multiplexed
1: Address/data multiplexed on databus (default after reset)
Bit 0 MBKEN: Memory bank enable bit
Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
disabled bank causes an ERROR on AHB bus.
0: Corresponding memory bank is disabled.
1: Corresponding memory bank is enabled.

SRAM/NOR-Flash chip-select timing register for bank x (FMC_BTRx)

Address offset: 0x04 + 8 * (x – 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then
this register is partitioned for write and read access, that is, 2 registers are available: one to
configure read accesses (this register) and one to configure write accesses (FMC_BWTRx
registers).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD[1:0] ACCMOD[1:0] DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 DATAHLD[1:0]: Data hold phase duration

These bits are written by software to define the duration of the data hold phase in HCLK
cycles (refer to Figure 54 to Figure 66), used in asynchronous accesses:
For read accesses
00: DATAHLD phase duration = 0 × HCLK clock cycle (default)
01: DATAHLD phase duration = 1 × HCLK clock cycle
10: DATAHLD phase duration = 2 × HCLK clock cycle
11: DATAHLD phase duration = 3 × HCLK clock cycle
For write accesses
00: DATAHLD phase duration = 1 × HCLK clock cycle (default)
01: DATAHLD phase duration = 2 × HCLK clock cycle
10: DATAHLD phase duration = 3 × HCLK clock cycle
11: DATAHLD phase duration = 4 × HCLK clock cycle

RM0438 Rev 7 609/2194

628
Flexible static memory controller (FSMC) RM0438

Bits 29:28 ACCMOD[1:0]: Access mode

Specifies the asynchronous access modes as shown in the timing diagrams. These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory
For synchronous access with read/write Burst mode enabled (BURSTEN / CBURSTRW bits
set), defines the number of memory clock cycles (+2) to issue to the memory before
reading/writing the first data:
This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.
For asynchronous access, this value is don't care.
0000: Data latency of 2 CLK clock cycles for first burst access
1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)
Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:
0000: FMC_CLK period= 1x HCLK period
0001: FMC_CLK period = 2 × HCLK periods
0010: FMC_CLK period = 3 × HCLK periods
1111: FMC_CLK period = 16 × HCLK periods (default value after reset)
In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.
Note: Refer to Section 19.6.5: Synchronous transactions for FMC_CLK divider ratio formula)
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of current read or write
transaction to next transaction on the same bank.
This delay allows to match the minimum time between consecutive transactions (tEHEL from
NEx high to NEx low) and the maximum time needed by the memory to free the data bus
after a read access (tEHQZ, chip enable high to output Hi-Z). This delay is recommended for
mode D and muxed mode. For non-muxed memory, the bus turnaround delay can be set to
minimum value.
(BUSTURN + 1)HCLK period ≥ max(tEHEL min, tEHQZ max)
For FRAM memories, the bus turnaround delay should be configured to match the minimum
tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive
transactions on the same bank (read/read, write/write, read/write and write/read) to match the
tPC memory timing. The chip select is toggling between any consecutive accesses.
(BUSTURN + 1)HCLK period ≥ tPC min

0000: BUSTURN phase duration = 1 HCLK clock cycle added

...
1111: BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset)

610/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Bits 15:8 DATAST[7:0]: Data-phase duration

These bits are written by software to define the duration of the data phase (refer to Figure 54
to Figure 66), used in asynchronous accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, refer to the respective figure
(Figure 54 to Figure 66).
Example: Mode 1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK
clock cycles.
Note: In synchronous accesses, this value is don’t care.
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
These bits are written by software to define the duration of the address hold phase (refer to
Figure 54 to Figure 66), used in mode D or multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration =1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, refer to the respective figure (Figure 54
to Figure 66).
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
memory clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 54 to Figure 66), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, refer to the respective figure
(Figure 54 to Figure 66).
Note: In synchronous accesses, this value is don’t care.
In Muxed mode or mode D, the minimum value for ADDSET is 1.
In mode 1 and PSRAM memory, the minimum value for ADDSET is 1.

Note: PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency
phase soon and starts sampling NWAIT from memory, then starts to read or write when the
memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).

RM0438 Rev 7 611/2194

628
Flexible static memory controller (FSMC) RM0438

SRAM/NOR-Flash write timing registers x (FMC_BWTRx)

Address offset: 0x104 + 8 * (x – 1), (x = 1 to 4)
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx
register, then this register is active for write access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAHLD[1:0] ACCMOD[1:0] Res. Res. Res. Res. Res. Res. Res. Res. BUSTURN[3:0]

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 DATAHLD[1:0]: Data hold phase duration

These bits are written by software to define the duration of the data hold phase in HCLK cycles
(refer to Figure 54 to Figure 66), used in asynchronous write accesses:
00: DATAHLD phase duration = 1 × HCLK clock cycle (default)
01: DATAHLD phase duration = 2 × HCLK clock cycle
10: DATAHLD phase duration = 3 × HCLK clock cycle
11: DATAHLD phase duration = 4 × HCLK clock cycle
Bits 29:28 ACCMOD[1:0]: Access mode.
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: Access mode A
01: Access mode B
10: Access mode C
11: Access mode D
Bits 27:20 Reserved, must be kept at reset value.
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of current write transaction to next
transaction on the same bank.
For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC
(precharge time) timings. The bus turnaround delay is inserted between any consecutive
transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is
toggling between any consecutive accesses.
(BUSTURN + 1)HCLK period ≥ tPC min

0000: BUSTURN phase duration = 1 HCLK clock cycle added

...
1111: BUSTURN phase duration = 16 x HCLK clock cycles added (default value after reset)

612/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Bits 15:8 DATAST[7:0]: Data-phase duration.

These bits are written by software to define the duration of the data phase (refer to Figure 54 to
Figure 66), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 63 to Figure 66), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK cycles
(refer to Figure 54 to Figure 66), used in asynchronous accesses:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.

PSRAM chip select counter register (FMC_PCSCNTR)

Address offset: 0x20
Reset value: 0x0000 0000
This register contains the PSRAM chip select counter value for Synchronous and
Asynchronous modes. The chip select counter is common to all banks and can be enabled
separately on each bank. During PSRAM read or write accesses, this value is loaded into a
timer which is decremented while the NE signal is held low. When the timer reaches 0, the
PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh, and
restarts a new access. The programmed counter value guarantees a maximum NE pulse
width (tCEM) as specified for PSRAM devices. The counter is reloaded and starts
decrementing each time a new access is started by a transition of NE from high to low.
h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CNTB4EN

CNTB3EN

CNTB2EN

CNTB1EN

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSCOUNT[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 613/2194

628
Flexible static memory controller (FSMC) RM0438

Bits 31:20 Reserved, must be kept at reset value.

Bit 19 CNTB4EN: Counter Bank 4 enable
This bit enables the chip select counter for PSRAM/NOR Bank 4.
0: Counter disabled for Bank 4
1: Counter enabled for Bank 4
Bit 18 CNTB3EN: Counter Bank 3 enable
This bit enables the chip select counter for PSRAM/NOR Bank 3.
0: Counter disabled for Bank 3.
1: Counter enabled for Bank 3
Bit 17 CNTB2EN: Counter Bank 2 enable
This bit enables the chip select counter for PSRAM/NOR Bank 2.
0: Counter disabled for Bank 2
1: Counter enabled for Bank 2
Bit 16 CNTB1EN: Counter Bank 1 enable
This bit enables the chip select counter for PSRAM/NOR Bank 1.
0: Counter disabled for Bank 1
1: Counter enabled for Bank 1
Bits 15:0 CSCOUNT[15:0]: Chip select counter.
These bits are written by software to define the maximum chip select low pulse duration. It is
expressed in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous
accesses.
The counter is disabled if the programmed value is 0.

19.7 NAND Flash controller

The FMC generates the appropriate signal timings to drive the following types of device:
• 8- and 16-bit NAND Flash memories
The NAND bank is configured through dedicated registers (Section 19.7.7). The
programmable memory parameters include access timings (shown in Table 145) and ECC
configuration.

Table 145. Programmable NAND Flash access parameters

Parameter Function Access mode Unit Min. Max.

Number of clock cycles (HCLK)

Memory setup AHB clock cycle
required to set up the address Read/Write 1 255
time (HCLK)
before the command assertion
Minimum duration (in HCLK clock AHB clock cycle
Memory wait Read/Write 2 255
cycles) of the command assertion (HCLK)

614/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Table 145. Programmable NAND Flash access parameters (continued)

Parameter Function Access mode Unit Min. Max.

Number of clock cycles (HCLK)

during which the address must be
AHB clock cycle
Memory hold held (as well as the data if a write Read/Write 1 254
(HCLK)
access is performed) after the
command de-assertion
Number of clock cycles (HCLK)
Memory during which the data bus is kept AHB clock cycle
Write 1 255
databus high-Z in high-Z state after a write (HCLK)
access has started

19.7.1 External memory interface signals

The following tables list the signals that are typically used to interface NAND Flash memory.
Note: The prefix “N” identifies the signals which are active low.

8-bit NAND Flash memory

Table 146. 8-bit NAND Flash

FMC signal name I/O Function

A[17] O NAND Flash address latch enable (ALE) signal

A[16] O NAND Flash command latch enable (CLE) signal
D[7:0] I/O 8-bit multiplexed, bidirectional address/data bus
NCE O Chip select
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT I NAND Flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

RM0438 Rev 7 615/2194

628
Flexible static memory controller (FSMC) RM0438

16-bit NAND Flash memory

Table 147. 16-bit NAND Flash

FMC signal name I/O Function

A[17] O NAND Flash address latch enable (ALE) signal

A[16] O NAND Flash command latch enable (CLE) signal
D[15:0] I/O 16-bit multiplexed, bidirectional address/data bus
NCE O Chip select
NOE(= NRE) O Output enable (memory signal name: read enable, NRE)
NWE O Write enable
NWAIT/INT I NAND Flash ready/busy input signal to the FMC

Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.

616/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

19.7.2 NAND Flash supported memories and transactions

Table 148 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND Flash controller are shown in gray.

Table 148. Supported memories and transactions

AHB Memory Allowed/
Device Mode R/W Comments
data size data size not allowed

Asynchronous R 8 8 Y -
Asynchronous W 8 8 Y -
Asynchronous R 16 8 Y Split into 2 FMC accesses
NAND 8-bit
Asynchronous W 16 8 Y Split into 2 FMC accesses
Asynchronous R 32 8 Y Split into 4 FMC accesses
Asynchronous W 32 8 Y Split into 4 FMC accesses
Asynchronous R 8 16 Y -
Asynchronous W 8 16 N -
Asynchronous R 16 16 Y -
NAND 16-bit
Asynchronous W 16 16 Y -
Asynchronous R 32 16 Y Split into 2 FMC accesses
Asynchronous W 32 16 Y Split into 2 FMC accesses

19.7.3 Timing diagrams for NAND Flash memory

The NAND Flash memory bank is managed through a set of registers:
• Control register: FMC_PCR
• Interrupt status register: FMC_SR
• ECC register: FMC_ECCR
• Timing register for Common memory space: FMC_PMEM
• Timing register for Attribute memory space: FMC_PATT
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any NAND Flash access, plus one parameter that
defines the timing for starting driving the data bus when a write access is performed.
Figure 72 shows the timing parameter definitions for common memory accesses, knowing
that Attribute memory space access timings are similar.

RM0438 Rev 7 617/2194

628
Flexible static memory controller (FSMC) RM0438

Figure 72. NAND Flash controller waveforms for common memory access

HCLK

A[25:0]

NCEx

NREG, High
NIOW,
NIOR MEMxSET
+1 MEMxWAIT + 1 MEMxHOLD
NWE,
NOE (1)
MEMxHIZ + 1
write_data

read_data Valid

MS33733V3

1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is
(MEMHOLD + 2) HCLK cycles.

19.7.4 NAND Flash operations

The command latch enable (CLE) and address latch enable (ALE) signals of the NAND
Flash memory device are driven by address signals from the FMC controller. This means
that to send a command or an address to the NAND Flash memory, the CPU has to perform
a write to a specific address in its memory space.
A typical page read operation from the NAND Flash device requires the following steps:
1. Program and enable the corresponding memory bank by configuring the FMC_PCR
and FMC_PMEM (and for some devices, FMC_PATT, see Section 19.7.5: NAND Flash
prewait functionality) registers according to the characteristics of the NAND Flash
memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, PWAITEN =
0 or 1 as needed, see Section 19.5.2: NAND Flash memory address mapping for
timing configuration).
2. The CPU performs a byte write to the common memory space, with data byte equal to
one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The
LE input of the NAND Flash memory is active during the write strobe (low pulse on
NWE), thus the written byte is interpreted as a command by the NAND Flash memory.
Once the command is latched by the memory device, it does not need to be written
again for the following page read operations.
3. The CPU can send the start address (STARTAD) for a read operation by writing four
bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9],
STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories)
in the common memory or attribute space. The ALE input of the NAND Flash device is
active during the write strobe (low pulse on NWE), thus the written bytes are
interpreted as the start address for read operations. Using the attribute memory space
makes it possible to use a different timing configuration of the FMC, which can be used

618/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

to implement the prewait functionality needed by some NAND Flash memories (see
details in Section 19.7.5: NAND Flash prewait functionality).
4. The controller waits for the NAND Flash memory to be ready (R/NB signal high), before
starting a new access to the same or another memory bank. While waiting, the
controller holds the NCE signal active (low).
5. The CPU can then perform byte read operations from the common memory space to
read the NAND Flash page (data field + Spare field) byte by byte.
6. The next NAND Flash page can be read without any CPU command or address write
operation. This can be done in three different ways:
– by simply performing the operation described in step 5
– a new random address can be accessed by restarting the operation at step 3
– a new command can be sent to the NAND Flash device by restarting at step 2

19.7.5 NAND Flash prewait functionality

Some NAND Flash devices require that, after writing the last part of the address, the
controller waits for the R/NB signal to go low. (see Figure 73).

Figure 73. Access to non ‘CE don’t care’ NAND-Flash

1. CPU wrote byte 0x00 at address 0x7001 0000.

2. CPU wrote byte A7~A0 at address 0x7002 0000.
3. CPU wrote byte A16~A9 at address 0x7002 0000.
4. CPU wrote byte A24~A17 at address 0x7002 0000.
5. CPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT timing
definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that
NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where
NCE is not don’t care).

RM0438 Rev 7 619/2194

628
Flexible static memory controller (FSMC) RM0438

When this functionality is required, it can be ensured by programming the MEMHOLD value
to meet the tWB timing. However any CPU read access to the NAND Flash memory has a
hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of
(MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next
access.
To cope with this timing constraint, the attribute memory space can be used by
programming its timing register with an ATTHOLD value that meets the tWB timing, and by
keeping the MEMHOLD value at its minimum value. The CPU must then use the common
memory space for all NAND Flash read and write accesses, except when writing the last
address byte to the NAND Flash device, where the CPU must write to the attribute memory
space.

19.7.6 Computation of the error correction code (ECC)

in NAND Flash memory
The FMC NAND Card controller includes two error correction code computation hardware
blocks, one per memory bank. They reduce the host CPU workload when processing the
ECC by software.
These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a
consequence, no hardware ECC computation is available for memories connected to
Bank 4.
The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit
error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the
NAND Flash memory. It is based on the Hamming coding algorithm and consists in
calculating the row and column parity.
The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and
NWE) each time the NAND Flash memory bank is active.
The ECC operates as follows:
• When accessing NAND Flash memory bank 2 or bank 3, the data present on the
D[15:0] bus is latched and used for ECC computation.
• When accessing any other address in NAND Flash memory, the ECC logic is idle, and
does not perform any operation. As a result, write operations to define commands or
addresses to the NAND Flash memory are not taken into account for ECC
computation.
Once the desired number of bytes has been read/written from/to the NAND Flash memory
by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value.
Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new
data block, the ECCEN bit must be set to one in the FMC_PCR registers.

620/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

To perform an ECC computation:

1. Enable the ECCEN bit in the FMC_PCR register.
2. Write data to the NAND Flash memory page. While the NAND page is written, the ECC
block computes the ECC value.
3. Read the ECC value available in the FMC_ECCR register and store it in a variable.
4. Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back
the written data from the NAND page. While the NAND page is read, the ECC block
computes the ECC value.
5. Read the new ECC value available in the FMC_ECCR register.
6. If the two ECC values are the same, no correction is required, otherwise there is an
ECC error and the software correction routine returns information on whether the error
can be corrected or not.

19.7.7 NAND Flash controller registers

NAND Flash control registers (FMC_PCR)
Address offset: 0x80
Reset value: 0x0000 0018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ECCPS[2:0] TAR3

rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAR[2:0] TCLR[3:0] Res. Res. ECCEN PWID[1:0] PTYP PBKEN PWAITEN Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:17 ECCPS[2:0]: ECC page size
Defines the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Bits 16:13 TAR[3:0]: ALE to RE delay
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.

RM0438 Rev 7 621/2194

628
Flexible static memory controller (FSMC) RM0438

Bits 12:9 TCLR[3:0]: CLE to RE delay

Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value.
Bit 6 ECCEN: ECC computation logic enable bit
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Bits 5:4 PWID[1:0]: Data bus width
Defines the external memory device width.
00: 8 bits
01: 16 bits (default after reset).
10: reserved.
11: reserved.
Bit 3 PTYP: Memory type
Defines the type of device attached to the corresponding memory bank:
0: Reserved, must be kept at reset value
1: NAND Flash (default after reset)
Bit 2 PBKEN: NAND Flash memory bank enable bit
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Bit 1 PWAITEN: Wait feature enable bit
Enables the Wait feature for the NAND Flash memory bank:
0: disabled
1: enabled
Bit 0 Reserved, must be kept at reset value.

622/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

FIFO status and interrupt register (FMC_SR)

Address offset: 0x84
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a
FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.
This is used to quickly write to the FIFO and free the AHB for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO into the memory. One of these
register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC,
the software must consequently wait until the FIFO is empty.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. FEMPT IFEN ILEN IREN IFS ILS IRS

r rw rw rw rw rw rw

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 FEMPT: FIFO empty
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
Bit 5 IFEN: Interrupt falling edge detection enable bit
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
Bit 4 ILEN: Interrupt high-level detection enable bit
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
Bit 3 IREN: Interrupt rising edge detection enable bit
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled
Bit 2 IFS: Interrupt falling edge status
The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
Note: If this bit is written by software to 1 it is set.
Bit 1 ILS: Interrupt high-level status
The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred

RM0438 Rev 7 623/2194

628
Flexible static memory controller (FSMC) RM0438

Bit 0 IRS: Interrupt rising edge status

The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it is set.

Common memory space timing register (FMC_PMEM)

Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND Flash
memory bank. This information is used to access either the common memory space of the
NAND Flash for command, address write access and data read/write access.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMHIZ[7:0] MEMHOLD[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MEMWAIT[7:0] MEMSET[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the
start of a NAND Flash write access to common memory space on socket. This is only valid
for write transactions:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Bits 23:16 MEMHOLD[7:0]: Common memory hold time
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write accesses) after the
command is deasserted (NWE, NOE), for NAND Flash read or write access to common
memory space on socket x:
0000 0000: reserved.
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Bits 15:8 MEMWAIT[7:0]: Common memory wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to common memory space on socket. The
duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.

624/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

Bits 7:0 MEMSET[7:0]: Common memory x setup time

Defines the number of HCLK (+1) clock cycles to set up the address before the command
assertion (NWE, NOE), for NAND Flash read or write access to common memory space on
socket x:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved

Attribute memory space timing register (FMC_PATT)

Address offset: 0x8C
Reset value: 0xFCFC FCFC
The FMC_PATT read/write register contains the timing information for NAND Flash memory
bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the
last address write access if the timing must differ from that of previous accesses (for
Ready/Busy management, refer to Section 19.7.5: NAND Flash prewait functionality).

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ATTHIZ[7:0] ATTHOLD[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ATTWAIT[7:0] ATTSET[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time

Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the
start of a NAND Flash write access to attribute memory space on socket. Only valid for writ
transaction:
0000 0000: 0 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Bits 23:16 ATTHOLD[7:0]: Attribute memory hold time
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write access) after the command
deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space
on socket:
0000 0000: reserved
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Bits 15:8 ATTWAIT[7:0]: Attribute memory wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to attribute memory space on socket x. The
duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.

RM0438 Rev 7 625/2194

628
Flexible static memory controller (FSMC) RM0438

Bits 7:0 ATTSET[7:0]: Attribute memory setup time

Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on
socket:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.

ECC result registers (FMC_ECCR)

Address offset: 0x94
Reset value: 0x0000 0000
This register contain the current error correction code value computed by the ECC
computation modules of the FMC NAND controller. When the CPU reads the data from a
NAND Flash memory page at the correct address (refer to Section 19.7.6: Computation of
the error correction code (ECC) in NAND Flash memory), the data read/written from/to the
NAND Flash memory are processed automatically by the ECC computation module. When
X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU
must read the computed ECC value from the FMC_ECC registers. It then verifies if these
computed parity data are the same as the parity value recorded in the spare area, to
determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register
should be cleared after being read by setting the ECCEN bit to 0. To compute a new data
block, the ECCEN bit must be set to 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC[31:16]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC[15:0]

r r r r r r r r r r r r r r r r

Bits 31:0 ECC[31:0]: ECC result

This field contains the value computed by the ECC computation logic. Table 149 describes
the contents of these bitfields.

Table 149. ECC result relevant bits

ECCPS[2:0] Page size in bytes ECC bits

000 256 ECC[21:0]

001 512 ECC[23:0]
010 1024 ECC[25:0]
011 2048 ECC[27:0]
100 4096 ECC[29:0]
101 8192 ECC[31:0]

626/2194 RM0438 Rev 7

RM0438 Flexible static memory controller (FSMC)

19.7.8 FMC register map

Table 150. FMC register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD
CCLKEN

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WFDIS

WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
FMC_BCR1 SET
0x00 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 1

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_BCR2 SET
0x08 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_BCR3 SET
0x10 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0

ASYNCWAIT
CBURSTRW

BURSTEN
WAITCFG

WAITPOL
EXTMOD

FACCEN
NBL

WAITEN

MUXEN
MBKEN
WREN
CPSIZE MWID MTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
FMC_BCR4 SET
0x18 [2:0] [1:0] [1:0]
[1:0]

Reset value 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
FMC_BTR1 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x04 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
FMC_BTR2 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x0C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
FMC_BTR3 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x14 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
FMC_BTR4 DATLAT[3:0] CLKDIV[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x1C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CNTB4EN
CNTB3EN
CNTB2EN
CNTB1EN

FMC_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CSCOUNT[15:0]
0x20 PCSCNTR

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

FMC_BWTR1 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

0x104 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RM0438 Rev 7 627/2194

628
Flexible static memory controller (FSMC) RM0438

Table 150. FMC register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DATAHLD[1:0]

ACCMOD[1:0]
BUSTURN

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BWTR2 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x10C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BWTR3 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x114 [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DATAHLD[1:0]

ACCMOD[1:0]

BUSTURN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BWTR4 DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x11C [3:0]

Reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

PWAITEN
ECCEN

PBKEN
ECCPS PWID

PTYP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

Res.
FMC_PCR TAR[3:0] TCLR[3:0]
0x80 [2:0] [1:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

FEMPT

IREN
IFEN
ILEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

IRS
FMC_SR

IFS
ILS
0x84
Reset value 1 0 0 0 0 0 0
FMC_PMEM MEMHIZx[7:0] MEMHOLDx[7:0] MEMWAITx[7:0] MEMSETx[7:0]
0x88
Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0
FMC_PATT ATTHIZ[7:0] ATTHOLD[7:0] ATTWAIT[7:0] ATTSET[7:0]
0x8C
Reset value 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0
FMC_ECCR ECCx[31:0]
0x94
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

628/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20 Octo-SPI interface (OCTOSPI)

20.1 Introduction
The OCTOSPI supports most external serial memories such as serial PSRAMs, serial
NAND and serial NOR Flash memories, HyperRAM™ and HyperFlash™ memories, with
the following functional modes:
• Indirect mode: all the operations are performed using the OCTOSPI registers to preset
commands, addresses, data and transfer parameters.
• Automatic status-polling mode: the external memory status register is periodically read
and an interrupt can be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped and it is seen by the
system as if it was an internal memory, supporting both read and write operations.
The OCTOSPI supports the following protocols with associated frame formats:
• the Regular-command frame format with the command, address, alternate byte,
dummy cycles and data phase
• the HyperBus™ frame format

20.2 OCTOSPI main features

• Functional modes: Indirect, Automatic status-polling, and Memory-mapped
• Read and write support in Memory-mapped mode
• External (P)SRAM memory support
• Support for single, dual, quad and octal communication
• Dual-quad configuration, where eight bits can be sent/received simultaneously by
accessing two quad memories in parallel
• SDR (single-data rate) and DTR (double-transfer rate) support
• Data strobe support
• Fully programmable opcode
• Fully programmable frame format
• Support wrapped-type access to memory in read direction
• HyperBus support
• Integrated FIFO for reception and transmission
• Asynchronous bus clock versus kernel clock support
• 8-, 16-, and 32-bit data accesses allowed
• DMA channel for Indirect mode operations
• Interrupt generation on FIFO threshold, timeout, operation complete, and access error
• AHB interface with transaction acceptance limited to one: the interface accepts the next
transfer on AHB bus only once the previous is completed on memory side.

RM0438 Rev 7 629/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.3 OCTOSPI implementation

Table 151. OCTOSPI implementation
OCTOSPI feature OCTOSPI1

HyperBus standard compliant X

Xcella standard compliant X
XSPI (JEDEC251ES) standard compliant X
AMBA® AHB compliant data interface X
Asynchronous AHB clock versus kernel clock X
Functional modes: Indirect, Automatic status-polling, and Memory-mapped X
Read and write support in Memory-mapped mode X
Dual-quad configuration X
SDR (single-data rate) and DTR (double-transfer rate) X
Data strobe (DS,DQS) X
Fully programmable opcode X
Fully programmable frame format X
Integrated FIFO for reception and transmission X
8-, 16-, and 32-bit data accesses X
Interrupt on FIFO threshold, timeout, operation complete, and access error X
Extended CSHT timeout -
Memory-mapped write X
Refresh counter X

630/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.4 OCTOSPI functional description

20.4.1 OCTOSPI block diagram

Figure 74. OCTOSPI block diagram in octal configuration

STM32 Octo-SPI
Registers/ Clock
memory
AHB control management
OCTOSPI_NCLK NCLK
OCTOSPI_CLK CLK
OCTOSPI_IO0 IO0
Data
OCTOSPI_IO1 IO1
octospi_ FIFO
OCTOSPI_IO2 IO2
ker_ck OCTOSPI_IO3 IO3
Shift OCTOSPI_IO4 IO4
register OCTOSPI_IO5 IO5
DMA signals OCTOSPI_IO6 IO6
5 OCTOSPI_IO7 IO7
Interrupts OCTOSPI_NCS NCS
OCTOSPI OCTOSPI_DQS DQS
MSv65072V2

Figure 75. OCTOSPI block diagram in quad configuration

STM32
AHB Registers/ Clock Quad-SPI
control management memory
octospi_
ker_ck OCTOSPI_CLK CLK
OCTOSPI_IO0 Q0/SI
Data FIFO OCTOSPI_IO1 Q1/SO
DMA signals Shift OCTOSPI_IO2 Q2/WP
register OCTOSPI_IO3 Q3/HOLD
5
OCTOSPI_NCS NCS
Interrupts OCTOSPI
6 MSv43486V3

RM0438 Rev 7 631/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Figure 76. OCTOSPI block diagram in dual-quad configuration

STM32
Registers/ Clock
Quad-SPI
control management
memory 1

OCTOSPI_CLK CLK
AHB OCTOSPI_IO0 Q0/SI
Data FIFO OCTOSPI_IO1 Q1/SO
octospi_ OCTOSPI_IO2 Q2/WP
ker_ck OCTOSPI_IO3 Q3/HOLD
OCTOSPI_NCS NCS

Shift
DMA signals Quad-SPI
register
5 memory 2
Interrupts
CLK
6
OCTOSPI_IO4 Q0/SI
OCTOSPI_IO5 Q1/SO
OCTOSPI_IO6 Q2/WP
OCTOSPI_IO7 Q3/HOLD
OCTOSPI
NCS

MSv43487V3

20.4.2 OCTOSPI interface to memory modes

The OCTOSPI supports the following protocols:
• Regular-command protocol
• HyperBus protocol
The OCTOSPI uses from 6 to 12 signals to interface with a memory, depending on the
functional mode:
• NCS: chip-select
• CLK: communication clock
• NCLK: inverted clock used only in the 1.8 V HyperBus protocol
• DQS: data strobe used only in Regular-command protocol as input only
• IO[3:0]: data bus LSB
• IO[7:4]: data bus MSB used in dual-quad and octal configurations

20.4.3 OCTOSPI Regular-command protocol

When in Regular-command protocol, the OCTOSPI communicates with the external device
using commands. Each command can include the following phases:
• Instruction phase
• Address phase
• Alternate-byte phase
• Dummy-cycle phase
• Data phase
Any of these phases can be configured to be skipped, but at least one of the instruction,
address, alternate byte, or data phases must be present.

632/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

The NCS falls before the start of each command and rises again after each command
finishes.
In Memory-mapped mode, both read and write operations are supported: as a
consequence, some of the configuration registers are duplicated to specify write operations
(read operations are configured using regular registers).

Figure 77. SDR read command in octal configuration

NCS

≈ ≈
CLK
Pre-drive

≈
IO[7:0] ECh 13h A[31:24] A[23:16] A[15:8] A[7:0] D0 D1 D2 D3

Address Dummy

MSv43488V1

The specific Regular-command protocol features are configured through the registers in the
0x0100-0x01FC offset range.

Instruction phase
During this phase, a 1- to 4-byte instruction is sent to the external device specifying the type
of operation to be performed. The size of the instruction to be sent is configured in
ISIZE[1:0] of OCTOSPI_CCR and the instruction is programmed in INSTRUCTION[31:0] of
OCTOSPI_IR.
The instruction phase can optionally send:
• 1 bit at a time from the IO0/SO signal (Single-SPI mode)
• 2 bits at a time (over IO0/IO1 in Dual-SPI mode)
• 4 bits at a time (over IO0 to IO3 in Quad-SPI mode)
• 8 bits at a time (over IO0 to IO7 in Octal-SPI mode).
This can be configured using IMODE[2:0] of OCTOSPI_CCR.
The instruction can be sent in DTR (double-transfer rate) mode on each rising and falling
edge of the clock, by setting IDTR in OCTOSPI_CCR.
When IMODE[2:0] = 000 in OCTOSPI_CCR, the instruction phase is skipped, and the
command sequence starts with the address phase, if present.
In Memory-mapped mode, the instruction used for the write operation is specified in
OCTOSPI_WIR and the instruction format is specified in OCTOSPI_WCCR. The instruction
used for the read operation and the instruction format are specified in OCTOSPI_IR and
OCTOSPI_CCR.

Address phase
In the address phase, 1 to 4 bytes are sent to the external device, to indicate the address of
the operation. The number of address bytes to be sent is configured in ADSIZE[1:0] of
OCTOSPI_CCR.
In Indirect and Automatic status-polling modes, the address bytes to be sent are specified in
ADDRESS[31:0] of OCTOSPI_AR. In Memory-mapped mode, the address is given directly
via the AHB (from any master in the system).

RM0438 Rev 7 633/2194

683
Octo-SPI interface (OCTOSPI) RM0438

The address phase can send:

• 1 bit at a time (over SOI in Single-SPI mode)
• 2 bits at a time (over IO0/IO1 in Dual-SPI mode)
• 4 bits at a time (over IO0 to IO3 in Quad-SPI mode)
• 8 bits at a time (over IO0 to IO7 in Octal-SPI mode)
This can be configured using ADMODE[2:0] of OCTOSPI_CCR.
The address can be sent in DTR mode (on each rising and falling edge of the clock) setting
ADDTR of OCTOSPI_CCR.
When ADMODE[2:0] = 000, the address phase is skipped and the command sequence
proceeds directly to the next phase, if any.
In Memory-mapped mode, the address format for the write operation is specified in
OCTOSPI_WCCR. The address format for the read operation is specified in
OCTOSPI_CCR.

Alternate-bytes phase
In the alternate-bytes phase, 1 to 4 bytes are sent to the external device, generally to control
the mode of operation. The number of alternate bytes to be sent is configured in
ABSIZE[1:0] of OCTOSPI_CCR. The bytes to be sent are specified in OCTOSPI_ABR.
The alternate-byte phase can send:
• 1 bit at a time (over SOI in Single-SPI mode)
• 2 bits at a time (over IO0/IO1 in Dual-SPI mode)
• 4 bits at a time (over IO0 to IO3 in Quad-SPI mode)
• 8 bits at a time (over IO0 to IO7 in Octal-SPI mode)
This can be configured using ABMODE[2:0] of OCTOSPI_CCR.
The alternate bytes can be sent in DTR mode (on each rising and falling edge of the clock)
setting ABDTR of OCTOSPI_CCR.
When ABMODE[2:0] = 000, the alternate-bytes phase is skipped and the command
sequence proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte
phase rather than a full byte, such as when the Dual-SPI mode is used and only two cycles
are used for the alternate bytes.
In this case, the firmware can use the Quad-SPI mode (ABMODE[2:0] = 011) and send a
byte with bits 7 and 3 of ALTERNATE[31:0] set to 1 (keeping the IO3 line high), and bits 6
and 2 set to 0 (keeping the IO2 line low), in OCTOSPI_IR.
The upper two bits of the nibble to be sent are then placed in bits 4:3 of ALTERNATE[31:0]
while the lower two bits are placed in bits 1:0. For example, if the nibble 2 (0010) is to be
sent over IO0/IO1, then ALTERNATE[31:0] must be set to 0x8A (1000_1010).
In Memory-mapped mode, the alternate bytes used for the write operation are specified in
OCTOSPI_WABR and the alternate byte format is specified in OCTOSPI_WCCR. The
alternate bytes used for read operation and the alternate byte format are specified in
OCTOSPI_ABR and OCTOSPI_CCR.

634/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Dummy-cycle phase
In the dummy-cycle phase, 1 to 31 cycles are given without any data being sent or received,
in order to give the external device, the time to prepare for the data phase when the higher
clock frequencies are used. The number of cycles given during this phase is specified in
DCYC[4:0] of OCTOSPI_TCR. In both SDR and DTR modes, the duration is specified as a
number of full CLK cycles.
When DCYC[4:0] = 00000, the dummy-cycle phase is skipped, and the command sequence
proceeds directly to the data phase, if present.
In order to assure enough “turn-around” time for changing the data signals from the output
mode to the input mode, there must be at least one dummy cycle when using the Dual-SPI,
the Quad-SPI or the Octal-SPI mode, to receive data from the external device.
In Memory-mapped mode, the dummy cycles for the write operations are specified in
OCTOSPI_WTCR. The dummy cycles for the read operation are specified in
OCTOSPI_TCR.

Data phase
During the data phase, any number of bytes can be sent to or received from the external
device.
In Indirect mode, the number of bytes to be sent/received is specified in OCTOSPI_DLR. In
this mode, the data to be sent to the external device must be written to OCTOSPI_DR, while
in Indirect-read mode the data received from the external device is obtained by reading
OCTOSPI_DR.
In Automatic status-polling mode, the number of bytes to be received is specified in
OCTOSPI_DLR and the data received from the external device can be obtained by reading
OCTOSPI_DR.
In Memory-mapped mode, the data read or written, is sent or received directly over the AHB
to the Cortex core or to a DMA.
The data phase can send/receive:
• 1 bit at a time (over SO/SI in Single-SPI mode)
• 2 bits at a time (over IO0/IO1 in Dual-SPI mode)
• 4 bits at a time (over IO0 to IO3 in Quad-SPI mode)
• 8 bits at a time (over IO0 to IO7 in Octal-SPI mode)
This can be configured using DMODE[2:0] of OCTOSPI_CCR.
The data can be sent or received in DTR mode (on each rising and falling edge of the clock)
setting DDTR of OCTOSPI_CCR.
When DMODE[2:0] = 000, the data phase is skipped, and the command sequence finishes
immediately by raising the NCS. This configuration must be used only in Indirect-write
mode.
In Memory-mapped mode, the data format for the write operation is specified in
OCTOSPI_WCCR. The data format for the read operation is specified in OCTOSPI_CCR.

DQS usage
The DQS signal can be used for data strobing during the read transactions when the device
toggles the DQS aligned with the data.

RM0438 Rev 7 635/2194

683
Octo-SPI interface (OCTOSPI) RM0438

The DQS management can be enabled by setting DQSE of OCTOSPI_CCR.

Figure 78. DTR read in Octal-SPI mode with DQS (Macronix mode) example

NCS

≈
CLK

≈
≈
DQS

≈
IO[7:0] EEh 11h A[31:24] A[23:16] A[15:8] A[7:0] D1 D0 D3 D2

Word Word
Address Dummy unit unit

MSv43489V1

20.4.4 OCTOSPI Regular-command protocol signal interface

Single-SPI mode
The legacy SPI mode allows just a single bit to be sent/received serially. In this mode, the
data is sent to the external device over the SO signal (whose I/Os are shared with IO0). The
data received from the external device arrives via SI (whose I/Os are shared with IO1).
The different phases can each be configured separately to use this Single-bit mode by
setting to 001 the IMODE, ADMODE, ABMODE, and DMODE fields in OCTOSPI_CCR and
OCTOSPI_WCCR.
In each phase configured in Single-SPI mode:
• IO0 (SO) is in output mode.
• IO1 (SI) is in input mode (high impedance).
• IO2 is in output mode and forced to 0 (to deactivate the “write protect” function).
• IO3 is in output mode and forced to 1 (to deactivate the “hold” function).
• IO4 to IO7 are in output mode and forced to 0.
This is the case even for the dummy phase if DMODE[2:0] = 001.

Dual-SPI mode
In Dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use Dual-SPI mode by setting
to 010 the IMODE,ADMODE, ABMODE, and DMODE fields in OCTOSPI_CCR and
OCTOSPI_WCCR.
In each phase configured in Dual-SPI mode:
• IO0/IO1 are at high-impedance (input) during the data phase for the read operations,
and outputs in all other cases.
• IO2 is in output mode and forced to 0.
• IO3 is in output mode and forced to 1.
• IO4 to IO7 are in output mode and forced to 0.

636/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

In the dummy phase when DMODE[2:0] = 010, IO0/IO1 are always high-impedance.

Quad-SPI mode
In Quad-SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3
signals.
The different phases can each be configured separately to use the Quad-SPI mode by
setting to 011 the IMODE,ADMODE, ABMODE, and DMODE fields in OCTOSPI_CCR and
OCTOSPI_WCCR.
In each phase configured in Quad-SPI mode:
• IO0 to IO3 are all at high-impedance (inputs) during the data phase for the read
operations, and outputs in all other cases.
• IO4 to IO7 are in output mode and forced to 0.
In the dummy phase when DMODE[2:0] = 011, IO0 to IO3 are all high-impedance.
IO2 and IO3 are used only in Quad-SPI mode. If none of the phases are configured to use
the Quad-SPI mode, then the pins corresponding to IO2 and IO3 can be used for other
functions even while the OCTOSPI is active.

Octal-SPI mode
In regular Octal-SPI mode, the eight bits are sent/received simultaneously over the IO[0:7]
signals.
The different phases can each be configured separately to use the Octal-SPI mode by
setting to 100 the IMODE,ADMODE, ABMODE, and DMODE fields in OCTOSPI_CCR and
OCTOSPI_WCCR.
In each phase that is configured in Octal-SPI mode, IO[0:7] are all at high-impedance (input)
during the data phase for read operations, and outputs in all other cases.
In the dummy phase when DMODE[2:0] = 100, IO[0:7] are all high-impedance.
IO[4:7] are used only in Octal-SPI mode. If none of the phases are configured to use
Octal-SPI mode, then the pins corresponding to IO[4:7] can be used for other functions even
while the OCTOSPI is active.

Single-data rate (SDR) mode

By default, all the phases operate in Single-data rate (SDR) mode.
In SDR mode, when the OCTOSPI drives the IO0/SO, IO1 to IO7 signals, these signals
transition only with the falling edge of CLK.
When receiving data in SDR mode, the OCTOSPI assumes that the external devices also
send the data using CLK falling edge. By default (when SSHIFT = 0 in OCTOSPI_TCR), the
signals are sampled using the following (rising) edge of CLK.

RM0438 Rev 7 637/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Figure 79. SDR write command in Octo-SPI mode example.

NCS

≈
CLK

≈
≈≈
IO[7:0] 02h FDh A[31:24] A[23:16] A[15:8] A[7:0] D0 D1 D254 D255

MSv43490V1

Double-transfer rate (DTR) mode

Each of the instruction, address, alternate-byte and data phases can be configured to
operate in DTR mode setting IDTR, ADDTR, ABDTR, and DDTR in OCTOSPI_CCR.
In Memory-mapped mode, the DTR mode for each phase of the write operations is specified
in OCTOSPI_WCCR. The DTR mode for each phase of the read operations is specified in
OCTOSPI_CCR.
In DTR mode, when the OCTOSPI drives the IO0/SO and IO1to IO7 signals in the
instruction, address, and alternate-byte phases, a bit is sent or received on each of the
falling and rising edges of CLK.
When receiving data in DTR mode, the OCTOSPI assumes that the external devices also
send the data using both CLK rising and falling edges. When DDTR = 1 in OCTOSPI_CCR,
the software must clear SSHIFT in OCTOSPI_TCR. Thus, the signals are sampled one half
of a CLK cycle later (on the following, opposite edge).
In DTR mode, it is recommended to set DHQC of OCTOSPI_TCR, to shift the outputs by a
quarter of cycle and avoid to hold issues on the memory side.
Note: DHQC must not be set when the prescaler value is 0, as this action leads to unpredictable
behavior.

Figure 80. DTR write in Octal-SPI mode (Macronix mode) example

NCS
≈

CLK
≈ ≈ ≈

IO[7:0] 02h FDh A[31:24] A[23:16] A[15:8] A[7:0] D1 D0 D255 D254

Word Unit Word Unit

MSv43491V1

Dual-quad configuration
When DMM = 1 in OCTOSPI_CR, the OCTOSPI is in dual-memory configuration: if
DMODE = 100,two external Quad-SPI devices (device A and device B) are used in order to
send/receive eight bits (or 16 bits in DTR mode) every cycle, effectively doubling the
throughput.
Each device (A or B) uses the same CLK and NCS signals, but each has separate IO0 to
IO3 signals.

638/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

The dual-quad configuration can be used in conjunction with the Single-SPI, Dual-SPI, and
Quad-SPI modes, as well as with either the SDR or DTR mode.
The device size, as specified in DEVSIZE[4:0] of OCTOSPI_DCR1, must reflect the total
external device capacity, that is the double of the size of one individual component.
If address X is even, then the byte that the OCTOSPI gives for address X is the byte at the
address X/2 of device A, and the byte that the OCTOSPI gives for address X + 1 is the byte
at the address X/2 of device B. In other words, the bytes at even addresses are all stored in
device A and the bytes at odd addresses are all stored in device B.
When reading the status registers of the devices in dual-quad configuration, twice as many
bytes must be read compared to the same read in Regular-command protocol: if each
device gives eight valid bits after the instruction for fetching the status register, then the
OCTOSPI must be configured with a data length of 2 bytes (16 bits), and the OCTOSPI
receives one byte from each device.
If each device gives a status of 16 bits, then the OCTOSPI must be configured to read
4 bytes to get all the status bits of both devices in dual-quad configuration. The
least-significant byte of the result (in the data register) is the least-significant byte of device
A status register. The next byte is the least-significant byte of device B status register. Then,
the third byte of the data register is the device A second byte. The forth byte is the device B
second byte (if devices have 16-bit status registers).
An even number of bytes must always be accessed in dual-quad configuration. For this
reason, bit 0 of DL[31:0] in OCTOSPI_DLR is stuck at 1 when DMM = 1.
In dual-quad configuration, the behavior of device A interface signals is basically the same
as in normal mode. Device B interface signals have exactly the same waveforms as
device A ones during the instruction, address, alternate-byte, and dummy-cycle phases. In
other words, each device always receives the same instruction and the same address.
Then, during the data phase, the AIOx and the BIOx buses both transfer data in parallel, but
the data that is sent to (or received from) device A is distinct than the one from device B.

20.4.5 HyperBus protocol

The OCTOSPI can communicate with the external device using the HyperBus protocol.
The HyperBus uses 11 to 12 pins depending on the operating voltage:
• IO[7:0] as bidirectional data bus
• RWDS for read and write data strobe and latency insertion (mapped on DQS pin)
• NCS
• CLK
• NCLK for 1.8 V operations
The HyperBus does not require any command specification nor any alternate bytes. As a
consequence, a separate register set is used to define the timing of the transaction.
The HyperBus frame is composed of the following phases:
• Command/address phase
• Data phase
The NCS falls before the start of a transaction and rises again after each transaction
finishes.

RM0438 Rev 7 639/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Figure 81. Example of HyperBus read operation

NCS

t RWR =Read write recovery t ACC = Initial access

CK

High = 2x Latency count

RWDS Low = 1x Latency count

RWDS and data

Latency count
are edge aligned.
47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1
DQ[7:0] A B A B

Command-Address
Memory drives DQ[7:0]
and RWDS.
Host drives DQ[7:0] and memory drives RWDS.
MSv43492V1

The specific HyperBus features are configured through the registers in the 0x0200-0x02FC
offset range.

Command/address phase
During this initial phase, the OCTOSPI sends 48 bits over IO[7:0] to specify the operations
to be performed with the external device.

Table 152. Command/address phase description

CA bit Bit name Description

47 R/W# Identifies the transaction as a read or a write.

46 Address space Indicates if the transaction accesses the memory or the register space.
45 Burst type Indicates if the burst is linear or wrapped.
Row and upper
44-16 Selects the row and the upper column addresses.
column address
15-3 Reserved -
Lower column
2-0 Selects the starting 16-bit word within the half page.
address

The address space is configured through the memory type MTYP[2:0] of OCTOSPI_DCR1.
The total size of the device is configured in DEVSIZE[4:0] of OCTOSPI_DCR1. In case of
multi-chip product (MCP), the device size is the sum of all the sizes of all the MCP dies.

Read/write operation with initial latency

The HyperBus read and write operations need to respect two timings:
• tRWR: minimal read/write recovery time for the device (defined in TRWR[7:0] of
OCTOSPI_HLCR)
• tACC: access time for the device (defined in TAC[7:0] of OCTOSPI_HLCR)

640/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

During the read operation, the RWDS is used by the device, in two ways (see Figure 81):
• during the command/address phase, to request an additional latency
• during the data phase, for data strobing
During the write operation the RWDS is used:
• by the device, during the command/address phase, to request an additional latency.
• by the OCTOSPI, during the data phase, for write data masking.

Figure 82. HyperBus write operation with initial latency

NCS

t RWR =Read Write Recovery tACC= Access

CK

High = 2x Latency count

Low = 1x Latency count
RWDS

CK and data
Latency count are center aligned
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 A B A B

Command-Address Host drives DQ[7:0]

and RWDS
Host drives DQ[7:0] and memory drives RWDS
MSv43494V1

Read/write operation with additional latency

If the device needs an additional latency (during refresh period of a SDRAM for example),
RWDS must be tied to one during one of the RWDS signals, during the command/address
phase.
An additional tACC duration is added by the OCTOSPI to meet the device request.

Figure 83. HyperBus read operation with additional latency

NCS
tRWR=Read write recovery Additional latency tACC = Access

CK
Latency count 1 Latency count 2

RWDS High = 2x Latency count

Low = 1x Latency count
RWDS and data
are edge aligned.

DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn

A
Dn
B
Dn+1
A
Dn+1
B

Command-Address Memory drives DQ[7:0]

and RWDS.
Host drives DQ[7:0] and memory drives RWDS.
MSv43495V1

RM0438 Rev 7 641/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Figure 84. HyperBus write operation with additional latency

NCS

Additional latency
tRWR= Read write recovery
t ACC = Initial access

CK

RWDS High = 2x Latency count

Low = 1x Latency count
CK and data
Latency count 1 Latency count 2 are center aligned.
Dn Dn Dn+1 Dn+1
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0
A B A B

Host drives DQ[7:0]

Command-Address and RWDS.
Host drives DQ[7:0] and memory drives RWDS.
MSv43496V1

Fixed-latency mode
Some devices or some applications may not want to operate with a variable latency time as
described above.
The latency can be forced to 2 x tACC by setting LM of OCTOSPI_HLCR.
In this OCTOSPI latency mode, the state of the RWDS signal is not taken into account by
the OCTOSPI and an additional latency is always added, leading to a fixed 2 x tACC latency
time.

Write operation with no latency

Some devices can also require a zero latency for the write operations. This write-zero
latency can be forced by setting WZL in OCTOSPI_HLCR.

Figure 85. HyperBus write operation with no latency

NCS

CK

RWDS Memory drives RWDS but master ignores

DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 15:8 7:0

Command-Address Data

MSv43497V1

642/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Latency on page-crossing during the read operations

An additional latency can be needed by some devices for the read operation when crossing
pages.
The initial latency must be respected for any page access, as a consequence, when the first
access is close to the page boundary, a latency is automatically added at the page crossing
to respect the tACC time.

Figure 86. HyperBus read operation page crossing with latency

12 clock 9 words
initial latency data
NCS

CK
3 clock initial page
crossing latency
RDS
DQ[7:0] A0 02 46 8A 80 07 dd dd dd dd dd dd dd dd dd dd dd dd dd dd

Read from Address = 123457h Address Address Address Address Address Address Address
123457 123458 12345D 12345E 12345F 123460 123461

MSv43498V2

20.4.6 Specific features

The OCTOSPI supports some specific features, such as:
• Wrap support
• NCS boundary and refresh

Wrap support
The OCTOSPI supports an hybrid wrap as defined by the HyperBus protocol. An hybrid
wrap is also supported in the Regular-command protocol.
In hybrid wrap, the transaction can continue after the initial wrap with an incremental
access.
The wrap size supported by the target memory is configured by WRAPSIZE in
OCTOSPI_DCR2.
Wrap is supported only in memory-read direction and only for data size = 4 bytes. Wrapped
reads are supported for both HyperBus and Regular-command protocols. To enable
wrapped-read accesses, the dedicated registers OCTOSPI_WPxxx must be programmed
according to the wrapped-read access characteristics. The dedicated OCTOSPI_WPxxx
registers apply for both HyperBus and Regular-command protocols.
If the target memory is not supporting the hybrid wrap, WRAPSIZE must be set to 0.

NCS boundary and refresh

Two processes can be activated to regulate the OCTOSPI transactions:
• NCS boundary
• Refresh
The NCS boundary feature limits a transaction to a boundary of aligned addresses. The size
of the address to be aligned with, is configured in CSBOUND[4:0] of OCTOSPI_DCR3 and it
is equal to 2CSBOUND.

RM0438 Rev 7 643/2194

683
Octo-SPI interface (OCTOSPI) RM0438

As an example, if CSBOUND(4:0] = 0x4, the boundary is set to 24 = 16 bytes. As a

consequence, the NCS is released each time that the LSB address is equal to 0xF and each
time that a new transaction is issued to address the next data.
If CSBOUND[4:0] = 0, the feature is disabled and a minimum value of 3 is recommended.
The NCS boundary feature cannot be used for Flash memory devices in write mode since a
command is necessary to program another page of the Flash memory.
The refresh feature limits the duration of the transactions to the value programmed in
REFRESH[31:0] of OCTOSPI_DCR4. The duration is expressed in number of cycles. This
allows an external RAM to perform its internal refresh operation regularly.
The refresh value must be greater than the minimal transaction size in terms of number of
cycles including the command/address/alternate/dummy phases.
If NCS boundary and refresh are enabled at the same time, the NCS is released on the first
condition met.

Re-starting after an interrupted transfer

When a read or write operation is interrupted by a timeout or communication regulation
feature, the Octo-SPI interface, as soon as possible after getting back the port ownership,
re-issues the initial command sequence together with the address following the last address
actually accessed before interruption. The transfer initially set goes on and ends
seamlessly.

20.4.7 OCTOSPI operating modes introduction

The OCTOSPI has the following operating modes regardless of the low-level protocol used
(either Regular-command or HyperBus):
• Indirect mode (read or write)
• Automatic status-polling mode
• Memory-mapped mode

20.4.8 OCTOSPI Indirect mode

In Indirect mode, the commands are started by writing to the OCTOSPI registers and the
data is transferred by writing or reading the data register, in a similar way to other
communication peripherals.
When FMODE[1:0] = 0 in OCTOSPI_CR, the OCTOSPI is in Indirect-write mode: bytes are
sent to the external device during the data phase. Data is provided by writing to
OCTOSPI_DR.
When FMODE[1:0] = 01, the OCTOSPI is in Indirect-read mode: bytes are received from
the external device during the data phase. Data is recovered by reading OCTOSPI_DR.
In Indirect mode, when the OCTOSPI is configured in DTR mode over eight lanes with DQS
disabled, the given starting address and the data length must be even.
Note: The OCTOSPI_AR register must be updated even if the start address is the same as the
start address of the previous indirect access

644/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

The number of bytes to be read/written is specified in OCTOSPI_DLR:

• If DL[31:0] = 0xFFFF FFFF, the data length is considered undefined and the OCTOSPI
simply continues to transfer data until it reaches the end of the external device (as
defined by DEVSIZE). If no bytes are to be transferred, DMODE[2:0] must be set to 0 in
OCTOSPI_CCR.
• If DL[31:0] = 0xFFFF FFFFF and DEVSIZE[4:0] = 0x1F (its maximum value indicating
at 4-Gbyte device), the transfers continue indefinitely, stopping only after an abort
request or after the OCTOSPI is disabled. After the last memory address is read (at
address 0xFFFF FFFF), reading continues with address = 0x0000 0000.
When the programmed number of bytes to be transmitted or received is reached, TCF bit is
set in OCTOSPI_SR and an interrupt is generated if TCIE = 1 in OCTOSPI_CR. In the case
of an undefined number of data, TCF is set when the limit of the external SPI memory is
reached, according to the device size defined in OCTOSPI_DCR1.

Triggering the start of a transfer in Regular-command protocol

Depending on the OCTOSPI configuration, there are three different ways to trigger the start
of a transfer in Indirect mode when using Regular-command protocol. In general, the start of
transfer is triggered as soon as the software gives the last information that is necessary for
the command. More specifically in Indirect mode, a transfer starts when one of the following
sequence of events occurs:
• if no address is necessary (ADMODE[2:0] = 000) and if no data needs to be provided
by the software (FMODE[1:0] = 01 or DMODE[2:0] = 000), and at the moment when a
write is performed to INSTRUCTION[31:0] in OCTOSPI_IR
• if an address is necessary (when ADMODE[2:0] ≠ 000) and if no data needs to be
provided by the software (when FMODE[1:0] = 01 or DMODE[2:0] = 000), and at the
moment when a write is performed to ADDRESS[31:0] in OCTOSPI_AR
• if an address is necessary (when ADMODE[2:0] ≠ 000) and if data needs to be
provided by the software (when FMODE[1:0] = 00 and DMODE[2:0] ≠ 000), and at the
moment when a write is performed to DATA[31:0] in OCTOSPI_DR
A write to OCTOSPI_ABR never triggers the communication start. If alternate bytes are
required, they must have been programmed before.
As soon as a command is started, the BUSY bit is automatically set in OCTOSPI_SR.

Triggering the start of a transfer in HyperBus protocol

Depending on the OCTOSPI configuration, there are different ways to trigger the start of a
command in Indirect mode. In general, it is triggered as soon as the firmware gives the last
information that is necessary for the transfer to start, and more specifically, a communication
in Indirect mode is triggered by one of the following register settings, when it is the last one
to be executed:
• when a write is performed to ADDRESS[31:0] (OCTOSPI_AR) in Indirect-read mode
(when FMODE = 01).
• when a write is performed to DATA[31:0] (OCTOSPI_DR) in Indirect-write mode (when
FMODE = 00).
• when a write is performed to INSTRUCTION[31:0] (OCTOSPI_IR) for both Indirect
read and write modes
Note: In case of HyperBus, a (dummy) write to OCTOSPI_IR is required to trigger the transfer, as
for Regular-command protocol.

RM0438 Rev 7 645/2194

683
Octo-SPI interface (OCTOSPI) RM0438

As soon as a transfer is started, the BUSY bit (OCTOSPI_SR[5]) is automatically set.

FIFO and data management

Data in Indirect mode passes through a 32-byte FIFO that is internal to the OCTOSPI.
FLEVEL in OCTOSPI_SR indicates how many bytes are currently being held in the FIFO.
AHB burst transactions are supported. Data of the burst are successively written in
OCTOSPI_DR and immediately transferred in the internal FIFO.
In Indirect-write mode (FMODE[1:0] = 00), the software adds data to the FIFO when it writes
in OCTOSPI_DR. A word write adds 4 bytes to the FIFO, an half-word write adds 2 bytes,
and a byte write adds only 1 byte. If the software adds too many bytes to the FIFO (more
than indicated in DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write
operation (when TCF is set).
The byte/half-word accesses to OCTOSPI_DR must be done only to the least significant
byte/halfword of the 32-bit register.
FTHRES is used to define a FIFO threshold after which point the FIFO threshold flag, FTF,
gets set. In Indirect-read mode, FTF is set when the number of valid bytes to be read from
the FIFO is above the threshold. FTF is also set if there is any data left in the FIFO after the
last byte is read from the external device, regardless of FTHRES setting. In Indirect-write
mode, the FTF is set when the number of empty bytes in the FIFO is above the threshold.
If FTIE = 1, there is an interrupt when the FTF is set. If DMAEN = 1, a DMA transfer is
initiated when the FTF is set. The FTF is cleared by hardware as soon as the threshold
condition is no longer true (after enough data has been transferred by the CPU or DMA).
The last data read in RX FIFO remains valid as long as there is no request for the next line.
This means that, when the application reads several times in a row at the same location, the
data is provided from the RX FIFO and not read again from the distant memory.

20.4.9 OCTOSPI Automatic status-polling mode

In Automatic status-polling mode, the OCTOSPI periodically starts a command to read a
defined number of status bytes (up to four). The received bytes can be masked to isolate
some status bits and an interrupt can be generated when the selected bits have a defined
value.
The access to the device begins in the same manner as in Indirect-read mode. BUSY in
OCTOSPI_SR goes high at this point and stays high even between the periodic accesses.
The content of MASK[31:0] in OCTOSPI_PSMAR is used to mask the data from the
external device in Automatic status-polling mode:
• If the MASK[n] = 0, then bit n of the result is masked and not considered.
• If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n] in
OCTOSPI_PSMAR, then there is a match for bit n.
If PMM = 0 in OCTOSPI_CR, the AND-match mode is activated: SMF is set in
OCTOSPI_SR only when there is a match on all of the unmasked bits.
If PMM = 1 in OCTOSPI_CR, the OR-match mode is activated: SMF gets set if there is a
match on any of the unmasked bits.
An interrupt is called when SMF = 1 if SMIE = 1.

646/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

If APMS is set in OCTOSPI_CR, the operation stops and BUSY goes to 0 as soon as a
match is detected. Otherwise, BUSY stays at 1 and the periodic accesses continue until
there is an abort or until the OCTOSPI is disabled (EN = 0).
OCTOSPI_DR contains the latest received status bytes (FIFO deactivated). The content of
this register is not affected by the masking used in the matching logic. FTF in OCTOSPI_SR
is set as soon as a new reading of the status is complete. FTF is cleared as soon as the
data is read.
In Automatic status-polling mode, variable latency is not supported. As a consequence, the
memory must be configured in fixed latency.

20.4.10 OCTOSPI Memory-mapped mode

When configured in Memory-mapped mode, the external SPI device is seen as an internal
memory.
Note: More than 256 Mbytes can be addressed even if the external device capacity is larger.
If an access is made to an address outside of the range defined by DEVSIZE[4:0] but still
within the 256 Mbytes range, then an AHB error is given. The effect of this error depends on
the AHB master that attempted the access:
• If it is the Cortex CPU, a hard-fault interrupt is generated.
• If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
Byte, half-word, and word access types are all supported.
A support for execute in place (XIP) operation is implemented, where the OCTOSPI
continues to load the bytes to the addresses following the most recent access. If
subsequent accesses are continuous to the bytes that follow, then these operations ends up
quickly since their results were pre-fetched.
By default, the OCTOSPI never stops its prefetch operation, it either keeps the previous
read operation active with the NCS maintained low or it relaunches a new transfer, even if
no access to the external device occurs for a long time.
Since external devices tend to consume more when the NCS is held low, the application
may want to activate the timeout counter (TCEN = 1 in OCTOSPI_CR): the NCS is released
after a period defined by TIMEOUT[15:0] in OCTOSPI_LPTR, when x cycles have elapsed
without an access since the clock is inactive.
BUSY goes high as soon as the first memory-mapped access occurs. Because of the
prefetch operations, BUSY does not fall until there is an abort, or the peripheral is disabled.

20.4.11 OCTOSPI configuration introduction

The OCTOSPI configuration is done in three steps:
1. OCTOSPI system configuration
2. OCTOSPI device configuration
3. OCTOSPI mode configuration

RM0438 Rev 7 647/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.4.12 OCTOSPI system configuration

The OCTOSPI is configured using OCTOSPI_CR. The user must program:
• Functional mode with FMODE[1:0]
• Automatic status-polling mode behavior if needed with PMM and APMS
• FIFO level with FTHRES
• DMA usage with DMAEN
• Timeout counter usage with TCEN
• Dual-quad configuration, if needed, with DMM (only for Quad-SPI mode)
In case of an interrupt usage, the respective enable bit can also be set during this phase.
If the timeout counter is used, the timeout value is programmed in OCTOSPI_LPTR.
The DMA channel must not be enabled during the OCTOSPI configuration: it must be
enabled only when the operation is fully configured, to avoid any unexpected request
generation.
The DMA and OCTOSPI must be configured in a coherent manner regarding data length:
FTHRES value must reflect the DMA burst size.

20.4.13 OCTOSPI device configuration

The parameters related to the external device targeted are configured through
OCTOSPI_DCR1 and OCTOSPI_DCR2.The user must program:
• Device size with DEVSIZE[4:0]
• Chip-select minimum high time with CSHT[2:0]
• Clock mode with FRCK and CKMODE
• Device frequency with PRESCALER[7:0]
MTYP[2:0] defines the memory type to be used for 8-line modes:
• Micron mode with D0/D1 ordering in 8-data-bit mode (DMODE[2:0] = 100)
• Macronix mode with D1/D0 ordering in 8-data-bit mode (DMODE[2:0] = 100)
• HyperBus memory mode: the protocol follows the HyperBus specification, and an
8-data-bit DTR mode must be selected.
• HyperBus register mode, addressing register space: the memory-mapped accesses in
this mode must be non-cacheable, or the Indirect read/write modes must be used.
DEVSIZE[4:0] defines the size of external memory using the following formula:
Number of bytes in the device = 2[DEVSIZE+1]
where DEVSIZE+1 is the number of address bits required to address the external device.
The external device capacity can go up to 4 Gbytes (addressed using 32 bits) in Indirect
mode, but the addressable space in Memory-mapped mode is limited to 256 Mbytes.
If DMM = 1, DEVSIZE[4:0] indicates the total capacity of the two devices together.
When the OCTOSPI executes two commands, one immediately after the other, it raises the
chip-select signal (NCS) high between the two commands for only one CLK cycle by default.
If the external device requires more time between commands, the chip-select high time
CSHT[2:0] can be used to specify the minimum number of CLK cycles for which the NCS
must remain high.

648/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

CKMODE indicates the level that the CLK takes between commands (when NCS = 1).
In HyperBus protocol, the device timing (tACC and tRWR) and the Latency mode must be
configured in OCTOSPI_HLCR.

20.4.14 OCTOSPI Regular-command mode configuration

Indirect mode configuration
When FMODE[1:0] = 00, the Indirect-write mode is selected and data can be sent to the
external device. When FMODE[1:0] = 01, the Indirect-read mode is selected and data can
be read from the external device.
When the OCTOSPI is used in Indirect mode, the frames are constructed in the following
way:
1. Specify a number of data bytes to read or write in OCTOSPI_DLR.
2. Specify the frame timing in OCTOSPI_TCR.
3. Specify the frame format in OCTOSPI_CCR.
4. Specify the instruction in OCTOSPI_IR.
5. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR.
6. Specify the targeted address in OCTOSPI_AR.
7. Enable the DMA channel if needed.
8. Read/write the data from/to the FIFO through OCTOSPI_DR (if no DMA usage).
If neither the address register (OCTOSPI_AR) nor the data register (OCTOSPI_DR) need to
be updated for a particular command, then the command sequence starts as soon as
OCTOSPI_IR is written. This is the case when both ADMODE[2:0] and DMODE[2:0]
equal 000, or if just ADMODE[2:0] = 000 when in Indirect-read mode (FMODE[1:0] = 01).
When an address is required (ADMODE[2:0] ≠ 000) and the data register does not need to
be written (FMODE[1:0] = 01 or DMODE[2:0] = 000), the command sequence starts as
soon as the address is updated with a write to OCTOSPI_AR.
In case of data transmission (FMODE[1:0] = 00 and DMODE[2:0] ≠ 000), the
communication start is triggered by a write in the FIFO through OCTOSPI_DR.

Automatic status-polling mode configuration

The Automatic status-polling mode is enabled by setting FMODE[1:0] = 10. In this mode,
the programmed frame is sent and the data is retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
OCTOSPI_DLR, it is ignored and only 4 bytes are read.The periodicity is specified in
OCTOSPI_PIR.
Once the status data has been retrieved, the following can be processed:
• Set SMF (an interrupt is generated if enabled).
• Stop automatically the periodic retrieving of the status bytes.
The received value can be masked with the value stored in OCTOSPI_PSMKR, and can be
ORed or ANDed with the value stored in OCTOSPI_PSMAR.

RM0438 Rev 7 649/2194

683
Octo-SPI interface (OCTOSPI) RM0438

In case of a match, SMF is set and an interrupt is generated if enabled; The OCTOSPI can
be automatically stopped if AMPS is set. In any case, the latest retrieved value is available
in OCTOSPI_DR.
When the OCTOSPI is used in Automatic status-polling mode, the frames are constructed in
the following way:
1. Specify the input mask in OCTOSPI_PSMKR.
2. Specify the comparison value in OCTOSPI_PSMAR.
3. Specify the read period in OCTOSPI_PIR.
4. Specify a number of data bytes to read in OCTOSPI_DLR.
5. Specify the frame timing in OCTOSPI_TCR.
6. Specify the frame format in OCTOSPI_CCR.
7. Specify the instruction in OCTOSPI_IR.
8. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR.
9. Specify the optional targeted address in OCTOSPI_AR.
If the address register (OCTOSPI_AR) does not need to be updated for a particular
command, then the command sequence starts as soon as OCTOSPI_CCR is written. This
is the case when ADMODE[2:0] = 000.
When an address is required (ADMODE[2:0] ≠ 000), the command sequence starts as soon
as the address is updated with a write to OCTOSPI_AR.

Memory-mapped mode configuration

In Memory-mapped mode, the external device is seen as an internal memory but with some
latency during accesses. Read and write operations are allowed to the external device in
this mode.
It is not recommended to program the Flash memory using memory-mapped writes, as the
internal flags for erase or programming status have to be polled.
Memory-mapped mode is entered by setting FMODE[1:0] = 11 in OCTOSPI_CR.
The programmed instruction and frame are sent when an AHB master accesses the
memory mapped space.
The FIFO is used as a prefetch buffer to anticipate any linear reads. Any access to
OCTOSPI_DR in this mode returns zero.
The data length register (OCTOSPI_DLR) has no meaning in Memory-mapped mode.
When the OCTOSPI is used in Memory-mapped mode, the frames are constructed in the
following way:

650/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

1. Specify the frame timing in OCTOSPI_TCR for read operation.

2. Specify the frame format in OCTOSPI_CCR for read operation.
3. Specify the instruction in OCTOSPI_IR.
4. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_ABR for read operation.
5. Specify the frame timing in OCTOSPI_WTCR for write operation.
6. Specify the frame format in OCTOSPI_WCCR for write operation.
7. Specify the instruction in OCTOSPI_WIR.
8. Specify the optional alternate byte to be sent right after the address phase in
OCTOSPI_WABR for read operation.
All the configuration operations must be completed before the first access to the memory
area. On the first access, the OCTOSPI becomes busy, and no further configuration is
allowed.

OCTOSPI delayed data sampling when no DQS is used

By default, when no DQS is used, the OCTOSPI samples the data driven by the external
device one half of a CLK cycle after the external device drives the signal.
In case of any external signal delays, it may be useful to sample the data later. Using
SSHIFT in OCTOSPI_TCR, the sampling of the data can be shifted by half of a CLK cycle.
The firmware must clear SSHIFT when the data phase is configured in DTR mode
(DDTR = 1).

OCTOSPI delayed data sampling when DQS is used

When external DQS is used as a sampling clock, it can be shifted in time to compensate the
data propagation delay. This shift is performed by an external delay block located outside
the OCTOSPI. The control of this feature depends on the device implementation (see the
product reference manual for more details).
In certain configuration cases, this external delay block is implemented but is not useful, so
it can be bypassed by setting DLYBYP in OCTOSPI_DCR1.

Sending the instruction only once (SIOO)

A Flash memory can provide a mode where an instruction must be sent only with the first
command sequence, while subsequent commands start directly with the address. The user
can take advantage of this type of features using SIOO in OCTOSPI_CCR.
SIOO is valid for Memory-mapped mode only. If this bit is set, the instruction is sent only for
the first command following a write to OCTOSPI_CCR.
Subsequent command sequences skip the instruction phase, until there is a write to
OCTOSPI_CCR. SIOO has no effect when IMODE[1:0] = 00 (no instruction).
SIOO mode is not supported when any of the communication regulation, NCS boundary or
refresh features are used.

RM0438 Rev 7 651/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.4.15 OCTOSPI HyperBus protocol configuration

Indirect mode configuration
When FMODE[1:0] = 00, the Indirect-write mode is selected and data can be sent to the
external device. When FMODE[1:0] = 01, the Indirect-read mode is selected where data can
be read from the external device.
When the OCTOSPI is used in Indirect mode, the frames are constructed in the following
way:
1. Specify a number of data bytes to read or write in OCTOSPI_DLR.
2. Specify the targeted address in OCTOSPI_AR.
3. Make a write operation in OCTOSPI_IR and enable the DMA channel if needed.
4. Read/write the data from/to the FIFO through OCTOSPI_DR (if no DMA usage).
In Indirect-read mode, the command sequence starts as soon as the address is updated
with a write to OCTOSPI_AR.
In Indirect-write mode, the communication start is triggered by a write in the FIFO through
OCTOSPI_DR.

Automatic status-polling mode configuration

The Automatic status-polling mode is enabled setting FMODE[1:0] = 10. In this mode, the
programmed frame is sent and the data is retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
OCTOSPI_DLR, it is ignored and only 4 bytes are read. The periodicity is specified in
OCTOSPI_PIR.
Once the status data has been retrieved, it can be internally processed to:
• Set SMF (an interrupt is generated if enabled).
• Stop automatically the periodic retrieving of the status bytes.
The received value can be masked with the value stored in OCTOSPI_PSMKR and can be
ORed or ANDed with the value stored in OCTOSPI_PSMAR.
In case of a match, SMF is set and an interrupt is generated if enabled. The OCTOSPI can
be automatically stopped if AMPS is set.
In any case, the latest retrieved value is available in OCTOSPI_DR.
When the OCTOSPI is used in Automatic status-polling mode, the frames are constructed in
the following way:
1. Specify the input mask in OCTOSPI_PSMKR.
2. Specify the comparison value in OCTOSPI_PSMAR.
3. Specify the read period in OCTOSPI_PIR.
4. Specify a number of data bytes to read in OCTOSPI_DLR.
5. Specify the targeted address in OCTOSPI_AR.
The command sequence starts as soon as the address is updated with a write to
OCTOSPI_AR.

652/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Memory-mapped mode configuration

In Memory-mapped mode, the external device is seen as an internal memory but with some
latency during the accesses. Read and write operations are allowed to the external device in
this mode.
The Memory-mapped mode is entered by setting FMODE[1:0] = 11. The programmed
instruction and frame is sent when an AHB master accesses the memory mapped space.
The FIFO is used as a prefetch buffer to anticipate any linear reads. Any access to
OCTOSPI_DR in this mode returns zero.
The data length register (OCTOSPI_DLR) has no meaning in Memory-mapped mode.
All the configuration operation must be completed prior to the first access to the memory
area. On the first access, the OCTOSPI becomes busy, and no configuration is allowed.

20.4.16 OCTOSPI error management

A error can be generated in the following cases:
• in Indirect or Automatic status-polling mode, when a wrong address has been
programmed in OCTOSPI_AR (according to the device size defined by DEVSIZE[4:0]).
This sets TEF and an interrupt is generated if enabled.
• in Indirect mode, if the address plus the data length exceed the device size. TEF is set
as soon as the access is triggered.
• in Memory-mapped mode when an out-of-range access is done by an AHB master.
This generates an AHB error as a response to the faulty AHB request.
• when the Memory-mapped mode is disabled. An access to the memory-mapped area
generates an AHB error as a response to the faulty AHB request.
The OCTOSPI generates an AHB slave error in the following situations:
• Memory-mapped mode is disabled and an AHB read request occurs.
• Read or write address exceeds the size of the external memory.
• Abort is received while a read or write burst is ongoing.
• OCTOSPI is disabled while a read or write burst is ongoing.
• Write wrap burst is received.
• Write request is received while DQSE = 0 in OCTOSPI_WCCR, which means that the
DQS output is disabled.
• Write request is received while DMODE[2:0] = 000 (no data phase), except when
MTYP[2:0] is HyperBus.
• Illegal access size when wrap read burst. This means the HSIZE is different from 4
bytes (only for Memory-mapped mode).
• Illegal wrap size when receiving read wrap burst with size different from 4 bytes (only
for Memory-mapped mode).

20.4.17 OCTOSPI BUSY and ABORT

Once the OCTOSPI starts an operation with the external device, BUSY is automatically set
in OCTOSPI_SR.
In Indirect mode, BUSY is reset once the OCTOSPI has completed the requested command
sequence and the FIFO is empty.

RM0438 Rev 7 653/2194

683
Octo-SPI interface (OCTOSPI) RM0438

In Automatic status-polling mode, BUSY goes low only after the last periodic access is
complete, due to a match when APMS = 1 or due to an abort.
After the first access in Memory-mapped mode, BUSY goes low only on an abort.
Any operation can be aborted by setting ABORT in OCTOSPI_CR. Once the abort is
completed, BUSY and ABORT are automatically reset, and the FIFO is flushed.
Before setting ABORT, the software must ensure that all the current transactions are
finished using the synchronization barriers.
Note: Some devices may misbehave if a write operation to a status register is aborted.

20.4.18 OCTOSPI reconfiguration or deactivation

Prior to any OCTOSPI reconfiguration, the software must ensure that all the transactions
are completed:
• After a Memory-mapped write, the software must perform a dummy read followed by a
synchronization barrier, then an abort.
• After a Memory-mapped read, the software must perform a synchronization barrier
then an abort.

20.4.19 NCS behavior

By default, NCS is high, deselecting the external device. NCS falls before an operation
begins and rises as soon as it finishes.
When CKMODE = 0 (Mode 0: CLK stays low when no operation is in progress), NCS falls
one CLK cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after
the operation final rising CLK edge (see the figure below).

Figure 87. NCS when CKMODE = 0 (T = CLK period)

T T

NCS

SCLK

MSv44100V1

654/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

When CKMODE = 1 (Mode 3: CLK goes high when no operation is in progress) and when in
SDR mode, NCS falls one CLK cycle before an operation first rising CLK edge, and NCS
rises one CLK cycle after the operation final rising CLK edge (see the figure below).

Figure 88. NCS when CKMODE = 1 in SDR mode (T = CLK period)

T T

NCS

SCLK

MSv44101V1

When the CKMODE = 1 (Mode 3) and DDTR = 1 (data DTR mode), NCS falls one CLK
cycle before an operation first rising CLK edge, and NCS rises one CLK cycle after the
operation final active rising CLK edge (see the figure below). Because the DTR operations
must finish with a falling edge, CLK is low when NCS rises, and CLK rises back up one half
of a CLK cycle afterwards.

Figure 89. NCS when CKMODE = 1 in DTR mode (T = CLK period)

T/2
T
T

NCS

SCLK

MSv44102V1

When the FIFO stays full during a read operation, or if the FIFO stays empty during a write
operation, the operation stalls and CLK stays low until the software services the FIFO. If an
abort occurs when an operation is stalled, NCS rises just after the abort is requested and
then CLK rises one half of a CLK cycle later (see the figure below).

Figure 90. NCS when CKMODE = 1 with an abort (T = CLK period)

T/2
Clock stalled
T

NCS

SCLK

Abort

MSv44103V1

When not in dual-quad configuration (DMM = 0), only device A is accessed and thus the
BNCS stays high. In dual-quad configuration, the BNCS behaves exactly the same as the
ANCS. Thus, if there is a device B and if the application always stays in dual-quad

RM0438 Rev 7 655/2194

683
Octo-SPI interface (OCTOSPI) RM0438

configuration, then the device B may use the ANCS and the pin outputting BNCS can be
used for other functions.

20.5 Address alignment and data number

The following table summarizes the effect of the address alignment and programmed data
number depending on the use case.

Table 153. Address alignment cases

Constraint Impact if constraint Constraint Impact if constraint
Transaction
Memory type on on address not on number on bytes not
type
address(1) respected of bytes(1) respected

IND(2) read

Single, dual, quad Flash MM(3) read

None None None None
or SRAM (DMM = 0) IND write
MM write
IND read Even ADDR[0] is set to 0. Even DLR[0] is set to 1.

Single, dual, quad Flash MM read None None None None

or SRAM (DMM = 1) IND write Even ADDR[0] is set to 0. Even DLR[0] is set to 1.
MM write Even Slave error Even Last byte is lost.
IND read

Octal Flash in SDR MM read

None None None None
mode IND write
MM write
IND read Even ADDR[0] is set to 0. Even DLR[0] is set to 1.
Octal Flash or RAM in MM read None None None None
DTR mode without RDS
nor WDM(4) IND write Even ADDR[0] is set to 0. Even DLR[0] is set to 1.
MM write Even Slave error Even Last byte is lost.
IND read Even ADDR[0] is set to 0. Even DLR[0] is set to 1.
Octal Flash or RAM in MM read
DTR mode with RDS or
WDM IND write None None None None
MM write
IND read Even ADDR[0] is set to 0. Even DLR[0] is set to 1.
MM read
HyperBus
IND write None None None None
MM write
1. To be respected by the software.
2. IND = Indirect mode.
3. MM = Memory-mapped mode
4. RDS = read data strobe, WDM = write data mask.

656/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.6 OCTOSPI interrupts

An interrupt can be produced on the following events:
• Timeout
• Status match
• FIFO threshold
• Transfer complete
• Transfer error
Separate interrupt enable bits are available to provide more flexibility.

Table 154. OCTOSPI interrupt requests

Interrupt event Event flag Enable control bit

Timeout TOF TOIE

Status match SMF SMIE
FIFO threshold FTF FTIE
Transfer complete TCF TCIE
Transfer error TEF TEIE

20.7 OCTOSPI registers

20.7.1 OCTOSPI control register (OCTOSPI_CR)

Address offset: 0x0000
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. FMODE[1:0] Res. Res. Res. Res. PMM APMS Res. TOIE SMIE FTIE TCIE TEIE

rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. FTHRES[4:0] MSEL DMM Res. Res. TCEN DMAEN ABORT EN

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

RM0438 Rev 7 657/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bits 29:28 FMODE[1:0]: Functional mode

This field defines the OCTOSPI functional mode of operation.
00: Indirect-write mode
01: Indirect-read mode
10: Automatic status-polling mode
11: Memory-mapped mode
If DMAEN = 1 already, then the DMA controller for the corresponding channel must be
disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are
wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive
state.
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 PMM: Polling match mode
This bit indicates which method must be used to determine a match during the Automatic
status-polling mode.
0: AND-match mode, SMF is set if all the unmasked bits received from the device match the
corresponding bits in the match register.
1: OR-match mode, SMF is set if any of the unmasked bits received from the device matches
its corresponding bit in the match register.
Bit 22 APMS: Automatic status-polling mode stop
This bit determines if the Automatic status-polling mode is stopped after a match.
0: Automatic status-polling mode is stopped only by abort or by disabling the OCTOSPI.
1: Automatic status-polling mode stops as soon as there is a match.
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: Timeout interrupt enable
This bit enables the timeout interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 19 SMIE: Status match interrupt enable
This bit enables the status match interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 18 FTIE: FIFO threshold interrupt enable
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 17 TCIE: Transfer complete interrupt enable
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 16 TEIE: Transfer error interrupt enable
This bit enables the transfer error interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bits 15:13 Reserved, must be kept at reset value.

658/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bits 12:8 FTHRES[4:0]: FIFO threshold level

This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes
the FIFO threshold flag FTF in OCTOSPI_SR, to be set.
00000: FTF is set if there are one or more free bytes available to be written to in the FIFO in
Indirect-write mode, or if there are one or more valid bytes can be read from the FIFO in
Indirect-read mode.
00001: FTF is set if there are two or more free bytes available to be written to in the FIFO in
Indirect-write mode, or if there are two or more valid bytes can be read from the FIFO in
Indirect-read mode.
...
11111: FTF is set if there are 32 free bytes available to be written to in the FIFO in Indirect-
write mode, or if there are 32 valid bytes can be read from the FIFO in Indirect-read mode.
Note: If DMAEN = 1, the DMA controller for the corresponding channel must be disabled
before changing the FTHRES[4:0] value.
Bit 7 MSEL: Flash select
This bit selects the Flash memory to be addressed in Single-, Dual-, Quad-SPI mode in
single-memory configuration (when DMM = 0).
0: FLASH 1 selected (data exchanged over IO[3:0])
1: FLASH 2 selected (data exchanged over IO[7:4])
This bit is ignored when DMM = 1 or when Octal-SPI mode is selected.
Bit 6 DMM: Dual-memory configuration
This bit activates the dual-memory configuration, where two external devices are used
simultaneously to double the throughput and the capacity
0: Dual-quad configuration disabled
1: Dual-quad configuration enabled
Bits 5:4 Reserved, must be kept at reset value.
Bit 3 TCEN: Timeout counter enable
This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit
enables the timeout counter.
0: Timeout counter is disabled, and thus the chip-select (NCS) remains active indefinitely
after an access in Memory-mapped mode.
1: Timeout counter is enabled, and thus the chip-select is released in the Memory-mapped
mode after TIMEOUT[15:0] cycles of external device inactivity.
Bit 2 DMAEN: DMA enable
In Indirect mode, the DMA can be used to input or output data via OCTOSPI_DR. DMA
transfers are initiated when FTF is set.
0: DMA disabled for Indirect mode
1: DMA enabled for Indirect mode
Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with
the DMA. Do not write this bit during DMA operation.
Bit 1 ABORT: Abort request
This bit aborts the on-going command sequence. It is automatically reset once the abort is
completed. This bit stops the current transfer.
0: No abort requested
1: Abort requested
Note: This bit is always read as 0.

RM0438 Rev 7 659/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bit 0 EN: Enable

This bit enables the OCTOSPI.
0: OCTOSPI disabled
1: OCTOSPI enabled
Note: The DMA request can be aborted without having received the ACK in case this EN bit is
cleared during the operation.
In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to
inactive state without waiting for the ACK signal from DMA to be active.

20.7.2 OCTOSPI device configuration register 1 (OCTOSPI_DCR1)

Address offset: 0x0008
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. MTYP[2:0] Res. Res. Res. DEVSIZE[4:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLY CKMO
Res. Res. Res. Res. Res. CSHT[2:0] Res. Res. Res. Res. Res. FRCK
BYP DE
rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:24 MTYP[2:0]: Memory type
This bit indicates the type of memory to be supported.
000: Micron mode, D0/D1 ordering in DTR 8-data-bit mode. Regular-command protocol in
Single-, Dual-, Quad- and Octal-SPI modes.
Note: In this mode, DQS signal polarity is inverted with respect to the memory clock signal.
This is the default value and care must be taken to change MTYP[2:0] for memories different
from Micron.
001: Macronix mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command protocol in
Single-, Dual-, Quad- and Octal-SPI modes.
010: Standard mode
011: Macronix RAM mode, D1/D0 ordering in DTR 8-data-bit mode. Regular-command
protocol in Single-, Dual-, Quad- and Octal-SPI modes with dedicated address mapping.
100: HyperBus memory mode, the protocol follows the HyperBus specification. 8-data-bit
DTR mode must be selected.
101: HyperBus register mode, addressing register space. The memory-mapped accesses in
this mode must be non-cacheable, or Indirect read/write modes must be used.
Others: Reserved
Bits 23:21 Reserved, must be kept at reset value.

660/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bits 20:16 DEVSIZE[4:0]: Device size

This field defines the size of the external device using the following formula:
Number of bytes in device = 2[DEVSIZE+1].
DEVSIZE+1 is effectively the number of address bits required to address the external device.
The device capacity can be up to 4 Gbytes (addressed using 32-bits) in Indirect mode, but
the addressable space in Memory-mapped mode is limited to 256 Mbytes.
In Regular-command protocol, if DMM = 1, DEVSIZE[4:0] indicates the total capacity of the
two devices together.
Bits 15:11 Reserved, must be kept at reset value.
Bits 10:8 CSHT[2:0]: Chip-select high time
CSHT + 1 defines the minimum number of CLK cycles where the chip-select (NCS) must
remain high between commands issued to the external device.
000: NCS stays high for at least 1 cycle between external device commands.
001: NCS stays high for at least 2 cycles between external device commands.
...
111: NCS stays high for at least 8 cycles between external device commands.
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 DLYBYP: Delay block bypass
0: The internal sampling clock (called feedback clock) or the DQS data strobe external signal
is delayed by the delay block (for more details on this block, refer to the dedicated section of
the reference manual as it is not part of the OCTOSPI peripheral).
1: The delay block is bypassed, so the internal sampling clock or the DQS data strobe
external signal is not affected by the delay block. The delay is shorter than when the delay
block is not bypassed, even with the delay value set to minimum value in delay block.
Bit 2 Reserved, must be kept at reset value.
Bit 1 FRCK: Free running clock
This bit configures the free running clock.
0: CLK is not free running.
1: CLK is free running (always provided).
Bit 0 CKMODE: Mode 0/Mode 3
This bit indicates the level taken by the CLK between commands (when NCS = 1).
0: CLK must stay low while NCS is high (chip-select released). This is referred to as Mode 0.
1: CLK must stay high while NCS is high (chip-select released). This is referred to as Mode 3.

20.7.3 OCTOSPI device configuration register 2 (OCTOSPI_DCR2)

Address offset: 0x000C
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRAPSIZE[2:0]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. PRESCALER[7:0]

rw rw rw rw rw rw rw rw

RM0438 Rev 7 661/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:16 WRAPSIZE[2:0]: Wrap size
This field indicates the wrap size to which the memory is configured. For memories which
have a separate command for wrapped instructions, this field indicates the wrap-size
associated with the command held in the OCTOSPI1_WPIR register.
000: Wrapped reads are not supported by the memory.
001: Reserved
010: External memory supports wrap size of 16 bytes.
011: External memory supports wrap size of 32 bytes.
100: External memory supports wrap size of 64 bytes.
101: External memory supports wrap size of 128 bytes.
110-111: Reserved
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 PRESCALER[7:0]: Clock prescaler
This field defines the scaler factor for generating the CLK based on the kernel clock
(value + 1).
0: FCLK = FKERNEL, kernel clock used directly as OCTOSPI CLK (prescaler bypassed). In this
case, if the DTR mode is used, it is mandatory to provide to the OCTOSPI a kernel clock that
has 50% duty-cycle.
1: FCLK = FKERNEL/2
2: FCLK = FKERNEL/3
...
255: FCLK = FKERNEL/256
For odd clock division factors, the CLK duty cycle is not 50 %. The clock signal remains low
one cycle longer than it stays high.

20.7.4 OCTOSPI device configuration register 3 (OCTOSPI_DCR3)

Address offset: 0x0010
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CSBOUND[4:0]

rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

662/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 CSBOUND[4:0]: NCS boundary
This field enables the transaction boundary feature. When active, a minimum value of 3 is
recommended.
The NCS is released on each boundary of 2CSBOUND bytes.
0: NCS boundary disabled
others: NCS boundary set to 2CSBOUND bytes
Bits 15:0 Reserved, must be kept at reset value.

20.7.5 OCTOSPI device configuration register 4 (OCTOSPI_DCR4)

Address offset: 0x0014
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REFRESH[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

REFRESH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 REFRESH[31:0]: Refresh rate

This field enables the refresh rate feature.
The NCS is released every REFRESH + 1 clock cycles for writes, and REFRESH + 4 clock
cycles for reads.
Note: These two values can be extended with few clock cycles when refresh occurs during a
byte transmission in Single-, Dual- or Quad-SPI mode, because the byte transmission
must be completed.
0: Refresh disabled
others: Maximum communication length is set to REFRESH + 1 clock cycles.

20.7.6 OCTOSPI status register (OCTOSPI_SR)

Address offset: 0x0020
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. FLEVEL[5:0] Res. Res. BUSY TOF SMF FTF TCF TEF

r r r r r r r r r r r r

RM0438 Rev 7 663/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:8 FLEVEL[5:0]: FIFO level
This field gives the number of valid bytes that are being held in the FIFO. FLEVEL = 0 when
the FIFO is empty, and 32 when it is full.
In Automatic status-polling mode, FLEVEL is zero.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 BUSY: Busy
This bit is set when an operation is ongoing. It is cleared automatically when the operation
with the external device is finished and the FIFO is empty.
Bit 4 TOF: Timeout flag
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.
Bit 3 SMF: Status match flag
This bit is set in Automatic status-polling mode when the unmasked received data matches
the corresponding bits in the match register (OCTOSPI_PSMAR).
It is cleared by writing 1 to CSMF.
Bit 2 FTF: FIFO threshold flag
In Indirect mode, this bit is set when the FIFO threshold has been reached, or if there is any
data left in the FIFO after the reads from the external device are complete.
It is cleared automatically as soon as the threshold condition is no longer true.
In Automatic status-polling mode, this bit is set every time the status register is read, and the
bit is cleared when the data register is read.
Bit 1 TCF: Transfer complete flag
This bit is set in Indirect mode when the programmed number of data has been transferred or
in any mode when the transfer has been aborted.It is cleared by writing 1 to CTCF.
Bit 0 TEF: Transfer error flag
This bit is set in Indirect mode when an invalid address is being accessed in Indirect mode.
It is cleared by writing 1 to CTEF.

20.7.7 OCTOSPI flag clear register (OCTOSPI_FCR)

Address offset: 0x0024
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CTOF CSMF Res. CTCF CTEF

w w w w

664/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bits 31:5 Reserved, must be kept at reset value.

Bit 4 CTOF: Clear timeout flag
Writing 1 clears the TOF flag in the OCTOSPI_SR register.
Bit 3 CSMF: Clear status match flag
Writing 1 clears the SMF flag in the OCTOSPI_SR register.
Bit 2 Reserved, must be kept at reset value.
Bit 1 CTCF: Clear transfer complete flag
Writing 1 clears the TCF flag in the OCTOSPI_SR register.
Bit 0 CTEF: Clear transfer error flag
Writing 1 clears the TEF flag in the OCTOSPI_SR register.

20.7.8 OCTOSPI data length register (OCTOSPI_DLR)

Address offset: 0x0040
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DL[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DL[31: 0]: Data length

Number of data to be retrieved (value+1) in Indirect and Automatic status-polling modes. A
value not greater than three (indicating 4 bytes) must be used for Automatic status-polling
mode.
All 1’s in Indirect mode means undefined length, where OCTOSPI continues until the end of
the memory, as defined by DEVSIZE.
0x0000_0000: 1 byte is to be transferred.
0x0000_0001: 2 bytes are to be transferred.
0x0000_0002: 3 bytes are to be transferred.
0x0000_0003: 4 bytes are to be transferred.
...
0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred.
0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred.
0xFFFF_FFFF: undefined length; all bytes, until the end of the external device, (as defined
by DEVSIZE) are to be transferred. Continue reading indefinitely if DEVSIZE = 0x1F.
DL[0] is stuck at 1 in dual-memory configuration (DMM = 1) even when 0 is written to this bit,
thus assuring that each access transfers an even number of bytes.
This field has no effect in Memory-mapped mode.

RM0438 Rev 7 665/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.7.9 OCTOSPI address register (OCTOSPI_AR)

Address offset: 0x0048
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADDRESS[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESS[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ADDRESS[31:0]: Address

Address to be sent to the external device. In HyperBus protocol, this field must be even as
this protocol is 16-bit word oriented. In dual-memory configuration, AR[0] is forced to 1.
Writes to this field are ignored when BUSY = 1 or when FMODE = 11 (Memory-mapped
mode).

20.7.10 OCTOSPI data register (OCTOSPI_DR)

Address offset: 0x0050
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 DATA[31: 0]: Data

Data to be sent/received to/from the external SPI device
In Indirect-write mode, data written to this register is stored on the FIFO before it is sent to
the external device during the data phase. If the FIFO is too full, a write operation is stalled
until the FIFO has enough space to accept the amount of data being written.
In Indirect-read mode, reading this register gives (via the FIFO) the data that was received
from the external device. If the FIFO does not have as many bytes as requested by the read
operation and if BUSY = 1, the read operation is stalled until enough data is present or until
the transfer is complete, whichever happens first.
In Automatic status-polling mode, this register contains the last data read from the external
device (without masking).
Word, half-word, and byte accesses to this register are supported. In Indirect-write mode, a
byte write adds 1 byte to the FIFO, a half-word write 2 bytes, and a word write 4 bytes.
Similarly, in Indirect-read mode, a byte read removes 1 byte from the FIFO, a halfword read
2 bytes, and a word read 4 bytes. Accesses in Indirect mode must be aligned to the bottom
of this register: A byte read must read DATA[7:0] and a half-word read must read DATA[15:0].

666/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.7.11 OCTOSPI polling status mask register (OCTOSPI_PSMKR)

Address offset: 0x0080
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MASK[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MASK[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MASK[31:0]: Status mask

Mask to be applied to the status bytes received in Automatic status-polling mode
For bit n:
0: Bit n of the data received in Automatic status-polling mode is masked and its value is not
considered in the matching logic.
1: Bit n of the data received in Automatic status-polling mode is unmasked and its value is
considered in the matching logic.

20.7.12 OCTOSPI polling status match register (OCTOSPI_PSMAR)

Address offset: 0x0088
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

MATCH[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MATCH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 MATCH[31: 0]: Status match

Value to be compared with the masked status register to get a match

RM0438 Rev 7 667/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.7.13 OCTOSPI polling interval register (OCTOSPI_PIR)

Address offset: 0x0090
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INTERVAL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 INTERVAL[15: 0]: Polling interval
Number of CLK cycle between a read during the Automatic status-polling phases

20.7.14 OCTOSPI communication configuration register (OCTOSPI_CCR)

Address offset: 0x0100
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SIOO Res. DQSE Res. DDTR DMODE[2:0] Res. Res. ABSIZE[1:0] ABDTR ABMODE[2:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD
Res. Res. ADSIZE[1:0] ADMODE[2:0] Res. Res. ISIZE[1:0] IDTR IMODE[2:0]
DTR
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 SIOO: Send instruction only once mode

This bit has no effect when IMODE = 00 (see Sending the instruction only once (SIOO)).
0: Send instruction on every transaction
1: Send instruction only for the first command
Bit 30 Reserved, must be kept at reset value.
Bit 29 DQSE: DQS enable
This bit enables the data strobe management.
0: DQS disabled
1: DQS enabled
Bit 28 Reserved, must be kept at reset value.

668/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bit 27 DDTR: Data double transfer rate

This bit sets the DTR mode for the data phase.
0: DTR mode disabled for data phase
1: DTR mode enabled for data phase
Bits 26:24 DMODE[2:0]: Data mode
This field defines the data phase mode of operation.
000: No data
001: Data on a single line
010: Data on two lines
011: Data on four lines
100: Data on eight lines
101-111: Reserved
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 ABSIZE[1:0]: Alternate bytes size
This bit defines alternate bytes size.
00: 8-bit alternate bytes
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
Bit 19 ABDTR: Alternate bytes double transfer rate
This bit sets the DTR mode for the alternate bytes phase.
0: DTR mode disabled for alternate bytes phase
1: DTR mode enabled for alternate bytes phase
This field can be written only when BUSY = 0.
Bits 18:16 ABMODE[2:0]: Alternate-byte mode
This field defines the alternate-byte phase mode of operation.
000: No alternate bytes
001: Alternate bytes on a single line
010: Alternate bytes on two lines
011: Alternate bytes on four lines
100: Alternate bytes on eight lines
101-111: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 ADSIZE[1:0]: Address size
This field defines address size.
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
Bit 11 ADDTR: Address double transfer rate
This bit sets the DTR mode for the address phase.
0: DTR mode disabled for address phase
1: DTR mode enabled for address phase

RM0438 Rev 7 669/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bits 10:8 ADMODE[2:0]: Address mode

This field defines the address phase mode of operation.
000: No address
001: Address on a single line
010: Address on two lines
011: Address on four lines
100: Address on eight lines
101-111: Reserved
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 ISIZE[1:0]: Instruction size
This bit defines instruction size.
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the instruction phase mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved

20.7.15 OCTOSPI timing configuration register (OCTOSPI_TCR)

Address offset: 0x0108
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S
Res. Res. DHQC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SHIFT
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCYC[4:0]

rw rw rw rw rw

670/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bit 31 Reserved, must be kept at reset value.

Bit 30 SSHIFT: Sample shift
By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the
external device.
This bit allows the data to be sampled later in order to consider the external signal delays.
0: No shift
1: 1/2 cycle shift
The software must ensure that SSHIFT = 0 when the data phase is configured in DTR mode
(when DDTR = 1.)
Bit 29 Reserved, must be kept at reset value.
Bit 28 DHQC: Delay hold quarter cycle
0: No delay hold
1: 1/4 cycle hold
Bits 27:5 Reserved, must be kept at reset value.
Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31).
It is recommended to have at least six dummy cycles when using memories with DQS
activated.

20.7.16 OCTOSPI instruction register (OCTOSPI_IR)

Address offset: 0x0110
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INSTRUCTION[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 INSTRUCTION[31:0]: Instruction

Instruction to be sent to the external SPI device

RM0438 Rev 7 671/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.7.17 OCTOSPI alternate bytes register (OCTOSPI_ABR)

Address offset: 0x0120
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALTERNATE[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALTERNATE[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ALTERNATE[31: 0]: Alternate bytes

Optional data to be sent to the external SPI device right after the address.

20.7.18 OCTOSPI low-power timeout register (OCTOSPI_LPTR)

Address offset: 0x00130
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TIMEOUT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 TIMEOUT[15: 0]: Timeout period
After each access in Memory-mapped mode, the OCTOSPI prefetches the subsequent bytes
and hold them in the FIFO.
This field indicates how many CLK cycles the OCTOSPI waits after the clock becomes
inactive and until it raises the NCS, putting the external device in a lower-consumption state.

672/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.7.19 OCTOSPI wrap communication configuration register

(OCTOSPI_WPCCR)
Address offset: 0x0140
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. DQSE Res. DDTR DMODE[2:0] Res. Res. ABSIZE[1:0] ABDTR ABMODE[2:0]

rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD
Res. Res. ADSIZE[1:0] ADMODE[2:0] Res. Res. ISIZE[1:0] IDTR IMODE[2:0]
DTR
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DQSE: DQS enable
This bit enables the data strobe management.
0: DQS disabled
1: DQS enabled
Bit 28 Reserved, must be kept at reset value.
Bit 27 DDTR: Data double transfer rate
This bit sets the DTR mode for the data phase.
0: DTR mode disabled for data phase
1: DTR mode enabled for data phase
Bits 26:24 DMODE[2:0]: Data mode
This field defines the data phase mode of operation.
000: No data
001: Data on a single line
010: Data on two lines
011: Data on four lines
100: Data on eight lines
101-111: Reserved
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 ABSIZE[1:0]: Alternate bytes size
This bit defines alternate bytes size.
00: 8-bit alternate bytes
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
Bit 19 ABDTR: Alternate bytes double transfer rate
This bit sets the DTR mode for the alternate bytes phase.
0: DTR mode disabled for alternate bytes phase
1: DTR mode enabled for alternate bytes phase

RM0438 Rev 7 673/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bits 18:16 ABMODE[2:0]: Alternate-byte mode

This field defines the alternate byte phase mode of operation.
000: No alternate bytes
001: Alternate bytes on a single line
010: Alternate bytes on two lines
011: Alternate bytes on four lines
100: Alternate bytes on eight lines
101-111: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 ADSIZE[1:0]: Address size
This field defines address size.
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
Bit 11 ADDTR: Address double transfer rate
This bit sets the DTR mode for the address phase.
0: DTR mode disabled for address phase
1: DTR mode enabled for address phase
Bits 10:8 ADMODE[2:0]: Address mode
This field defines the address phase mode of operation.
000: No address
001: Address on a single line
010: Address on two lines
011: Address on four lines
100: Address on eight lines
101-111: Reserved
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 ISIZE[1:0]: Instruction size
This field defines instruction size.
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the instruction phase mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved

674/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.7.20 OCTOSPI wrap timing configuration register (OCTOSPI_WPTCR)

Address offset: 0x0148
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
S
Res. Res. DHQC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
SHIFT
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCYC[4:0]

rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 SSHIFT: Sample shift
By default, the OCTOSPI samples data 1/2 of a CLK cycle after the data is driven by the
external device.
This bit allows the data to be sampled later in order to consider the external signal delays.
0: No shift
1: 1/2 cycle shift
The firmware must assure that SSHIFT=0 when the data phase is configured in DTR mode
(when DDTR = 1).
Bit 29 Reserved, must be kept at reset value.
Bit 28 DHQC: Delay hold quarter cycle
Add a quarter cycle delay on the outputs in DTR communication to match hold requirement.
0: No quarter cycle delay
1: Quarter cycle delay inserted
Bits 27:5 Reserved, must be kept at reset value.
Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended
to have at least 5 dummy cycles when using memories with DQS activated.

RM0438 Rev 7 675/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.7.21 OCTOSPI wrap instruction register (OCTOSPI_WPIR)

Address offset: 0x0150
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INSTRUCTION[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 INSTRUCTION[31: 0]: Instruction

Instruction to be sent to the external SPI device

20.7.22 OCTOSPI wrap alternate bytes register (OCTOSPI_WPABR)

Address offset: 0x0160
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALTERNATE[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALTERNATE[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ALTERNATE[31: 0]: Alternate bytes

Optional data to be sent to the external SPI device right after the address

676/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.7.23 OCTOSPI write communication configuration register

(OCTOSPI_WCCR)
Address offset: 0x0180
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. DQSE Res. DDTR DMODE[2:0] Res. Res. ABSIZE[1:0] ABDTR ABMODE[2:0]

rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDT
Res. Res. ADSIZE[1:0] ADMODE[2:0] Res. Res. ISIZE[1:0] IDTR IMODE[2:0]
R
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept at reset value.

Bit 29 DQSE: DQS enable
This bit enables the data strobe management.
0: DQS disabled
1: DQS enabled
Bit 28 Reserved, must be kept at reset value.
Bit 27 DDTR: data double transfer rate
This bit sets the DTR mode for the data phase.
0: DTR mode disabled for data phase
1: DTR mode enabled for data phase
Bits 26:24 DMODE[2:0]: Data mode
This field defines the data phase mode of operation.
000: No data
001: Data on a single line
010: Data on two lines
011: Data on four lines
100: Data on eight lines
101-111: Reserved
Bits 23:22 Reserved, must be kept at reset value.
Bits 21:20 ABSIZE[1:0]: Alternate bytes size
This field defines alternate bytes size:
00: 8-bit alternate bytes
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
Bit 19 ABDTR: Alternate bytes double transfer rate
This bit sets the DTR mode for the alternate-bytes phase.
0: DTR mode disabled for alternate-bytes phase
1: DTR mode enabled for alternate-bytes phase

RM0438 Rev 7 677/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Bits 18:16 ABMODE[2:0]: Alternate-byte mode

This field defines the alternate-byte phase mode of operation.
000: No alternate bytes
001: Alternate bytes on a single line
010: Alternate bytes on two lines
011: Alternate bytes on four lines
100: Alternate bytes on eight lines
101-111: Reserved
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:12 ADSIZE[1:0]: Address size
This field defines address size.
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
Bit 11 ADDTR: Address double transfer rate
This bit sets the DTR mode for the address phase.
0: DTR mode disabled for address phase
1: DTR mode enabled for address phase
Bits 10:8 ADMODE[2:0]: Address mode
This field defines the address phase mode of operation.
000: No address
001: Address on a single line
010: Address on two lines
011: Address on four lines
100: Address on eight lines
101-111: Reserved
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 ISIZE[1:0]: Instruction size
This bit defines instruction size:
00: 8-bit instruction
01: 16-bit instruction
10: 24-bit instruction
11: 32-bit instruction
Bit 3 IDTR: Instruction double transfer rate
This bit sets the DTR mode for the instruction phase.
0: DTR mode disabled for instruction phase
1: DTR mode enabled for instruction phase
Bits 2:0 IMODE[2:0]: Instruction mode
This field defines the instruction phase mode of operation.
000: No instruction
001: Instruction on a single line
010: Instruction on two lines
011: Instruction on four lines
100: Instruction on eight lines
101-111: Reserved

678/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

20.7.24 OCTOSPI write timing configuration register (OCTOSPI_WTCR)

Address offset: 0x0188
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCYC[4:0]

rw rw rw rw rw

Bits 31:5 Reserved, must be kept at reset value.

Bits 4:0 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase.
In both SDR and DTR modes, it specifies a number of CLK cycles (0-31). It is recommended
to have at least 5 dummy cycles when using memories with DQS activated.

20.7.25 OCTOSPI write instruction register (OCTOSPI_WIR)

Address offset: 0x0190
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INSTRUCTION[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INSTRUCTION[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 INSTRUCTION[31:0]: Instruction

Instruction to be sent to the external SPI device

RM0438 Rev 7 679/2194

683
Octo-SPI interface (OCTOSPI) RM0438

20.7.26 OCTOSPI write alternate bytes register (OCTOSPI_WABR)

Address offset: 0x01A0
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ALTERNATE[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ALTERNATE[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 ALTERNATE[31: 0]: Alternate bytes

Optional data to be sent to the external SPI device right after the address

20.7.27 OCTOSPI HyperBus latency configuration register

(OCTOSPI_HLCR)
Address offset: 0x0200
Reset value: 0x0000 0000
This register can be modified only when BUSY = 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. TRWR[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TACC[7:0] Res. Res. Res. Res. Res. Res. WZL LM

rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 TRWR[7:0]: Read write recovery time
Device read write recovery time expressed in number of communication clock cycles
Bits 15:8 TACC[7: 0]: Access time
Device access time expressed in number of communication clock cycles

680/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Bits 7:2 Reserved, must be kept at reset value.

Bit 1 WZL: Write zero latency
This bit enables zero latency on write operations.
0: Latency on write accesses
1: No latency on write accesses
Bit 0 LM: Latency mode
This bit selects the Latency mode.
0: Variable initial latency
1: Fixed latency

20.7.28 OCTOSPI register map

Table 155. OCTOSPI register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
FMDOE[1:0]

DMAEN
ABORT
APMS

TCEN
MSEL
SMIE

DMM
PMM

TOIE

TCIE
TEIE
FTIE
Res.
Res.

Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.

Res.
Res.

EN
OCTOSPI_CR FTHRES[4:0]
0x0000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0004 Reserved Reserved

CKMODE
DLYBYP

FRCK
MTYP CSHT
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
OCTOSPI_DCR1 DEVSIZE[4:0]
0x0008 [2:0] [2:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WRAPSIZE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
[2:0]

OCTOSPI_DCR2 PRESCALER[7:0]
0x000C

Reset value 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OCTOSPI_DCR3 CSBOUND[4:0]
0x0010
Reset value 0 0 0 0 0

OCTOSPI_DCR4 REFRESH[31:0]
0x0014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0018-
Reserved Reserved
0x001C
BUSY

SMF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.

TOF

TCF
TEF
FTF

OCTOSPI_SR FLEVEL[5:0]
0x0020

Reset value 0 0 0 0 0 0 0 0 0 0 0 0
CSMF
CTOF

CTCF
CTEF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

OCTOSPI_FCR
0x0024
Reset value 0 0 0 0

0x0028-
Reserved Reserved
0x003C

OCTOSPI_DLR DL[31:0]
0x0040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 681/2194

683
Octo-SPI interface (OCTOSPI) RM0438

Table 155. OCTOSPI register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
0x0044 Reserved Reserved

OCTOSPI_AR ADDRESS[31:0]
0x0048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x004C Reserved Reserved

OCTOSPI_DR DATA[31:0]
0x0050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0054-
Reserved Reserved
0x007C

OCTOSPI_
MASK[31:0]
PSMKR
0x0080
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0084 Reserved Reserved

OCTOSPI_
MATCH[31:0]
PSMAR
0x0088
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x008C Reserved Reserved

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OCTOSPI_PIR INTERVAL[15:0]
0x0090
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0094-
Reserved Reserved
0x00FC

ISIZE[1:0]
ADMODE
ABMODE

ADSIZE
ABSIZE

ADDTR
ABDTR

IMODE
DQSE

DDTR
SIOO

DMODE

IDTR
Res.

Res.

Res.
Res.

Res.
Res.

Res.
Res.
[1:0]

[2:0]

[1:0]

[2:0]

[2:0]
OCTOSPI_CCR
[2:0]
0x0100

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0104 Reserved Reserved

SSHIFT

DHQC
Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OCTOSPI_TCR DCYC[4:0]
0x0108

Reset value 0 0 0 0 0 0 0

0x010C Reserved Reserved

OCTOSPI_IR INSTRUCTION[31:0]
0x0110
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0114-
Reserved Reserved
0x011C

OCTOSPI_ABR ALTERNATE[31:0]
0x0120
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0124-
Reserved Reserved
0x012C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

OCTOSPI_LPTR TIMEOUT[15:0]
0x0130
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0134-
Reserved Reserved
0x013C

682/2194 RM0438 Rev 7

RM0438 Octo-SPI interface (OCTOSPI)

Table 155. OCTOSPI register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
ADMODE
ABMODE

ADSIZE
ABSIZE

ADDTR
ABDTR

IMODE
DQSE

DDTR

ISIZE
OCTOSPI_ DMODE

IDTR
Res.
Res.

Res.

Res.
Res.

Res.
Res.

Res.
Res.
[1:0]

[2:0]

[1:0]

[2:0]

[1:0]

[2:0]
WPCCR [2:0]
0x0140

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0144 Reserved Reserved

SSHIFT

OCTOSPI_ DHQC
Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DCYC[4:0]
WPTCR
0x0148

Reset value 0 0 0 0 0 0 0

0x014C Reserved Reserved

OCTOSPI_WPIR INSTRUCTION[31:0]
0x0150
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0154-
Reserved Reserved
0x015C

OCTOSPI_
ALTERNATE[31:0]
WPABR
0x0160
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0164-
Reserved Reserved
0x017C

ADMODE
ABMODE

ADSIZE
ABSIZE

ADDTR
ABDTR

IMODE
DQSE

DDTR

ISIZE
DMODE

IDTR
Res.
Res.

Res.

Res.
Res.

Res.
Res.

Res.
Res.
[1:0]

[2:0]

[1:0]

[2:0]

[1:0]

[2:0]
OCTOSPI_WCCR
[2:0]
0x0180

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0184 Reserved Reserved

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OCTOSPI_WTCR DCYC[4:0]
0x0188
Reset value 0 0 0 0 0

0x018C Reserved Reserved

OCTOSPI_WIR INSTRUCTION[31:0]
0x0190
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x0194-
Reserved Reserved
0x019C

OCTOSPI_WABR ALTERNATE[31:0]
0x01A0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x01A4-
Reserved Reserved
0x01FC
WZL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.

LM

OCTOSPI_HLCR TRWR[7:0] TACC[7:0]

0x0200
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 for the register boundary addresses.

RM0438 Rev 7 683/2194

683
Analog-to-digital converters (ADC) RM0438

21 Analog-to-digital converters (ADC)

21.1 Introduction
This section describes the implementation of up to 2 ADCs:
• ADC1 and ADC2 are tightly coupled and can operate in dual mode (ADC1 is master).
Each ADC consists of a 12-bit successive approximation analog-to-digital converter.
Each ADC has up to 20 multiplexed channels. A/D conversion of the various channels can
be performed in single, continuous, scan or discontinuous mode. The result of the ADC is
stored in a left-aligned or right-aligned 16-bit data register.
The ADCs are mapped on the AHB bus to allow fast data handling.
The analog watchdog features allow the application to detect if the input voltage goes
outside the user-defined high or low thresholds.
A built-in hardware oversampler allows to improve analog performance while off-loading the
related computational burden from the CPU.
An efficient low-power mode is implemented to allow very low consumption at low
frequency.

684/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.2 ADC main features

• High-performance features
– Up to 2 ADCs which can operate in dual mode:
ADC1 is connected to 16 external channels + 3 internal channels
ADC2 is connected to 16 external channels
– 12, 10, 8 or 6-bit configurable resolution
– ADC conversion time is independent from the AHB bus clock frequency
– Faster conversion time by lowering resolution
– Manage single-ended or differential inputs
– AHB slave bus interface to allow fast data handling
– Self-calibration
– Channel-wise programmable sampling time
– Up to four injected channels (analog inputs assignment to regular or injected
channels is fully configurable)
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching
– Data alignment with in-built data coherency
– Data can be managed by DMA for regular channel conversions
– Data can be routed to DFSDM for post processing
– 4 dedicated data registers for the injected channels
• Oversampler
– 16-bit data register
– Oversampling ratio adjustable from 2 to 256
– Programmable data shift up to 8-bit
• Low-power features
– Speed adaptive low-power mode to reduce ADC consumption when operating at
low frequency
– Allows slow bus frequency application while keeping optimum ADC performance
– Provides automatic control to avoid ADC overrun in low AHB bus clock frequency
application (auto-delayed mode)
• Number of external analog input channels per ADC
– Up to 5 fast channels from GPIO pads
– Up to 11 slow channels from GPIO pads
• In addition, there are several internal dedicated channels
– The internal reference voltage (VREFINT), connected to ADC1
– The internal temperature sensor (VTS), connected to ADC1
– The VBAT monitoring channel (VBAT/3), connected to ADC1
– DAC1 and DAC2 internal channels, connected to ADC2
• Start-of-conversion can be initiated:
– By software for both regular and injected conversions
– By hardware triggers with configurable polarity (internal timers events or GPIO
input events) for both regular and injected conversions

RM0438 Rev 7 685/2194

796
Analog-to-digital converters (ADC) RM0438

• Conversion modes
– Each ADC can convert a single channel or can scan a sequence of channels
– Single mode converts selected inputs once per trigger
– Continuous mode converts selected inputs continuously
– Discontinuous mode
• Dual ADC mode for ADC1 and 2
• Interrupt generation at ADC ready, the end of sampling, the end of conversion (regular
or injected), end of sequence conversion (regular or injected), analog watchdog 1, 2 or
3 or overrun events
• 3 analog watchdogs per ADC
• ADC input range: VREF– ≤ VIN ≤ VREF+
Figure 91 shows the block diagram of one ADC.

21.3 ADC implementation

Table 156. ADC features
ADC modes/features ADC1 ADC2

Dual mode X X
DFSDM interface X X
SMPPLUS control - -

686/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4 ADC functional description

21.4.1 ADC block diagram

Figure 91 shows the ADC block diagram and Table 158 gives the ADC pin description.

Figure 91. ADC block diagram

VREF+
1.62 to 3.6 V

Cortex
AREADY
M4 with
EOSMP
ADC Interrupt FPU
EOC
EOS IRQ
OVR
RDATA[11:0] JEOS master

AHB
JQOVF slave
AWDx

ADEN/ADDIS
JDATA1[11:0] master
JAUTO Analog Supply (VDDA)
1.62V to 3.6 V JDATA2[11:0]
JDATA3[11:0] DMA
ADC_JSQRx
JDATA4[11:0] AHB
ADC_SQRx
interface DMA request
CONT
single/cont
DFSDM
VTS Bias & Ref 16
VREFINT ADCAL
self calibration Oversampler DMACFG
VBAT/3 VINP[18:0] Input DMAEN
ADC_INP[16:1] SAR ADC
VINN[18:0] selection & VIN
ADC_INN[16:1] scan control ROVSM
analog input CONVERTED
VREF- channels SMPx[2:0] TROVS
DATA
sampling time start
Start & Stop OVSS[3:0]
Control
OVSR[2:0]
AUTDLY OVRMOD
auto delayed S/W trigger overrun mode JOVSE
ADSTP ALIGN
stop conv left/right ROVSE
RES[1:0] Oversampling
12, 10, 8 bits options
JOFFSETx[11:0]
EXT0 JOFFSETx_CH[11:0]
EXT1 h/w
EXT2 trigger
....... DISCEN
....... EXTEN[1:0] DISCNU[:0]
trigger enable Analog watchdog 1,2,3
EXT13 and edge selection Discontinuous
EXT14
mode TIMERs
EXT15
AWD1 AWD1_OUT
EXTi mapped at AWD2 AWD2_OUT ETR
EXTSEL[3:0] AWD3 AWD3_OUT
product level trigger selection

J
S/W trigger
AWD1EN
JEXT0 JAWD1EN
JEXT1 H/W AWD1SGL
JEXT2 trigger
JDISCEN AWDCH1[4:0]
.......
....... JEXTEN[1:0] JDISCNUM[2:0] LT1[11:0]
trigger enable
JEXT13 and edge selection HT1[11:0]
JQM
JEXT14 Injced Context AWDCH2[18:0]
JEXT15 Queue Mode LT2[7:0]
JEXTi mapped at AWDCH3[18:0]
product level HT2[7:0]
JEXTSEL[3:0]
trigger selection HT3[7:0]
LT3[7:0]

MSv43755V5

RM0438 Rev 7 687/2194

796
Analog-to-digital converters (ADC) RM0438

21.4.2 ADC pins and internal signals

Table 157. ADC internal input/output signals

Signal
Internal signal name Description
type

Up to 16 external trigger inputs for the regular conversions (can

be connected to on-chip timers).
EXT[15:0] Inputs
These inputs are shared between the ADC master and the ADC
slave.
Up to 16 external trigger inputs for the injected conversions (can
be connected to on-chip timers).
JEXT[15:0] Inputs
These inputs are shared between the ADC master and the ADC
slave.
Internal analog watchdog output signal connected to on-chip
ADC_AWDx_OUT Output
timers. (x = Analog watchdog number 1,2,3)
VTS Input Output voltage from internal temperature sensor
VREFINT Input Output voltage from internal reference voltage
Input
VBAT External battery voltage supply
supply

Table 158. ADC input/output pins

Pin name Signal type Comments

Input, analog reference The higher/positive reference voltage for the ADC,
VREF+
positive 1.62 V ≤ VREF+ ≤ VDDA
Analog power supply equal VDDA:
VDDA Input, analog supply
1.62 V ≤ VDDA ≤ 3.6 V
Input, analog reference The lower/negative reference voltage for the ADC.
VREF−
negative VREF− is internally connected to VSSA
Ground for analog power supply. On device package
Input, analog supply
VSSA which do not have a dedicated VSSA pin, VSSA is
ground
internally connected to VSS.
Connected either to ADCx_INPi external channels or
Positive analog input
VINPi to internal channels. This input is converted in single-
channels for each ADC
ended mode
Negative analog input Connected either to VREF− or to external channels:
VINNi
channels for each ADC ADCx_INNi and ADCx_INP[i+1].
Up to 16 analog input channels (x = ADC number = 1
Negative external analog or 2)
ADCx_INNi
input signals Refer to Section 21.4.4: ADC1/2 connectivity for
details.
Up to 10 analog input channels (x = ADC number = 1
Positive external analog or 2)
ADCx_INPi
input signals Refer to Section 21.4.4: ADC1/2 connectivity for
details

688/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.3 ADC clocks

Dual clock domain architecture
The dual clock-domain architecture means that the ADC clock is independent from the AHB
bus clock.
The input clock is the same for all ADCs and can be selected between two different clock
sources (see Figure 92: ADC clock scheme):
1. The ADC clock can be a specific clock source, derived from the following clock
sources:
– The system clock
– PLLSAI1 (single ADC implementation)
Refer to RCC Section for more information on how to generate ADC dedicated clock.
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be reset.
2. The ADC clock can be derived from the AHB clock of the ADC bus interface, divided by
a programmable factor (1, 2 or 4). In this mode, a programmable divider factor can be
selected (/1, 2 or 4 according to bits CKMODE[1:0]).
To select this scheme, bits CKMODE[1:0] of the ADCx_CCR register must be different
from “00”.
Note: For option 2), a prescaling factor of 1 (CKMODE[1:0]=01) can be used only if the AHB
prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register).
Option 1) has the advantage of reaching the maximum ADC clock frequency whatever the
AHB clock scheme selected. The ADC clock can eventually be divided by the following ratio:
1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256; using the prescaler configured with bits PRESC[3:0] in
the ADCx_CCR register.
Option 2) has the advantage of bypassing the clock domain resynchronizations. This can be
useful when the ADC is triggered by a timer and if the application requires that the ADC is
precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant
time is added by the resynchronizations between the two clock domains).

RM0438 Rev 7 689/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 92. ADC clock scheme

RCC ADC1 and ADC2

(Reset and
clock HCLK
controller) AHB interface

Bits CKMODE[1:0]
of ADCx_CCR
Analog ADC1
(master)
/1 or /2 or /4 Others
Analog ADC2
/1, 2, 4, 6, 8, 10, (slave)
ADC12_CK 00
12, 16, 32, 64,
128, 256

Bits PREC[3:0] Bits CKMODE[1:0]

of ADCx_CCR of ADCx_CCR

MSv50635V1

Clock ratio constraint between ADC clock and AHB clock

There are generally no constraints to be respected for the ratio between the ADC clock and
the AHB clock except if some injected channels are programmed. In this case, it is
mandatory to respect the following ratio:
• FHCLK ≥ FADC / 4 if the resolution of all channels are 12-bit or 10-bit
• FHCLK ≥ FADC / 3 if there are some channels with resolutions equal to 8-bit (and none
with lower resolution)
• FHCLK ≥ FADC / 2 if there are some channels with resolutions equal to 6-bit

690/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.4 ADC1/2 connectivity

ADC1 and ADC2 are tightly coupled and share some external channels as described in the
below figures.

Figure 93. ADC1 connectivity

ADC1
Channel selection
VINP[0]
VREFINT
VINN[0] Fast channel
VREF−
VINP[1]
ADC12_INP1
VINN[1] Fast channel
ADC12_INN1 VINP[2]
ADC12_INP2 VINN[2] Fast channel
ADC12_INN2 VINP[3]
ADC12_INP3 VINN[3] Fast channel
ADC12_INN3 VINP[4]
ADC12_INP4 VINN[4] Fast channel
ADC12_INN4 VINP[5]
ADC12_INP5 VINN[5] Fast channel
ADC12_INN5 VINP[6]
ADC12_INP6 VINN[6] Slow channel
ADC12_INN6 VINP[7] VREF+
ADC12_INP7 VINN[7] Slow channel
ADC12_INN7 VINP[8] VINP
ADC12_INP8 VINN[8] Slow channel
SAR
ADC12_INN8 VINP[9]
ADC1
ADC12_INP9 VINN[9] Slow channel VINN
ADC12_INN9 VINP[10]
ADC12_INP10 VINN[10] Slow channel
ADC12_INN10 VINP[11] VREF−
ADC12_INP11 VINN[11] Slow channel
ADC12_INN11 VINP[12]
ADC12_INP12 VINN[12] Slow channel
ADC12_INN12 VINP[13]
ADC12_INP13 VINN[13] Slow channel
ADC12_INN13 VINP[14]
ADC12_INP14 VINN[14] Slow channel
ADC12_INN14 VINP[15]
ADC12_INP15 VINN[15] Slow channel
ADC12_INN15 VINP[16]
ADC12_INP16 VINN[16] Slow channel
VREF−
VINP[17]
VTS
VINN[17] Slow channel
VREF−
VINP[18]
VBAT/3
VINN[18] Slow channel
VREF−

MSv50651V1

RM0438 Rev 7 691/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 94. ADC2 connectivity

ADC2
Channel selection
VINP[0]
Reserved
VINN[0] Fast channel
VREF−
VINP[1]
ADC12_INP1
VINN[1] Fast channel
ADC12_INN1 VINP[2]
ADC12_INP2 VINN[2] Fast channel
ADC12_INN2 VINP[3]
ADC12_INP3 VINN[3] Fast channel
ADC12_INN3 VINP[4]
ADC12_INP4 VINN[4] Fast channel
ADC12_INN4 VINP[5]
ADC12_INP5 VINN[5] Fast channel
ADC12_INN5 VINP[6]
ADC12_INP6 VINN[6] Slow channel
ADC12_INN6 VINP[7] VREF+
ADC12_INP7 VINN[7] Slow channel
ADC12_INN7 VINP[8] VINP
ADC12_INP8 VINN[8] Slow channel
SAR
ADC12_INN8 VINP[9]
ADC2
ADC12_INP9 VINN[9] Slow channel VINN
ADC12_INN9 VINP[10]
ADC12_INP10 VINN[10] Slow channel
ADC12_INN10 VINP[11] VREF−
ADC12_INP11 VINN[11] Slow channel
ADC12_INN11 VINP[12]
ADC12_INP12 VINN[12] Slow channel
ADC12_INN12 VINP[13]
ADC12_INP13 VINN[13] Slow channel
ADC12_INN13 VINP[14]
ADC12_INP14 VINN[14] Slow channel
ADC12_INN14 VINP[15]
ADC12_INP15 VINN[15] Slow channel
ADC12_INN15 VINP[16]
ADC12_INP16 VINN[16] Slow channel
VREF−
VINP[17]
dac_out1
VINN[17] Slow channel
VREF−
VINP[18]
dac_out2
VINN[18] Slow channel
VREF−

MSv50650V1

692/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.5 Slave AHB interface

The ADCs implement an AHB slave port for control/status register and data access. The
features of the AHB interface are listed below:
• Word (32-bit) accesses
• Single cycle response
• Response to all read/write accesses to the registers with zero wait states.
The AHB slave interface does not support split/retry requests, and never generates AHB
errors.

21.4.6 ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator

(ADVREGEN)
By default, the ADC is in Deep-power-down mode where its supply is internally switched off
to reduce the leakage currents (the reset state of bit DEEPPWD is 1 in the ADC_CR
register).
To start ADC operations, it is first needed to exit Deep-power-down mode by setting bit
DEEPPWD=0.
When ADC operations are complete, the ADC can be disabled (ADEN=0). It is possible to
save power by also disabling the ADC voltage regulator. This is done by writing bit
ADVREGEN=0.
Then, to save more power by reducing the leakage currents, it is also possible to re-enter in
ADC Deep-power-down mode by setting bit DEEPPWD=1 into ADC_CR register. This is
particularly interesting before entering Stop mode.
Note: Writing DEEPPWD=1 automatically disables the ADC voltage regulator and bit ADVREGEN
is automatically cleared.
When the internal voltage regulator is disabled (ADVREGEN=0), the internal analog
calibration is kept.
In ADC Deep-power-down mode (DEEPPWD=1), the internal analog calibration is lost and
it is necessary to either relaunch a calibration or re-apply the calibration factor which was
previously saved (refer to Section 21.4.8: Calibration (ADCAL, ADCALDIF,
ADC_CALFACT)).

21.4.7 Single-ended and differential input channels

Channels can be configured to be either single-ended input or differential input by
programming DIFSEL[i] bits in the ADC_DIFSEL register. This configuration must be written
while the ADC is disabled (ADEN=0). Note that the DIFSEL[i] bits corresponding to single-
ended channels are always programmed at 0.
In single-ended input mode, the analog voltage to be converted for channel “i” is the
difference between the ADCy_INPx external voltage equal to VINP[i] (positive input) and
VREF− (negative input).
In differential input mode, the analog voltage to be converted for channel “i” is the difference
between the ADCy_INPx external voltage positive input equal to VINP[i], and the
ADCy_INNx negative input equal to VINN[i].
The input voltage in differential mode ranges from VREF- to VREF+, which makes a full scale
range of 2xVREF+. When VINP[i] equals VREF-, VINN[i] equals VREF+and the maximum

RM0438 Rev 7 693/2194

796
Analog-to-digital converters (ADC) RM0438

negative input differential voltage (VREF-) corresponds to 0x000 ADC output. When VINP[i]
equals VREF+, VINN[i] equals VREF- and the maximum positive input differential voltage
(VREF+) corresponds to 0xFFF ADC output. When VINP[i] and VINN[i] are connected together,
the zero input differential voltage corresponds to 0x800 ADC output.
The ADC sensitivity in differential mode is twice smaller than in single-ended mode.
When ADC is configured as differential mode, both inputs should be biased at (VREF+) / 2
voltage. Refer to the device datasheet for the allowed common mode input voltage VCMIN.
The input signals are supposed to be differential (common mode voltage should be fixed).
Internal channels (such as VTS and VREFINT) are used in single-ended mode only.
For a complete description of how the input channels are connected for each ADC, refer to
Section 21.4.4: ADC1/2 connectivity.
Caution: When configuring the channel “i” in differential input mode, its negative input voltage VINN[i]
is connected to another channel. As a consequence, this channel is no longer usable in
single-ended mode or in differential mode and must never be configured to be converted.
Some channels are shared between ADC1/ADC2: this can make the channel on the other
ADC unusable. Only exception is interleaved mode for ADC master and the slave.

21.4.8 Calibration (ADCAL, ADCALDIF, ADC_CALFACT)

Each ADC provides an automatic calibration procedure which drives all the calibration
sequence including the power-on/off sequence of the ADC. During the procedure, the ADC
calculates a calibration factor which is 7-bit wide and which is applied internally to the ADC
until the next ADC power-off. During the calibration procedure, the application must not use
the ADC and must wait until calibration is complete.
Calibration is preliminary to any ADC operation. It removes the offset error which may vary
from chip to chip due to process or bandgap variation.
The calibration factor to be applied for single-ended input conversions is different from the
factor to be applied for differential input conversions:
• Write ADCALDIF=0 before launching a calibration which will be applied for single-
ended input conversions.
• Write ADCALDIF=1 before launching a calibration which will be applied for differential
input conversions.
The calibration is then initiated by software by setting bit ADCAL=1. Calibration can only be
initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the
calibration sequence. It is then cleared by hardware as soon the calibration completes. At
this time, the associated calibration factor is stored internally in the analog ADC and also in
the bits CALFACT_S[6:0] or CALFACT_D[6:0] of ADC_CALFACT register (depending on
single-ended or differential input calibration)
The internal analog calibration is kept if the ADC is disabled (ADEN=0). However, if the ADC
is disabled for extended periods, then it is recommended that a new calibration cycle is run
before re-enabling the ADC.
The internal analog calibration is lost each time the power of the ADC is removed (example,
when the product enters in Standby or VBAT mode). In this case, to avoid spending time
recalibrating the ADC, it is possible to re-write the calibration factor into the ADC_CALFACT
register without recalibrating, supposing that the software has previously saved the
calibration factor delivered during the previous calibration.

694/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and
ADSTART=0 and JADSTART=0). Then, at the next start of conversion, the calibration factor
will automatically be injected into the analog ADC. This loading is transparent and does not
add any cycle latency to the start of the conversion. It is recommended to recalibrate when
VREF+ voltage changed more than 10%.

Software procedure to calibrate the ADC

1. Ensure DEEPPWD=0, ADVREGEN=1 and that ADC voltage regulator startup time has
elapsed.
2. Ensure that ADEN=0.
3. Select the input mode for this calibration by setting ADCALDIF=0 (single-ended input)
or ADCALDIF=1 (differential input).
4. Set ADCAL=1.
5. Wait until ADCAL=0.
6. The calibration factor can be read from ADC_CALFACT register.

Figure 95. ADC calibration

ADCALDIF 0: Single-ended input 1: Differential input

tCAB
ADCAL

ADC State OFF Startup Calibrate OFF

CALFACT_x[6:0] 0x00 Calibration factor

by S/W by H/W Indicative timings

MSv30263V2

Software procedure to re-inject a calibration factor into the ADC

1. Ensure ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no
conversion is ongoing).
2. Write CALFACT_S and CALFACT_D with the new calibration factors.
3. When a conversion is launched, the calibration factor will be injected into the analog
ADC only if the internal analog calibration factor differs from the one stored in bits
CALFACT_S for single-ended input channel or bits CALFACT_D for differential input
channel.

RM0438 Rev 7 695/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 96. Updating the ADC calibration factor

ADC state Ready (not converting) Converting channel Ready Converting channel
(Single ended) (Single ended)
Updating calibration
Internal
calibration factor[6:0] F1 F2

Start conversion
(hardware or sofware)

WRITE ADC_CALFACT

CALFACT_S[6:0] F2

by s/w by h/w
MSv30529V2

Converting single-ended and differential analog inputs with a single ADC

If the ADC is supposed to convert both differential and single-ended inputs, two calibrations
must be performed, one with ADCALDIF=0 and one with ADCALDIF=1. The procedure is
the following:
1. Disable the ADC.
2. Calibrate the ADC in single-ended input mode (with ADCALDIF=0). This updates the
register CALFACT_S[6:0].
3. Calibrate the ADC in differential input modes (with ADCALDIF=1). This updates the
register CALFACT_D[6:0].
4. Enable the ADC, configure the channels and launch the conversions. Each time there
is a switch from a single-ended to a differential inputs channel (and vice-versa), the
calibration will automatically be injected into the analog ADC.

Figure 97. Mixing single-ended and differential channels

Trigger event

ADC state RDY CONV CH 1 RDY CONV CH2 RDY CONV CH3 RDY CONV CH4
Single ended (Differential (Differential (Single inputs
inputs channel) inputs channel) inputs channel) channel)

Internal
calibration factor[6:0] F2 F3 F2

CALFACT_S[6:0] F2

CALFACT_D[6:0] F3

MSv30530V2

696/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.9 ADC on-off control (ADEN, ADDIS, ADRDY)

First of all, follow the procedure explained in Section 21.4.6: ADC Deep-power-down mode
(DEEPPWD) and ADC voltage regulator (ADVREGEN)).
Once DEEPPWD=0 and ADVREGEN=1, the ADC can be enabled and the ADC needs a
stabilization time of tSTAB before it starts converting accurately, as shown in Figure 98. Two
control bits enable or disable the ADC:
• ADEN=1 enables the ADC. The flag ADRDY will be set once the ADC is ready for
operation.
• ADDIS=1 disables the ADC. ADEN and ADDIS are then automatically cleared by
hardware as soon as the analog ADC is effectively disabled.
Regular conversion can then start either by setting ADSTART=1 (refer to Section 21.4.18:
Conversion on external trigger and trigger polarity (EXTSEL, EXTEN, JEXTSEL, JEXTEN))
or when an external trigger event occurs, if triggers are enabled.
Injected conversions start by setting JADSTART=1 or when an external injected trigger
event occurs, if injected triggers are enabled.

Software procedure to enable the ADC

1. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’.
2. Set ADEN=1.
3. Wait until ADRDY=1 (ADRDY is set after the ADC startup time). This can be done
using the associated interrupt (setting ADRDYIE=1).
4. Clear the ADRDY bit in the ADC_ISR register by writing ‘1’ (optional).
Caution: ADEN bit cannot be set when ADCAL is set and during four ADC clock cycles after the
ADCAL bit is cleared by hardware (end of the calibration).

Software procedure to disable the ADC

1. Check that both ADSTART=0 and JADSTART=0 to ensure that no conversion is
ongoing. If required, stop any regular and injected conversion ongoing by setting
ADSTP=1 and JADSTP=1 and then wait until ADSTP=0 and JADSTP=0.
2. Set ADDIS=1.
3. If required by the application, wait until ADEN=0, until the analog ADC is effectively
disabled (ADDIS will automatically be reset once ADEN=0).

RM0438 Rev 7 697/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 98. Enabling / disabling the ADC

ADEN
tSTAB

ADRDY

ADDIS

ADC REQ
state OFF Startup RDY Converting CH RDY OFF
-OF

by S/W by H/W
MSv30264V2

21.4.10 Constraints when writing the ADC control bits

The software is allowed to write the RCC control bits to configure and enable the ADC clock
(refer to RCC Section), the DIFSEL[i] control bits in the ADC_DIFSEL register and the
control bits ADCAL and ADEN in the ADC_CR register, only if the ADC is disabled (ADEN
must be equal to 0).
The software is then allowed to write the control bits ADSTART, JADSTART and ADDIS of
the ADC_CR register only if the ADC is enabled and there is no pending request to disable
the ADC (ADEN must be equal to 1 and ADDIS to 0).
For all the other control bits of the ADC_CFGR, ADC_SMPRx, ADC_SQRy, ADC_JDRy,
ADC_OFRy, ADC_OFCHRy and ADC_IER registers:
• For control bits related to configuration of regular conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no regular conversion
ongoing (ADSTART must be equal to 0).
• For control bits related to configuration of injected conversions, the software is allowed
to write them only if the ADC is enabled (ADEN=1) and if there is no injected
conversion ongoing (JADSTART must be equal to 0).
The software is allowed to write the ADSTP or JADSTP control bits of the ADC_CR register
only if the ADC is enabled, possibly converting, and if there is no pending request to disable
the ADC (ADSTART or JADSTART must be equal to 1 and ADDIS to 0).
The software can write the register ADC_JSQR at any time, when the ADC is enabled
(ADEN=1). Refer to Section 21.6.16: ADC injected sequence register (ADC_JSQR) for
additional details.
Note: There is no hardware protection to prevent these forbidden write accesses and ADC
behavior may become in an unknown state. To recover from this situation, the ADC must be
disabled (clear ADEN=0 as well as all the bits of ADC_CR register).

698/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.11 Channel selection (SQRx, JSQRx)

There are up to 20 multiplexed channels per ADC:
• Up to 11 slow analog inputs coming from GPIO pads (ADCx_INP/INN[6:16])
Depending on the products, not all of them are available on GPIO pads.
• The ADCs are connected to the following internal analog inputs:
– The internal reference voltage (VREFINT) is connected to ADC1_INP0/INN0.
– The internal temperature sensor (VTS) is connected to ADC1_INP17/INN17.
– The VBAT monitoring channel (VBAT/3) is connected to ADC1_INP18/INN18.
– The DAC1 internal channel 1 is connected to ADC2_INP/INN17.
– The DAC1 internal channel 2 is connected to ADC2_INP/INN18.
Note: To convert one of the internal analog channels, the corresponding analog sources must first
be enabled by programming bits VREFEN, CH17SEL or CH18SEL in the ADCx_CCR
registers.
It is possible to organize the conversions in two groups: regular and injected. A group
consists of a sequence of conversions that can be done on any channel and in any order.
For instance, it is possible to implement the conversion sequence in the following order:
ADCx_INP/INN3, ADCx_INP/INN8, ADCx_INP/INN2, ADCx_INN/INP2, ADCx_INP/INN0,
ADCx_INP/INN2, ADCx_INP/INN2, ADCx_INP/INN15.
• A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRy registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
• An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
ADC_SQRy registers must not be modified while regular conversions can occur. For this,
the ADC regular conversions must be first stopped by writing ADSTP=1 (refer to
Section 21.4.17: Stopping an ongoing conversion (ADSTP, JADSTP)).
The software is allowed to modify on-the-fly the ADC_JSQR register when JADSTART is
set to 1 (injected conversions ongoing) only when the context queue is enabled (JQDIS=0 in
ADC_CFGR register). Refer to Section 21.4.21: Queue of context for injected conversions

RM0438 Rev 7 699/2194

796
Analog-to-digital converters (ADC) RM0438

21.4.12 Channel-wise programmable sampling time (SMPR1, SMPR2)

Before starting a conversion, the ADC must establish a direct connection between the
voltage source under measurement and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the embedded
capacitor to the input voltage level.
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADC_SMPR1 and ADC registers. It is therefore possible to select
among the following sampling time values:
• SMP = 000: 2.5 ADC clock cycles
• SMP = 001: 6.5 ADC clock cycles
• SMP = 010: 12.5 ADC clock cycles
• SMP = 011: 24.5 ADC clock cycles
• SMP = 100: 47.5 ADC clock cycles
• SMP = 101: 92.5 ADC clock cycles
• SMP = 110: 247.5 ADC clock cycles
• SMP = 111: 640.5 ADC clock cycles
The total conversion time is calculated as follows:
TCONV = Sampling time + 12.5 ADC clock cycles
Example:
With FADC_CLK = 30 MHz and a sampling time of 2.5 ADC clock cycles:
TCONV = (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 500 ns
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).

Constraints on the sampling time

For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC characteristics section of the datasheets.

I/O analog switches voltage booster

The I/O analog switches resistance increases when the VDDA voltage is too low. This
requires to have the sampling time adapted accordingly (cf datasheet for electrical
characteristics). This resistance can be minimized at low VDDA by enabling an internal
voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register.

21.4.13 Single conversion mode (CONT=0)

In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
• Setting the ADSTART bit in the ADC_CR register (for a regular channel)
• Setting the JADSTART bit in the ADC_CR register (for an injected channel)
• External hardware trigger event (for a regular or injected channel)

700/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Inside the regular sequence, after each conversion is complete:

• The converted data are stored into the 16-bit ADC_DR register
• The EOC (end of regular conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
Inside the injected sequence, after each conversion is complete:
• The converted data are stored into one of the four 16-bit ADC_JDRy registers
• The JEOC (end of injected conversion) flag is set
• An interrupt is generated if the JEOCIE bit is set
After the regular sequence is complete:
• The EOS (end of regular sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
After the injected sequence is complete:
• The JEOS (end of injected sequence) flag is set
• An interrupt is generated if the JEOSIE bit is set
Then the ADC stops until a new external regular or injected trigger occurs or until bit
ADSTART or JADSTART is set again.
Note: To convert a single channel, program a sequence with a length of 1.

21.4.14 Continuous conversion mode (CONT=1)

This mode applies to regular channels only.
In continuous conversion mode, when a software or hardware regular trigger event occurs,
the ADC performs once all the regular conversions of the channels and then automatically
restarts and continuously converts each conversions of the sequence. This mode is started
with the CONT bit at 1 either by external trigger or by setting the ADSTART bit in the
ADC_CR register.
Inside the regular sequence, after each conversion is complete:
• The converted data are stored into the 16-bit ADC_DR register
• The EOC (end of conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
After the sequence of conversions is complete:
• The EOS (end of sequence) flag is set
• An interrupt is generated if the EOSIE bit is set
Then, a new sequence restarts immediately and the ADC continuously repeats the
conversion sequence.
Note: To convert a single channel, program a sequence with a length of 1.
It is not possible to have both discontinuous mode and continuous mode enabled: it is
forbidden to set both DISCEN=1 and CONT=1.
Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection mode section).

RM0438 Rev 7 701/2194

796
Analog-to-digital converters (ADC) RM0438

21.4.15 Starting conversions (ADSTART, JADSTART)

Software starts ADC regular conversions by setting ADSTART=1.
When ADSTART is set, the conversion starts:
• Immediately: if EXTEN[1:0] = 00 (software trigger)
• At the next active edge of the selected regular hardware trigger: if EXTEN[1:0] is not
equal to 00
Software starts ADC injected conversions by setting JADSTART=1.
When JADSTART is set, the conversion starts:
• Immediately, if JEXTEN[1:0] = 00 (software trigger)
• At the next active edge of the selected injected hardware trigger: if JEXTEN[1:0] is not
equal to 00
Note: In auto-injection mode (JAUTO=1), use ADSTART bit to start the regular conversions
followed by the auto-injected conversions (JADSTART must be kept cleared).
ADSTART and JADSTART also provide information on whether any ADC operation is
currently ongoing. It is possible to re-configure the ADC while ADSTART=0 and
JADSTART=0 are both true, indicating that the ADC is idle.
ADSTART is cleared by hardware:
• In single mode with software regular trigger (CONT=0, EXTSEL=0x0)
– At any end of regular conversion sequence (EOS assertion) or at any end of
subgroup processing if DISCEN = 1
• In all cases (CONT=x, EXTSEL=x)
– After execution of the ADSTP procedure asserted by the software.
Note: In continuous mode (CONT=1), ADSTART is not cleared by hardware with the assertion of
EOS because the sequence is automatically relaunched.
When a hardware trigger is selected in single mode (CONT=0 and EXTSEL≠0x00),
ADSTART is not cleared by hardware with the assertion of EOS to help the software which
does not need to reset ADSTART again for the next hardware trigger event. This ensures
that no further hardware triggers are missed.
JADSTART is cleared by hardware:
• In single mode with software injected trigger (JEXTSEL = 0x0)
– At any end of injected conversion sequence (JEOS assertion) or at any end of
subgroup processing if JDISCEN = 1
• in all cases (JEXTSEL=x)
– After execution of the JADSTP procedure asserted by the software.
Note: When the software trigger is selected, ADSTART bit should not be set if the EOC flag is still
high.

702/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.16 ADC timing

The elapsed time between the start of a conversion and the end of conversion is the sum of
the configured sampling time plus the successive approximation time depending on data
resolution:

TCONV= TSMPL + TSAR = [2.5 |min + 12.5 |12bit ] x TADC_CLK

TCONV = TSMPL + TSAR = 83.33 ns |min + 416.67 ns |12bit = 500.0 ns (for FADC_CLK = 30 MHz)

Figure 99. Analog to digital conversion time

ADC state RDY Sampling Ch(N) Converting Ch(N) Sampling Ch(N+1)

Analog channel Ch(N) Ch(N+1)

Internal S/H Sample AIN(N) Hold AIN(N) Sample AIN(N+1)

tSMPL(1) tSAR(2)
Set by
ADSTART SW
Set by Cleared
EOSMP SW by SW
Set by Cleared
SW by SW
EOC

ADC_DR Data N-1 Data N

Indicative timings
MS30532V1

1. TSMPL depends on SMP[2:0].

2. TSAR depends on RES[2:0].

21.4.17 Stopping an ongoing conversion (ADSTP, JADSTP)

The software can decide to stop regular conversions ongoing by setting ADSTP=1 and
injected conversions ongoing by setting JADSTP=1.
Stopping conversions will reset the ongoing ADC operation. Then the ADC can be
reconfigured (ex: changing the channel selection or the trigger) ready for a new operation.
Note that it is possible to stop injected conversions while regular conversions are still
operating and vice-versa. This allows, for instance, re-configuration of the injected
conversion sequence and triggers while regular conversions are still operating (and vice-
versa).
When the ADSTP bit is set by software, any ongoing regular conversion is aborted with
partial result discarded (ADC_DR register is not updated with the current conversion).
When the JADSTP bit is set by software, any ongoing injected conversion is aborted with
partial result discarded (ADC_JDRy register is not updated with the current conversion).
The scan sequence is also aborted and reset (meaning that relaunching the ADC would
restart a new sequence).
Once this procedure is complete, bits ADSTP/ADSTART (in case of regular conversion), or
JADSTP/JADSTART (in case of injected conversion) are cleared by hardware and the
software must poll ADSTART (or JADSTART) until the bit is reset before assuming the ADC
is completely stopped.

RM0438 Rev 7 703/2194

796
Analog-to-digital converters (ADC) RM0438

Note: In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (JADSTP must not be used).

Figure 100. Stopping ongoing regular conversions

Trigger Trigger

ADC state Sample Convert Sample

RDY Ch(N-1) RDY C RDY
Ch(N-1) Ch(N)

JADSTART

Cleared by Cleared by
ADSTART HW REGULAR CONVERSIONS ongoing HW
(software is not allowed to configure regular conversions selection and triggers)

Set by Cleared by
ADSTP SW HW

ADC_DR Data N-2 Data N-1

MSv30533V2

Figure 101. Stopping ongoing regular and injected conversions

Regular trigger Injected trigger Regular trigger

Sample Convert Sample

ADC state RDY
Ch(N-1) Ch(N-1)
RDY
Ch(M)
C RDY Sampl RDY

Set by Cleared
JADSTART SW INJECTED CONVERSIONS ongoing by HW
(software is not allowed to configure injected conversions selection and triggers)
Set by Cleared
JADSTP SW by HW

ADC_JDR DATA M-1

Set by Cleared
ADSTART SW REGULAR CONVERSIONS ongoing by HW
(software is not allowed to configure regular conversions selection and triggers)
Set by Cleared
ADSTP SW by HW

ADC_DR DATA N-2 DATA N-1

MS30534V1

704/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.18 Conversion on external trigger and trigger polarity

(EXTSEL, EXTEN, JEXTSEL, JEXTEN)
A conversion or a sequence of conversions can be triggered either by software or by an
external event (e.g. timer capture, input pins). If the EXTEN[1:0] control bits (for a regular
conversion) or JEXTEN[1:0] bits (for an injected conversion) are different from 0b00, then
external events are able to trigger a conversion with the selected polarity.
When the Injected Queue is enabled (bit JQDIS=0), injected software triggers are not
possible.
The regular trigger selection is effective once software has set bit ADSTART=1 and the
injected trigger selection is effective once software has set bit JADSTART=1.
Any hardware triggers which occur while a conversion is ongoing are ignored.
• If bit ADSTART=0, any regular hardware triggers which occur are ignored.
• If bit JADSTART=0, any injected hardware triggers which occur are ignored.
Table 159 provides the correspondence between the EXTEN[1:0] and JEXTEN[1:0] values
and the trigger polarity.

Table 159. Configuring the trigger polarity for regular external triggers
EXTEN[1:0] Source

00 Hardware Trigger detection disabled, software trigger detection enabled

01 Hardware Trigger with detection on the rising edge
10 Hardware Trigger with detection on the falling edge
11 Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the regular trigger cannot be changed on-the-fly.

Table 160. Configuring the trigger polarity for injected external triggers
JEXTEN[1:0] Source

– If JQDIS=1 (Queue disabled): Hardware trigger detection disabled, software

00 trigger detection enabled
– If JQDIS=0 (Queue enabled), Hardware and software trigger detection disabled
01 Hardware Trigger with detection on the rising edge
10 Hardware Trigger with detection on the falling edge
11 Hardware Trigger with detection on both the rising and falling edges

Note: The polarity of the injected trigger can be anticipated and changed on-the-fly when the
queue is enabled (JQDIS=0). Refer to Section 21.4.21: Queue of context for injected
conversions.
The EXTSEL and JEXTSEL control bits select which out of 16 possible events can trigger
conversion for the regular and injected groups.
A regular group conversion can be interrupted by an injected trigger.

RM0438 Rev 7 705/2194

796
Analog-to-digital converters (ADC) RM0438

Note: The regular trigger selection cannot be changed on-the-fly.

The injected trigger selection can be anticipated and changed on-the-fly. Refer to
Section 21.4.21: Queue of context for injected conversions on page 710
Each ADC master shares the same input triggers with its ADC slave as described in
Figure 102.

Figure 102. Triggers sharing between ADC master and ADC slave

ADC MASTER

Regular EXT0
sequencer EXT1 External regular trigger
..............
triggers
EXT15

EXTSEL[3:0]

External injected trigger

JEXTSEL[3:0]

ADC SLAVE

External regular trigger

EXTSEL[3:0]
JEXT0
Injected JEXT1 External injected trigger
sequencer ..............
triggers
JEXT15
JEXTSEL[3:0]
MS35356V1

Table 161 to Table 162 give all the possible external triggers of the three ADCs for regular
and injected conversions.

Table 161. ADC1/2 - External triggers for regular channels

Name Source Type EXTSEL[3:0]

EXT0 TIM1_CH1 Internal signal from on-chip timers 0000

EXT1 TIM1_CH2 Internal signal from on-chip timers 0001
EXT2 TIM1_CH3 Internal signal from on-chip timers 0010
EXT3 TIM2_CH2 Internal signal from on-chip timers 0011
EXT4 TIM3_TRGO Internal signal from on-chip timers 0100
EXT5 TIM4_CH4 Internal signal from on-chip timers 0101
EXT6 EXTI line 11 External pin 0110
EXT7 TIM8_TRGO Internal signal from on-chip timers 0111
EXT8 TIM8_TRGO2 Internal signal from on-chip timers 1000
EXT9 TIM1_TRGO Internal signal from on-chip timers 1001

706/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Table 161. ADC1/2 - External triggers for regular channels (continued)

Name Source Type EXTSEL[3:0]

EXT10 TIM1_TRGO2 Internal signal from on-chip timers 1010

EXT11 TIM2_TRGO Internal signal from on-chip timers 1011
EXT12 TIM4_TRGO Internal signal from on-chip timers 1100
EXT13 TIM6_TRGO Internal signal from on-chip timers 1101
EXT14 TIM15_TRGO Internal signal from on-chip timers 1110
EXT15 TIM3_CH4 Internal signal from on-chip timers 1111

Table 162. ADC1/2 - External trigger for injected channels

Name Source Type JEXTSEL[3:0]

JEXT0 TIM1_TRGO Internal signal from on-chip timers 0000

JEXT1 TIM1_CH4 Internal signal from on-chip timers 0001
JEXT2 TIM2_TRGO Internal signal from on-chip timers 0010
JEXT3 TIM2_CH1 Internal signal from on-chip timers 0011
JEXT4 TIM3_CH4 Internal signal from on-chip timers 0100
JEXT5 TIM4_TRGO Internal signal from on-chip timers 0101
JEXT6 EXTI line 15 External pin 0110
JEXT7 TIM8_CH4 Internal signal from on-chip timers 0111
JEXT8 TIM1_TRGO2 Internal signal from on-chip timers 1000
JEXT9 TIM8_TRGO Internal signal from on-chip timers 1001
JEXT10 TIM8_TRGO2 Internal signal from on-chip timers 1010
JEXT11 TIM3_CH3 Internal signal from on-chip timers 1011
JEXT12 TIM3_TRGO Internal signal from on-chip timers 1100
JEXT13 TIM3_CH1 Internal signal from on-chip timers 1101
JEXT14 TIM6_TRGO Internal signal from on-chip timers 1110
JEXT15 TIM15_TRGO Internal signal from on-chip timers 1111

21.4.19 Injected channel management

Triggered injection mode
To use triggered injection, the JAUTO bit in the ADC_CFGR register must be cleared.
1. Start the conversion of a group of regular channels either by an external trigger or by
setting the ADSTART bit in the ADC_CR register.
2. If an external injected trigger occurs, or if the JADSTART bit in the ADC_CR register is
set during the conversion of a regular group of channels, the current conversion is

RM0438 Rev 7 707/2194

796
Analog-to-digital converters (ADC) RM0438

reset and the injected channel sequence switches are launched (all the injected
channels are converted once).
3. Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
4. If a regular event occurs during an injected conversion, the injected conversion is not
interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 103 shows the corresponding timing diagram.
Note: When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 30 ADC clock
cycles (that is two conversions with a sampling time of 2.5 clock periods), the minimum
interval between triggers must be 31 ADC clock cycles.

Auto-injection mode
If the JAUTO bit in the ADC_CFGR register is set, then the channels in the injected group
are automatically converted after the regular group of channels. This can be used to convert
a sequence of up to 20 conversions programmed in the ADC_SQRy and ADC_JSQR
registers.
In this mode, the ADSTART bit in the ADC_CR register must be set to start regular
conversions, followed by injected conversions (JADSTART must be kept cleared). Setting
the ADSTP bit aborts both regular and injected conversions (JADSTP bit must not be used).
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note: It is not possible to use both the auto-injected and discontinuous modes simultaneously.
When the DMA is used for exporting regular sequencer’s data in JAUTO mode, it is
necessary to program it in circular mode (CIRC bit set in DMA_CCRx register). If the CIRC
bit is reset (single-shot mode), the JAUTO sequence will be stopped upon DMA Transfer
Complete event.

708/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 103. Injected conversion latency

ADCCLK

Injection event

Reset ADC

(1)
max. latency
SOC

ai16049b

1. The maximum latency value can be found in the electrical characteristics of the device datasheet.

21.4.20 Discontinuous mode (DISCEN, DISCNUM, JDISCEN)

Regular group mode
This mode is enabled by setting the DISCEN bit in the ADC_CFGR register.
It is used to convert a short sequence (subgroup) of n conversions (n ≤ 8) that is part of the
sequence of conversions selected in the ADC_SQRy registers. The value of n is specified
by writing to the DISCNUM[2:0] bits in the ADC_CFGR register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRy
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
Example:
• DISCEN=1, n=3, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10, 11
– 1st trigger: channels converted are 1, 2, 3 (an EOC event is generated at each
conversion).
– 2nd trigger: channels converted are 6, 7, 8 (an EOC event is generated at each
conversion).
– 3rd trigger: channels converted are 9, 10, 11 (an EOC event is generated at each
conversion) and an EOS event is generated after the conversion of channel 11.
– 4th trigger: channels converted are 1, 2, 3 (an EOC event is generated at each
conversion).
– ...
• DISCEN=0, channels to be converted = 1, 2, 3, 6, 7, 8, 9, 10,11
– 1st trigger: the complete sequence is converted: channel 1, then 2, 3, 6, 7, 8, 9, 10
and 11. Each conversion generates an EOC event and the last one also generates
an EOS event.
– All the next trigger events will relaunch the complete sequence.

RM0438 Rev 7 709/2194

796
Analog-to-digital converters (ADC) RM0438

Note: The channel numbers referred to in the above example might not be available on all
microcontrollers.
When a regular group is converted in discontinuous mode, no rollover occurs (the last
subgroup of the sequence can have less than n conversions).
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 1, 2 and 3 in the
1st subgroup.
It is not possible to have both discontinuous mode and continuous mode enabled. In this
case (if DISCEN=1, CONT=1), the ADC behaves as if continuous mode was disabled.

Injected group mode

This mode is enabled by setting the JDISCEN bit in the ADC_CFGR register. It converts the
sequence selected in the ADC_JSQR register, channel by channel, after an external
injected trigger event. This is equivalent to discontinuous mode for regular channels where
‘n’ is fixed to 1.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
• JDISCEN=1, channels to be converted = 1, 2, 3
– 1st trigger: channel 1 converted (a JEOC event is generated)
– 2nd trigger: channel 2 converted (a JEOC event is generated)
– 3rd trigger: channel 3 converted and a JEOC event + a JEOS event are generated
– ...
Note: The channel numbers referred to in the above example might not be available on all
microcontrollers.
When all injected channels have been converted, the next trigger starts the conversion of
the first injected channel. In the example above, the 4th trigger reconverts the 1st injected
channel 1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously:
the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.

21.4.21 Queue of context for injected conversions

A queue of context is implemented to anticipate up to 2 contexts for the next injected
sequence of conversions. JQDIS bit of ADC_CFGR register must be reset to enable this
feature. Only hardware-triggered conversions are possible when the context queue is
enabled.
This context consists of:
• Configuration of the injected triggers (bits JEXTEN[1:0] and JEXTSEL bits in
ADC_JSQR register)
• Definition of the injected sequence (bits JSQx[4:0] and JL[1:0] in ADC_JSQR register)

710/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

All the parameters of the context are defined into a single register ADC_JSQR and this
register implements a queue of 2 buffers, allowing the bufferization of up to 2 sets of
parameters:
• The JSQR register can be written at any moment even when injected conversions are
ongoing.
• Each data written into the JSQR register is stored into the Queue of context.
• At the beginning, the Queue is empty and the first write access into the JSQR register
immediately changes the context and the ADC is ready to receive injected triggers.
• Once an injected sequence is complete, the Queue is consumed and the context
changes according to the next JSQR parameters stored in the Queue. This new
context is applied for the next injected sequence of conversions.
• A Queue overflow occurs when writing into register JSQR while the Queue is full. This
overflow is signaled by the assertion of the flag JQOVF. When an overflow occurs, the
write access of JSQR register which has created the overflow is ignored and the queue
of context is unchanged. An interrupt can be generated if bit JQOVFIE is set.
• Two possible behaviors are possible when the Queue becomes empty, depending on
the value of the control bit JQM of register ADC_CFGR:
– If JQM=0, the Queue is empty just after enabling the ADC, but then it can never be
empty during run operations: the Queue always maintains the last active context
and any further valid start of injected sequence will be served according to the last
active context.
– If JQM=1, the Queue can be empty after the end of an injected sequence or if the
Queue is flushed. When this occurs, there is no more context in the queue and
hardware triggers are disabled. Therefore, any further hardware injected triggers
are ignored until the software re-writes a new injected context into JSQR register.
• Reading JSQR register returns the current JSQR context which is active at that
moment. When the JSQR context is empty, JSQR is read as 0x0000.
• The Queue is flushed when stopping injected conversions by setting JADSTP=1 or
when disabling the ADC by setting ADDIS=1:
– If JQM=0, the Queue is maintained with the last active context.
– If JQM=1, the Queue becomes empty and triggers are ignored.
Note: When configured in discontinuous mode (bit JDISCEN=1), only the last trigger of the
injected sequence changes the context and consumes the Queue.The 1st trigger only
consumes the queue but others are still valid triggers as shown by the discontinuous mode
example below (length = 3 for both contexts):
• 1st trigger, discontinuous. Sequence 1: context 1 consumed, 1st conversion carried out
• 2nd trigger, disc. Sequence 1: 2nd conversion.
• 3rd trigger, discontinuous. Sequence 1: 3rd conversion.
• 4th trigger, discontinuous. Sequence 2: context 2 consumed, 1st conversion carried out.
• 5th trigger, discontinuous. Sequence 2: 2nd conversion.
• 6th trigger, discontinuous. Sequence 2: 3rd conversion.

RM0438 Rev 7 711/2194

796
Analog-to-digital converters (ADC) RM0438

Behavior when changing the trigger or sequence context

The Figure 104 and Figure 105 show the behavior of the context Queue when changing the
sequence or the triggers.

Figure 104. Example of JSQR queue of context (sequence change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3 P3

Trigger 1
ADC J context
EMPTY P1 P2 P3
(returned by reading
JQSR)
ADC state RDY Conversion1 Conversion2 Conversion3 RDY Conversion1 RDY

MS30536V2

1. Parameters:
P1: sequence of 3 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 4 conversions, hardware trigger 1

Figure 105. Example of JSQR queue of context (trigger change)

P1 P2 P3

Write JSQR

JSQR queue EMPTY P1 P1,P2 P2 P2,P3 P3

Ignored

Trigger 1

Ignored
Trigger 2
ADC J context
EMPTY P1 P2 P3
(returned by reading
JQSR)
ADC state RDY Conversion1 Conversion2 RDY Conversion1 RDY

MS30537V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 4 conversions, hardware trigger 1

712/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Queue of context: Behavior when a queue overflow occurs

The Figure 106 and Figure 107 show the behavior of the context Queue if an overflow
occurs before or during a conversion.

Figure 106. Example of JSQR queue of context with overflow before conversion
P1 P2 P3 => Overflow, P4
ignored
Write JSQR

JSQR
EMPTY P1 P1, P2 P2 P2, P4
queue
Cleared by SW
JQOVF

Trigger 1

Trigger 2

ADC
J context
EMPTY P1 P2
(returned by
reading JQSR)

ADC state RDY Conversion1 Conversion2 RDY Conversion1

JEOS

MS30538V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

Figure 107. Example of JSQR queue of context with overflow during conversion

P1 P2 P3 => Overflow, P4
ignored
Write JSQR

JSQR
EMPTY P1 P1, P2 P2 P2, P4
queue
Cleared by SW
JQOVF

Trigger 1

Trigger 2
ADC
J context
(returned by EMPTY P1 P2
reading JQSR)

ADC state RDY Conversion1 Conversion2 RDY Conversion1

JEOS

MS30539V2

1. Parameters:
P1: sequence of 2 conversions, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 2
P3: sequence of 3 conversions, hardware trigger 1
P4: sequence of 4 conversions, hardware trigger 1

RM0438 Rev 7 713/2194

796
Analog-to-digital converters (ADC) RM0438

It is recommended to manage the queue overflows as described below:

• After each P context write into JSQR register, flag JQOVF shows if the write has been
ignored or not (an interrupt can be generated).
• Avoid Queue overflows by writing the third context (P3) only once the flag JEOS of the
previous context P2 has been set. This ensures that the previous context has been
consumed and that the queue is not full.

Queue of context: Behavior when the queue becomes empty

Figure 108 and Figure 109 show the behavior of the context Queue when the Queue
becomes empty in both cases JQM=0 or 1.

Figure 108. Example of JSQR queue of context with empty queue (case JQM=0)

Queue not empty

The queue is not empty
(P3 maintained)
and maintains P2 because JQM=0
P1 P2 P3

Write JSQR

EMPTY P1 P1, P2 P2 P3
JSQR queue

Trigger 1

ADC J context
(returned by EMPTY P1 P2 P3
reading JQSR)

ADC state RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY Conv

MS30540V3

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1
Note: When writing P3, the context changes immediately. However, because of internal
resynchronization, there is a latency and if a trigger occurs just after or before writing P3, it
can happen that the conversion is launched considering the context P2. To avoid this
situation, the user must ensure that there is no ADC trigger happening when writing a new
context that applies immediately.

714/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 109. Example of JSQR queue of context with empty queue (case JQM=1)

Queue becomes empty

and triggers are ignored
P1 P2 because JQM=1 P3
Write JSQR

JSQR
EMPTY P1 P1,P2 P2 EMPTY P3 EMPTY
queue
Ignored Ignored
Trigger 1
ADC
J context EMPTY P1 P2 EMPTY (0x0000) P3 EMPTY
(returned by reading JQSR)
ADC state RDY Conversion1 RDY Conversion1 RDY Conversion1 RDY

MS30541V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Flushing the queue of context

The figures below show the behavior of the context Queue in various situations when the
queue is flushed.

Figure 110. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion.

Queue is flushed and maintains

P1 P2 the last active context P3
(P2 is lost)
Write JSQR

JSQR queue EMPTY P1 P1, P2 P1 P3

Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J context EMPTY P1 P3

(returned by reading JSQR)

ADC state RDY STP RDY Conversion1 RDY

MS30544V2

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

RM0438 Rev 7 715/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 111. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs during an ongoing conversion and a new
trigger occurs.
Queue is flushed and maintains
P1 P2 the last active context P3
(P2 is lost)
Write JSQR
JSQR
queue EMPTY P1 P1, P2 P1 P1, P3 P3
Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J
context EMPTY P1 P3
(returned by reading JSQR)

ADC state RDY Conv1 STP RDY Conversion1 RDY Conversion1 RDY
(Aborted)
MS30543V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 112. Flushing JSQR queue of context by setting JADSTP=1 (JQM=0).

Case when JADSTP occurs outside an ongoing conversion
P1 P2 the last active context P3
(P2 is lost)
Write JSQR

JSQR queue EMPTY P1 P1, P2 P1 P3

Set Reset
JADSTP by S/W by H/W
JADSTART Reset
by H/W Set
by S/W
Trigger 1

ADC J context EMPTY P1 P3

(returned byreading JSQR)

ADC state RDY STP RDY Conversion1 RDY

MS30544V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

716/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 113. Flushing JSQR queue of context by setting JADSTP=1 (JQM=1)

Queue is flushed and
becomes empty (P2 is lost)
P1 P2 P3
Write JSQR

JSQR queue EMPTY P1 P1, P2 EMPTY P3 EMPTY

Set Reset
by S/W by H/W
JADSTP
JADSTART
Reset Set
by H/W by S/W
Ignored
Trigger 1

ADC J context EMPTY P1 EMPTY (0x0000) P3 EMPTY

(returned by reading JSQR)

ADC state RDY Conv1 STP RDY Conversion1 RDY

(Aborted)
MS30545V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Figure 114. Flushing JSQR queue of context by setting ADDIS=1 (JQM=0)

Queue is flushed and maintains

the last active context
(P2 which was not consumed is lost)

JSQR queue P1, P2 P1

Set Reset
ADDIS by S/W by H/W

ADC J context P1
(returned by reading JSQR)

ADC state RDY REQ-OFF OFF

MS30546V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

RM0438 Rev 7 717/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 115. Flushing JSQR queue of context by setting ADDIS=1 (JQM=1)

Queue is flushed and beomes empty

(JSQR is read as 0x0000)

JSQR queue P1, P2 EMPTY

Set Reset
ADDIS by S/W by H/W

ADC J context P1 EMPTY (0x0000)

(returned by reading JSQR)

ADC state RDY REQ-OFF OFF

MS30547V1

1. Parameters:
P1: sequence of 1 conversion, hardware trigger 1
P2: sequence of 1 conversion, hardware trigger 1
P3: sequence of 1 conversion, hardware trigger 1

Queue of context: Starting the ADC with an empty queue

The following procedure must be followed to start ADC operation with an empty queue, in
case the first context is not known at the time the ADC is initialized. This procedure is only
applicable when JQM bit is reset:
5. Write a dummy JSQR with JEXTEN[1:0] not equal to 00 (otherwise triggering a
software conversion)
6. Set JADSTART
7. Set JADSTP
8. Wait until JADSTART is reset
9. Set JADSTART.

Disabling the queue

It is possible to disable the queue by setting bit JQDIS=1 into the ADC_CFGR register.

21.4.22 Programmable resolution (RES) - Fast conversion mode

It is possible to perform faster conversion by reducing the ADC resolution.
The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the control
bits RES[1:0]. Figure 120, Figure 121, Figure 122 and Figure 123 show the conversion
result format with respect to the resolution as well as to the data alignment.
Lower resolution allows faster conversion time for applications where high-data precision is
not required. It reduces the conversion time spent by the successive approximation steps
according to Table 163.

718/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Table 163. TSAR timings depending on resolution

TCONV (ADC clock cycles)
RES TSAR TSAR (ns) at TCONV (ns) at
(bits) FADC= 30 MHz (with Sampling Time= FADC= 30 MHz
(ADC clock cycles)
2.5 ADC clock cycles)

12 12.5 ADC clock cycles 416.67 ns 15 ADC clock cycles 500.0 ns

10 10.5 ADC clock cycles 350.0 ns 13 ADC clock cycles 433.33 ns
8 8.5 ADC clock cycles 203.33 ns 11 ADC clock cycles 366.67 ns
6 6.5 ADC clock cycles 216.67 ns 9 ADC clock cycles 300.0 ns

21.4.23 End of conversion, end of sampling phase (EOC, JEOC, EOSMP)

The ADC notifies the application for each end of regular conversion (EOC) event and each
injected conversion (JEOC) event.
The ADC sets the EOC flag as soon as a new regular conversion data is available in the
ADC_DR register. An interrupt can be generated if bit EOCIE is set. EOC flag is cleared by
the software either by writing 1 to it or by reading ADC_DR.
The ADC sets the JEOC flag as soon as a new injected conversion data is available in one
of the ADC_JDRy register. An interrupt can be generated if bit JEOCIE is set. JEOC flag is
cleared by the software either by writing 1 to it or by reading the corresponding ADC_JDRy
register.
The ADC also notifies the end of Sampling phase by setting the status bit EOSMP (for
regular conversions only). EOSMP flag is cleared by software by writing 1 to it. An interrupt
can be generated if bit EOSMPIE is set.

21.4.24 End of conversion sequence (EOS, JEOS)

The ADC notifies the application for each end of regular sequence (EOS) and for each end
of injected sequence (JEOS) event.
The ADC sets the EOS flag as soon as the last data of the regular conversion sequence is
available in the ADC_DR register. An interrupt can be generated if bit EOSIE is set. EOS
flag is cleared by the software either by writing 1 to it.
The ADC sets the JEOS flag as soon as the last data of the injected conversion sequence is
complete. An interrupt can be generated if bit JEOSIE is set. JEOS flag is cleared by the
software either by writing 1 to it.

RM0438 Rev 7 719/2194

796
Analog-to-digital converters (ADC) RM0438

21.4.25 Timing diagrams example (single/continuous modes,

hardware/software triggers)

Figure 116. Single conversions of a sequence, software trigger

ADSTART(1)

EOC

EOS

ADC state(2) RDY CH1 CH9 CH10 CH17 RDY CH1 CH9 CH10 CH17 RDY

D1 D9 D10 D17 D1 D9 D10 D17

ADC_DR

by SW by HW Indicative timings

MS30549V1

1. EXTEN[1:0]=00, CONT=0
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

Figure 117. Continuous conversion of a sequence, software trigger

ADCSTART(1)

EOC

EOS

ADSTP
ADC state(2) READY CH1 CH9 CH10 CH17 CH1 CH9 CH10 STP READY CH1 CH9

ADC_DR D1 D9 D10 D17 D1 D9 D1

by SW by HW Indicative timings

MS30550V1

1. EXTEN[1:0]=00, CONT=1
2. Channels selected = 1,9, 10, 17; AUTDLY=0.

720/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 118. Single conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

TRGX(1)

ADC state(2) RDY CH1 CH2 CH3 CH4 READY CH1 CH2 CH3 CH4 RDY

ADC_DR D1 D2 D3 D4 D1 D2 D3 D4

by s/w by h/w triggered ignored Indicative timings

MS31013V2

1. TRGx (over-frequency) is selected as trigger source, EXTEN[1:0] = 01, CONT = 0

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

Figure 119. Continuous conversions of a sequence, hardware trigger

ADSTART

EOC

EOS

ADSTP

TRGx(1)

ADC(2) RDY CH1 CH2 CH3 CH4 CH1 CH2 CH3 CH4 CH1 STOP RDY

ADC_DR D1 D2 D3 D4 D1 D2 D3 D4

by s/w by h/w triggered ignored Not in scale timings

MS31014V2

1. TRGx is selected as trigger source, EXTEN[1:0] = 10, CONT = 1

2. Channels selected = 1, 2, 3, 4; AUTDLY=0.

RM0438 Rev 7 721/2194

796
Analog-to-digital converters (ADC) RM0438

21.4.26 Data management

Data register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH,
ALIGN)

Data and alignment

At the end of each regular conversion channel (when EOC event occurs), the result of the
converted data is stored into the ADC_DR data register which is 16 bits wide.
At the end of each injected conversion channel (when JEOC event occurs), the result of the
converted data is stored into the corresponding ADC_JDRy data register which is 16 bits
wide.
The ALIGN bit in the ADC_CFGR register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 120, Figure 121,
Figure 122 and Figure 123.
Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. In that case, the data are aligned on a byte basis as shown in
Figure 122 and Figure 123.
Note: Left-alignment is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the ALIGN bit value is ignored and the ADC only provides right-aligned data.

Offset
An offset y (y=1,2,3,4) can be applied to a channel by setting the bit OFFSETy_EN=1 into
ADC_OFRy register. The channel to which the offset will be applied is programmed into the
bits OFFSETy_CH[4:0] of ADC_OFRy register. In this case, the converted value is
decreased by the user-defined offset written in the bits OFFSETy[11:0]. The result may be a
negative value so the read data is signed and the SEXT bit represents the extended sign
value.
Note: Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as
reset).
Table 166 describes how the comparison is performed for all the possible resolutions for
analog watchdog 1.

Table 164. Offset computation versus data resolution

Subtraction between raw
converted data and offset
Resolution
(bits Raw Result Comments
RES[1:0]) converted
Offset
Data, left
aligned

Signed
00: 12-bit DATA[11:0] OFFSET[11:0] -
12-bit data
Signed The user must configure OFFSET[1:0]
01: 10-bit DATA[11:2],00 OFFSET[11:0]
10-bit data to “00”

722/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Table 164. Offset computation versus data resolution (continued)

Subtraction between raw
converted data and offset
Resolution
(bits Raw Result Comments
RES[1:0]) converted
Offset
Data, left
aligned

DATA[11:4],00 Signed The user must configure OFFSET[3:0]

10: 8-bit OFFSET[11:0]
00 8-bit data to “0000”
DATA[11:6],00 Signed The user must configure OFFSET[5:0]
11: 6-bit OFFSET[11:0]
0000 6-bit data to “000000”

When reading data from ADC_DR (regular channel) or from ADC_JDRy (injected channel,
y=1,2,3,4) corresponding to the channel “i”:
• If one of the offsets is enabled (bit OFFSETy_EN=1) for the corresponding channel, the
read data is signed.
• If none of the four offsets is enabled for this channel, the read data is not signed.
Figure 120, Figure 121, Figure 122 and Figure 123 show alignments for signed and
unsigned data.

Figure 120. Right alignment (offset disabled, unsigned value)

12-bit data
bit15 bit7 bit0
0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10-bit data
bit15 bit7 bit0
0 0 0 0 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

8-bit data
bit15 bit7 bit0
0 0 0 0 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0

6-bit data
bit15 bit7 bit0
0 0 0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0

MS31015V1

RM0438 Rev 7 723/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 121. Right alignment (offset enabled, signed value)

12-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

8-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D7 D6 D5 D4 D3 D2 D1 D0

6-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0

MS31016V1

Figure 122. Left alignment (offset disabled, unsigned value)

12-bit data
bit15 bit7 bit0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0

10-bit data
bit15 bit7 bit0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0

8-bit data
bit15 bit7 bit0
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0

6-bit data
bit15 bit7 bit0
0 0 0 0 0 0 0 0 D5 D4 D3 D2 D1 D0 0 0

MS31017V1

724/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 123. Left alignment (offset enabled, signed value)

12-bit data
bit15 bit7 bit0
SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0

10-bit data
bit15 bit7 bit0
SEXT D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0

8-bit data
bit15 bit7 bit0
SEXT D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0

6-bit data
bit15 bit7 bit0
SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT SEXT D5 D4 D3 D2 D1 D0 0

MS31018V1

ADC overrun (OVR, OVRMOD)

The overrun flag (OSR) notifies of that a buffer overrun event occurred when the regular
converted data has not been read (by the CPU or the DMA) before new converted data
became available.
The OVR flag is set if the EOC flag is still 1 at the time when a new conversion completes.
An interrupt can be generated if bit OVRIE=1.
When an overrun condition occurs, the ADC is still operating and can continue converting
unless the software decides to stop and reset the sequence by setting bit ADSTP=1.
OVR flag is cleared by software by writing 1 to it.
It is possible to configure if data is preserved or overwritten when an overrun event occurs
by programming the control bit OVRMOD:
• OVRMOD=0: The overrun event preserves the data register from being overrun: the
old data is maintained and the new conversion is discarded and lost. If OVR remains at
1, any further conversions will occur but the result data will be also discarded.
• OVRMOD=1: The data register is overwritten with the last conversion result and the
previous unread data is lost. If OVR remains at 1, any further conversions will operate
normally and the ADC_DR register will always contain the latest converted data.

RM0438 Rev 7 725/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 124. Example of overrun (OVR)

ADSTART(1)

EOC

EOS

OVR

ADSTP

TRGx(1)

ADC state(2) RDY CH1 CH2 CH3 CH4 CH5 CH6 CH7 STOP RDY
Overun
ADC_DR read access

ADC_DR D1
(OVRMOD=0) D2 D3 D4

ADC_DR D1 D2 D3 D4 D5 D6
(OVRMOD=1)

by s/w by h/w triggered Indicative timings

MS31019V1

Note: There is no overrun detection on the injected channels since there is a dedicated data
register for each of the four injected channels.

Managing a sequence of conversions without using the DMA

If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the software must use the EOC flag and its associated interrupt to
handle each data. Each time a conversion is complete, EOC is set and the ADC_DR
register can be read. OVRMOD should be configured to 0 to manage overrun events as an
error.

Managing conversions without using the DMA and without overrun

It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). In this case, the OVRMOD bit must be
configured to 1 and OVR flag should be ignored by the software. An overrun event will not
prevent the ADC from continuing to convert and the ADC_DR register will always contain
the latest conversion.

Managing conversions using the DMA

Since converted channel values are stored into a unique data register, it is useful to use
DMA for conversion of more than one channel. This avoids the loss of the data already
stored in the ADC_DR register.
When the DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR register in single
ADC mode or MDMA different from 0b00 in dual ADC mode), a DMA request is generated
after each conversion of a channel. This allows the transfer of the converted data from the
ADC_DR register to the destination location selected by the software.

726/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA
transfer request in time, the ADC stops generating DMA requests and the data
corresponding to the new conversion is not transferred by the DMA. Which means that all
the data transferred to the RAM can be considered as valid.
Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten
(refer to Section : ADC overrun (OVR, OVRMOD)).
The DMA transfer requests are blocked until the software clears the OVR bit.
Two different DMA modes are proposed depending on the application use and are
configured with bit DMACFG of the ADC_CFGR register in single ADC mode, or with bit
DMACFG of the ADC_CCR register in dual ADC mode:
• DMA one shot mode (DMACFG=0).
This mode is suitable when the DMA is programmed to transfer a fixed number of data.
• DMA circular mode (DMACFG=1)
This mode is suitable when programming the DMA in circular mode.

DMA one shot mode (DMACFG=0)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available and stops generating DMA requests once the DMA has reached the last DMA
transfer (when DMA_EOT interrupt occurs - refer to DMA paragraph) even if a conversion
has been started again.
When the DMA transfer is complete (all the transfers configured in the DMA controller have
been done):
• The content of the ADC data register is frozen.
• Any ongoing conversion is aborted with partial result discarded.
• No new DMA request is issued to the DMA controller. This avoids generating an
overrun error if there are still conversions which are started.
• Scan sequence is stopped and reset.
• The DMA is stopped.

DMA circular mode (DMACFG=1)

In this mode, the ADC generates a DMA transfer request each time a new conversion data
is available in the data register, even if the DMA has reached the last DMA transfer. This
allows configuring the DMA in circular mode to handle a continuous analog input data
stream.

21.4.27 Managing conversions using the DFSDM

The ADC conversion results can be transferred directly to the Digital filter for sigma delta
modulators (DFSDM).
In this case, the DFSDMCFG bit must be set to 1 and DMAEN bit must be cleared to 0.
The ADC transfers all the 16 bits of the regular data register to the DFSDM and resets the
EOC flag once the transfer is complete.

RM0438 Rev 7 727/2194

796
Analog-to-digital converters (ADC) RM0438

The data format must be 16-bit signed:

ADC_DR[15:12] = sign extended
ADC_DR[11] = sign
ADC_DR[11:0] = data
To obtain 16-bit signed format in 12-bit ADC mode, the software needs to configure the
OFFSETy[11:0] to 0x800 after having set OFFSETy_EN to 1.
Only right aligned data format is available for the DFSDM interface (see Figure 121: Right
alignment (offset enabled, signed value)).

21.4.28 Dynamic low-power features

Auto-delayed conversion mode (AUTDLY)
The ADC implements an auto-delayed conversion mode controlled by the AUTDLY
configuration bit. Auto-delayed conversions are useful to simplify the software as well as to
optimize performance of an application clocked at low frequency where there would be risk
of encountering an ADC overrun.
When AUTDLY=1, a new conversion can start only if all the previous data of the same group
has been treated:
• For a regular conversion: once the ADC_DR register has been read or if the EOC bit
has been cleared (see Figure 125).
• For an injected conversion: when the JEOS bit has been cleared (see Figure 126).
This is a way to automatically adapt the speed of the ADC to the speed of the system which
will read the data.
The delay is inserted after each regular conversion (whatever DISCEN=0 or 1) and after
each sequence of injected conversions (whatever JDISCEN=0 or 1).
Note: There is no delay inserted between each conversions of the injected sequence, except after
the last one.
During a conversion, a hardware trigger event (for the same group of conversions) occurring
during this delay is ignored.
Note: This is not true for software triggers where it remains possible during this delay to set the
bits ADSTART or JADSTART to restart a conversion: it is up to the software to read the data
before launching a new conversion.
No delay is inserted between conversions of different groups (a regular conversion followed
by an injected conversion or conversely):
• If an injected trigger occurs during the automatic delay of a regular conversion, the
injected conversion starts immediately (see Figure 126).
• Once the injected sequence is complete, the ADC waits for the delay (if not ended) of
the previous regular conversion before launching a new regular conversion (see
Figure 128).
The behavior is slightly different in auto-injected mode (JAUTO=1) where a new regular
conversion can start only when the automatic delay of the previous injected sequence of
conversion has ended (when JEOS has been cleared). This is to ensure that the software
can read all the data of a given sequence before starting a new sequence (see Figure 129).

728/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

To stop a conversion in continuous auto-injection mode combined with autodelay mode

(JAUTO=1, CONT=1 and AUTDLY=1), follow the following procedure:
1. Wait until JEOS=1 (no more conversions are restarted)
2. Clear JEOS,
3. Set ADSTP=1
4. Read the regular data.
If this procedure is not respected, a new regular sequence can restart if JEOS is cleared
after ADSTP has been set.
In AUTDLY mode, a hardware regular trigger event is ignored if it occurs during an already
ongoing regular sequence or during the delay that follows the last regular conversion of the
sequence. It is however considered pending if it occurs after this delay, even if it occurs
during an injected sequence of the delay that follows it. The conversion then starts at the
end of the delay of the injected sequence.
In AUTDLY mode, a hardware injected trigger event is ignored if it occurs during an already
ongoing injected sequence or during the delay that follows the last injected conversion of
the sequence.

Figure 125. AUTODLY=1, regular conversion in continuous mode, software trigger

ADSTART (1)

EOC

EOS

ADSTP
ADC_DR read access

ADC state RDY CH1 DLY CH2 DLY CH3 DLY CH1 DLY STOP RDY

ADC_DR D1 D2 D3 D1

by SW by HW
Indicative timings

MS31020V1

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, CHANNELS = 1,2,3
3. Injected configuration DISABLED

RM0438 Rev 7 729/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 126. AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=0; JDISCEN=0)

Not ignored
Ignored (occurs during injected sequence)
Regular
trigger
ADC state RDY CH1 DLY CH2 DLY CH5 CH6 CH3 DLY CH1 DLY CH2
regular regular injected regular injected regular regular
DLY (CH1) DLY (CH2) DLY (CH3) DLY (CH1)

EOC
EOS
ADC_DR
read access
ADC_DR D1 D2 D3 D1
Injected Ignored
trigger
DLY (inj)
JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31021V2

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

730/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 127. AUTODLY=1, regular HW conversions interrupted by injected conversions

(DISCEN=1, JDISCEN=1)

Ignored Not ignored (occurs during

injected sequence)
Regular trigger
ADC state RDY CH1 DLY RDY CH2 DLY RDY CH5 RDY CH6 CH3 DLY RDY CH1 DLY RDY CH2
regular regular injected injected regular regular regular
DLY (CH1) DLY (CH2) DLY (CH3) DLY (CH1)

EOC
EOS
ADC_DR
read access
ADC_DR D1 D2 D3 D1
Ignored Ignored
Injected trigger
DLY (inj)
JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by SW by HW Indicative timings

MS31022V1

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=01 (HW trigger), CONT=0, DISCEN=1, DISCNUM=1, CHANNELS = 1, 2, 3.
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=1, CHANNELS = 5,6

RM0438 Rev 7 731/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 128. AUTODLY=1, regular continuous conversions interrupted by injected conversions

ADSTART(1)
ADC
RDY CH1 DLY CH2 DLY CH5 CH6 DLY CH3 DLY CH1
state
regular regular injected injected regular
DLY (CH1) DLY (CH2) regular
DLY (CH3)

EOC
EOS
ADC_DR read
access
ADC_DR D1 D2 D3
Ignored
Injected
trigger
DLY (inj)
JEOS
ADC_JDR1 D5
ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31023V3

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2, 3
3. Injected configuration: JEXTEN[1:0]=01 (HW Trigger), JDISCEN=0, CHANNELS = 5,6

Figure 129. AUTODLY=1 in auto- injected mode (JAUTO=1)

ADSTART(1) No delay

ADC state RDY CH1 DLY (CH1) CH2 CH5 CH6 DLY (inj) DLY(CH2) CH3 DLY CH1
regular regular injected injected regular regular
EOC
EOS
ADC_DR read access

ADC_DR D1 D2 D3

JEOS
ADC_JDR1 D5

ADC_JDR2 D6

by s/w by h/w Indicative timings

MS31024V3

1. AUTDLY=1
2. Regular configuration: EXTEN[1:0]=00 (SW trigger), CONT=1, DISCEN=0, CHANNELS = 1, 2
3. Injected configuration: JAUTO=1, CHANNELS = 5,6

732/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.29 Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL,

AWD1CH, AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
The three AWD analog watchdogs monitor whether some channels remain within a
configured voltage range (window).

Figure 130. Analog watchdog guarded area

Analog voltage

Higher threshold HTx

Guarded area
Lower threshold LTx

MS45396V1

AWDx flag and interrupt

An interrupt can be enabled for each of the 3 analog watchdogs by setting AWDxIE in the
ADC_IER register (x=1,2,3).
AWDx (x=1,2,3) flag is cleared by software by writing 1 to it.
The ADC conversion result is compared to the lower and higher thresholds before
alignment.
Description of analog watchdog 1
The AWD analog watchdog 1 is enabled by setting the AWD1EN bit in the ADC_CFGR
register. This watchdog monitors whether either one selected channel or all enabled
channels(1) remain within a configured voltage range (window).
Table 165 shows how the ADC_CFGR registers should be configured to enable the analog
watchdog on one or more channels.

Table 165. Analog watchdog channel selection

Channels guarded by the analog
AWD1SGL bit AWD1EN bit JAWD1EN bit
watchdog

None x 0 0
All injected channels 0 0 1
All regular channels 0 1 0
All regular and injected channels 0 1 1
(1)
Single injected channel 1 0 1
Single(1) regular channel 1 1 0
(1)
Single regular or injected channel 1 1 1
1. Selected by the AWD1CH[4:0] bits. The channels must also be programmed to be converted in the
appropriate regular or injected sequence.

The AWD1 analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold.

RM0438 Rev 7 733/2194

796
Analog-to-digital converters (ADC) RM0438

These thresholds are programmed in bits HT1[11:0] and LT1[11:0] of the ADC_TR1 register
for the analog watchdog 1. When converting data with a resolution of less than 12 bits
(according to bits RES[1:0]), the LSB of the programmed thresholds must be kept cleared
because the internal comparison is always performed on the full 12-bit raw converted data
(left aligned).
Table 166 describes how the comparison is performed for all the possible resolutions for
analog watchdog 1.

Table 166. Analog watchdog 1 comparison

Analog watchdog comparison
Resolution( between:
bit Comments
RES[1:0]) Raw converted data,
Thresholds
left aligned

LT1[11:0] and
00: 12-bit DATA[11:0] -
HT1[11:0]
LT1[11:0] and User must configure LT1[1:0] and HT1[1:0]
01: 10-bit DATA[11:2],00
HT1[11:0] to 00
LT1[11:0] and User must configure LT1[3:0] and HT1[3:0]
10: 8-bit DATA[11:4],0000
HT1[11:0] to 0000
LT1[11:0] and User must configure LT1[5:0] and HT1[5:0]
11: 6-bit DATA[11:6],000000
HT1[11:0] to 000000

Description of analog watchdog 2 and 3

The second and third analog watchdogs are more flexible and can guard several selected
channels by programming the corresponding bits in AWDxCH[18:0] (x=2,3).
The corresponding watchdog is enabled when any bit of AWDxCH[18:0] (x=2,3) is set.
They are limited to a resolution of 8 bits and only the 8 MSBs of the thresholds can be
programmed into HTx[7:0] and LTx[7:0]. Table 167 describes how the comparison is
performed for all the possible resolutions.

Table 167. Analog watchdog 2 and 3 comparison

Analog watchdog comparison between:
Resolution
Comments
(bits RES[1:0]) Raw converted data,
Thresholds
left aligned

00: 12-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:0] are not relevant for the comparison
01: 10-bit DATA[11:4] LTx[7:0] and HTx[7:0] DATA[3:2] are not relevant for the comparison
10: 8-bit DATA[11:4] LTx[7:0] and HTx[7:0] -
11: 6-bit DATA[11:6],00 LTx[7:0] and HTx[7:0] User must configure LTx[1:0] and HTx[1:0] to 00

734/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

ADCy_AWDx_OUT signal output generation

Each analog watchdog is associated to an internal hardware signal ADCy_AWDx_OUT
(y=ADC number, x=watchdog number) which is directly connected to the ETR input
(external trigger) of some on-chip timers. Refer to the on-chip timers section to understand
how to select the ADCy_AWDx_OUT signal as ETR.
ADCy_AWDx_OUT is activated when the associated analog watchdog is enabled:
• ADCy_AWDx_OUT is set when a guarded conversion is outside the programmed
thresholds.
• ADCy_AWDx_OUT is reset after the end of the next guarded conversion which is
inside the programmed thresholds (It remains at 1 if the next guarded conversions are
still outside the programmed thresholds).
• ADCy_AWDx_OUT is also reset when disabling the ADC (when setting ADDIS=1).
Note that stopping regular or injected conversions (setting ADSTP=1 or JADSTP=1)
has no influence on the generation of ADCy_AWDx_OUT.
Note: AWDx flag is set by hardware and reset by software: AWDx flag has no influence on the
generation of ADCy_AWDx_OUT (ex: ADCy_AWDx_OUT can toggle while AWDx flag
remains at 1 if the software did not clear the flag).

Figure 131. ADCy_AWDx_OUT signal generation (on all regular channels)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
STATE
inside outside inside outside outside outside inside
EOC FLAG

AWDx FLAG cleared cleared cleared cleared

by S/W by S/W by S/W by S/W

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31025V1

RM0438 Rev 7 735/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 132. ADCy_AWDx_OUT signal generation (AWDx flag not cleared by software)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion5 Conversion6 Conversion7
STATE
inside outside inside outside outside outside inside
EOC FLAG

not cleared by S/W

AWDx FLAG

ADCy_AWDx_OUT

- Converting regular channels 1,2,3,4,5,6,7

- Regular channels 1,2,3,4,5,6,7 are all guarded

MS31026V1

Figure 133. ADCy_AWDx_OUT signal generation (on a single regular channel)

ADC
Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2 Conversion1 Conversion2
STATE
outside inside outside outside
EOC FLAG

EOS FLAG

AWDx FLAG cleared cleared

by S/W by S/W

ADCy_AWDx_OUT

- Converting regular channels 1 and 2

- Only channel 1 is guarded
MS31027V1

Figure 134. ADCy_AWDx_OUT signal generation (on all injected channels)

ADC
RDY Conversion1 Conversion2 Conversion3 Conversion4 Conversion Conversion Conversion
STATE
inside outside inside outside outside outside inside
JEOS FLAG

cleared cleared cleared cleared

AWDx FLAG by S/W by S/W by S/W by S/W

ADCy_AWDx_OUT

- Converting the injected channels 1, 2, 3, 4

- All injected channels 1, 2, 3, 4 are guarded

MS31028V1

736/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.30 Oversampler
The oversampling unit performs data pre-processing to offload the CPU. It is able to handle
multiple conversions and average them into a single data with increased data width, up to
16-bit.
It provides a result with the following form, where N and M can be adjusted:

n = N–1
1
Result = ----- ×
M  Conversion(t n)
n=0

It allows to perform by hardware the following functions: averaging, data rate reduction,
SNR improvement, basic filtering.
The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register,
and can range from 2x to 256x. The division coefficient M consists of a right bit shift up to
8 bits, and is defined using the OVSS[3:0] bits in the ADC_CFGR2 register.
The summation unit can yield a result up to 20 bits (256x 12-bit results), which is first shifted
right. It is then truncated to the 16 least significant bits, rounded to the nearest value using
the least significant bits left apart by the shifting, before being finally transferred into the
ADC_DR data register.
Note: If the intermediary result after the shifting exceeds 16-bit, the result is truncated as is,
without saturation.

Figure 135. 20-bit to 16-bit result truncation

19 15 11 7 3 0
Raw 20-bit data

Shifting

15 0
Truncation and rounding
MS34453V1

Figure 136 gives a numerical example of the processing, from a raw 20-bit accumulated
data to the final 16-bit result.

Figure 136. Numerical example with 5-bit shift and rounding

19 15 11 7 3
Raw 20-bit data 3 B 7 D 7

15 0
Final result after 5-bit shift
1 D B F
and rounding to nearest
MS34454V1

Table 168 gives the data format for the various N and M combinations, for a raw conversion
data equal to 0xFFF.

RM0438 Rev 7 737/2194

796
Analog-to-digital converters (ADC) RM0438

Table 168. Maximum output results versus N and M (gray cells indicate truncation)
No-shift 1-bit 2-bit 3-bit 4-bit 5-bit 6-bit 7-bit 8-bit
Over
Max shift shift shift shift shift shift shift shift
sampling
Raw data OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS = OVSS =
ratio
0000 0001 0010 0011 0100 0101 0110 0111 1000

2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x020
4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040
8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080
16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100
32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200
64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400
128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800
256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF

There are no changes for conversion timings in oversampled mode: the sample time is
maintained equal during the whole oversampling sequence. A new data is provided every N
conversions, with an equivalent delay equal to N x TCONV = N x (tSMPL + tSAR). The flags are
set as follows:
• The end of the sampling phase (EOSMP) is set after each sampling phase
• The end of conversion (EOC) occurs once every N conversions, when the
oversampled result is available
• The end of sequence (EOS) occurs once the sequence of oversampled data is
completed (i.e. after N x sequence length conversions total)

ADC operating modes supported when oversampling (single ADC mode)

In oversampling mode, most of the ADC operating modes are maintained:
• Single or continuous mode conversions
• ADC conversions start either by software or with triggers
• ADC stop during a conversion (abort)
• Data read via CPU or DMA with overrun detection
• Low-power modes (AUTDLY)
• Programmable resolution: in this case, the reduced conversion values (as per RES[1:0]
bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the
same way as 12-bit conversions are
Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in
ADC_CFGR1 is ignored and the data are always provided right-aligned.
Offset correction is not supported in oversampling mode. When ROVSE and/or JOVSE bit is
set, the value of the OFFSETy_EN bit in ADC_OFRy register is ignored (considered as
reset).

738/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Analog watchdog
The analog watchdog functionality is maintained (AWDSGL and AWDEN bits), with the
following difference:
– The RES[1:0] bits are ignored, comparison is always done using the full 12-bit
values HT[11:0] and LT[11:0]
– the comparison is performed on the most significant 12-bit of the 16-bit
oversampled results ADC_DR[15:4]
Note: Care must be taken when using high shifting values, this will reduce the comparison range.
For instance, if the oversampled result is shifted by 4 bits, thus yielding a 12-bit data right-
aligned, the effective analog watchdog comparison can only be performed on 8 bits. The
comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8]
must be kept reset.

Triggered mode
The averager can also be used for basic filtering purpose. Although not a very powerful filter
(slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject
constant parasitic frequencies (typically coming from the mains or from a switched mode
power supply). For this purpose, a specific discontinuous mode can be enabled with
TROVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a
user and independent from the conversion time itself.
Figure 137 below shows how conversions are started in response to triggers during
discontinuous mode.
If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.

Figure 137. Triggered regular oversampling mode (TROVS bit = 1)

Trigger Trigger
CONT=0
DISCEN = 1
TROVS = 0
Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3

EOC flag set

Trigger Trigger Trigger Trigger Trigger Trigger Trigger

CONT=0
DISCEN = 1
TROVS = 1
Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(N)0 Ch(N)1 Ch(N)2

EOC flag set

MS34455V2

Injected and regular sequencer management when oversampling

In oversampling mode, it is possible to have differentiated behavior for injected and regular
sequencers. The oversampling can be enabled for both sequencers with some limitations if
they have to be used simultaneously (this is related to a unique accumulation unit).

RM0438 Rev 7 739/2194

796
Analog-to-digital converters (ADC) RM0438

Oversampling regular channels only

The regular oversampling mode bit ROVSM defines how the regular oversampling
sequence is resumed if it is interrupted by injected conversion:
• In continued mode, the accumulation restarts from the last valid data (prior to the
conversion abort request due to the injected trigger). This ensures that oversampling
will be complete whatever the injection frequency (providing at least one regular
conversion can be complete between triggers);
• In resumed mode, the accumulation restarts from 0 (previous conversion results are
ignored). This mode allows to guarantee that all data used for oversampling were
converted back-to-back within a single timeslot. Care must be taken to have a injection
trigger period above the oversampling period length. If this condition is not respected,
the oversampling cannot be complete and the regular sequencer will be blocked.
Figure 138 gives examples for a 4x oversampling ratio.

Figure 138. Regular oversampling modes (4x ratio)

Oversampling Oversampling
stopped continued

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)1 Ch(M)2 Ch(M)3 Ch(O)0
Abort
Trigger

Injected channels Ch(J) Ch(K)

JEOC

Continued mode: ROVSE = 1, JOVSE = 0, ROVSM = 0, TROVS = X

Oversampling Oversampling
aborted resumed

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)0 Ch(M)1 Ch(M)2 Ch(M)3
Abort
Trigger

Injected channels Ch(J) Ch(K)

JEOC

Resumed mode: ROVSE = 1, JOVSE = 0, ROVSM = 1, TROVS = X

MS34456V1

Oversampling Injected channels only

The Injected oversampling mode bit JOVSE enables oversampling solely for conversions in
the injected sequencer.

740/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Oversampling regular and Injected channels

It is possible to have both ROVSE and JOVSE bits set. In this case, the regular
oversampling mode is forced to resumed mode (ROVSM bit ignored), as represented on
Figure 139 below.

Figure 139. Regular and injected oversampling modes used simultaneously

Oversampling Oversampling
aborted resumed

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)3 Ch(M)0 Ch(M)1 Ch(M)0 Ch(M)1
Abort
Trigger

Injected channels Ch(J)0 Ch(J)1 Ch(J)2 Ch(J)3

JEOC

ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34457V1

Triggered regular oversampling with injected conversions

It is possible to have triggered regular mode with injected conversions. In this case, the
injected mode oversampling mode must be disabled, and the ROVSM bit is ignored
(resumed mode is forced). The JOVSE bit must be reset. The behavior is represented on
Figure 140 below.

Figure 140. Triggered regular oversampling with injection

Oversampling
resumed

Trigger Trigger Trigger Trigger Trigger

Regular channels Ch(N)0 Ch(N)1 Ch(N)2 Ch(N)0

Abort
Trigger

Injected channels Ch(J) Ch(K)

ROVSE = 1, JOVSE = 0, ROVSM = X, TROVS = 1

MS34458V2

RM0438 Rev 7 741/2194

796
Analog-to-digital converters (ADC) RM0438

Auto-injected mode
It is possible to oversample auto-injected sequences and have all conversions results stored
in registers to save a DMA resource. This mode is available only with both regular and
injected oversampling active: JAUTO = 1, ROVSE = 1 and JOVSE = 1, other combinations
are not supported. The ROVSM bit is ignored in auto-injected mode. The Figure 141 below
shows how the conversions are sequenced.

Figure 141. Oversampling in auto-injected mode

Regular channels N0 N1 N2 N3 N0 N1 N2 N3

Injected channels I0 I1 I2 I3 J0 J1 J2 J3 K0 K1 K2 K3 L0 L1 L2 L3

JAUTO =1, ROVSE = 1, JOVSE = 1, ROVSM = X, TROVS = 0

MS34459V1

It is possible to have also the triggered mode enabled, using the TROVS bit. In this case,
the ADC must be configured as following: JAUTO = 1, DISCEN = 0, JDISCEN = 0, ROVSE
= 1, JOVSE = 1 and TROVSE = 1.

Dual ADC modes supported when oversampling

It is possible to have oversampling enabled when working in dual ADC configuration, for the
injected simultaneous mode and regular simultaneous mode. In this case, the two ADCs
must be programmed with the very same settings (including oversampling).
All other dual ADC modes are not supported when either regular or injected oversampling is
enabled (ROVSE = 1 or JOVSE = 1).

Combined modes summary

The Table 169 below summarizes all combinations, including modes not supported.

Table 169. Oversampler operating modes summary

Oversampler
Regular Injected mode Triggered
Oversampling Oversampling ROVSM Regular mode Comment
ROVSE JOVSE 0 = continued TROVS
1 = resumed

1 0 0 0 Regular continued mode

1 0 0 1 Not supported
1 0 1 0 Regular resumed mode
Triggered regular resumed
1 0 1 1
mode
1 1 0 X Not supported
Injected and regular resumed
1 1 1 0
mode
1 1 1 1 Not supported
0 1 X X Injected oversampling

742/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.31 Dual ADC modes

Dual ADC modes can be used in devices with two ADCs or more (see Figure 142).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADCx master to the ADC slave, depending on the mode selected by the bits DUAL[4:0] in
the ADCx_CCR register.
Four possible modes are implemented:
• Injected simultaneous mode
• Regular simultaneous mode
• Interleaved mode
• Alternate trigger mode
It is also possible to use these modes combined in the following ways:
• Injected simultaneous mode + Regular simultaneous mode
• Regular simultaneous mode + Alternate trigger mode
• Injected simultaneous mode + Interleaved mode
In dual ADC mode (when bits DUAL[4:0] in ADCx_CCR register are not equal to zero), the
bits CONT, AUTDLY, DISCEN, DISCNUM[2:0], JDISCEN, JQM, JAUTO of the ADC_CFGR
register are shared between the master and slave ADC: the bits in the slave ADC are
always equal to the corresponding bits of the master ADC.
To start a conversion in dual mode, the user must program the bits EXTEN[1:0], EXTSEL,
JEXTEN[1:0], JEXTSEL of the master ADC only, to configure a software or hardware
trigger, and a regular or injected trigger. (the bits EXTEN[1:0] and JEXTEN[1:0] of the slave
ADC are don’t care).
In regular simultaneous or interleaved modes: once the user sets bit ADSTART or bit
ADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit ADSTART or bit ADSTP of the slave ADC is not necessary cleared at the
same time as the master ADC bit.
In injected simultaneous or alternate trigger modes: once the user sets bit JADSTART or bit
JADSTP of the master ADC, the corresponding bit of the slave ADC is also automatically
set. However, bit JADSTART or bit JADSTP of the slave ADC is not necessary cleared at
the same time as the master ADC bit.
In dual ADC mode, the converted data of the master and slave ADC can be read in parallel,
by reading the ADC common data register (ADCx_CDR). The status bits can be also read in
parallel by reading the dual-mode status register (ADCx_CSR).

RM0438 Rev 7 743/2194

796
Analog-to-digital converters (ADC) RM0438

Figure 142. Dual ADC block diagram(1)

Regular data register (16-

bits)

Injected data registers (4

Internal analog inputs x16-bits)
ADCx_INN1 Regular
ADCx_INP1

Address/data bus
channels
ADCx_INN2
ADCx_INP2 Injected
Slave ADC
channels

Internal triggers

Regular data register (16-

bits)
ADCx_INN16
ADCx_INP16 Injected data registers (4
x16-bits)
Internal analog inputs Regular
channels

Injected
channels

Dual mode
control

Start trigger mux.

(regular group)

Master ADC

Start trigger mux.

(injected group)

MSv36025V2

1. External triggers also exist on slave ADC but are not shown for the purposes of this diagram.
2. The ADC common data register (ADCx_CDR) contains both the master and slave ADC regular converted data.

744/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Injected simultaneous mode

This mode is selected by programming bits DUAL[4:0]=00101
This mode converts an injected group of channels. The external trigger source comes from
the injected group multiplexer of the master ADC (selected by the JEXTSEL bits in the
ADC_JSQR register).
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
In simultaneous mode, one must convert sequences with the same length or ensure that the
interval between triggers is longer than the longer of the 2 sequences. Otherwise, the ADC
with the shortest sequence may restart while the ADC with the longest sequence is
completing the previous conversions.
Regular conversions can be performed on one or all ADCs. In that case, they are
independent of each other and are interrupted when an injected event occurs. They are
resumed at the end of the injected conversion group.
• At the end of injected sequence of conversion event (JEOS) on the master ADC, the
converted data is stored into the master ADC_JDRy registers and a JEOS interrupt is
generated (if enabled)
• At the end of injected sequence of conversion event (JEOS) on the slave ADC, the
converted data is stored into the slave ADC_JDRy registers and a JEOS interrupt is
generated (if enabled)
• If the duration of the master injected sequence is equal to the duration of the slave
injected one (like in Figure 143), it is possible for the software to enable only one of the
two JEOS interrupt (ex: master JEOS) and read both converted data (from master
ADC_JDRy and slave ADC_JDRy registers).

Figure 143. Injected simultaneous mode on 4 channels: dual ADC mode

MASTER ADC CH1 CH2 CH3 CH4

SLAVE ADC CH15 CH14 CH13 CH12

Trigger
Sampling End of injected sequence on
MASTER and SLAVE ADC
Conversion

MS31900V1

If JDISCEN=1, each simultaneous conversion of the injected sequence requires an injected

trigger event to occur.
This mode can be combined with AUTDLY mode:
• Once a simultaneous injected sequence of conversions has ended, a new injected
trigger event is accepted only if both JEOS bits of the master and the slave ADC have
been cleared (delay phase). Any new injected trigger events occurring during the
ongoing injected sequence and the associated delay phase are ignored.
• Once a regular sequence of conversions of the master ADC has ended, a new regular
trigger event of the master ADC is accepted only if the master data register (ADC_DR)
has been read. Any new regular trigger events occurring for the master ADC during the

RM0438 Rev 7 745/2194

796
Analog-to-digital converters (ADC) RM0438

ongoing regular sequence and the associated delay phases are ignored.
There is the same behavior for regular sequences occurring on the slave ADC.

Regular simultaneous mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00110.
This mode is performed on a regular group of channels. The external trigger source comes
from the regular group multiplexer of the master ADC (selected by the EXTSEL bits in the
ADC_CFGR register). A simultaneous trigger is provided to the slave ADC.
In this mode, independent injected conversions are supported. An injection request (either
on master or on the slave) will abort the current simultaneous conversions, which are
restarted once the injected conversion is completed.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
In regular simultaneous mode, one must convert sequences with the same length or ensure
that the interval between triggers is longer than the longer conversion time of the 2
sequences. Otherwise, the ADC with the shortest sequence may restart while the ADC with
the longest sequence is completing the previous conversions.
Software is notified by interrupts when it can read the data:
• At the end of each conversion event (EOC) on the master ADC, a master EOC interrupt
is generated (if EOCIE is enabled) and software can read the ADC_DR of the master
ADC.
• At the end of each conversion event (EOC) on the slave ADC, a slave EOC interrupt is
generated (if EOCIE is enabled) and software can read the ADC_DR of the slave ADC.
• If the duration of the master regular sequence is equal to the duration of the slave one
(like in Figure 144), it is possible for the software to enable only one of the two EOC
interrupt (ex: master EOC) and read both converted data from the Common Data
register (ADCx_CDR).
It is also possible to read the regular data using the DMA. Two methods are possible:
• Using two DMA channels (one for the master and one for the slave). In this case bits
MDMA[1:0] must be kept cleared.
– Configure the DMA master ADC channel to read ADC_DR from the master. DMA
requests are generated at each EOC event of the master ADC.
– Configure the DMA slave ADC channel to read ADC_DR from the slave. DMA
requests are generated at each EOC event of the slave ADC.
• Using MDMA mode, which leaves one DMA channel free for other uses:
– Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution).
– A single DMA channel is used (the one of the master). Configure the DMA master
ADC channel to read the common ADC register (ADCx_CDR)
– A single DMA request is generated each time both master and slave EOC events
have occurred. At that time, the slave ADC converted data is available in the
upper half-word of the ADCx_CDR 32-bit register and the master ADC converted
data is available in the lower half-word of ADCx_CCR register.
– Both EOC flags are cleared when the DMA reads the ADCx_CCR register.
Note: In MDMA mode (MDMA[1:0]=0b10 or 0b11), the user must program the same number of
conversions in the master’s sequence as in the slave’s sequence. Otherwise, the remaining
conversions will not generate a DMA request.

746/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 144. Regular simultaneous mode on 16 channels: dual ADC mode

MASTER ADC CH1 CH2 CH3 CH4 ... CH16

SLAVE ADC CH16 CH14 CH13 CH12 ... CH1

Trigger End of regular sequence on

Sampling MASTER and SLAVE ADC

Conversion
ai16054b

If DISCEN=1 then each “n” simultaneous conversions of the regular sequence require a
regular trigger event to occur (“n” is defined by DISCNUM).
This mode can be combined with AUTDLY mode:
• Once a simultaneous conversion of the sequence has ended, the next conversion in
the sequence is started only if the common data register, ADCx_CDR (or the regular
data register of the master ADC) has been read (delay phase).
• Once a simultaneous regular sequence of conversions has ended, a new regular
trigger event is accepted only if the common data register (ADCx_CDR) has been read
(delay phase). Any new regular trigger events occurring during the ongoing regular
sequence and the associated delay phases are ignored.
It is possible to use the DMA to handle data in regular simultaneous mode combined with
AUTDLY mode, assuming that multi-DMA mode is used: bits MDMA must be set to 0b10 or
0b11.
When regular simultaneous mode is combined with AUTDLY mode, it is mandatory for the
user to ensure that:
• The number of conversions in the master’s sequence is equal to the number of
conversions in the slave’s.
• For each simultaneous conversions of the sequence, the length of the conversion of
the slave ADC is inferior to the length of the conversion of the master ADC. Note that
the length of the sequence depends on the number of channels to convert and the
sampling time and the resolution of each channels.
Note: This combination of regular simultaneous mode and AUTDLY mode is restricted to the use
case when only regular channels are programmed: it is forbidden to program injected
channels in this combined mode.

Interleaved mode with independent injected

This mode is selected by programming bits DUAL[4:0] = 00111.
This mode can be started only on a regular group (usually one channel). The external
trigger source comes from the regular channel multiplexer of the master ADC.
After an external trigger occurs:
• The master ADC starts immediately.
• The slave ADC starts after a delay of several ADC clock cycles after the sampling
phase of the master ADC has complete.
The minimum delay which separates two conversions in interleaved mode is configured in
the DELAY bits in the ADCx_CCR register. This delay starts counting one half cycle after the
end of the sampling phase of the master conversion. This way, an ADC cannot start a

RM0438 Rev 7 747/2194

796
Analog-to-digital converters (ADC) RM0438

conversion if the complementary ADC is still sampling its input (only one ADC can sample
the input signal at a given time).
• The minimum possible DELAY is 1 to ensure that there is at least one cycle time
between the opening of the analog switch of the master ADC sampling phase and the
closing of the analog switch of the slave ADC sampling phase.
• The maximum DELAY is equal to the number of cycles corresponding to the selected
resolution. However the user must properly calculate this delay to ensure that an ADC
does not start a conversion while the other ADC is still sampling its input.
If the CONT bit is set on both master and slave ADCs, the selected regular channels of both
ADCs are continuously converted.
The software is notified by interrupts when it can read the data at the end of each
conversion event (EOC) on the slave ADC. A slave and master EOC interrupts are
generated (if EOCIE is enabled) and the software can read the ADC_DR of the slave/master
ADC.
Note: It is possible to enable only the EOC interrupt of the slave and read the common data
register (ADCx_CDR). But in this case, the user must ensure that the duration of the
conversions are compatible to ensure that inside the sequence, a master conversion is
always followed by a slave conversion before a new master conversion restarts. It is
recommended to use the MDMA mode.
It is also possible to have the regular data transferred by DMA. In this case, individual DMA
requests on each ADC cannot be used and it is mandatory to use the MDMA mode, as
following:
• Configure MDMA[1:0]=0b10 or 0b11 (depending on resolution).
• A single DMA channel is used (the one of the master). Configure the DMA master ADC
channel to read the common ADC register (ADCx_CDR).
• A single DMA request is generated each time both master and slave EOC events have
occurred. At that time, the slave ADC converted data is available in the upper half-word
of the ADCx_CDR 32-bit register and the master ADC converted data is available in
the lower half-word of ADCx_CCR register.
• Both EOC flags are cleared when the DMA reads the ADCx_CCR register.

Figure 145. Interleaved mode on 1 channel in continuous conversion mode: dual ADC
mode

0.5 ADCCLK 0.5 ADCCLK

cycle cycle

MASTER ADC CH1 CH1

SLAVE ADC
CH1 CH1
Trigger

4 ADCCLK 4 ADCCLK End of conversion on master and

cycles cycles slave ADC
Sampling

Conversion
MSv31030V3

748/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 146. Interleaved mode on 1 channel in single conversion mode: dual ADC
mode
0.5 ADCCLK 0.5 ADCCLK
cycle cycle

MASTER ADC CH1 CH1

SLAVE ADC CH1 CH1

Trigger

4 ADCCLK End of conversion on 4 ADCCLK End of conversion on

cycles master and slave ADC cycles master and slave ADC

Sampling

Conversion
MSv31031V3

If DISCEN=1, each “n” simultaneous conversions (“n” is defined by DISCNUM) of the

regular sequence require a regular trigger event to occur.
In this mode, injected conversions are supported. When injection is done (either on master
or on slave), both the master and the slave regular conversions are aborted and the
sequence is restarted from the master (see Figure 147 below).

Figure 147. Interleaved conversion with injection

Injected trigger Resume (always on master)

CH11

ADC1 (master) CH1 CH1 CH1 CH1 CH1 CH1

ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH0

read read conversions read read

Legend: CDR CDR aborted CDR CDR

Sampling Conversion
MS34460V1

Alternate trigger mode

This mode is selected by programming bits DUAL[4:0] = 01001.
This mode can be started only on an injected group. The source of external trigger comes
from the injected group multiplexer of the master ADC.
This mode is only possible when selecting hardware triggers: JEXTEN[1:0] must not be 00.
Injected discontinuous mode disabled (JDISCEN=0 for both ADC)

RM0438 Rev 7 749/2194

796
Analog-to-digital converters (ADC) RM0438

1. When the 1st trigger occurs, all injected master ADC channels in the group are
converted.
2. When the 2nd trigger occurs, all injected slave ADC channels in the group are
converted.
3. And so on.
A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in
the group have been converted.
A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the
group have been converted.
JEOC interrupts, if enabled, can also be generated after each injected conversion.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts by converting the injected channels of
the master ADC in the group.

Figure 148. Alternate trigger: injected group of each ADC

JEOC on JEOC on JEOC,JEOS on

1st trigger master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

2nd trigger JEOC on JEOC on JEOC, JEOS

slave ADC slave ADC on slave ADC

JEOC on JEOC on JEOC,JEOS on

3rd trigger master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

4th trigger
JEOC on JEOC on JEOC, JEOS
Sampling slave ADC slave ADC on slave ADC
Conversion
ai16059-m

Note: Regular conversions can be enabled on one or all ADCs. In this case the regular
conversions are independent of each other. A regular conversion is interrupted when the
ADC has to perform an injected conversion. It is resumed when the injected conversion is
finished.
The time interval between 2 trigger events must be greater than or equal to 1 ADC clock
period. The minimum time interval between 2 trigger events that start conversions on the
same ADC is the same as in the single ADC mode.
Injected discontinuous mode enabled (JDISCEN=1 for both ADC)

750/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

If the injected discontinuous mode is enabled for both master and slave ADCs:
• When the 1st trigger occurs, the first injected channel of the master ADC is converted.
• When the 2nd trigger occurs, the first injected channel of the slave ADC is converted.
• And so on.
A JEOS interrupt, if enabled, is generated after all injected channels of the master ADC in
the group have been converted.
A JEOS interrupt, if enabled, is generated after all injected channels of the slave ADC in the
group have been converted.
JEOC interrupts, if enabled, can also be generated after each injected conversions.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts.

Figure 149. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode

1st trigger 3rd trigger 5th trigger 7th trigger

JEOC on JEOC on JEOC on JEOC, JEOS on
master ADC master ADC master ADC master ADC

MASTER ADC
SLAVE ADC

JEOC on JEOC on JEOC on JEOC, JEOS on

master ADC master ADC master ADC master ADC
Sampling 2nd trigger 4th trigger 6th trigger 8th trigger
Conversion
ai16060V2-m

Combined regular/injected simultaneous mode

This mode is selected by programming bits DUAL[4:0] = 00001.
It is possible to interrupt the simultaneous conversion of a regular group to start the
simultaneous conversion of an injected group.
Note: In combined regular/injected simultaneous mode, one must convert sequences with the
same length or ensure that the interval between triggers is longer than the long conversion
time of the 2 sequences. Otherwise, the ADC with the shortest sequence may restart while
the ADC with the longest sequence is completing the previous conversions.

Combined regular simultaneous + alternate trigger mode

This mode is selected by programming bits DUAL[4:0]=00010.
It is possible to interrupt the simultaneous conversion of a regular group to start the
alternate trigger conversion of an injected group. Figure 150 shows the behavior of an
alternate trigger interrupting a simultaneous regular conversion.
The injected alternate conversion is immediately started after the injected event. If a regular
conversion is already running, in order to ensure synchronization after the injected
conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed
synchronously at the end of the injected conversion.

RM0438 Rev 7 751/2194

796
Analog-to-digital converters (ADC) RM0438

Note: In combined regular simultaneous + alternate trigger mode, one must convert sequences
with the same length or ensure that the interval between triggers is longer than the long
conversion time of the 2 sequences. Otherwise, the ADC with the shortest sequence may
restart while the ADC with the longest sequence is completing the previous conversions.

Figure 150. Alternate + regular simultaneous

1st trigger

ADC MASTER reg CH1 CH2 CH3 CH3 CH4 CH4 CH5
ADC MASTER inj CH1

ADC SLAVE reg CH4 CH6 CH7 CH7 CH8 CH8 CH9
ADC SLAVE inj CH1
synchronization not lost

2nd trigger
ai16062V2-m

If a trigger occurs during an injected conversion that has interrupted a regular conversion,
the alternate trigger is served. Figure 151 shows the behavior in this case (note that the 6th
trigger is ignored because the associated alternate conversion is not complete).

Figure 151. Case of trigger occurring during injected conversion

1st trigger 3rd trigger 5th trigger

ADC MASTER reg CH1 CH2 CH3 CH3 CH4 CH4 CH5 CH5 CH6
ADC MASTER inj CH14 CH14 CH14

ADC SLAVE reg CH7 CH8 CH9 CH9 CH10 CH10 CH11 CH11 CH12
ADC SLAVE inj CH15 CH15

2nd trigger 4th trigger 6th trigger

(ignored)
ai16063V2

Combined injected simultaneous plus interleaved

This mode is selected by programming bits DUAL[4:0]=00011
It is possible to interrupt an interleaved conversion with a simultaneous injected event.
In this case the interleaved conversion is interrupted immediately and the simultaneous
injected conversion starts. At the end of the injected sequence the interleaved conversion is
resumed. When the interleaved regular conversion resumes, the first regular conversion
which is performed is alway the master’s one. Figure 152, Figure 153 and Figure 154 show
the behavior using an example.
Caution: In this mode, it is mandatory to use the Common Data Register to read the regular data with
a single read access. On the contrary, master-slave data coherency is not guaranteed.

752/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 152. Interleaved single channel CH0 with injected sequence CH11, CH12

ADC1 (master) CH0 CH0 CH0 Conversions CH0 CH0 CH0

aborted
ADC2 (slave) CH0 CH0 CH0 CH0 CH0 CH0

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34461V1

Figure 153. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 1: Master interrupted first

ADC1 (master) CH1 CH1 CH1 Conversions CH1 CH1 CH1

aborted
ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH2

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34462V1

Figure 154. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first

ADC1 (master) CH1 CH1 CH1 Conversions CH1 CH1 CH1

aborted
ADC2 (slave) CH2 CH2 CH2 CH2 CH2 CH2

read read CH11 CH11 read read

CDR CDR CDR CDR
CH12 CH12

Legend:
Injected trigger Resume
(always restart with the master)
Sampling Conversion
MS34463V2

RM0438 Rev 7 753/2194

796
Analog-to-digital converters (ADC) RM0438

DMA requests in dual ADC mode

In all dual ADC modes, it is possible to use two DMA channels (one for the master, one for
the slave) to transfer the data, like in single mode (refer to Figure 155: DMA Requests in
regular simultaneous mode when MDMA=0b00).

Figure 155. DMA Requests in regular simultaneous mode when MDMA=0b00

Trigger Trigger

ADC Master regular CH1 CH1

ADC Master EOC

ADC Slave regular CH2 CH2

ADC Slave EOC

DMA request from ADC Master

DMA reads Master DMA reads Mater

ADC_DR ADC_DR

DMA request from ADC Slave

DMA reads Slave DMA reads Slave

ADC_DR ADC_DR
Configuration where each sequence contains only one conversion
MSv31032V2

In simultaneous regular and interleaved modes, it is also possible to save one DMA channel
and transfer both data using a single DMA channel. For this MDMA bits must be configured
in the ADCx_CCR register:
• MDMA=0b10: A single DMA request is generated each time both master and slave
EOC events have occurred. At that time, two data items are available and the 32-bit
register ADCx_CDR contains the two half-words representing two ADC-converted data
items. The slave ADC data take the upper half-word and the master ADC data take the
lower half-word.
This mode is used in interleaved mode and in regular simultaneous mode when
resolution is 10-bit or 12-bit.
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] | MST_ADC_DR[15:0]
2nd DMA request: ADCx_CDR[31:0] = SLV_ADC_DR[15:0] |
MST_ADC_DR[15:0]

754/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Figure 156. DMA requests in regular simultaneous mode when MDMA=0b10

Trigger Trigger Trigger Trigger

ADC Master regular CH1 CH1 CH1 CH1

ADC Slave EOC

CH2 CH2 CH2 CH2

ADC Slave regular

ADC Slave EOC

DMA request from

ADC Master
DMA request from
ADC Slave

Configuration where each sequence contains only one conversion

MSv31033V2

Figure 157. DMA requests in interleaved mode when MDMA=0b10

Trigger Trigger Trigger Trigger Trigger

CH1 CH1 CH1 CH1 CH1

ADC Master regular

ADC Master EOC Delay Delay Delay Delay Delay

ADC Slave regular

CH2 CH2 CH2 CH2 CH2
ADC Slave EOC

DMA request from

ADC Master
DMA request from
ADC Slave

Configuration where each sequence contains only one conversion

MSv31034V2

RM0438 Rev 7 755/2194

796
Analog-to-digital converters (ADC) RM0438

Note: When using MDMA mode, the user must take care to configure properly the duration of the
master and slave conversions so that a DMA request is generated and served for reading
both data (master + slave) before a new conversion is available.
• MDMA=0b11: This mode is similar to the MDMA=0b10. The only differences are that
on each DMA request (two data items are available), two bytes representing two ADC
converted data items are transferred as a half-word.
This mode is used in interleaved and regular simultaneous mode when resolution is 6-
bit or when resolution is 8-bit and data is not signed (offsets must be disabled for all the
involved channels).
Example:
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]
2nd DMA request: ADCx_CDR[15:0] = SLV_ADC_DR[7:0] | MST_ADC_DR[7:0]

Overrun detection
In dual ADC mode (when DUAL[4:0] is not equal to b00000), if an overrun is detected on
one of the ADCs, the DMA requests are no longer issued to ensure that all the data
transferred to the RAM are valid (this behavior occurs whatever the MDMA configuration). It
may happen that the EOC bit corresponding to one ADC remains set because the data
register of this ADC contains valid data.

DMA one shot mode/ DMA circular mode when MDMA mode is selected
When MDMA mode is selected (0b10 or 0b11), bit DMACFG of the ADCx_CCR register
must also be configured to select between DMA one shot mode and circular mode, as
explained in section Section : Managing conversions using the DMA (bits DMACFG of
master and slave ADC_CFGR are not relevant).

Stopping the conversions in dual ADC modes

The user must set the control bits ADSTP/JADSTP of the master ADC to stop the
conversions of both ADC in dual ADC mode. The other ADSTP control bit of the slave ADC
has no effect in dual ADC mode.
Once both ADC are effectively stopped, the bits ADSTART/JADSTART of the master and
slave ADCs are both cleared by hardware.

21.4.32 Temperature sensor

The temperature sensor can be used to measure the junction temperature (Tj) of the device.
The temperature sensor is internally connected to the ADC input channels which are used
to convert the sensor output voltage to a digital value. When not in use, the sensor can be
put in power down mode. It support the temperature range –40 to 125 °C.
Figure 158 shows the block diagram of connections between the temperature sensor and
the ADC.
The temperature sensor output voltage changes linearly with temperature. The offset of this
line varies from chip to chip due to process variation (up to 45 °C from one chip to another).

756/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

The uncalibrated internal temperature sensor is more suited for applications that detect
temperature variations instead of absolute temperatures. To improve the accuracy of the
temperature sensor measurement, calibration values are stored in system memory for each
device by ST during production.
During the manufacturing process, the calibration data of the temperature sensor and the
internal voltage reference are stored in the system memory area. The user application can
then read them and use them to improve the accuracy of the temperature sensor or the
internal reference (refer to the datasheet for additional information).
The temperature sensor is internally connected to the ADC input channel which is used to
convert the sensor’s output voltage to a digital value. Refer to the electrical characteristics
section of the device datasheet for the sampling time value to be applied when converting
the internal temperature sensor.
When not in use, the sensor can be put in power-down mode.
Figure 158 shows the block diagram of the temperature sensor.

Figure 158. Temperature sensor channel block diagram

CH17SEL control bit

Converted

Address/data bus
data

ADCx

Temperature VTS
sensor ADC input

MSv37243V3

Reading the temperature

To use the sensor:
1. Select the ADC input channels that is connected to VTS.
2. Program with the appropriate sampling time (refer to electrical characteristics section of
the device datasheet).
3. Set the CH17SEL bit in the ADCx_CCR register to wake up the temperature sensor
from power-down mode.
4. Start the ADC conversion.
5. Read the resulting VTS data in the ADC data register.
6. Calculate the actual temperature using the following formula:

TS_CAL2_TEMP – TS_CAL1_TEMP
Temperature ( in °C ) = -------------------------------------------------------------------------------------------------- × ( TS_DATA – TS_CAL1 ) + 30 °C
TS_CAL2 – TS_CAL1

RM0438 Rev 7 757/2194

796
Analog-to-digital converters (ADC) RM0438

Where:
• TS_CAL2 is the temperature sensor calibration value acquired at TS_CAL2_TEMP.
• TS_CAL1 is the temperature sensor calibration value acquired at TS_CAL1_TEMP.
• TS_DATA is the actual temperature sensor output value converted by ADC.
Refer to the device datasheet for more information about TS_CAL1 and TS_CAL2
calibration points.
Note: The sensor has a startup time after waking from power-down mode before it can output VTS
at the correct level. The ADC also has a startup time after power-on, so to minimize the
delay, the ADEN and CH17SEL bits should be set at the same time.
The above formula is given for TS_DATA measurement done with the same VREF+voltage
as TS_CAL1/TS_CAL2 values. If VREF+ is different, the formula must be adapted. For
example if VREF+ = 3.3 V and TS_CAL data are acquired at VREF+= 3.0 V, TS_DATA must
be replaced by TS_DATA x (3.3/3.0).

21.4.33 VBAT supply monitoring

The CH18SEL bit in the ADCx_CCR register is used to switch to the battery voltage. As the
VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the
VBAT pin is internally connected to a bridge divider by 3. This bridge is automatically enabled
when CH18SEL is set, to connect VBAT/3 to the ADC input channels. As a consequence, the
converted digital value is one third of the VBAT voltage. To prevent any unwanted
consumption on the battery, it is recommended to enable the bridge divider only when
needed, for ADC conversion.
Refer to the electrical characteristics of the device datasheet for the sampling time value to
be applied when converting the VBAT/3 voltage.
The figure below shows the block diagram of the VBAT sensing feature.

Figure 159. VBAT channel block diagram

VBAT

CH18SEL control bit

Address/data bus

ADCx

VBAT/3
ADC input

MSv37245V1

1. The CH18SEL bit must be set to enable the conversion of internal channel for VBAT/3.

758/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.4.34 Monitoring the internal voltage reference

It is possible to monitor the internal voltage reference (VREFINT) to have a reference point for
evaluating the ADC VREF+ voltage level.
The internal voltage reference is internally connected to the input channel 0 of the ADC1
(ADC1_INP0).
Refer to the electrical characteristics section of the product datasheet for the sampling time
value to be applied when converting the internal voltage reference voltage.
Figure 160 shows the block diagram of the VREFINT sensing feature.

Figure 160. VREFINT channel block diagram

VREFEN control bit

ADCx

VREFINT
Internal ADC input
power block

MSv34467V5

1. The VREFEN bit into ADCx_CCR register must be set to enable the conversion of internal channels
(VREFINT).

Calculating the actual VREF+ voltage using the internal reference voltage
The power supply voltage applied to the device may be subject to variations or not precisely
known. When VDDA is connected to VREF+, it is possible to compute the actual VDDA voltage
using the embedded internal reference voltage (VREFINT). VREFINT and its calibration data,
acquired by the ADC during the manufacturing process at VDDA_Charac, can be used to
evaluate the actual VDDA voltage level.
The following formula gives the actual VREF+ voltage supplying the device:

V REF+ = V REF+_Charac × VREFINT_CAL ⁄ VREFINT_DATA

Where:
• VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process. It is specified in the device datasheet.
• VREFINT_CAL is the VREFINT calibration value
• VREFINT_DATA is the actual VREFINT output value converted by ADC

Converting a supply-relative ADC measurement to an absolute voltage value

The ADC is designed to deliver a digital value corresponding to the ratio between VREF+ and
the voltage applied on the converted channel.
For most applications VDDA value is unknown and ADC converted values are right-aligned.
In this case, it is necessary to convert this ratio into a voltage independent from VDDA:

RM0438 Rev 7 759/2194

796
Analog-to-digital converters (ADC) RM0438

V REF+
V CHANNELx = ------------------------------------- × ADC_DATA
FULL_SCALE

By replacing VREF+ by the formula provided above, the absolute voltage value is given by
the following formula
V REF+_Charac × VREFINT_CAL × ADC_DATA
V CHANNELx = -----------------------------------------------------------------------------------------------------------------------
VREFINT_DATA × FULL_SCALE

For applications where VREF+ is known and ADC converted values are right-aligned, the
absolute voltage value can be obtained by using the following formula:
V REF+
V CHANNELx = ------------------------------------- × ADC_DATA
FULL_SCALE

Where:
– VREF+_Charac is the value of VREF+ voltage characterized at VREFINT during the
manufacturing process.
– VREFINT_CAL is the VREFINT calibration value
– ADC_DATA is the value measured by the ADC on channel x (right-aligned)
– VREFINT_DATA is the actual VREFINT output value converted by the ADC
– FULL_SCALE is the maximum digital value of the ADC output. For example with
12-bit resolution, it will be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255.
Note: If ADC measurements are done using an output format other than 16-bit right-aligned, all
the parameters must first be converted to a compatible format before the calculation is
done.

21.5 ADC interrupts

For each ADC, an interrupt can be generated:
• After ADC power-up, when the ADC is ready (flag ADRDY)
• On the end of any conversion for regular groups (flag EOC)
• On the end of a sequence of conversion for regular groups (flag EOS)
• On the end of any conversion for injected groups (flag JEOC)
• On the end of a sequence of conversion for injected groups (flag JEOS)
• When an analog watchdog detection occurs (flag AWD1, AWD2 and AWD3)
• When the end of sampling phase occurs (flag EOSMP)
• When the data overrun occurs (flag OVR)
• When the injected sequence context queue overflows (flag JQOVF)
Separate interrupt enable bits are available for flexibility.

760/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Table 170. ADC interrupts per each ADC

Interrupt event Event flag Enable control bit

ADC ready ADRDY ADRDYIE

End of conversion of a regular group EOC EOCIE
End of sequence of conversions of a regular group EOS EOSIE
End of conversion of a injected group JEOC JEOCIE
End of sequence of conversions of an injected group JEOS JEOSIE
Analog watchdog 1 status bit is set AWD1 AWD1IE
Analog watchdog 2 status bit is set AWD2 AWD2IE
Analog watchdog 3 status bit is set AWD3 AWD3IE
End of sampling phase EOSMP EOSMPIE
Overrun OVR OVRIE
Injected context queue overflows JQOVF JQOVFIE

RM0438 Rev 7 761/2194

796
Analog-to-digital converters (ADC) RM0438

21.6 ADC registers (for each ADC)

Refer to Section 1.2 on page 76 for a list of abbreviations used in register descriptions.

21.6.1 ADC interrupt and status register (ADC_ISR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. JQOVF AWD3 AWD2 AWD1 JEOS JEOC OVR EOS EOC EOSMP ADRDY

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVF: Injected context queue overflow
This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared
by software writing 1 to it. Refer to Section 21.4.21: Queue of context for injected conversions for
more information.
0: No injected context queue overflow occurred (or the flag event was already acknowledged and
cleared by software)
1: Injected context queue overflow has occurred
Bit 9 AWD3: Analog watchdog 3 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it.
0: No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 3 event occurred
Bit 8 AWD2: Analog watchdog 2 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it.
0: No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 2 event occurred
Bit 7 AWD1: Analog watchdog 1 flag
This bit is set by hardware when the converted voltage crosses the values programmed in the fields
LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it.
0: No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared
by software)
1: Analog watchdog 1 event occurred
Bit 6 JEOS: Injected channel end of sequence flag
This bit is set by hardware at the end of the conversions of all injected channels in the group. It is
cleared by software writing 1 to it.
0: Injected conversion sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected conversions complete

762/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bit 5 JEOC: Injected channel end of conversion flag

This bit is set by hardware at the end of each injected conversion of a channel when a new data is
available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by
reading the corresponding ADC_JDRy register
0: Injected channel conversion not complete (or the flag event was already acknowledged and
cleared by software)
1: Injected channel conversion complete
Bit 4 OVR: ADC overrun
This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new
conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to
it.
0: No overrun occurred (or the flag event was already acknowledged and cleared by software)
1: Overrun has occurred
Bit 3 EOS: End of regular sequence flag
This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is
cleared by software writing 1 to it.
0: Regular Conversions sequence not complete (or the flag event was already acknowledged and
cleared by software)
1: Regular Conversions sequence complete
Bit 2 EOC: End of conversion flag
This bit is set by hardware at the end of each regular conversion of a channel when a new data is
available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR
register
0: Regular channel conversion not complete (or the flag event was already acknowledged and
cleared by software)
1: Regular channel conversion complete
Bit 1 EOSMP: End of sampling flag
This bit is set by hardware during the conversion of any channel (only for regular channels), at the
end of the sampling phase.
0: not at the end of the sampling phase (or the flag event was already acknowledged and cleared by
software)
1: End of sampling phase reached
Bit 0 ADRDY: ADC ready
This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC
reaches a state where it is ready to accept conversion requests.
It is cleared by software writing 1 to it.
0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared
by software)
1: ADC is ready to start conversion

RM0438 Rev 7 763/2194

796
Analog-to-digital converters (ADC) RM0438

21.6.2 ADC interrupt enable register (ADC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF EOSMP ADRDY
Res. Res. Res. Res. Res. AWD3IE AWD2IE AWD1IE JEOSIE JEOCIE OVRIE EOSIE EOCIE
IE IE IE
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bit 10 JQOVFIE: Injected context queue overflow interrupt enable
This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow
interrupt.
0: Injected Context Queue Overflow interrupt disabled
1: Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit
is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
Bit 9 AWD3IE: Analog watchdog 3 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 3 interrupt disabled
1: Analog watchdog 3 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 8 AWD2IE: Analog watchdog 2 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt.
0: Analog watchdog 2 interrupt disabled
1: Analog watchdog 2 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 7 AWD1IE: Analog watchdog 1 interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt.
0: Analog watchdog 1 interrupt disabled
1: Analog watchdog 1 interrupt enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 6 JEOSIE: End of injected sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of injected sequence of conversions
interrupt.
0: JEOS interrupt disabled
1: JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).

764/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bit 5 JEOCIE: End of injected conversion interrupt enable

This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt.
0: JEOC interrupt disabled.
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no
injected conversion is ongoing).
Bit 4 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular
conversion.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 3 EOSIE: End of regular sequence of conversions interrupt enable
This bit is set and cleared by software to enable/disable the end of regular sequence of conversions
interrupt.
0: EOS interrupt disabled
1: EOS interrupt enabled. An interrupt is generated when the EOS bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 2 EOCIE: End of regular conversion interrupt enable
This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt.
0: EOC interrupt disabled.
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 1 EOSMPIE: End of sampling flag interrupt enable for regular conversions
This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for
regular conversions.
0: EOSMP interrupt disabled.
1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 0 ADRDYIE: ADC ready interrupt enable
This bit is set and cleared by software to enable/disable the ADC Ready interrupt.
0: ADRDY interrupt disabled
1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set.
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

RM0438 Rev 7 765/2194

796
Analog-to-digital converters (ADC) RM0438

21.6.3 ADC control register (ADC_CR)

Address offset: 0x08
Reset value: 0x2000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADCA ADCA DEEP ADVREG
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
L LDIF PWD EN
rs rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JADST JADST ADSTA
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADSTP ADDIS ADEN
P ART RT
rs rs rs rs rs rs

Bit 31 ADCAL: ADC calibration

This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF
to determine if this calibration applies for single-ended or differential inputs mode.
It is cleared by hardware after calibration is complete.
0: Calibration complete
1: Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress.
Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0.
The software is allowed to update the calibration factor by writing ADC_CALFACT only
when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion
is ongoing)
Bit 30 ADCALDIF: Differential mode for calibration
This bit is set and cleared by software to configure the single-ended or differential inputs
mode for the calibration.
0: Writing ADCAL will launch a calibration in single-ended inputs mode.
1: Writing ADCAL will launch a calibration in differential inputs mode.
Note: The software is allowed to write this bit only when the ADC is disabled and is not
calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0
and ADEN=0).
Bit 29 DEEPPWD: Deep-power-down enable
This bit is set and cleared by software to put the ADC in Deep-power-down mode.
0: ADC not in Deep-power down
1: ADC in Deep-power-down (default reset state)
Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bit 28 ADVREGEN: ADC voltage regulator enable
This bits is set by software to enable the ADC voltage regulator.
Before performing any operation such as launching a calibration or enabling the ADC, the
ADC voltage regulator must first be enabled and the software must wait for the regulator
start-up time.
0: ADC Voltage regulator disabled
1: ADC Voltage regulator enabled.
For more details about the ADC voltage regulator enable and disable sequences, refer to
Section 21.4.6: ADC Deep-power-down mode (DEEPPWD) and ADC voltage regulator
(ADVREGEN).
The software can program this bit field only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

766/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bits 27:6 Reserved, must be kept at reset value.

Bit 5 JADSTP: ADC stop of injected conversion command
This bit is set by software to stop and discard an ongoing injected conversion (JADSTP
Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC injected
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of
injected conversions (JADSTART command).
0: No ADC stop injected conversion command ongoing
1: Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is
in progress.
Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is
enabled and eventually converting an injected conversion and there is no pending
request to disable the ADC)
In Auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP)
Bit 4 ADSTP: ADC stop of regular conversion command
This bit is set by software to stop and discard an ongoing regular conversion (ADSTP
Command).
It is cleared by hardware when the conversion is effectively discarded and the ADC regular
sequence and triggers can be re-configured. The ADC is then ready to accept a new start of
regular conversions (ADSTART command).
0: No ADC stop regular conversion command ongoing
1: Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in
progress.
Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is
enabled and eventually converting a regular conversion and there is no pending request
to disable the ADC).
In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected
conversions (do not use JADSTP).
Bit 3 JADSTART: ADC start of injected conversion
This bit is set by software to start ADC conversion of injected channels. Depending on the
configuration bits JEXTEN[1:0], a conversion will start immediately (software trigger
configuration) or once an injected hardware trigger event occurs (hardware trigger
configuration).
It is cleared by hardware:
– in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the
assertion of the End of Injected Conversion Sequence (JEOS) flag.
– in all cases: after the execution of the JADSTP command, at the same time that JADSTP is
cleared by hardware.
0: No ADC injected conversion is ongoing.
1: Write 1 to start injected conversions. Read 1 means that the ADC is operating and
eventually converting an injected channel.
Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is
enabled and there is no pending request to disable the ADC).
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by
setting bit ADSTART (JADSTART must be kept cleared)

RM0438 Rev 7 767/2194

796
Analog-to-digital converters (ADC) RM0438

Bit 2 ADSTART: ADC start of regular conversion

This bit is set by software to start ADC conversion of regular channels. Depending on the
configuration bits EXTEN[1:0], a conversion will start immediately (software trigger
configuration) or once a regular hardware trigger event occurs (hardware trigger
configuration).
It is cleared by hardware:
– in single conversion mode when software trigger is selected (EXTSEL=0x0): at the assertion
of the End of Regular Conversion Sequence (EOS) flag.
– in all cases: after the execution of the ADSTP command, at the same time that ADSTP is
cleared by hardware.
0: No ADC regular conversion is ongoing.
1: Write 1 to start regular conversions. Read 1 means that the ADC is operating and
eventually converting a regular channel.
Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is
enabled and there is no pending request to disable the ADC)
In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by
setting bit ADSTART (JADSTART must be kept cleared)
Bit 1 ADDIS: ADC disable command
This bit is set by software to disable the ADC (ADDIS command) and put it into power-down
state (OFF state).
It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by
hardware at this time).
0: no ADDIS command ongoing
1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress.
Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and
JADSTART=0 (which ensures that no conversion is ongoing)
Bit 0 ADEN: ADC enable control
This bit is set by software to enable the ADC. The ADC will be effectively ready to operate
once the flag ADRDY has been set.
It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS
command.
0: ADC is disabled (OFF state)
1: Write 1 to enable the ADC.
Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for
bit ADVREGEN which must be 1 (and the software must have wait for the startup time of
the voltage regulator)

768/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.4 ADC configuration register (ADC_CFGR)

Address offset: 0x0C
Reset value: 0x8000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JAWD1 AWD1 AWD1S JDISC DISC
JQDIS AWD1CH[4:0] JAUTO JQM DISCNUM[2:0]
EN EN GL EN EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AUT OVR EXTSE EXTSE EXTSE EXTSE DFSD DMA DMA
Res. CONT EXTEN[1:0] ALIGN RES[1:0]
DLY MOD L3 L2 L1 L0 MCFG CFG EN
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 JQDIS: Injected Queue disable

These bits are set and cleared by software to disable the Injected Queue mechanism :
0: Injected Queue enabled
1: Injected Queue disabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no regular nor injected conversion is ongoing).
A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is
cleared.
Bits 30:26 AWD1CH[4:0]: Analog watchdog 1 channel selection
These bits are set and cleared by software. They select the input channel to be guarded by the
analog watchdog.
00000: ADC analog input channel 0 monitored by AWD1 (available on ADC1 only)
00001: ADC analog input channel 1 monitored by AWD1
.....
10010: ADC analog input channel 18 monitored by AWD1
others: reserved, must not be used
Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to
the reset value.
The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 25 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion after
regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no regular nor injected conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the
master ADC.

RM0438 Rev 7 769/2194

796
Analog-to-digital converters (ADC) RM0438

Bit 24 JAWD1EN: Analog watchdog 1 enable on injected channels

This bit is set and cleared by software
0: Analog watchdog 1 disabled on injected channels
1: Analog watchdog 1 enabled on injected channels
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
Bit 23 AWD1EN: Analog watchdog 1 enable on regular channels
This bit is set and cleared by software
0: Analog watchdog 1 disabled on regular channels
1: Analog watchdog 1 enabled on regular channels
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bit 22 AWD1SGL: Enable the watchdog 1 on a single channel or on all channels
This bit is set and cleared by software to enable the analog watchdog on the channel identified by
the AWD1CH[4:0] bits or on all the channels
0: Analog watchdog 1 enabled on all channels
1: Analog watchdog 1 enabled on a single channel
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bit 21 JQM: JSQR queue mode
This bit is set and cleared by software.
It defines how an empty Queue is managed.
0: JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR.
1: JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware
triggers of the injected sequence are both internally disabled just after the completion of the last valid
injected sequence.
Refer to Section 21.4.21: Queue of context for injected conversions for more information.
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master
ADC.
Bit 20 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no
injected conversion is ongoing).
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
When dual mode is enabled (bits DUAL of ADCx_CCR register are not equal to zero), the bit
JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of
the master ADC.

770/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bits 19:17 DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to be converted in
discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bits
DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits
DISCNUM[2:0] of the master ADC.
Bit 16 DISCEN: Discontinuous mode for regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels.
0: Discontinuous mode for regular channels disabled
1: Discontinuous mode for regular channels enabled
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the
bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the
master ADC.
Bit 15 Reserved, must be kept at reset value.
Bit 14 AUTDLY: Delayed conversion mode
This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.
0: Auto-delayed conversion mode off
1: Auto-delayed conversion mode on
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the
master ADC.
Bit 13 CONT: Single / continuous conversion mode for regular conversions
This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden
to set both DISCEN=1 and CONT=1.
The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
When dual mode is enabled (DUAL bits in ADCx_CCR register are not equal to zero), the bit
CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the
master ADC.

RM0438 Rev 7 771/2194

796
Analog-to-digital converters (ADC) RM0438

Bit 12 OVRMOD: Overrun mode

This bit is set and cleared by software and configure the way data overrun is managed.
0: ADC_DR register is preserved with the old data when an overrun is detected.
1: ADC_DR register is overwritten with the last conversion result when an overrun is detected.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular
conversion is ongoing).
Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable the
trigger of a regular group.
00: Hardware trigger detection disabled (conversions can be launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bits 9:6 EXTSEL[3:0]: External trigger selection for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Event 0
0001: Event 1
0010: Event 2
0011: Event 3
0100: Event 4
0101: Event 5
0110: Event 6
0111: Event 7
...
1111: Event 15
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 5 ALIGN: Data alignment
This bit is set and cleared by software to select right or left alignment. Refer to Section : Data
register, data alignment and offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN)
0: Right alignment
1: Left alignment
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 4:3 RES[1:0]: Data resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit
01: 10-bit
10: 8-bit
11: 6-bit
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

772/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bit 2 DFSDMCFG: DFSDM mode configuration

This bit is set and cleared by software to enable the DFSDM mode. It is effective only when
DMAEN=0.
0: DFSDM mode disabled
1: DFSDM mode enabled
Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when
ADSTART= 0 and JADSTART= 0.
Bit 1 DMACFG: Direct memory access configuration
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot mode selected
1: DMA Circular mode selected
For more details, refer to Section : Managing conversions using the DMA
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bit DMACFG of the
ADCx_CCR register.
Bit 0 DMAEN: Direct memory access enable
This bit is set and cleared by software to enable the generation of DMA requests. This allows to use
the DMA to manage automatically the converted data. For more details, refer to Section : Managing
conversions using the DMA.
0: DMA disabled
1: DMA enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
In dual-ADC modes, this bit is not relevant and replaced by control bits MDMA[1:0] of the
ADCx_CCR register.

21.6.5 ADC configuration register 2 (ADC_CFGR2)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ROV
Res. Res. Res. Res. Res. TROVS OVSS[3:0] OVSR[2:0] JOVSE ROVSE
SM
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:17 Reserved, must be kept at reset value.
Bits 16:11 Reserved, must be kept at reset value.

RM0438 Rev 7 773/2194

796
Analog-to-digital converters (ADC) RM0438

Bit 10 ROVSM: Regular Oversampling mode

This bit is set and cleared by software to select the regular oversampling mode.
0: Continued mode: When injected conversions are triggered, the oversampling is temporary
stopped and continued after the injection sequence (oversampling buffer is maintained during
injected sequence)
1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted
and resumed from start after the injection sequence (oversampling buffer is zeroed by injected
sequence start)
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 9 TROVS: Triggered Regular Oversampling
This bit is set and cleared by software to enable triggered oversampling
0: All oversampled conversions for a channel are done consecutively following a trigger
1: Each oversampled conversion for a channel needs a new trigger
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 8:5 OVSS[3:0]: Oversampling shift
This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling
result.
0000: No shift
0001: Shift 1-bit
0010: Shift 2-bits
0011: Shift 3-bits
0100: Shift 4-bits
0101: Shift 5-bits
0110: Shift 6-bits
0111: Shift 7-bits
1000: Shift 8-bits
Other codes reserved
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).

774/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bits 4:2 OVSR[2:0]: Oversampling ratio

This bitfield is set and cleared by software to define the oversampling ratio.
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
111: 256x
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 1 JOVSE: Injected Oversampling Enable
This bit is set and cleared by software to enable injected oversampling.
0: Injected Oversampling disabled
1: Injected Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)
Bit 0 ROVSE: Regular Oversampling Enable
This bit is set and cleared by software to enable regular oversampling.
0: Regular Oversampling disabled
1: Regular Oversampling enabled
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing)

21.6.6 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP5[
SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0]
0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 775/2194

796
Analog-to-digital converters (ADC) RM0438

Bits 31:30 Reserved, must be kept at reset value.

.
Bits 29:0 SMP[9:0][2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Some channels are not connected physically. Keep the corresponding SMPx[2:0]
setting to the reset value.

21.6.7 ADC sample time register 2 (ADC_SMPR2)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMP15[0] SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept at reset value.

Bits 26:0 SMP[18:10][2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
000: 2.5 ADC clock cycles
001: 6.5 ADC clock cycles
010: 12.5 ADC clock cycles
011: 24.5 ADC clock cycles
100: 47.5 ADC clock cycles
101: 92.5 ADC clock cycles
110: 247.5 ADC clock cycles
111: 640.5 ADC clock cycles
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Some channels are not connected physically. Keep the corresponding SMPx[2:0]
setting to the reset value.

776/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.8 ADC watchdog threshold register 1 (ADC_TR1)

Address offset: 0x20
Reset value: 0x0FFF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. HT1[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. LT1[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 1.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 LT1[11:0]: Analog watchdog 1 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 1.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

21.6.9 ADC watchdog threshold register 2 (ADC_TR2)

Address offset: 0x24
Reset value: 0x00FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. HT2[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. LT2[7:0]

rw rw rw rw rw rw rw rw

RM0438 Rev 7 777/2194

796
Analog-to-digital converters (ADC) RM0438

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 2.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT2[7:0]: Analog watchdog 2 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 2.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

21.6.10 ADC watchdog threshold register 3 (ADC_TR3)

Address offset: 0x28
Reset value: 0x00FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. HT3[7:0]

rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. LT3[7:0]

rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold
These bits are written by software to define the higher threshold for the analog watchdog 3.
Refer to Section 21.4.29: Analog window watchdog (AWD1EN, JAWD1EN, AWD1SGL, AWD1CH,
AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx)
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 LT3[7:0]: Analog watchdog 3 lower threshold
These bits are written by software to define the lower threshold for the analog watchdog 3.
This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).

778/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.11 ADC regular sequence register 1 (ADC_SQR1)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ4[4:0] Res. SQ3[4:0] Res. SQ2[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ2[3:0] Res. SQ1[4:0] Res. Res. L[3:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 4th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 3rd in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 2nd in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 1st in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bits 5:4 Reserved, must be kept at reset value.
Bits 3:0 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

RM0438 Rev 7 779/2194

796
Analog-to-digital converters (ADC) RM0438

21.6.12 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ9[4:0] Res. SQ8[4:0] Res. SQ7[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7[3:0] Res. SQ6[4:0] Res. SQ5[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 9th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 8th in
the regular conversion sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 7th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 6th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 5th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

780/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.13 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ14[4:0] Res. SQ13[4:0] Res. SQ12[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ12[3:0] Res. SQ11[4:0] Res. SQ10[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:29 Reserved, must be kept at reset value.

Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 14th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 13th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 12th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 11th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 10th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

RM0438 Rev 7 781/2194

796
Analog-to-digital converters (ADC) RM0438

21.6.14 ADC regular sequence register 4 (ADC_SQR4)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. SQ16[4:0] Res. SQ15[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, must be kept at reset value.

Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 16th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence
These bits are written by software with the channel number (0 to 18) assigned as the 15th in
the regular conversion sequence.
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

21.6.15 ADC regular data register (ADC_DR)

Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 RDATA[15:0]: Regular data converted
These bits are read-only. They contain the conversion result from the last converted regular channel.
The data are left- or right-aligned as described in Section 21.4.26: Data management.

782/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.16 ADC injected sequence register (ADC_JSQR)

Address offset: 0x4C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. JSQ4[4:0] Res. JSQ3[4:0] Res. JSQ2[4:2]
rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ2[1:0] Res. JSQ1[4:0] JEXTEN[1:0] JEXTSEL[3:0] JL[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 4th in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).
Bit 25 Reserved, must be kept at reset value.
Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 3rd in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).
Bit 19 Reserved, must be kept at reset value.
Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 2nd in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).
Bit 13 Reserved, must be kept at reset value.
Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence
These bits are written by software with the channel number (0 to 18) assigned as the 1st in
the injected conversion sequence.
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).

RM0438 Rev 7 783/2194

796
Analog-to-digital converters (ADC) RM0438

Bits 7:6 JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled
00: If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be
launched by software)
01: Hardware trigger detection on the rising edge
10: Hardware trigger detection on the falling edge
11: Hardware trigger detection on both the rising and falling edges
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).
If JQM=1 and if the Queue of Context becomes empty, the software and hardware
triggers of the injected sequence are both internally disabled (refer to Section 21.4.21:
Queue of context for injected conversions)
Bits 5:2 JEXTSEL[3:0]: External Trigger Selection for injected group
These bits select the external event used to trigger the start of conversion of an injected
group:
0000: Event 0
0001: Event 1
0010: Event 2
0011: Event 3
0100: Event 4
0101: Event 5
0110: Event 6
0111: Event 7
...
1111: Event 15
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).
Bits 1:0 JL[1:0]: Injected channel sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Note: The software is allowed to write these bits only when JADSTART=0 (which ensures
that no injected conversion is ongoing).

Note: Some channels are not connected physically and must not be selected for conversion.

784/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.17 ADC offset y register (ADC_OFRy)

Address offset: 0x60 + 0x04 * (y -1), (y= 1 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OFFSETy
OFFSETy_CH[4:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
_EN
rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. OFFSETy[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 OFFSETy_EN: Offset y enable

This bit is written by software to enable or disable the offset programmed into bits
OFFSETy[11:0].
Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Bits 30:26 OFFSETy_CH[4:0]: Channel selection for the data offset y
These bits are written by software to define the channel to which the offset programmed into
bits OFFSETy[11:0] will apply.
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the data
offset y.
Bits 25:12 Reserved, must be kept at reset value.
Bits 11:0 OFFSETy[11:0]: Data offset y for the channel programmed into bits OFFSETy_CH[4:0]
These bits are written by software to define the offset y to be subtracted from the raw
converted data when converting a channel (can be regular or injected). The channel to which
applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion
result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi
registers (injected conversion).
Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0
(which ensures that no conversion is ongoing).
If several offset (OFFSETy) point to the same channel, only the offset with the lowest x
value is considered for the subtraction.
Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[11:0] which is
subtracted when converting channel 4.

RM0438 Rev 7 785/2194

796
Analog-to-digital converters (ADC) RM0438

21.6.18 ADC injected channel y data register (ADC_JDRy)

Address offset: 0x80 + 0x04 * (y - 1), (y = 1 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDATA[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 JDATA[15:0]: Injected data
These bits are read-only. They contain the conversion result from injected channel y. The
data are left -or right-aligned as described in Section 21.4.26: Data management.

21.6.19 ADC analog watchdog 2 configuration register (ADC_AWD2CR)

Address offset: 0xA0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD2CH[18:16]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWD2CH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD2CH[18:0]: Analog watchdog 2 channel selection
These bits are set and cleared by software. They enable and select the input channels to be
guarded by the analog watchdog 2.
AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2
AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2
When AWD2CH[18:0] = 000..0, the analog watchdog 2 is disabled
Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the analog
watchdog.

786/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.6.20 ADC analog watchdog 3 configuration register (ADC_AWD3CR)

Address offset: 0xA4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWD3CH[18:16]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWD3CH[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 AWD3CH[18:0]: Analog watchdog 3 channel selection
These bits are set and cleared by software. They enable and select the input channels to be
guarded by the analog watchdog 3.
AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3
AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3
When AWD3CH[18:0] = 000..0, the analog watchdog 3 is disabled
Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers.
The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which
ensures that no conversion is ongoing).
Some channels are not connected physically and must not be selected for the analog
watchdog.

21.6.21 ADC differential mode selection register (ADC_DIFSEL)

Address offset: 0xB0
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DIFSEL[18:16]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIFSEL[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw r

Bits 31:19 Reserved, must be kept at reset value.

Bits 18:0 DIFSEL[18:0]: Differential mode for channels 18 to 0.
These bits are set and cleared by software. They allow to select if a channel is configured as single-
ended or differential mode.
DIFSEL[i] = 0: ADC analog input channel is configured in single ended mode
DIFSEL[i] = 1: ADC analog input channel i is configured in differential mode
Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port
or to an internal channel must be kept their reset value (single-ended input mode).
The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

RM0438 Rev 7 787/2194

796
Analog-to-digital converters (ADC) RM0438

21.6.22 ADC calibration factors (ADC_CALFACT)

Address offset: 0xB4
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT_D[6:0]

rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. CALFACT_S[6:0]

rw rw rw rw rw rw rw

Bits 31:23 Reserved, must be kept at reset value.

Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode
These bits are written by hardware or by software.
Once a differential inputs calibration is complete, they are updated by hardware with the calibration
factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new differential
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and
JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT_S[6:0]: Calibration Factors In single-ended mode
These bits are written by hardware or by software.
Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and
JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing).

21.7 ADC common registers

These registers define the control and status registers common to master and slave ADCs:

21.7.1 ADC common status register (ADC_CSR)

Address offset: 0x00 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing 0 to it in the corresponding ADC_ISR register.

788/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_
Res. Res. Res. Res. Res.
SLV SLV SLV SLV SLV SLV SLV SLV SLV SLV SLV
r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JQOVF_ AWD3_ AWD2_ AWD1_ JEOS_ JEOC_ OVR_ EOS_ EOC_ EOSMP_ ADRDY_
Res. Res. Res. Res. Res.
MST MST MST MST MST MST MST MST MST MST MST
r r r r r r r r r r r

Bits 31:27 Reserved, must be kept at reset value.

Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC
This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC
This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC
This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC
This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC
This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC
This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
Bit 20 OVR_SLV: Overrun flag of the slave ADC
This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC. This bit is a copy of the EOS bit in
the corresponding ADC_ISR register.
Bit 18 EOC_SLV: End of regular conversion of the slave ADC
This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC
This bit is a copy of the EOSMP2 bit in the corresponding ADC_ISR register.
Bit 16 ADRDY_SLV: Slave ADC ready
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC
This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC
This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC
This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC
This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
Bit 6 JEOS_MST: End of injected sequence flag of the master ADC
This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.

RM0438 Rev 7 789/2194

796
Analog-to-digital converters (ADC) RM0438

Bit 5 JEOC_MST: End of injected conversion flag of the master ADC

This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
Bit 4 OVR_MST: Overrun flag of the master ADC
This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
Bit 3 EOS_MST: End of regular sequence flag of the master ADC
This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
Bit 2 EOC_MST: End of regular conversion of the master ADC
This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC
This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
Bit 0 ADRDY_MST: Master ADC ready
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.

21.7.2 ADC common control register (ADC_CCR)

Address offset: 0x08 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CH18S VREF
Res. Res. Res. Res. Res. Res. Res. CH17SEL PRESC[3:0] CKMODE[1:0]
EL EN
rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA
MDMA[1:0] Res. DELAY[3:0] Res. Res. Res. DUAL[4:0]
CFG
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:25 Reserved, must be kept at reset value.

Bit 24 CH18SEL: CH18 selection
This bit is set and cleared by software to control channel 18.
0: VBAT channel disabled.
1: VBAT channel enabled
Bit 23 CH17SEL: CH17 selection
This bit is set and cleared by software to control channel 17.
0: Temperature sensor channel disabled
1: Temperature sensor channel enabled
Bit 22 VREFEN: VREFINT enable
This bit is set and cleared by software to enable/disable the VREFINT channel.
0: VREFINT channel disabled
1: VREFINT channel enabled

790/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Bits 21:18 PRESC[3:0]: ADC prescaler

These bits are set and cleared by software to select the frequency of the clock to the ADC.
The clock is common for all the ADCs.
0000: input ADC clock not divided
0001: input ADC clock divided by 2
0010: input ADC clock divided by 4
0011: input ADC clock divided by 6
0100: input ADC clock divided by 8
0101: input ADC clock divided by 10
0110: input ADC clock divided by 12
0111: input ADC clock divided by 16
1000: input ADC clock divided by 32
1001: input ADC clock divided by 64
1010: input ADC clock divided by 128
1011: input ADC clock divided by 256
other: reserved
Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0,
JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). The ADC prescaler
value is applied only when CKMODE[1:0] = 0b00.
Bits 17:16 CKMODE[1:0]: ADC clock mode
These bits are set and cleared by software to define the ADC clock scheme (which is
common to both master and slave ADCs):
00: CK_ADCx (x=123) (Asynchronous clock mode), generated at product level (refer to
Section 6: Reset and clock control (RCC))
01: HCLK/1 (Synchronous clock mode). This configuration must be enabled only if the AHB
clock prescaler is set to 1 (HPRE[3:0] = 0xxx in RCC_CFGR register) and if the system clock
has a 50% duty cycle.
10: HCLK/2 (Synchronous clock mode)
11: HCLK/4 (Synchronous clock mode)

In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start
of a conversion.
Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode
This bitfield is set and cleared by software. Refer to the DMA controller section for more
details.
00: MDMA mode disabled
01: Enable dual interleaved mode to output to the master channel of DFSDM interface both
Master and the Slave result (16-bit data width)
10: MDMA mode enabled for 12 and 10-bit resolution
11: MDMA mode enabled for 8 and 6-bit resolution
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).
Bit 13 DMACFG: DMA configuration (for dual ADC mode)
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot mode selected
1: DMA Circular mode selected
For more details, refer to Section : Managing conversions using the DMA
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
no regular conversion is ongoing).

RM0438 Rev 7 791/2194

796
Analog-to-digital converters (ADC) RM0438

Bit 12 Reserved, must be kept at reset value.

Bits 11:8 DELAY: Delay between 2 sampling phases
These bits are set and cleared by software. These bits are used in dual interleaved modes.
Refer to Table 171 for the value of ADC resolution versus DELAY bits values.
Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DUAL[4:0]: Dual ADC mode selection
These bits are written by software to select the operating mode.
All the ADCs independent:
00000: Independent mode

00001 to 01001: Dual mode, master and slave ADCs working together
00001: Combined regular simultaneous + injected simultaneous mode
00010: Combined regular simultaneous + alternate trigger mode
00011: Combined Interleaved mode + injected simultaneous mode
00100: Reserved
00101: Injected simultaneous mode only
00110: Regular simultaneous mode only
00111: Interleaved mode only
01001: Alternate trigger mode only
All other combinations are reserved and must not be programmed

Note: The software is allowed to write these bits only when the ADCs are disabled
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Table 171. DELAY bits versus ADC resolution

DELAY bits 12-bit resolution 10-bit resolution 8-bit resolution 6-bit resolution

0000 1 * TADC_CLK 1 * TADC_CLK 1 * TADC_CLK 1 * TADC_CLK

0001 2 * TADC_CLK 2 * TADC_CLK 2 * TADC_CLK 2 * TADC_CLK
0010 3 * TADC_CLK 3 * TADC_CLK 3 * TADC_CLK 3 * TADC_CLK
0011 4 * TADC_CLK 4 * TADC_CLK 4 * TADC_CLK 4 * TADC_CLK
0100 5 * TADC_CLK 5 * TADC_CLK 5 * TADC_CLK 5 * TADC_CLK
0101 6 * TADC_CLK 6 * TADC_CLK 6 * TADC_CLK 6 * TADC_CLK
0110 7 * TADC_CLK 7 * TADC_CLK 7 * TADC_CLK 6 * TADC_CLK
0111 8 * TADC_CLK 8 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1000 9 * TADC_CLK 9 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1001 10 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1010 11 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
1011 12 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK
others 12 * TADC_CLK 10 * TADC_CLK 8 * TADC_CLK 6 * TADC_CLK

792/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

21.7.3 ADC common regular data register for dual mode (ADC_CDR)
Address offset: 0x0C (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA_SLV[15:0]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA_MST[15:0]
r r r r r r r r r r r r r r r r

Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC

In dual mode, these bits contain the regular data of the slave ADC. Refer to Section 21.4.31:
Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and
offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))
Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC.
In dual mode, these bits contain the regular data of the master ADC. Refer to
Section 21.4.31: Dual ADC modes.
The data alignment is applied as described in Section : Data register, data alignment and
offset (ADC_DR, OFFSETy, OFFSETy_CH, ALIGN))
In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains
MST_ADC_DR[7:0].

21.8 ADC register map

The following table summarizes the ADC registers.

Table 172. ADC global register map(1)

Offset Register

0x000 - 0x0B4 Master ADC1

0x0B8 - 0x0FC Reserved
0x100 - 0x1B4 Slave ADC2
0x1B8 - 0x2FC Reserved
0x300 - 0x30C Master and slave ADCs common registers
1. Reserved area highlighted in gray.

RM0438 Rev 7 793/2194

796
Analog-to-digital converters (ADC) RM0438

Table 173. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EOSMP
ADRDY
JQOVF
AWD3
AWD2
AWD1

JEOC
JEOS

OVR

EOC
EOS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_ISR
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0

EOSMPIE
ADRDYIE
JQOVFIE
AWD3IE
AWD2IE
AWD1IE

JEOCIE
JEOSIE

OVRIE

EOCIE
EOSIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_IER
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0
ADVREGEN

JADSTART
DEEPPWD
ADCALDIF

ADSTART
JADSTP
ADCAL

ADSTP

ADDIS
ADEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CR
0x08

Reset value 0 0 1 0 0 0 0 0 0 0

DFSDMCFG
EXTEN[1:0]
AWD1SGL
JAWD1EN

OVRMOD

EXTSEL3
EXTSEL2
EXTSEL1
EXTSEL0

DMACFG
JDISCEN
AWD1EN

AUTDLY
DISCEN

DMAEN
JAUTO
JQDIS.

ALIGN
CONT
DISCNUM RES
JQM

Res.
ADC_CFGR AWD1CH[4:0]
0x0C [2:0] [1:0]

Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ROVSM

ROVSE
TROVS

JOVSE
OVSR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CFGR2 OVSS[3:0]
0x0C [2:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0
SMP9 SMP8 SMP7 SMP6 SMP5 SMP4 SMP3 SMP2 SMP1 SMP0
Res.
Res.

ADC_SMPR1
0x14 [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SMP18 SMP17 SMP16 SMP15 SMP14 SMP13 SMP12 SMP11 SMP10
Res.
Res.
Res.
Res.
Res.

ADC_SMPR2
0x18 [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0] [2:0]
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x1C Reserved Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

ADC_TR1 HT1[11:0] LT1[11:0]

0x20
Reset value 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_TR2 HT2[[7:0] LT2[7:0]

0x24
Reset value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_TR3 HT3[[7:0] LT3[7:0]

0x28
Reset value 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
0x2C Reserved Res.
Res.
Res.
Res.

Res.

Res.

Res.

Res.
Res.

ADC_SQR1 SQ4[4:0] SQ3[4:0] SQ2[4:0] SQ1[4:0] L[3:0]

0x30
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.

Res.

Res.

Res.

ADC_SQR2 SQ9[4:0] SQ8[4:0] SQ7[4:0] SQ6[4:0] SQ5[4:0]

0x34
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.

Res.

Res.

Res.

Res.

ADC_SQR3 SQ14[4:0] SQ13[4:0] SQ12[4:0] SQ11[4:0] SQ10[4:0]

0x38
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

ADC_SQR4 SQ16[4:0] SQ15[4:0]

0x3C
Reset value 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_DR regular RDATA[15:0]

0x40
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x44-
Reserved Res.
0x48

794/2194 RM0438 Rev 7

RM0438 Analog-to-digital converters (ADC)

Table 173. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
JEXTEN[1:0]
Res. JEXTSEL

Res.

Res.

Res.
ADC_JSQR JSQ4[4:0] JSQ3[4:0] JSQ2[4:0] JSQ1[4:0] JL[1:0]
0x4C [3:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x50-
Reserved Res.
0x5C
OFFSET1_EN

OFFSET1_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_OFR1 OFFSET1[11:0]
0x60 CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET2_EN

OFFSET2_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_OFR2 OFFSET2[11:0]
0x64 CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET3_EN

OFFSET3_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_OFR3 OFFSET3[11:0]
0x68 CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OFFSET4_EN

OFFSET4_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_OFR4 OFFSET4[11:0]
0x6C CH[4:0]

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x70-
Reserved Res.
0x7C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR1 JDATA1[15:0]
0x80
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR2 JDATA2[15:0]
0x84
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR3 JDATA3[15:0]
0x88
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_JDR4 JDATA4[15:0]
0x8C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x8C-
Reserved Res.
0x9C
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_AWD2CR AWD2CH[18:0]
0xA0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_AWD3CR AWD3CH[18:0]
0xA4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0xA8-
Reserved
0xAC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

ADC_DIFSEL DIFSEL[18:0]
0xB0
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 795/2194

796
Analog-to-digital converters (ADC) RM0438

Table 173. ADC register map and reset values for each ADC (offset=0x000
for master ADC, 0x100 for slave ADC) (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CALFACT CALFACT_D[6:0] CALFACT_S[6:0]
0xB4
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 174. ADC register map and reset values (master and slave ADC
common registers) offset = 0x300

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
EOSMP_MST
ADRDY_MST
JQOVF_MST
EOSMP_SLV
ADRDY_SLV
JQOVF_SLV

AWD3_MST
AWD2_MST
AWD1_MST

JEOC_MST
JEOS_MST
AWD3_SLV
AWD2_SLV
AWD1_SLV

JEOC_SLV
JEOS_SLV

OVR_MST

EOC_MST
EOS_MST
OVR_SLV

EOC_SLV
EOS_SLV
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
ADC_CSR
0x00

slave ADC2 master ADC1

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x04 Reserved Res.

CKMODE[1:0]

MDMA[1:0]
CH18SEL
CH17SEL

DMACFG
VREFEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
ADC_CCR PRESC[3:0] DELAY[3:0] DUAL[4:0]
0x08

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADC_CDR RDATA_SLV[15:0] RDATA_MST[15:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

796/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22 Digital-to-analog converter (DAC)

22.1 Introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. The DAC features two output channels,
each with its own converter. In dual DAC channel mode, conversions could be done
independently or simultaneously when both channels are grouped together for synchronous
update operations. An input reference pin, VREF+ (shared with others analog peripherals) is
available for better resolution. An internal reference can also be set on the same input.
Refer to voltage reference buffer (VREFBUF) section.
The DACx_OUTy pin can be used as general purpose input/output (GPIO) when the DAC
output is disconnected from output pad and connected to on chip peripheral. The DAC
output buffer can be optionally enabled to allow a high drive output current. An individual
calibration can be applied on each DAC output channel. The DAC output channels support
a low power mode, the Sample and hold mode.

22.2 DAC main features

The DAC main features are the following (see Figure 161: Dual-channel DAC block
diagram)
• One DAC interface, maximum two output channels
• Left or right data alignment in 12-bit mode
• Synchronized update capability
• Noise-wave and Triangular-wave generation
• Dual DAC channel for independent or simultaneous conversions
• DMA capability for each channel including DMA underrun error detection
• External triggers for conversion
• DAC output channel buffered/unbuffered modes
• Buffer offset calibration
• Each DAC output can be disconnected from the DACx_OUTy output pin
• DAC output connection to on chip peripherals
• Sample and hold mode for low power operation in Stop mode
• Input voltage reference, VREF+
Figure 161 shows the block diagram of a DAC channel and Table 176 gives the pin
description.

RM0438 Rev 7 797/2194

834
Digital-to-analog converter (DAC) RM0438

22.3 DAC implementation

Table 175. DAC features
DAC features DAC1

Dual channel X
Output buffer X
I/O connection DAC1_OUT1 on PA4, DAC1_OUT2 on PA5
Maximum sampling time 1MSPS
Autonomous mode -

798/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.4 DAC functional description

22.4.1 DAC block diagram

Figure 161. Dual-channel DAC block diagram

VREF+ VDDA

Offset calibration
Sample & Hold Registers
Control registers OTRIM1[5:0]bits
& logic Channel1 TSAMPLE1

THOLD1
TSEL1[3:0]
bits DMA_Request TREFRESH1

DACx_OUT1
DAC Buffer 1
TRIG DAC_DOR1
converter 1
12-bit
1

MODE1 bits

dac_out1
LSI clock
DAC channel 1

Offset calibration
Sample & Hold Registers
Control registers OTRIM2[5:0]bits On-chip
& logic Channel2 TSAMPLE2
Peripherals
THOLD2
TSEL2[3:0]
bits DMA_Request TREFRESH2

DACx_OUT2
TRIG
DAC
DAC_DOR2 Buffer 2
converter 2
12-bit
1

MODE2 bits

dac_out2
DAC channel 2

APB1 Bus On-chip

Peripherals

VSSA
MSv40461V4

1. MODEx bits in the DAC_MCR control the output mode and allow switching between the Normal mode in
buffer/unbuffered configuration and the Sample and hold mode.
2. Refer to Section 22.3: DAC implementation for channel2 availability.

RM0438 Rev 7 799/2194

834
Digital-to-analog converter (DAC) RM0438

The DAC includes:

• Up to two output channels
• The DACx_OUTy can be disconnected from the output pin and used as an ordinary
GPIO
• The DAC_OUTx can use an internal pin connection to on-chip peripherals such as
comparator, operational amplifier and ADC (if available).
• DAC output channel buffered or non buffered
• Sample and hold block and registers operational in Stop mode, using the LSI clock
source for static conversion.
The DAC includes up to two separate output channels. Each output channel can be
connected to on-chip peripherals such as comparator, operational amplifier and ADC (if
available). In this case, the DAC output channel can be disconnected from the DACx_OUTy
output pin and the corresponding GPIO can be used for another purpose.
The DAC output can be buffered or not. The Sample and hold block and its associated
registers can run in Stop mode using the LSI clock source.

Table 176. DAC input/output pins

Pin name Signal type Remarks

Input, analog reference The higher/positive reference voltage for the DAC,
VREF+
positive VREF+ ≤ VDDAmax (refer to datasheet)
VDDA Input, analog supply Analog power supply
VSSA Input, analog supply ground Ground for analog power supply
DACx_OUTy Analog output signal DACx channely analog output

22.4.2 DAC channel enable

Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a tWAKEUP startup time.
Note: The ENx bit enables the analog DAC channelx only. The DAC channelx digital interface is
enabled even if the ENx bit is reset.

22.4.3 DAC data format

Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
• Single DAC channel
There are three possibilities:
– 8-bit right alignment: the software has to load data into the DAC_DHR8Rx[7:0] bits
(stored into the DHRx[11:4] bits)
– 12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
– 12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memory-

800/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

mapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.

Figure 162. Data registers in single DAC channel mode

31 24 15 7 0
8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14710b
• Dual DAC channels (when available)
There are three possibilities:
– 8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD
[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded
into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
– 12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD
[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be
loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
– 12-bit right alignment: data for DAC channel1 to be loaded into the
DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC
channel2 to be loaded into the DAC_DHR12RD [27:16] bits (stored into the
DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-
mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1
and DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.

Figure 163. Data registers in dual DAC channel mode

31 24 15 7 0
8-bit right aligned

12-bit left aligned

12-bit right aligned

ai14709b

RM0438 Rev 7 801/2194

834
Digital-to-analog converter (DAC) RM0438

22.4.4 DAC conversion

The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write operation to DAC_DHR8Rx,
DAC_DHR12Lx, DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12RD or DAC_DHR12LD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles after
the trigger signal.
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.
HFSEL bit of DAC_CR must be set when APB1 clock speed is faster than 80 MHz. It adds
an extra delay of three APB1 clock cycles to the transfer from DAC_DHRx register to
DAC_DORx register (tSETTLING).
The DAC_DORx update rate is limited to 1/3 of APB1 clock frequency. When HFSEL bit is
set, this rate is limited to 1/8 of the APB1 clock frequency.
When HFSEL is set, it is not allowed to write the DHRx register during a period of eight clock
cycles after the ENx bit is set. During this period, making software/hardware triggering is not
allowed either.

Figure 164. Timing diagram for conversion with trigger disabled TEN = 0

APB1_CLK

DHR 0x1AC

Output voltage
DOR 0x1AC available on DAC_OUT pin
tSETTLING
ai14711c

22.4.5 DAC output voltage

Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DOR
DACoutput = V REF × --------------
4096

802/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.4.6 DAC trigger selection

If the TENx control bit is set, the conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[3:0] control bits determine which out of 16 pos-
sible events triggers the conversion as shown in TSELx[3:0] bits of the DAC_CR register.
These events can be either the software trigger or hardware triggers. Refer to Table 177:
DAC trigger selection.
Each time a DAC interface detects a rising edge on the selected trigger source (refer to the
table below), the last data stored into the DAC_DHRx register are transferred into the
DAC_DORx register. The DAC_DORx register is updated three APB1 cycles after the
trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note: TSELx[3:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB1 clock cycle.

Table 177. DAC trigger selection

Source Type TSELx[3:0]

SWTRIG Software control bit 0000

TIM1_TRGO Internal signal from on-chip timers 0001
TIM2_TRGO Internal signal from on-chip timers 0010
TIM4_TRGO Internal signal from on-chip timers 0011
TIM5_TRGO Internal signal from on-chip timers 0100
TIM6_TRGO Internal signal from on-chip timers 0101
TIM7_TRGO Internal signal from on-chip timers 0110
TIM8_TRGO Internal signal from on-chip timers 0111
TIM15_TRGO Internal signal from on-chip timers 1000
Reserved - 1001
Reserved - 1010
LPTIM1_OUT Internal signal from on-chip timers 1011
LPTIM2_OUT Internal signal from on-chip timers 1100
EXTI9 External pin 1101
Reserved - 1110
Reserved - 1111

RM0438 Rev 7 803/2194

834
Digital-to-analog converter (DAC) RM0438

22.4.7 DMA requests

Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
When an external trigger (but not a software trigger) occurs while the DMAENx bit is set, the
value of the DAC_DHRx register is transferred into the DAC_DORx register when the
transfer is complete, and a DMA request is generated.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, only the corresponding DMAENx bit must be set. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
As DAC_DHRx to DAC_DORx data transfer occurred before the DMA request, the very first
data has to be written to the DAC_DHRx before the first trigger event occurs.

DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgment for the first external trigger is received (first request), then no new request
is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register is set,
reporting the error condition. The DAC channelx continues to convert old data.
The software must clear the DMAUDRx flag by writing 1, clear the DMAEN bit of the used
DMA stream and re-initialize both DMA and DAC channelx to restart the transfer correctly.
The software must modify the DAC trigger conversion frequency or lighten the DMA
workload to avoid a new DMA underrun. Finally, the DAC conversion could be resumed by
enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.

22.4.8 Noise generation

In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to 01. The
preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after
each trigger event, following a specific calculation algorithm.

804/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Figure 165. DAC LFSR register calculation algorithm

XOR

X6 X4 X X0
X 12
11 10 9 8 7 6 5 4 3 2 1 0

12

NOR

ai14713c

The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then transferred into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.

Figure 166. DAC conversion (SW trigger enabled) with LFSR wave generation

APB1_CLK

DHR 0x00

DOR 0xAAA 0xD55

SWTRIG

ai14714b

Note: The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.

RM0438 Rev 7 805/2194

834
Digital-to-analog converter (DAC) RM0438

22.4.9 Triangle-wave generation

It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to 10”. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB1 clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is transferred into the
DAC_DORx register. The triangle counter is incremented as long as it is less than the
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.

Figure 167. DAC triangle wave generation

MAMPx[3:0] max amplitude

+ DAC_DHRx base value

De
n
tio

cr
ta

em
en

en
em

ta
cr

tio
In

n
DAC_DHRx base value
0

ai14715c

Figure 168. DAC conversion (SW trigger enabled) with triangle wave generation

APB1_CLK

DHR 0xABE

DOR 0xABE 0xABF 0xAC0

SWTRIG

ai14716b

Note: The DAC trigger must be enabled for triangle wave generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.

806/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.4.10 DAC channel modes

Each DAC channel can be configured in Normal mode or Sample and hold mode. The
output buffer can be enabled to allow a high drive capability. Before enabling output buffer,
the voltage offset needs to be calibrated. This calibration is performed at the factory (loaded
after reset) and can be adjusted by software during application operation.

Normal mode
In Normal mode, there are four combinations, by changing the buffer state and by changing
the DACx_OUTy pin interconnections.
To enable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 000: DAC is connected to the external pin
• 001: DAC is connected to external pin and to on-chip peripherals
To disable the output buffer, the MODEx[2:0] bits in DAC_MCR register must be:
• 010: DAC is connected to the external pin
• 011: DAC is connected to on-chip peripherals

Sample and hold mode

In Sample and hold mode, the DAC core converts data on a triggered conversion, and then
holds the converted voltage on a capacitor. When not converting, the DAC cores and buffer
are completely turned off between samples and the DAC output is tri-stated, therefore
reducing the overall power consumption. A stabilization period, which value depends on the
buffer state, is required before each new conversion.
In this mode, the DAC core and all corresponding logic and registers are driven by the LSI
low-speed clock in addition to the APB1 clock, allowing to use the DAC channels in deep
low power modes such as Stop mode.
The LSI low-speed clock must not be stopped when the Sample and hold mode is enabled.
The sample/hold mode operations can be divided into 3 phases:
1. Sample phase: the sample/hold element is charged to the desired voltage. The
charging time depends on capacitor value (internal or external, selected by the user).
The sampling time is configured with the TSAMPLEx[9:0] bits in DAC_SHSRx register.
During the write of the TSAMPLEx[9:0] bits, the BWSTx bit in DAC_SR register is set to
1 to synchronize between both clocks domains (APB and low speed clock) and
allowing the software to change the value of sample phase during the DAC channel
operation
2. Hold phase: the DAC output channel is tri-stated, the DAC core and the buffer are
turned off, to reduce the current consumption. The hold time is configured with the
THOLDx[9:0] bits in DAC_SHHR register
3. Refresh phase: the refresh time is configured with the TREFRESHx[7:0] bits in
DAC_SHRR register
The timings for the three phases above are in units of LSI clock periods. As an example, to
configure a sample time of 350 µs, a hold time of 2 ms and a refresh time of 100 µs
assuming LSI ~32 KHz is selected:
12 cycles are required for sample phase: TSAMPLEx[9:0] = 11,
62 cycles are required for hold phase: THOLDx[9:0] = 62,
and 4 cycles are required for refresh period: TREFRESHx[7:0] = 4.

RM0438 Rev 7 807/2194

834
Digital-to-analog converter (DAC) RM0438

In this example, the power consumption is reduced by almost a factor of 15 versus Normal
modes.
The formulas to compute the right sample and refresh timings are described in the table
below, the Hold time depends on the leakage current.

Table 178. Sample and refresh timings

Buffer
State
tSAMP(1)(2) tREFRESH(2)(3)

Enable 7 μs + (10*RBON*CSH) 7 μs + (RBON*CSH)*ln(2*NLSB)

Disable 3 μs + (10*RBOFF*CSH) 3 μs + (RBOFF*CSH)*ln(2*NLSB)
1. In the above formula the settling to the desired code value with ½ LSB or accuracy requires 10 constant
time for 12 bits resolution. For 8 bits resolution, the settling time is 7 constant time.
2. CSH is the capacitor in Sample and hold mode.
3. The tolerated voltage drop during the hold phase “Vd” is represented by the number of LSBs after the
capacitor discharging with the output leakage current. The settling back to the desired value with ½ LSB
error accuracy requires ln(2*Nlsb) constant time of the DAC.

Example of the sample and refresh time calculation with output buffer on
The values used in the example below are provided as indication only. Please refer to the
product datasheet for product data.
CSH = 100 nF
VDDA= 3.0 V
Sampling phase:
tSAMP = 7 μs + (10 * 2000 * 100 * 10-9) = 2.007 ms
(where RBON = 2 kΩ)
Refresh phase:
tREFRESH = 7 μs + (2000 * 100 * 10-9) * ln(2*10) = 606.1 μs
(where NLSB = 10 (10 LSB drop during the hold phase)
Hold phase:
Dv = ileak * thold / CSH = 0.0073 V (10 LSB of 12bit at 3 V)
ileak = 150 nA (worst case on the IO leakage on all the temperature range)
thold = 0.0073 * 100 * 10-9 / (150 * 10-9) = 4.867 ms

808/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Figure 169. DAC Sample and hold mode phase diagram

V1
Vd
V2

t
Sampling phase Hold phase Refresh Sampling phase
LSI phase

t
DAC

ON ON ON
MSv40462V2

Like in Normal mode, the Sample and hold mode has different configurations.
To enable the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:
• 100: DAC is connected to the external pin
• 101: DAC is connected to external pin and to on chip peripherals
To disabled the output buffer, MODEx[2:0] bits in DAC_MCR register must be set to:
• 110: DAC is connected to external pin and to on chip peripherals
• 111: DAC is connected to on chip peripherals
When MODEx[2:0] bits are equal to 111, an internal capacitor, CLint, holds the voltage
output of the DAC core and then drive it to on-chip peripherals.
All Sample and hold phases are interruptible, and any change in DAC_DHRx immediately
triggers a new sample phase.

Table 179. Channel output modes summary

MODEx[2:0] Mode Buffer Output connections

0 0 0 Connected to external pin

Enabled Connected to external pin and to on chip-peripherals (such as
0 0 1
Normal mode comparators)
0 1 0 Connected to external pin
Disabled
0 1 1 Connected to on chip peripherals (such as comparators)

RM0438 Rev 7 809/2194

834
Digital-to-analog converter (DAC) RM0438

Table 179. Channel output modes summary (continued)

MODEx[2:0] Mode Buffer Output connections

1 0 0 Connected to external pin

Enabled Connected to external pin and to on chip peripherals (such as
1 0 1
Sample and comparators)
hold mode Connected to external pin and to on chip peripherals (such as
1 1 0
Disabled comparators)
1 1 1 Connected to on chip peripherals (such as comparators)

22.4.11 DAC channel buffer calibration

The transfer function for an N-bit digital-to-analog converter (DAC) is:

V = ( ( D ⁄ 2N – 1 ) × G × V )+V
out ref OS
Where VOUT is the analog output, D is the digital input, G is the gain, Vref is the nominal full-
scale voltage, and Vos is the offset voltage. For an ideal DAC channel, G = 1 and Vos = 0.
Due to output buffer characteristics, the voltage offset may differ from part-to-part and
introduce an absolute offset error on the analog output. To compensate the Vos, a calibration
is required by a trimming technique.
The calibration is only valid when the DAC channelx is operating with buffer enabled
(MODEx[2:0] = 000b or 001b or 100b or 101b). if applied in other modes when the buffer is
off, it has no effect. During the calibration:
• The buffer output is disconnected from the pin internal/external connections and put in
tristate mode (HiZ).
• The buffer acts as a comparator to sense the middle-code value 0x800 and compare it
to VREF+/2 signal through an internal bridge, then toggle its output signal to 0 or 1
depending on the comparison result (CAL_FLAGx bit).
Two calibration techniques are provided:
• Factory trimming (default setting)
The DAC buffer offset is factory trimmed. The default value of OTRIMx[4:0] bits in
DAC_CCR register is the factory trimming value and it is loaded once DAC digital
interface is reset.
• User trimming
The user trimming can be done when the operating conditions differs from nominal
factory trimming conditions and in particular when VDDA voltage, temperature, VREF+
values change and can be done at any point during application by software.
Note: Refer to the datasheet for more details of the Nominal factory trimming conditions
In addition, when VDD is removed (example the device enters in STANDBY or VBAT modes)
the calibration is required.
The steps to perform a user trimming calibration are as below:

810/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

1. If the DAC channel is active, write 0 to ENx bit in DAC_CR to disable the channel.
2. Select a mode where the buffer is enabled, by writing to DAC_MCR register,
MODEx[2:0] = 000b or 001b or 100b or 101b.
3. Start the DAC channelx calibration, by setting the CENx bit in DAC_CR register to 1.
4. Apply a trimming algorithm:
a) Write a code into OTRIMx[4:0] bits, starting by 00000b.
b) Wait for tTRIM delay.
c) Check if CAL_FLAGx bit in DAC_SR is set to 1.
d) If CAL_FLAGx is set to 1, the OTRIMx[4:0] trimming code is found and can be
used during device operation to compensate the output value, else increment
OTRIMx[4:0] and repeat sub-steps from (a) to (d) again.
The software algorithm may use either a successive approximation or dichotomy techniques
to compute and set the content of OTRIMx[4:0] bits in a faster way.
The commutation/toggle of CAL_FLAGx bit indicates that the offset is correctly
compensated and the corresponding trim code must be kept in the OTRIMx[4:0] bits in
DAC_CCR register.
Note: A tTRIM delay must be respected between the write to the OTRIMx[4:0] bits and the read of
the CAL_FLAGx bit in DAC_SR register in order to get a correct value.This parameter is
specified into datasheet electrical characteristics section.
If VDDA, VREF+ and temperature conditions do not change during device operation while it
enters more often in standby and VBAT mode, the software may store the OTRIMx[4:0] bits
found in the first user calibration in the flash or in back-up registers. then to load/write them
directly when the device power is back again thus avoiding to wait for a new calibration time.
When CENx bit is set, it is not allowed to set ENx bit.

22.4.12 Dual DAC channel conversion modes (if dual channels are
available)
To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time. For
the wave generation, no accesses to DHRxxxD registers are required. As a result, two
output channels can be used either independently or simultaneously.
11 conversion modes are possible using the two DAC channels and these dual registers. All
the conversion modes can nevertheless be obtained using separate DHRx registers if
needed.
All modes are described in the paragraphs below.

Independent trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).

RM0438 Rev 7 811/2194

834
Digital-to-analog converter (DAC) RM0438

When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three APB1 clock cycles later).

Independent trigger with single LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value
in the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). Then the LFSR2 counter is updated.

Independent trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.

812/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Independent trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value in the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then
updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same
triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then
updated.

Independent trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure different trigger sources by setting different values in the TSEL1 and TSEL2
bits.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle
amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is
transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle
counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle
amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is
transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle
counter is then updated.

Simultaneous software start

To configure the DAC in this conversion mode, the following sequence is required:
• Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are
transferred into DAC_DOR1 and DAC_DOR2, respectively.

Simultaneous trigger without wave generation

To configure the DAC in this conversion mode, the following sequence is required:

RM0438 Rev 7 813/2194

834
Digital-to-analog converter (DAC) RM0438

1. Set the two DAC channel trigger enable bits TEN1 and TEN2.
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three APB1 clock cycles).

Simultaneous trigger with single LFSR generation

1. To configure the DAC in this conversion mode, the following sequence is required:
2. Set the two DAC channel trigger enable bits TEN1 and TEN2.
3. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
4. Configure the two DAC channel WAVEx[1:0] bits as 01 and the same LFSR mask value
in the MAMPx[3:0] bits.
5. Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD).
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1
register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,
is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1
clock cycles later). The LFSR2 counter is then updated.

Simultaneous trigger with different LFSR generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 01 and set different LFSR mask
values using the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is
added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock
cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). The LFSR2 counter is then updated.

Simultaneous trigger with single triangle generation

To configure the DAC in this conversion mode, the following sequence is required:

814/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and the same maximum
amplitude value using the MAMPx[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle
amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.

Simultaneous trigger with different triangle generation

To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.

22.5 DAC low-power modes

Table 180. Effect of low-power modes on DAC
Mode Description

Sleep No effect, DAC used with DMA

Low-power run No effect.
Low-power sleep No effect. DAC used with DMA.
DAC remains active with a static value, if Sample and hold mode is
Stop 0 / Stop 1
selected using LSI clock
The DAC registers content is kept. The DAC must be disabled before
Stop 2
entering Stop 2.

RM0438 Rev 7 815/2194

834
Digital-to-analog converter (DAC) RM0438

Table 180. Effect of low-power modes on DAC (continued)

Mode Description

Standby The DAC peripheral is powered down and must be reinitialized after exiting
Shutdown Standby or Shutdown mode.

22.6 DAC interrupts

Table 181. DAC interrupts
Interrupt Interrupt Enable Interrupt clear Exit Sleep Exit Stop Exit Standby
Event flag
acronym event control bit method mode mode mode

DMA DMAUDRI Write

DAC DMAUDRx Yes No No
underrun Ex DMAUDRx = 1

816/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.7 DAC registers

Refer to Section 1 on page 76 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32-bit).

22.7.1 DAC control register (DAC_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMAU DMAE
Res. CEN2 MAMP2[3:0] WAVE2[1:0] TSEL2[3] TSEL2[2] TSEL2[1] TSEL2[0] TEN2 EN2
DRIE2 N2
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAU DMAE
HFSEL CEN1 MAMP1[3:0] WAVE1[1:0] TSEL1[3] TSEL1[2] TSEL1[1] TSEL1[0] TEN1 EN1
DRIE1 N1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 CEN2: DAC channel2 calibration enable
This bit is set and cleared by software to enable/disable DAC channel2 calibration, it can be
written only if EN2 bit is set to 0 into DAC_CR (the calibration mode can be entered/exit only
when the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel2 in Normal operating mode
1: DAC channel2 in calibration mode
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
This bit is set and cleared by software.
0: DAC channel2 DMA underrun interrupt disabled
1: DAC channel2 DMA underrun interrupt enabled
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.

RM0438 Rev 7 817/2194

834
Digital-to-analog converter (DAC) RM0438

Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector

These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 21:18 TSEL2[3:0]: DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
0000: SWTRIG2
0001: dac_ch2_trg1
0010: dac_ch2_trg2
...
1111: dac_ch2_trg15
Refer to the trigger selection tables in Section 22.4.6: DAC trigger selection for details on
trigger configuration and mapping.
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 17 TEN2: DAC channel2 trigger enable
This bit is set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into the DAC_DHR2 register are
transferred one APB1 clock cycle later to the DAC_DOR2 register
1: DAC channel2 trigger enabled and data from the DAC_DHR2 register are transferred
three APB1 clock cycles later to the DAC_DOR2 register
Note: When software trigger is selected, the transfer from the DAC_DHR2 register to the
DAC_DOR2 register takes only one APB1 clock cycle.
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.

818/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Bit 16 EN2: DAC channel2 enable

This bit is set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
Note: These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 15 HFSEL: High frequency interface mode enable
This bit is set and cleared by software to enable/disable DAC interface high speed mode
This bit need to be set when APB1 clock frequency is higher than 80 MHz.
0: High frequency interface mode disabled
1: High frequency interface mode enabled
Bit 14 CEN1: DAC channel1 calibration enable
This bit is set and cleared by software to enable/disable DAC channel1 calibration, it can be
written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when
the DAC channel is disabled) Otherwise, the write operation is ignored.
0: DAC channel1 in Normal operating mode
1: DAC channel1 in calibration mode
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set and cleared by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).

RM0438 Rev 7 819/2194

834
Digital-to-analog converter (DAC) RM0438

Bits 5:2 TSEL1[3:0]: DAC channel1 trigger selection

These bits select the external event used to trigger DAC channel1
0000: SWTRIG1
0001: dac_ch1_trg1
0010: dac_ch1_trg2
...
1111: dac_ch1_trg15
Refer to the trigger selection tables in Section 22.4.6: DAC trigger selection for details on
trigger configuration and mapping.
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bit 1 TEN1: DAC channel1 trigger enable
This bit is set and cleared by software to enable/disable DAC channel1 trigger.
0: DAC channel1 trigger disabled and data written into the DAC_DHR1 register are
transferred one APB1 clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHR1 register are transferred
three APB1 clock cycles later to the DAC_DOR1 register
Note: When software trigger is selected, the transfer from the DAC_DHR1 register to the
DAC_DOR1 register takes only one APB1 clock cycle.
Bit 0 EN1: DAC channel1 enable
This bit is set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled

22.7.2 DAC software trigger register (DAC_SWTRGR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SWTRIG2 SWTRIG1
w w

820/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2 register.
This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set by software to trigger the DAC in software trigger mode.
0: No trigger
1: Trigger
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.

22.7.3 DAC channel1 12-bit right-aligned data holding register

(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel1.

22.7.4 DAC channel1 12-bit left aligned data holding register

(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 821/2194

834
Digital-to-analog converter (DAC) RM0438

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software.
They specify 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.

22.7.5 DAC channel1 8-bit right aligned data holding register

(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. DACC1DHR[7:0]
rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software. They specify 8-bit data for DAC channel1.

22.7.6 DAC channel2 12-bit right aligned data holding register

(DAC_DHR12R2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software. They specify 12-bit data for DAC channel2.

822/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.7.7 DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved, must be kept at reset value.

22.7.8 DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. DACC2DHR[7:0]
rw rw rw rw rw rw rw rw

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.

RM0438 Rev 7 823/2194

834
Digital-to-analog converter (DAC) RM0438

22.7.9 Dual DAC 12-bit right-aligned data holding register

(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. DACC2DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC1DHR[11:0]
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.

22.7.10 Dual DAC 12-bit left aligned data holding register

(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DACC2DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC1DHR[11:0] Res. Res. Res. Res.
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data

These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.

824/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.7.11 Dual DAC 8-bit right aligned data holding register

(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DACC2DHR[7:0] DACC1DHR[7:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.

22.7.12 DAC channel1 data output register (DAC_DOR1)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC1DOR[11:0]
r r r r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.

RM0438 Rev 7 825/2194

834
Digital-to-analog converter (DAC) RM0438

22.7.13 DAC channel2 data output register (DAC_DOR2)

This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. DACC2DOR[11:0]
r r r r r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.

22.7.14 DAC status register (DAC_SR)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CAL_ DMAU
BWST2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FLAG2 DR2
r r rc_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL_ DMAU
BWST1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
FLAG1 DR1
r r rc_w1

826/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Bit 31 BWST2: DAC channel2 busy writing sample time flag

This bit is systematically set just after Sample and hold mode enable. It is set each time the
software writes the register DAC_SHSR2, It is cleared by hardware when the write operation
of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR2 ongoing: DAC_SHSR2 can be written
1:There is a write operation of DAC_SHSR2 ongoing: DAC_SHSR2 cannot be written
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 30 CAL_FLAG2: DAC channel2 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel2
1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
driving DAC channel2 conversion at a frequency higher than the DMA service capability
rate).
Note: This bit is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bit 28 Reserved, must be kept at reset value.
Bit 27 Reserved, must be kept at reset value.
Bits 26:16 Reserved, must be kept at reset value.
Bit 15 BWST1: DAC channel1 busy writing sample time flag
This bit is systematically set just after Sample and hold mode enable and is set each time the
software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of
DAC_SHSR1 is complete. (It takes about 3 LSI periods of synchronization).
0:There is no write operation of DAC_SHSR1 ongoing: DAC_SHSR1 can be written
1:There is a write operation of DAC_SHSR1 ongoing: DAC_SHSR1 cannot be written
Bit 14 CAL_FLAG1: DAC channel1 calibration offset status
This bit is set and cleared by hardware
0: calibration trimming value is lower than the offset correction value
1: calibration trimming value is equal or greater than the offset correction value
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bit 12 Reserved, must be kept at reset value.
Bit 11 Reserved, must be kept at reset value.
Bits 10:0 Reserved, must be kept at reset value.

RM0438 Rev 7 827/2194

834
Digital-to-analog converter (DAC) RM0438

22.7.15 DAC calibration control register (DAC_CCR)

Address offset: 0x38
Reset value: 0x00XX 00XX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM2[4:0]
rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OTRIM1[4:0]
rw rw rw rw rw

Bits 31:21 Reserved, must be kept at reset value.

Bits 20:16 OTRIM2[4:0]: DAC channel2 offset trimming value
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 15:5 Reserved, must be kept at reset value.
Bits 4:0 OTRIM1[4:0]: DAC channel1 offset trimming value

22.7.16 DAC mode control register (DAC_MCR)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE2[2:0]

rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MODE1[2:0]

rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bit 25 Reserved, must be kept at reset value.
Bit 24 Reserved, must be kept at reset value.
Bits 23:19 Reserved, must be kept at reset value.

828/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

Bits 18:16 MODE2[2:0]: DAC channel2 mode

These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write
operation is ignored.
They can be set and cleared by software to select the DAC channel2 mode:
– DAC channel2 in Normal mode
000: DAC channel2 is connected to external pin with Buffer enabled
001: DAC channel2 is connected to external pin and to on chip peripherals with buffer
enabled
010: DAC channel2 is connected to external pin with buffer disabled
011: DAC channel2 is connected to on chip peripherals with Buffer disabled
– DAC channel2 in Sample and hold mode
100: DAC channel2 is connected to external pin with Buffer enabled
101: DAC channel2 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel2 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel2 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN2=0.
Refer to Section 22.3: DAC implementation for the availability of DAC channel2.
Bits 15:14 Reserved, must be kept at reset value.
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 Reserved, must be kept at reset value.
Bit 8 Reserved, must be kept at reset value.
Bits 7:3 Reserved, must be kept at reset value.
Bits 2:0 MODE1[2:0]: DAC channel1 mode
These bits can be written only when the DAC is disabled and not in the calibration mode
(when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write
operation is ignored.
They can be set and cleared by software to select the DAC channel1 mode:
– DAC channel1 in Normal mode
000: DAC channel1 is connected to external pin with Buffer enabled
001: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
010: DAC channel1 is connected to external pin with Buffer disabled
011: DAC channel1 is connected to on chip peripherals with Buffer disabled
– DAC channel1 in sample & hold mode
100: DAC channel1 is connected to external pin with Buffer enabled
101: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
enabled
110: DAC channel1 is connected to external pin and to on chip peripherals with Buffer
disabled
111: DAC channel1 is connected to on chip peripherals with Buffer disabled
Note: This register can be modified only when EN1=0.

RM0438 Rev 7 829/2194

834
Digital-to-analog converter (DAC) RM0438

22.7.17 DAC channel1 sample and hold sample time register

(DAC_SHSR1)
Address offset: 0x40
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. TSAMPLE1[9:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 TSAMPLE1[9:0]: DAC channel1 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel1 is disabled or also during normal operation.
in the latter case, the write can be done only when BWST1 of DAC_SR register is low, If
BWST1=1, the write operation is ignored.

Note: It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.

22.7.18 DAC channel2 sample and hold sample time register

(DAC_SHSR2)
This register is available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Address offset: 0x44
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. TSAMPLE2[9:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:10 Reserved, must be kept at reset value.

Bits 9:0 TSAMPLE2[9:0]: DAC channel2 sample time (only valid in Sample and hold mode)
These bits can be written when the DAC channel2 is disabled or also during normal
operation. in the latter case, the write can be done only when BWST2 of DAC_SR register is
low, if BWST2=1, the write operation is ignored.

Note: It represents the number of LSI clocks to perform a sample phase. Sampling time =
(TSAMPLE1[9:0] + 1) x LSI clock period.

830/2194 RM0438 Rev 7

RM0438 Digital-to-analog converter (DAC)

22.7.19 DAC sample and hold time register (DAC_SHHR)

Address offset: 0x48
Reset value: 0x0001 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. THOLD2[9:0]
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. THOLD1[9:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved, must be kept at reset value.

Bits 25:16 THOLD2[9:0]: DAC channel2 hold time (only valid in Sample and hold mode).
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 15:10 Reserved, must be kept at reset value.
Bits 9:0 THOLD1[9:0]: DAC channel1 hold time (only valid in Sample and hold mode)
Hold time= (THOLD[9:0]) x LSI clock period
Note: This register can be modified only when EN1=0.

Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.

22.7.20 DAC sample and hold refresh time register (DAC_SHRR)

Address offset: 0x4C
Reset value: 0x0001 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. TREFRESH2[7:0]
rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. TREFRESH1[7:0]
rw rw rw rw rw rw rw rw

RM0438 Rev 7 831/2194

834
Digital-to-analog converter (DAC) RM0438

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 TREFRESH2[7:0]: DAC channel2 refresh time (only valid in Sample and hold mode)
Refresh time= (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN2=0.
These bits are available only on dual-channel DACs. Refer to Section 22.3: DAC
implementation.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 TREFRESH1[7:0]: DAC channel1 refresh time (only valid in Sample and hold mode)
Refresh time= (TREFRESH[7:0]) x LSI clock period
Note: This register can be modified only when EN1=0.

Note: These bits can be written only when the DAC channel is disabled and in Normal operating
mode (when bit ENx=0 and bit CENx=0 in the DAC_CR register). If ENx=1 or CENx=1 the
write operation is ignored.

832/2194 RM0438 Rev 7

 0x34
0x30
0x28
0x24
0x20
0x18
0x14
0x10
0x08
0x04
0x00

0x2C
0x1C
0x0C
Offset
RM0438

22.7.21

DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_

DOR2
DOR1
name

DHR8R2
DHR8R1

DAC_SR
DHR8RD
DAC_CR

SWTRGR

DHR12L2
DHR12L1

DHR12R2
DHR12R1

DHR12LD
DHR12RD
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

0
0
BWST2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
CAL_FLAG2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CEN2 30

0
0
0
DMAUDR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAUDRIE2 29

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAEN2 28

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26
MAMP2[3:0]

0
0
0
DAC register map

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

DACC2DHR[11:0]

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 23
WAVE2[2:0]

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 22

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL23 21

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL22 20

DACC2DHR[11:0]

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL21 19
Table 182 summarizes the DAC registers.

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TSEL20 18

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TEN2 17

RM0438 Rev 7
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EN2 16

0
0
0

0
0
0
BWST1 Res. Res. Res. Res. Res. Res. Res. Res. HFSEL 15

0
0
0

0
0
0
CAL_FLAG1 Res. Res. Res. Res. Res. Res. Res. Res. CEN1 14

0
0
0

0
0
0

DMAUDR1 Res. Res. Res. Res. Res. Res. Res. Res. DMAUDRIE1 13

0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. DMAEN1 12

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. 11

0
0
0

0
0
0
0
0
0
0
Table 182. DAC register map and reset values

Res. Res. Res. Res. 10

DACC2DHR[7:0]
MAMP1[3:0]

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. 9

0
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. 8

DACC1DHR[11:0]
DACC2DHR[11:0]
DACC1DHR[11:0]

0
0

0
0
0
0
0

0
0
0

0
0

Res. Res. 7
WAVE1[1:0]

0
0
0

0
0
0
0
0

0
0
0
0

Res. Res. 6

0
0
0

0
0
0
0
0

0
0
0
0

Res. Res. TSEL13 5

0
0
0

0
0
0
0
0
0

0
0
0

Res. Res. TSEL12 4

DACC1DHR[11:0]
DACC2DHR[11:0]
DACC1DHR[11:0]

DACC2DOR[11:0]
DACC1DOR[11:0]
0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. TSEL11 3

0
0

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. TSEL10 2

DACC1DHR[7:0]
DACC2DHR[7:0]
DACC1DHR[7:0]

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. SWTRIG2 TEN1 1

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. SWTRIG1 EN1 0

833/2194
Digital-to-analog converter (DAC)

834
 0x48
0x44
0x40
0x38

0x4C
0x3C
Offset

834/2194
DAC_
DAC_
DAC_
DAC_

SHRR
SHHR
SHSR2
SHSR1
name

DAC_CCR

DAC_MCR
Register

Reset value
Reset value
Reset value
Reset value
Reset value

Reset value
Res. Res. Res. Res. Res. Res. 31
Res. Res. Res. Res. Res. Res. 30
Res. Res. Res. Res. Res. Res. 29
Res. Res. Res. Res. Res. Res. 28
Res. Res. Res. Res. Res. Res. 27
Res. Res. Res. Res. Res. Res. 26

0
Digital-to-analog converter (DAC)

Res. Res. Res. Res. Res. 25

0
Res. Res. Res. Res. Res. 24

0
0
Res. Res. Res. Res. 23

0
0
Res. Res. Res. Res. 22

0
0
Res. Res. Res. Res. 21

0
0
X

Res. Res. Res. 20

THOLD2[9:0]

0
0
X

Res. Res. Res. 19

0
0

0
X

Res. Res. 18
TREFRESH2[7:0]

0
0

0
X

Res. Res. 17
[2:0]
OTRIM2[4:0]

RM0438 Rev 7
MODE2

1
0

1
X

Res. Res. 16
Res. Res. Res. Res. Res. Res. 15
Res. Res. Res. Res. Res. Res. 14
Res. Res. Res. Res. Res. Res. 13
Res. Res. Res. Res. Res. Res. 12
Res. Res. Res. Res. Res. Res. 11
Res. Res. Res. Res. Res. Res. 10
0
0
0

Res. Res. Res. 9

0
0
0

Refer to Section 2.3 on page 87 for the register boundary addresses.

Res. Res. Res. 8

Table 182. DAC register map and reset values (continued)

0
0
0
0

Res. Res. 7
0
0
0
0

Res. Res. 6
0
0
0
0

Res. Res. 5
0
0
0
0
X

Res. 4
0
0
0
0
X

THOLD1[9:0]

Res. 3
TSAMPLE2[9:0]
TSAMPLE1[9:0]

0
0
0

0
0
X

2
TREFRESH1[7:0]

0
0
0

0
0
X

1
[2:0]
OTRIM1[4:0]

MODE1

1
1
0

0
0
X

0
RM0438
RM0438 Voltage reference buffer (VREFBUF)

23 Voltage reference buffer (VREFBUF)

23.1 Introduction
The devices embed a voltage reference buffer which can be used as voltage reference for
ADCs, DACs and also as voltage reference for external components through the VREF+
pin. When the VREF+ pin is double-bonded with VDDA pin in a package, the voltage
reference buffer is not available and must be kept disabled (refer to datasheet for packages
pinout description).

23.2 VREFBUF functional description

The internal voltage reference buffer supports two voltages(a), which are configured with
VRS bits in the VREFBUF_CSR register:
• VRS = 0: VREF_OUT1 around 2.048 V.
• VRS = 1: VREF_OUT2 around 2.5 V.
The internal voltage reference can be configured in four different modes depending on
ENVR and HIZ bits configuration. These modes are provided in the table below:

Table 183. VREF buffer modes

ENVR HIZ VREF buffer configuration

VREFBUF buffer off mode:

0 0
– VREF+ pin pulled-down to VSSA
External voltage reference mode (default value):
0 1 – VREFBUF buffer off
– VREF+ pin input mode
Internal voltage reference mode:
1 0 – VREFBUF buffer on
– VREF+ pin connected to VREFBUF buffer output
Hold mode:
– VREFBUF buffer off
1 1
– VREF+ pin floating. The voltage is held with the external capacitor
– VRR detection disabled and VRR bit keeps last state

After enabling the VREFBUF by setting ENVR bit and clearing HIZ bit in the VREFBUF_CSR register,
the user must wait until VRR bit is set, meaning that the voltage reference output has reached its
expected value.

23.3 VREFBUF trimming

The VREFBUF output voltage is factory-calibrated by ST. For the VRS = 1 setting, the
calibration data is automatically loaded to the TRIM register at reset. For the VRS = 0

a. The minimum VDDA voltage depends on VRS setting, refer to the product datasheet.

RM0438 Rev 7 835/2194

838
Voltage reference buffer (VREFBUF) RM0438

setting, the software must take care of copying the calibration data from the read-only
system memory area (Flash memory) to the TRIM register.
Optionally user can trim the output voltage by changing the TRIM register bits.

Table 184. VREFBUF trimming data

Calibration value name Description Memory address

VREF_SC0 VREFBUF trimming value for VRS = 0 0x0BFA 0579

VREF_SC1 VREFBUF trimming value for VRS = 1 0x0BFA 0530

836/2194 RM0438 Rev 7

RM0438 Voltage reference buffer (VREFBUF)

23.4 VREFBUF registers

23.4.1 VREFBUF control and status register (VREFBUF_CSR)

Address offset: 0x00
Reset value: 0x0000 0002

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VRR VRS HIZ ENVR
r rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 VRR: Voltage reference buffer ready
0: the voltage reference buffer output is not ready.
1: the voltage reference buffer output reached the requested level.
Bit 2 VRS: Voltage reference scale
This bit selects the value generated by the voltage reference buffer.
0: Voltage reference set to VREF_OUT1 (around 2.048 V).
1: Voltage reference set to VREF_OUT2 (around 2.5 V).
Bit 1 HIZ: High impedance mode
This bit controls the analog switch to connect or not the VREF+ pin.
0: VREF+ pin is internally connected to the voltage reference buffer output.
1: VREF+ pin is high impedance.
Refer to Table 183: VREF buffer modes for the mode descriptions depending on ENVR bit
configuration.
Bit 0 ENVR: Voltage reference buffer mode enable
This bit is used to enable the voltage reference buffer mode.
0: Internal voltage reference mode disable (external voltage reference mode).
1: Internal voltage reference mode (reference buffer enable or hold mode) enable.

RM0438 Rev 7 837/2194

838
Voltage reference buffer (VREFBUF) RM0438

23.4.2 VREFBUF calibration control register (VREFBUF_CCR)

Address offset: 0x04
Reset value: 0x0000 00XX

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TRIM[5:0]
rw rw rw rw rw rw

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 TRIM[5:0]: Trimming code
For VRS = 1 (2.5 V), these bits are automatically initialized after reset with the trimming
value stored in the Flash memory during the production test.
For VRS = 0 (2.048V), the software must take care of copying the calibration data from the
read-only system memory area (Flash memory) to the TRIM[5:0] bitfield. Writing into these
bits allows the tuning of the internal reference buffer voltage.
Note: If the user application performs the trimming, the trimming code should start from
000000 to 111111 in ascending order.

23.4.3 VREFBUF register map

The following table gives the VREFBUF register map and the reset values.

Table 185. VREFBUF register map and reset values

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0 ENVR
VRR
VRS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

HIZ
VREFBUF_CSR
0x00
Reset value 0 0 1 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

VREFBUF_CCR TRIM[5:0]
0x04
Reset value x x x x x x

Refer to Section 2.3 on page 87 for the register boundary addresses.

838/2194 RM0438 Rev 7

RM0438 Comparator (COMP)

24 Comparator (COMP)

24.1 Introduction
The device embeds two ultra-low-power comparators COMP1, and COMP2
The comparators can be used for a variety of functions including:
• Wakeup from low-power mode triggered by an analog signal,
• Analog signal conditioning,
• Cycle-by-cycle current control loop when combined with a PWM output from a timer.

24.2 COMP main features

• Each comparator has configurable plus and minus inputs used for flexible voltage
selection:
– Multiplexed I/O pins
– DAC Channel1 and Channel2
– Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by
scaler (buffered voltage divider)
• Programmable hysteresis
• Programmable speed / consumption
• The outputs can be redirected to an I/O or to timer inputs for triggering:
– Break events for fast PWM shutdowns
• Comparator outputs with blanking source
• The two comparators can be combined in a window comparator
• Each comparator has interrupt generation capability with wakeup from Sleep and Stop
modes (through the EXTI controller)

RM0438 Rev 7 839/2194

850
Comparator (COMP) RM0438

24.3 COMP functional description

24.3.1 COMP block diagram

The block diagram of the comparators is shown in Figure 170.

Figure 170. Comparator block diagram

COMPx_INPSEL GPIO
alternate
function
COMPx_POL COMPx_OUT
COMPx_INP
COMPx_INP I/Os +
COMPx
COMPx_ COMPx_INM COMPx_VALUE Wakeup EXTI line
INMSEL - interrupt

COMPx_INM I/Os Polarity selection

DAC_CH1 TIMERS
DAC_CH2
VREFINT
3/4 VREFINT
1/2 VREFINT
1/4 VREFINT
MS34498V1

24.3.2 COMP pins and internal signals

The I/Os used as comparators inputs must be configured in analog mode in the GPIOs
registers.
The comparator output can be connected to the I/Os using the alternate function channel
given in “Alternate function mapping” table in the datasheet.
The output can also be internally redirected to a variety of timer input for the following
purposes:
• Emergency shut-down of PWM signals, using BKIN and BKIN2 inputs
• Cycle-by-cycle current control, using OCREF_CLR inputs
• Input capture for timing measures
It is possible to have the comparator output simultaneously redirected internally and
externally.

Table 186. COMP1 input plus assignment

COMP1_INP COMP1_INPSEL [1:0]

PC5 00
PB2 01
PA2 10

840/2194 RM0438 Rev 7

RM0438 Comparator (COMP)

Table 187. COMP1 input minus assignment

COMP1_INM COMP1_INMSEL[2:0]

¼ VREFINT 000
½ VREFINT 001
¾ VREFINT 010
VREFINT 011
DAC Channel1 100
DAC Channel2 101
PB1 110
PC4 111

Table 188. COMP2 input plus assignment

COMP2_INP COMP2_INPSEL

PB4 0
PB6 1

Table 189. COMP2 input minus assignment

COMP2_INM COMP2_INMSEL[2:0]

¼ VREFINT 000
½ VREFINT 001
¾ VREFINT 010
VREFINT 011
DAC Channel1 100
DAC Channel2 101
PB3 110
PB7 111

24.3.3 COMP reset and clocks

The COMP clock provided by the clock controller is synchronous with the APB2 clock.
There is no clock enable control bit provided in the RCC controller. Reset and clock enable
bits are common for COMP and SYSCFG.
Important: The polarity selection logic and the output redirection to the port works
independently from the APB2 clock. This allows the comparator to work even in Stop mode.

24.3.4 Comparator LOCK mechanism

The comparators can be used for safety purposes, such as over-current or thermal
protection. For applications having specific functional safety requirements, it is necessary to

RM0438 Rev 7 841/2194

850
Comparator (COMP) RM0438

insure that the comparator programming cannot be altered in case of spurious register
access or program counter corruption.
For this purpose, the comparator control and status registers can be write-protected (read-
only).
Once the programming is completed, the COMPx LOCK bit can be set to 1. This causes the
whole register to become read-only, including the COMPx LOCK bit.
The write protection can only be reset by a MCU reset.

24.3.5 Window comparator

The purpose of window comparator is to monitor the analog voltage if it is within specified
voltage range defined by lower and upper threshold.
Two embedded comparators can be utilized to create window comparator. The monitored
analog voltage is connected to the non-inverting (plus) inputs of comparators connected
together and the upper and lower threshold voltages are connected to the inverting (minus)
inputs of the comparators. Two non-inverting inputs can be connected internally together by
enabling WINMODE bit to save one IO for other purposes.

Figure 171. Window mode

COMPx_INPSEL

COMPx_INP
COMPx_INP I/Os +
COMPx
COMPx_INM
COMPx_INMSEL -

COMPx_INM I/Os

.
Internal sources .
.

WINMODE
COMPx_INPSEL
COMPy_INP
+
COMPy_INP I/Os
COMPy
COMPy_INM
COMPy_INMSEL -

COMPy_INM I/Os

.
Internal sources .
.
MS35329V1

24.3.6 Hysteresis
The comparator includes a programmable hysteresis to avoid spurious output transitions in
case of noisy signals. The hysteresis can be disabled if it is not needed (for instance when
exiting from low-power mode) to be able to force the hysteresis value using external
components.

842/2194 RM0438 Rev 7

RM0438 Comparator (COMP)

Figure 172. Comparator hysteresis

INP

INM
INM - Vhyst

COMP_OUT

MS19984V1

24.3.7 Comparator output blanking function

The purpose of the blanking function is to prevent the current regulation to trip upon short
current spikes at the beginning of the PWM period (typically the recovery current in power
switches anti parallel diodes).It consists of a selection of a blanking window which is a timer
output compare signal. The selection is done by software (refer to the comparator register
description for possible blanking signals). Then, the complementary of the blanking signal is
ANDed with the comparator output to provide the wanted comparator output. See the
example provided in the figure below.

Figure 173. Comparator output blanking

PWM

Current limit

Current

Raw comp output

Blanking window

Final comp output

Comp out
Comp out (to TIM_BK …)
Blank

MS30964V1

RM0438 Rev 7 843/2194

850
Comparator (COMP) RM0438

24.3.8 COMP power and speed modes

COMP1 and COMP2 power consumption versus propagation delay can be adjusted to have
the optimum trade-off for a given application.
The bits PWRMODE[1:0] in COMPx_CSR registers can be programmed as follows:
00: High speed / full power
01 or 10: Medium speed / medium power
11: Low speed / ultra-low-power

24.4 COMP low-power modes

Table 190. Comparator behavior in the low power modes
Mode Description

No effect on the comparators.

Sleep
Comparator interrupts cause the device to exit the Sleep mode.

Low-power run No effect.

Low-power sleep No effect. COMP interrupts cause the device to exit the Low-power sleep mode.

Stop 0

No effect on the comparators.

Stop 1
Comparator interrupts cause the device to exit the Stop mode.

Stop 2

Standby
The COMP registers are powered down and must be reinitialized after exiting
Standby or Shutdown mode.
Shutdown

24.5 COMP interrupts

The comparator outputs are internally connected to the Extended interrupts and events
controller. Each comparator has its own EXTI line and can generate either interrupts or
events. The same mechanism is used to exit from low-power modes.
Refer to Interrupt and events section for more details.
To enable COMPx interrupt, it is required to follow this sequence:
1. Configure and enable the EXTI line corresponding to the COMPx output event in
interrupt mode and select the rising, falling or both edges sensitivity
2. Configure and enable the NVIC IRQ channel mapped to the corresponding EXTI lines
3. Enable COMPx.

844/2194 RM0438 Rev 7

RM0438 Comparator (COMP)

Table 191. Interrupt control bits

Enable Exit from Exit from Exit from
Interrupt event Event flag
control bit Sleep mode Stop modes Standby mode

VALUE in
COMP1 output Through EXTI Yes Yes N/A
COMP1_CSR
VALUE in
COMP2 output Through EXTI Yes Yes N/A
COMP2_CSR

24.6 COMP registers

24.6.1 Comparator 1 control and status register (COMP1_CSR)
The COMP1_CSR is the Comparator 1 control/status register. It contains all the bits /flags
related to comparator1.
Address offset: 0x00
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCAL BRG
LOCK VALUE Res. Res. Res. Res. Res. Res. Res. BLANKING HYST
EN EN
rs r rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLA INP
Res. Res. Res. Res. Res. Res. INMSEL PWRMODE Res. EN
RITY SEL.
rw rw rw rw rw

Bit 31 LOCK: COMP1_CSR register lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 1 control register, COMP1_CSR[31:0].
0: COMP1_CSR[31:0] for comparator 1 are read/write
1: COMP1_CSR[31:0] for comparator 1 are read-only
Bit 30 VALUE: Comparator 1 output status bit
This bit is read-only. It reflects the current comparator 1 output taking into account
POLARITY bit effect.
Bits 29: Reserved, must be kept at reset value.
Bit 23 SCALEN: Voltage scaler enable bit
This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider
available on the minus input of the Comparator 1.
0: Bandgap scaler disable (if SCALEN bit of COMP2_CSR register is also reset)
1: Bandgap scaler enable

RM0438 Rev 7 845/2194

850
Comparator (COMP) RM0438

Bit 22 BRGEN: Scaler bridge enable

This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of
the scaler.
0: Scaler resistor bridge disable (if BRGEN bit of COMP2_CSR register is also reset)
1: Scaler resistor bridge enable
If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4 BGAP,
1/2 BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4 BGAP, 1/2 BGAP, 3/4 BGAP.
If SCALEN and BRGEN are set, 1/4 BGAP 1/2 BGAP 3/4 BGAP and BGAP voltage
references are available.
Bit 21 Reserved, must be kept at reset value
Bits 20:18 BLANKING[2:0]: Comparator 1 blanking source selection bits
These bits select which timer output controls the comparator 1 output blanking.
000: No blanking
001: TIM1 OC5 selected as blanking source
010: TIM2 OC3 selected as blanking source
100: TIM3 OC3 selected as blanking source
All other values: reserved
Bits 17:16 HYST[1:0]: Comparator 1 hysteresis selection bits
These bits are set and cleared by software (only if LOCK not set). They select the
hysteresis voltage of the comparator 1.
00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
Bit 15 POLARITY: Comparator 1 polarity selection bit
This bit is set and cleared by software (only if LOCK not set). It inverts Comparator 1
polarity.
0: Comparator 1 output value not inverted
1: Comparator 1 output value inverted
Bits 14:9 Reserved, must be kept at reset value.
Bits 8:7 INPSEL: Comparator1 input plus selection bit
This bit is set and cleared by software (only if LOCK not set).
00: PC5
01: PB2
10: PA2
11: Reserved
Bits 6:4 INMSEL: Comparator 1 input minus selection bits
These bits are set and cleared by software (only if LOCK not set). They select which input is
connected to the input minus of comparator 1.
000 = 1/4 VREFINT
001 = 1/2 VREFINT
010 = 3/4 VREFINT
011 = VREFINT
100 = DAC Channel1
101 = DAC Channel2
110 = PB1111 = PC4

846/2194 RM0438 Rev 7

RM0438 Comparator (COMP)

Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 1

These bits are set and cleared by software (only if LOCK not set). They control the
power/speed of the Comparator 1.
00: High speed
01 or 10: Medium speed
11: Ultra low power
Bit 1 Reserved, must be kept cleared.
Bit 0 EN: Comparator 1 enable bit
This bit is set and cleared by software (only if LOCK not set). It switches on Comparator1.
0: Comparator 1 switched OFF
1: Comparator 1 switched ON

24.6.2 Comparator 2 control and status register (COMP2_CSR)

The COMP2_CSR is the Comparator 2 control/status register. It contains all the bits /flags
related to comparator 2.
Address offset: 0x04
System reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SCAL BRG
LOCK VALUE Res. Res. Res. Res. Res. Res. Res. BLANKING HYST
EN EN
rs r rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
POLA WIN INP
Res. Res. Res. Res. Res. Res. INMSEL PWRMODE Res. EN
RITY MODE SEL
rw rw rw rw rw rw

Bit 31 LOCK: CSR register lock bit

This bit is set by software and cleared by a hardware system reset. It locks the whole
content of the comparator 2 control register, COMP2_CSR[31:0].
0: COMP2_CSR[31:0] for comparator 2 are read/write
1: COMP2_CSR[31:0] for comparator 2 are read-only
Bit 30 VALUE: Comparator 2 output status bit
This bit is read-only. It reflects the current comparator 2 output taking into account
POLARITY bit effect.
Bits 29: Reserved, must be kept at reset value
Bit 23 SCALEN: Voltage scaler enable bit
This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider
available on the minus input of the Comparator 2.
0: Bandgap scaler disable (if SCALEN bit of COMP1_CSR register is also reset)
1: Bandgap scaler enable

RM0438 Rev 7 847/2194

850
Comparator (COMP) RM0438

Bit 22 BRGEN: Scaler bridge enable

This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of
the scaler.
0: Scaler resistor bridge disable (if BRGEN bit of COMP1_CSR register is also reset)
1: Scaler resistor bridge enable
If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4 BGAP,
1/2 BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4 BGAP, 1/2 BGAP, 3/4 BGAP.
If SCALEN and BRGEN are set, 1/4 BGAP 1/2 BGAP 3/4 BGAP and BGAP voltage
references are available.
Bit 21 Reserved, must be kept at reset value
Bits 20:18 BLANKING[2:0]: Comparator 2 blanking source selection bits
These bits select which timer output controls the comparator 2 output blanking.
000: No blanking
001: TIM3 OC4 selected as blanking source
010: TIM8 OC5 selected as blanking source
100: TIM15 OC1 selected as blanking source
All other values: reserved
Bits 17:16 HYST[1:0]: Comparator 2 hysteresis selection bits
These bits are set and cleared by software (only if LOCK not set). Select the hysteresis
voltage of the comparator 2.
00: No hysteresis
01: Low hysteresis
10: Medium hysteresis
11: High hysteresis
Bit 15 POLARITY: Comparator 2 polarity selection bit
This bit is set and cleared by software (only if LOCK not set). It inverts Comparator 2
polarity.
0: Comparator 2 output value not inverted
1: Comparator 2 output value inverted
Bits 14:10 Reserved, must be kept at reset value.
Bit 9 WINMODE: Windows mode selection bit
This bit is set and cleared by software (only if LOCK not set). This bit selects the window
mode of the comparators. If set, both positive inputs of comparators will be connected
together.
0: Input plus of Comparator 2 is not connected to Comparator 1
1: Input plus of Comparator 2 is connected with input plus of Comparator 1
Bit 8 Reserved, must be kept at reset value.
Bit 7 INPSEL: Comparator 1 input plus selection bit
This bit is set and cleared by software (only if LOCK not set).
0: PB4
1: PB6

848/2194 RM0438 Rev 7

RM0438 Comparator (COMP)

Bits 6:4 INMSEL: Comparator 2 input minus selection bits

These bits are set and cleared by software (only if LOCK not set). They select which input is
connected to the input minus of comparator 2.
000 = 1/4 VREFINT
001 = 1/2 VREFINT
010 = 3/4 VREFINT
011 = VREFINT
100 = DAC Channel1
101 = DAC Channel2
110 = PB3
111 = PB7
Bits 3:2 PWRMODE[1:0]: Power Mode of the comparator 2
These bits are set and cleared by software (only if LOCK not set). They control the
power/speed of the Comparator 2.
00: High speed
01 or 10: Medium speed
11: Ultra low power
Bit 1 Reserved, must be kept cleared.
Bit 0 EN: Comparator 2 enable bit
This bit is set and cleared by software (only if LOCK not set). It switches oncomparator2.
0: Comparator 2 switched OFF
1: Comparator 2 switched ON

RM0438 Rev 7 849/2194

850
Comparator (COMP) RM0438

24.6.3 COMP register map

The following table summarizes the comparator registers.

Table 192. COMP register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
PWRMODE
POLARITY.
BLANKING
SCALEN
BRGEN.

INPSEL.

INMSEL
VALUE
LOCK

HYST
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
Res.
Res.

Res.
COMP1_CSR

EN
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PWRMODE
POLARITY.
BLANKING

WINMODE
SCALEN.
BRGEN.

INMSEL
INPSEL
VALUE

HYST.
LOCK

Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
Res.

Res.

Res.
COMP2_CSR

EN
0x04

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

850/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

25 Operational amplifiers (OPAMP)

25.1 Introduction
The device embeds two operational amplifiers with two inputs and one output each. The
three I/Os can be connected to the external pins, this enables any type of external
interconnections. The operational amplifier can be configured internally as a follower or as
an amplifier with a non-inverting gain ranging from 2 to 16.
The positive input can be connected to the internal DAC.
The output can be connected to the internal ADC.

25.2 OPAMP main features

• Rail-to-rail input and output voltage range
• Low input bias current (down to 1 nA)
• Low input offset voltage (1.5 mV after calibration, 3 mV with factory calibration)
• Low-power mode (current consumption reduced to 30 µA instead of 100 µA)
• Fast wakeup time (10 µs in normal mode, 30 µs in low-power mode)
• Gain bandwidth of 1.6 MHz

25.3 OPAMP functional description

The OPAMP has several modes.
Each OPAMP can be individually enabled, when disabled the output is high-impedance.
When enabled, it can be in calibration mode, all input and output of the OPAMP are then
disconnected, or in functional mode.
There are two functional modes, the low-power mode or the normal mode. In functional
mode the inputs and output of the OPAMP are connected as described in the
Section 25.3.3: Signal routing.

25.3.1 OPAMP reset and clocks

The operational amplifier clock is necessary for accessing the registers. When the
application does not need to have read or write access to those registers, the clock can be
switched off using the peripheral clock enable register (see OPAMPEN bit in Section 9.8.19:
RCC APB1 peripheral clock enable register 1 (RCC_APB1ENR1)).
The bit OPAEN enables and disables the OPAMP operation. The OPAMP registers
configurations should be changed before enabling the OPAEN bit in order to avoid spurious
effects on the output.
When the output of the operational amplifier is no more needed the operational amplifier can
be disabled to save power. All the configurations previously set (including the calibration)
are maintained while OPAMP is disabled.

RM0438 Rev 7 851/2194

863
Operational amplifiers (OPAMP) RM0438

25.3.2 Initial configuration

The default configuration of the operational amplifier is a functional mode where the three
IOs are connected to external pins. In the default mode the operational amplifier uses the
factory trimming values. See electrical characteristics section of the datasheet for factory
trimming conditions, usually the temperature is 30 °C and the voltage is 3 V. The trimming
values can be adjusted, see Section 25.3.5: Calibration for changing the trimming values.
The default configuration uses the normal mode, which provides the highest performance.
Bit OPALPM can be set in order to switch the operational amplifier to low-power mode and
reduced performance. Both normal and low-power mode characteristics are defined in the
section “electrical characteristics” of the datasheet. Before utilization, the bit OPA_RANGE
of OPAMP_CSR must be set to 1 if VDDA is above 2.4V, or kept at 0 otherwise.
As soon as the OPAEN bit in OPAMP_CSR register is set, the operational amplifier is
functional. The two input pins and the output pin are connected as defined in Section 25.3.3:
Signal routing and the default connection settings can be changed.
Note: The inputs and output pins must be configured in analog mode (default state) in the
corresponding GPIOx_MODER register.

25.3.3 Signal routing

The routing for the operational amplifier pins is determined by OPAMP_CSR register.
The connections of the two operational amplifiers (OPAMP1 and OPAMP2) are described in
the table below

Table 193. Operational amplifier possible connections

Signal Pin Internal comment

OPAMP1_OUT or Controlled by bits OPAMODE

OPAMP1_VINM PA1 or dedicated pin(1)
PGA and VM_SEL.
OPAMP1_VINP PA0 DAC1_OUT1 Controlled by bit VP_SEL.
The pin is connected when the
OPAMP1_VOUT PA3 ADC1_IN8 OPAMP is enabled. The ADC
input is controlled by ADC.

PA7 or dedicated OPAMP2_OUT or Controlled by bits OPAMODE

OPAMP2_VINM
pinChapter 1. PGA and VM_SEL.
OPAMP2_VINP PA6 DAC1_OUT2 Controlled by bit VP_SEL
The pin is connected when the
OPAMP2_VOUT PB0 ADC1_IN15 OPAMP is enabled. The ADC
input is controlled by ADC.
1. The dedicated pin is only available on BGA132 and BGA169 package. This configuration provides the
lowest input bias current (see datasheet).

852/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

25.3.4 OPAMP modes

The operational amplifier inputs and outputs are all accessible on terminals. The amplifiers
can be used in multiple configuration environments:
• Standalone mode (external gain setting mode)
• Follower configuration mode
• PGA modes
Note: The amplifier output pin is directly connected to the output pad to minimize the output
impedance. It cannot be used as a general purpose I/O, even if the amplifier is configured
as a PGA and only connected to the ADC channel.
Note: The impedance of the signal must be maintained below a level which avoids the input
leakage to create significant artifacts (due to a resistive drop in the source). Please refer to
the electrical characteristics section in the datasheet for further details.

Standalone mode (external gain setting mode)

The procedure to use the OPAMP in standalone mode is presented hereafter.
Starting from the default value of OPAMP_CSR, and the default state of GPIOx_MODER,
configure bit OPA_RANGE according the VDDA voltage. As soon as the OPAEN bit is set,
the two input pins and the output pin are connected to the operational amplifier.
This default configuration uses the factory trimming values and operates in normal mode
(highest performance). The behavior of the OPAMP can be changed as follows:
• OPALPM can be set to “operational amplifier low-power” mode in order to save power.
• USERTRIM can be set to modify the trimming values for the input offset.

Figure 174. Standalone mode: external gain setting mode

STM32

GPIO
+
DAC_OUT
ADC
GPIO

MS35324V1

RM0438 Rev 7 853/2194

863
Operational amplifiers (OPAMP) RM0438

Follower configuration mode

The procedure to use the OPAMP in follower mode is presented hereafter.
• configure OPAMODE bits as “internal follower”
• configure VP_SEL bits as “GPIO connected to VINP”.
• As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is copied to pin
OPAMP_VOUT.
Note: The pin corresponding to OPAMP_VINM is free for another usage.
Note: The signal on the operational amplifier output is also seen as an ADC input. As a
consequence, the OPAMP configured in follower mode can be used to perform impedance
adaptation on input signals before feeding them to the ADC input, assuming the input signal
frequency is compatible with the operational amplifier gain bandwidth specification.

Figure 175. Follower configuration

STM32

GPIO
+
DAC_OUT
ADC

GPIO
-

Always connected to
OPAMP output (can be
used during debug)

MS35325V1

854/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

Programmable Gain Amplifier mode

The procedure to use the OPAMP to amplify the amplitude of an input signal is
presented hereafter.
• configure OPAMODE bits as “internal PGA enabled”,
• configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”,
• configure VM_SEL bits as “inverting not externally connected”,
• configure VP_SEL bits as “GPIO connected to VINP”.
As soon as the OPAEN bit is set, the signal on pin OPAMP_VINP is amplified by the
selected gain and visible on pin OPAMP_VOUT.
Note: To avoid saturation, the input voltage should stay below VDDA divided by the selected gain.

Figure 176. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input not used

STM32

GPIO
+
DAC_OUT
ADC

GPIO
-

Always connected to
OPAMP output (can be
used during debug)

MS35326V1

RM0438 Rev 7 855/2194

863
Operational amplifiers (OPAMP) RM0438

Programmable Gain Amplifier mode with external filtering

The procedure to use the OPAMP to amplify the amplitude of an input signal, with an
external filtering, is presented hereafter.
• configure OPAMODE bits as “internal PGA enabled”,
• configure PGA_GAIN bits as “internal PGA Gain 2, 4, 8 or 16”,
• configure VM_SEL bits as “GPIO connected to VINM”,
• configure VP_SEL bits as “GPIO connected to VINP”.
Any external connection on VINP can be used in parallel with the internal PGA, for
example a capacitor can be connected between VOUT and VINM for filtering purpose
(see datasheet for the value of resistors used in the PGA resistor network).

Figure 177. PGA mode, internal gain setting (x2/x4/x8/x16), inverting input used for
filtering

STM32

GPIO
+
DAC_OUT
ADC
GPIO

Allows optional
low-pass
filtering (1)
Equivalent to

MS35327V1

1. The gain depends on the cut-off frequency.

25.3.5 Calibration
At startup, the trimming values are initialized with the preset ‘factory’ trimming value.
Each operational amplifier offset can be trimmed by the user. Specific registers allow to
have different trimming values for normal mode and for low-power mode.
The aim of the calibration is to cancel as much as possible the OPAMP inputs offset voltage.
The calibration circuitry allows to reduce the inputs offset voltage to less than +/-1.5 mV
within stable voltage and temperature conditions.
For each operational amplifier and each mode two trimming values need to be trimmed, one
for N differential pair and one for P differential pair.
There are two registers for trimming the offsets for each operational amplifiers, one for
normal mode (OPAMP_OTR) and one low-power mode (OPAMP_LPOTR). Each register is
composed of five bits for P differential pair trimming and five bits for N differential pair
trimming. These are the ‘user’ values.

856/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

The user is able to switch from ‘factory’ values to ‘user’ trimmed values using the
USERTRIM bit in the OPAMP_CSR register. This bit is reset at startup and so the ‘factory’
value are applied by default to the OPAMP trimming registers.
User is liable to change the trimming values in calibration or in functional mode.

The offset trimming registers are typically configured after the calibration operation is
initialized by setting bit CALON to 1. When CALON = 1 the inputs of the operational
amplifier are disconnected from the functional environment.
• Setting CALSEL to 1 initializes the offset calibration for the P differential pair (low
voltage reference used).
• Resetting CALSEL to 0 initializes the offset calibration for the N differential pair (high
voltage reference used).
When CALON = 1, the bit CALOUT will reflect the influence of the trimming value selected
by CALSEL and OPALPM. When the value of CALOUT switches between two consecutive
trimming values, this means that those two values are the best trimming values. The
CALOUT flag needs up to 1 ms after the trimming value is changed to become steady (see
tOFFTRIMmax delay specification in the electrical characteristics section of the datasheet).
Note: The closer the trimming value is to the optimum trimming value, the longer it takes to
stabilize (with a maximum stabilization time remaining below 1 ms in any case).

Table 194. Operating modes and calibration

Control bits Output
Mode
CALOUT
OPAEN OPALPM CALON CALSEL VOUT
flag

Normal operating
1 0 0 X analog 0
mode
Low-power mode 1 1 0 X analog 0
Power down 0 X X X Z 0
Offset cal high for
1 0 1 0 analog X
normal mode
Offset cal low for
1 0 1 1 analog X
normal mode
Offset cal high for
1 1 1 0 analog X
low-power mode
Offset cal low for
1 1 1 1 analog X
low-power mode

RM0438 Rev 7 857/2194

863
Operational amplifiers (OPAMP) RM0438

Calibration procedure
Here are the steps to perform a full calibration of either one of the operational amplifiers:
1. Select correct OPA_RANGE in OPAMP_CSR, then set the OPAEN bit in OPAMP_CSR
to 1 to enable the operational amplifier.
2. Set the USERTRIM bit in the OPAMP_CSR register to 1.
3. Choose a calibration mode (refer to Table 194: Operating modes and calibration). The
steps 3 to 4 will have to be repeated 4 times. For the first iteration select
– Normal mode, offset cal high (N differential pair)
The above calibration mode correspond to OPALPM=0 and CALSEL=0 in the
OPAMP_CSR register.
4. Increment TRIMOFFSETN[4:0] in OPAMP_OTR starting from 00000b until CALOUT
changes to 1 in OPAMP_CSR.
Note: CALOUT will switch from 0 to 1 for offset cal high and from 1 to 0 for offset cal low.
Note: Between the write to the OPAMP_OTR register and the read of the CALOUT value, make
sure to wait for the tOFFTRIMmax delay specified in the electrical characteristics section of
the datasheet, to get the correct CALOUT value.
The commutation means that the offset is correctly compensated and that the
corresponding trim code must be saved in the OPAMP_OTR register.
Repeat steps 3 to 4 for:
– Normal_mode and offset cal low
– Low power mode and offset cal high
– Low power mode and offset cal low
If a mode is not used it is not necessary to perform the corresponding calibration.
All operational amplifier can be calibrated at the same time.
Note: During the whole calibration phase the external connection of the operational amplifier
output must not pull up or down currents higher than 500 µA.
During the calibration procedure, it is necessary to set up OPAMODE bits as 00 or 01 (PGA
disable) or 11 (internal follower).

25.4 OPAMP low-power modes

Table 195. Effect of low-power modes on the OPAMP
Mode Description

Sleep No effect.
Low-power run No effect.
Low-power sleep No effect.
Stop 0 / Stop 1 No effect, OPAMP registers content is kept.
OPAMP registers content is kept. OPAMP must be disabled before entering
Stop 2
Stop 2 mode.

858/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

Table 195. Effect of low-power modes on the OPAMP (continued)

Mode Description

Standby The OPAMP registers are powered down and must be re-initialized after
Shutdown exiting Standby or Shutdown mode.

25.5 OPAMP registers

25.5.1 OPAMP1 control/status register (OPAMP1_CSR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OPA_
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
RANGE
rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CAL USER CAL VP_ OPA
CALON Res. VM_SEL Res. Res. PGA_GAIN OPAMODE OPAEN
OUT TRIM SEL SEL LPM
r rw rw rw rw rw rw rw rw rw w rw rw

Bit 31 OPA_RANGE: Operational amplifier power supply range for stability

All AOP must be in power down to allow AOP-RANGE bit write. It applies to all AOP
embedded in the product.
0: Low range (VDDA < 2.4V)
1: High range (VDDA > 2.4V)
Bits 30:16 Reserved, must be kept at reset value.
Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’
trimmed values
This bit is active for both mode normal and low-power.
0: ‘factory’ trim code used
1: ‘user’ trim code used
Bit 13 CALSEL: Calibration selection
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
Bit 12 CALON: Calibration mode enabled
0: Normal mode
1: Calibration mode (all switches opened by HW)
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
0: GPIO connected to VINP
1: DAC connected to VINP

RM0438 Rev 7 859/2194

863
Operational amplifiers (OPAMP) RM0438

Bits 9:8 VM_SEL: Inverting input selection

These bits are used only when OPAMODE = 00, 01 or 10.
00: GPIO connected to VINM (valid also in PGA mode for filtering
01: Dedicated low leakage input, connected to VINM (valid also in PGA mode for filtering)
1x: Inverting input not externally connected. These configurations are valid only when
OPAMODE = 10 (PGA mode)
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 PGA_GAIN: Operational amplifier Programmable amplifier gain value
00: internal PGA Gain 2
01: internal PGA Gain 4
10: internal PGA Gain 8
11: internal PGA Gain 16
Bits 3:2 OPAMODE: Operational amplifier PGA mode
00: internal PGA disable
01: internal PGA disable
10: internal PGA enable, gain programmed in PGA_GAIN
11: internal follower
Bit 1 OPALPM: Operational amplifier Low Power Mode
The operational amplifier must be disable to change this configuration.
0: operational amplifier in normal mode
1: operational amplifier in low-power mode
Bit 0 OPAEN: Operational amplifier Enable
0: operational amplifier disabled
1: operational amplifier enabled

25.5.2 OPAMP1 offset trimming register in normal mode (OPAMP1_OTR)

Address offset: 0x04
Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMOFFSETP[4:0] Res. Res. Res. TRIMOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs

25.5.3 OPAMP1 offset trimming register in low-power mode

(OPAMP1_LPOTR)
Address offset: 0x08

860/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMLPOFFSETP[4:0] Res. Res. Res. TRIMLPOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs

25.5.4 OPAMP2 control/status register (OPAMP2_CRS)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CALOU USERT CALSE VP_SE OPALP
CALON Res. VM_SEL Res. Res. PGA_GAIN OPAMODE OPAEN
T RIM L L M
r rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 CALOUT: Operational amplifier calibration output
During calibration mode offset is trimmed when this signal toggle.
Bit 14 USERTRIM: allows to switch from ‘factory’ AOP offset trimmed values to AOP offset ‘user’
trimmed values
This bit is active for both mode normal and low-power.
0: ‘factory’ trim code used
1: ‘user’ trim code used
Bit 13 CALSEL: Calibration selection
0: NMOS calibration (200mV applied on OPAMP inputs)
1: PMOS calibration (VDDA-200mV applied on OPAMP inputs)
Bit 12 CALON: Calibration mode enabled
0: Normal mode
1: Calibration mode (all switches opened by HW)
Bit 11 Reserved, must be kept at reset value.
Bit 10 VP_SEL: Non inverted input selection
0: GPIO connected to VINP
1: DAC connected to VINP

RM0438 Rev 7 861/2194

863
Operational amplifiers (OPAMP) RM0438

Bits 9:8 VM_SEL: Inverting input selection

These bits are used only when OPAMODE = 00, 01 or 10.
00:GPIO connected to VINM (valid also in PGA mode for filtering)
01: Dedicated low leakage input, (available only on BGA132) connected to VINM (valid also
in PGA mode for filtering)
1x: Inverting input not externally connected. These configurations are valid only when
OPAMODE = 10 (PGA mode)
Bits 7:6 Reserved, must be kept at reset value.
Bits 5:4 PGA_GAIN: Operational amplifier Programmable amplifier gain value
00: internal PGA Gain 2
01: internal PGA Gain 4
10: internal PGA Gain 8
11: internal PGA Gain 16
Bits 3:2 OPAMODE: Operational amplifier PGA mode
00: internal PGA disable
01: internal PGA disable
10: internal PGA enable, gain programmed in PGA_GAIN
11: internal follower
Bit 1 OPALPM: Operational amplifier Low Power Mode
The operational amplifier must be disable to change this configuration.
0: operational amplifier in normal mode
1: operational amplifier in low-power mode
Bit 0 OPAEN: Operational amplifier Enable
0: operational amplifier disabled
1: operational amplifier enabled

25.5.5 OPAMP2 offset trimming register in normal mode (OPAMP2_OTR)

Address offset: 0x14
Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMOFFSETP[4:0] Res. Res. Res. TRIMOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMOFFSETP[4:0]: Trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMOFFSETN[4:0]: Trim for NMOS differential pairs

25.5.6 OPAMP2 offset trimming register in low-power mode

(OPAMP2_LPOTR)
Address offset: 0x18

862/2194 RM0438 Rev 7

RM0438 Operational amplifiers (OPAMP)

Reset value: 0x0000 XXXX (factory trimmed values)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. TRIMLPOFFSETP[4:0] Res. Res. Res. TRIMLPOFFSETN[4:0]
rw rw rw rw rw rw rw rw rw rw

Bits 31:13 Reserved, must be kept at reset value.

Bits 12:8 TRIMLPOFFSETP[4:0]: Low-power mode trim for PMOS differential pairs
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 TRIMLPOFFSETN[4:0]: Low-power mode trim for NMOS differential pairs

25.5.7 OPAMP register map

Table 196. OPAMP register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
OPA_RANGE

USERTRIM

PGA_GAIN

OPAMODE

OPALPM
CALOUT

VM_SEL
CALSEL

VP_SEL
CALON

OPAEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
OPAMP1_CSR
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TRIM TRIM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
OPAMP1_OTR
0x04 OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

OPAMP1_ TRIMLP TRIMLP

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
0x08 LPOTR OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

USERTRIM

PGA_GAIN

OPAMODE

OPALPM
CALOUT

VM_SEL
CALSEL

VP_SEL
CALON

OPAEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.

OPAMP2_CSR
0x10

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

TRIM TRIM
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

OPAMP2_OTR
0x14 OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

OPAMP2_LPO TRIMLP TRIMLP

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

0x18 TR OFFSETP[4:0] OFFSETN[4:0]

Reset value (1) (1)

1. Factory trimmed values.

Refer to Section 2.3.2: Memory map and register boundary addresses for the register
boundary addresses.

RM0438 Rev 7 863/2194

863
Digital filter for sigma delta modulators (DFSDM) RM0438

26 Digital filter for sigma delta modulators (DFSDM)

26.1 Introduction
Digital filter for sigma delta modulators (DFSDM) is a high-performance module dedicated
to interface external Σ∆ modulators. It is featuring up to 4 external digital serial interfaces
(channels) and up to 4 digital filters with flexible Sigma Delta stream digital processing
options to offer up to 24-bit final ADC resolution. DFSDM also features optional parallel data
stream input from internal ADC peripherals or from device memory.
An external Σ∆ modulator provides digital data stream of converted analog values from the
external Σ∆ modulator analog input. This digital data stream is sent into a DFSDM input
channel through a serial interface. DFSDM supports several standards to connect various
Σ∆ modulator outputs: SPI interface and Manchester coded 1-wire interface (both with
adjustable parameters). DFSDM module supports the connection of up to 4 multiplexed
input digital serial channels which are shared with up to 4 DFSDM modules. DFSDM
module also supports alternative parallel data inputs from up to 4 internal 16-bit data
channels (from internal ADCs or from device memory).
DFSDM is converting an input data stream into a final digital data word which represents an
analog input value on a Σ∆ modulator analog input. The conversion is based on a
configurable digital process: the digital filtering and decimation of the input serial data
stream.
The conversion speed and resolution are adjustable according to configurable parameters
for digital processing: filter type, filter order, length of filter, integrator length. The maximum
output data resolution is up to 24 bits. There are two conversion modes: single conversion
mode and continuous mode. The data can be automatically stored in a system RAM buffer
through DMA, thus reducing the software overhead.
A flexible timer triggering system can be used to control the start of conversion of DFSDM.
This timing control is capable of triggering simultaneous conversions or inserting a
programmable delay between conversions.
DFSDM features an analog watchdog function. Analog watchdog can be assigned to any of
the input channel data stream or to final output data. Analog watchdog has its own digital
filtering of input data stream to reach the required speed and resolution of watched data.
To detect short-circuit in control applications, there is a short-circuit detector. This block
watches each input channel data stream for occurrence of stable data for a defined time
duration (several 0’s or 1’s in an input data stream).
An extremes detector block watches final output data and stores maximum and minimum
values from the output data values. The extremes values stored can be restarted by
software.
Two power modes are supported: normal mode and stop mode.

864/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

26.2 DFSDM main features

• Up to 4 multiplexed input digital serial channels:
– configurable SPI interface to connect various Σ∆ modulators
– configurable Manchester coded 1 wire interface support
– clock output for Σ∆ modulator(s)
• Alternative inputs from up to 4 internal digital parallel channels:
– inputs with up to 16 bit resolution
– internal sources: ADCs data or memory (CPU/DMA write) data streams
• Adjustable digital signal processing:
– Sincx filter: filter order/type (1..5), oversampling ratio (up to 1..1024)
– integrator: oversampling ratio (1..256)
• Up to 24-bit output data resolution:
– right bit-shifter on final data (0..31 bits)
• Signed output data format
• Automatic data offset correction (offset stored in register by user)
• Continuous or single conversion
• Start-of-conversion synchronization with:
– software trigger
– internal timers
– external events
– start-of-conversion synchronously with first DFSDM filter (DFSDM_FLT0)
• Analog watchdog feature:
– low value and high value data threshold registers
– own configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
– input from output data register or from one or more input digital serial channels
– continuous monitoring independently from standard conversion
• Short-circuit detector to detect saturated analog input values (bottom and top ranges):
– up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on input data stream
– monitoring continuously each channel (4 serial channel transceiver outputs)
• Break generation on analog watchdog event or short-circuit detector event
• Extremes detector:
– store minimum and maximum values of output data values
– refreshed by software
• Pulse skipper feature to support beamforming applications (delay line like behavior)
• DMA may be used to read the conversion data
• Interrupts: end of conversion, overrun, analog watchdog, short-circuit, channel clock
absence
• “regular” or “injected” conversions:
– “regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
– “injected” conversions for precise timing and with high conversion priority

RM0438 Rev 7 865/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

26.3 DFSDM implementation

This section describes the configuration implemented in DFSDMx.

Table 197. DFSDM1 implementation

DFSDM features DFSDM1

Number of channels 4
Number of filters 4
Input from internal ADC X
Supported trigger sources 32(1)
Pulses skipper X
ID registers support -
1. Refer to Table 200: DFSDM triggers connection for available trigger sources.

866/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

26.4 DFSDM functional description

26.4.1 DFSDM block diagram

Figure 178. Single DFSDM block diagram

APB bus
ADC 0

ADC 3
Sample 1 Sample 0 16
Parallel input data
register 0
Sample 1 Sample 0
16
Parallel input data
register 3

Channel multiplexer
EXTRG[1:0]

Data 0
Filter Oversampling Oversampling
Clock 0 order ratio ratio
CKOUT Clock Mode 16
control control Pulse
DATIN0 skipper Sincx filter 0 Integrator unit 0
Serial transceiver 0 Data 3 Filter Oversampling Oversampling
CKIN0
order ratio ratio
Clock Mode Clock 3
control control Pulse 16
DATIN7 skipper Sincx filter 3 Integrator unit 3
CKIN7 Serial transceiver 3

4 watchdog filters
4 watchdog comparators Right bit-shift
count
Config
Status

Interrupt, Right bit-shift

break Calibration
count data
1's, 0's counter correction unit
threshold Interrupt,
Calibration data
High threshold break DFSDMcorrection
data 0 unit
Short circuit
detector
1's, 0
0's counter Filter 0 Low threshold
threshold config DFSDM data 3
Analog watchdog 0
Short circuit
detector 3 High threshold
Filter 3 Low threshold Data output
config
Analog watchdog 3

APB bus

Control unit Maximum value

Minimum value
Configuration Extremes
Interrupts and events:
registers detector 0
1) end of conversion Maximum value
2) analog watchdog Minimum value
DMA, interrupt, break 3) short circuit detection
control, clock control 4) overrun Extremes
detector 3
MSv47474V1

1. This example shows 4 DFSDM filters and 4 input channels.

RM0438 Rev 7 867/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

26.4.2 DFSDM pins and internal signals

Table 198. DFSDM external pins

Name Signal Type Remarks

VDD Power supply Digital power supply.

VSS Power supply Digital ground power supply.
CKIN[3:0] Clock input Clock signal provided from external Σ∆ modulator. FT input.
DATIN[3:0] Data input Data signal provided from external Σ∆ modulator. FT input.
Clock output to provide clock signal into external Σ∆
CKOUT Clock output
modulator.
External trigger Input trigger from two EXTI signals to start analog
EXTRG[1:0]
signal conversion (from GPIOs: EXTI11, EXTI15).

Table 199. DFSDM internal signals

Name Signal Type Remarks

Input trigger from internal/external trigger sources in order

Internal/
to start analog conversion (from internal sources:
dfsdm_jtrg[31:0] external trigger
synchronous input, from external sources: asynchronous
signal
input with synchronization). See Table 200 for details.
break signal Break signals event generation from Analog watchdog or
dfsdm_break[3:0]
output short-circuit detector
DMA request DMA request signal from each DFSDM_FLTx (x=0..3):
dfsdm_dma[3:0]
signal end of injected conversion event.
Interrupt
dfsdm_it[3:0] Interrupt signal for each DFSDM_FLTx (x=0..3)
request signal
ADC input
dfsdm_dat_adc[15:0] Up to 4 internal ADC data buses as parallel inputs.
data

Table 200. DFSDM triggers connection

Trigger name Trigger source

dfsdm_jtrg0 TIM1_TRGO
dfsdm_jtrg1 TIM1_TRGO2
dfsdm_jtrg2 TIM8_TRGO
dfsdm_jtrg3 TIM8_TRGO2
dfsdm_jtrg[23:9] Reserved
dfsdm_jtrg24 EXTI11
dfsdm_jtrg25 EXTI15
dfsdm_jtrg26 LPTIMER1
dfsdm_jtrg[31:27] Reserved

868/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Table 201. DFSDM break connection

Break name Break destination

dfsdm_break[0] TIM1/TIM15 break

dfsdm_break[1] TIM1 break2 / TIM16 break
dfsdm_break[2] TIM8/TIM17 break
dfsdm_break[3] TIM8 break2

26.4.3 DFSDM reset and clocks

DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the
DFSDM_CH0CFGR1 register. Once DFSDM is globally enabled, all input channels (y=0..3)
and digital filters DFSDM_FLTx (x=0..3) start to work if their enable bits are set (channel
enable bit CHEN in DFSDM_CHyCFGR1 and DFSDM_FLTx enable bit DFEN in
DFSDM_FLTxCR1).
Digital filter x DFSDM_FLTx (x=0..3) is enabled by setting DFEN=1 in the
DFSDM_FLTxCR1 register. Once DFSDM_FLTx is enabled (DFEN=1), both Sincx digital
filter unit and integrator unit are reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and
DFSDM_FLTx is put into stop mode. All register settings remain unchanged except
DFSDM_FLTxAWSR and DFSDM_FLTxISR (which are reset).
Channel y (y=0..3) is enabled by setting CHEN=1 in the DFSDM_CHyCFGR1 register.
Once the channel is enabled, it receives serial data from the external Σ∆ modulator or
parallel internal data sources (ADCs or CPU/DMA wire from memory).
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CH0CFGR1) before
stopping the system clock to enter in the STOP mode of the device.

DFSDM clocks
The internal DFSDM clock fDFSDMCLK, which is used to drive the channel transceivers,
digital processing blocks (digital filter, integrator) and next additional blocks (analog
watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC
block and is derived from the system clock SYSCLK or peripheral clock PCLK2 (see
Section 9.8.32: RCC peripherals independent clock configuration register 2
(RCC_CCIPR2)). The DFSDM clock is automatically stopped in stop mode (if DFEN = 0 for
all DFSDM_FLTx, x=0..3).
The DFSDM serial channel transceivers can receive an external serial clock to sample an
external serial data stream. The internal DFSDM clock must be at least 4 times faster than
the external serial clock if standard SPI coding is used, and 6 times faster than the external
serial clock if Manchester coding is used.
DFSDM can provide one external output clock signal to drive external Σ∆ modulator(s) clock
input(s). It is provided on CKOUT pin. This output clock signal must be in the range
specified in given device datasheet and is derived from DFSDM clock or from audio clock
(see CKOUTSRC bit in DFSDM_CH0CFGR1 register) by programmable divider in the
range 2 - 256 (CKOUTDIV in DFSDM_CH0CFGR1 register). Audio clock source is SAI1
clock selected by SAI1SEL[1:0] field in RCC configuration (see ).

RM0438 Rev 7 869/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

26.4.4 Serial channel transceivers

There are 4 multiplexed serial data channels which can be selected for conversion by each
filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data
stream from external Σ∆ modulator. Data stream can be sent in SPI format or Manchester
coded format (see SITP[1:0] bits in DFSDM_CHyCFGR1 register).
The channel is enabled for operation by setting CHEN=1 in DFSDM_CHyCFGR1 register.

Channel inputs selection

Serial inputs (data and clock signals) from DATINy and CKINy pins can be redirected from
the following channel pins. This serial input channel redirection is set by CHINSEL bit in
DFSDM_CHyCFGR1 register.
Channel redirection can be used to collect audio data from PDM (pulse density modulation)
stereo microphone type. PDM stereo microphone has one data and one clock signal. Data
signal provides information for both left and right audio channel (rising clock edge samples
for left channel and falling clock edge samples for right channel).
Configuration of serial channels for PDM microphone input:
• PDM microphone signals (data, clock) will be connected to DFSDM input serial
channel y (DATINy, CKOUT) pins.
• Channel y will be configured: CHINSEL = 0 (input from given channel pins: DATINy,
CKINy).
• Channel (y-1) (modulo 4) will be configured: CHINSEL = 1 (input from the following
channel ((y-1)+1) pins: DATINy, CKINy).
• Channel y: SITP[1:0] = 0 (rising edge to strobe data) => left audio channel on channel
y.
• Channel (y-1): SITP[1:0] = 1 (falling edge to strobe data) => right audio channel on
channel y-1.
• Two DFSDM filters will be assigned to channel y and channel (y-1) (to filter left and
right channels from PDM microphone).

870/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Figure 179. Input channel pins redirection

(. . .)

CH(ymax)
Decode
DATIN(ymax)
CKIN(ymax)

. . .
. . .
. . .
FLT(xmax)
.
CHy .
Decode .
DATINy
CKINy FLT(x+1)

FLTx
CH(y-1) .
Decode .
DATIN(y-1)
.
CKIN(y-1)
FLT0
. . .
. . .
. . .

CH0
Decode
DATAIN0
CKIN0

(. . .)
CHINSEL

RCH

MSv41632V1

Output clock generation

A clock signal can be provided on CKOUT pin to drive external Σ∆ modulator clock inputs.
The frequency of this CKOUT signal is derived from DFSDM clock or from audio clock (see
CKOUTSRC bit in DFSDM_CH0CFGR1 register) divided by a predivider (see CKOUTDIV
bits in DFSDM_CH0CFGR1 register). If the output clock is stopped, then CKOUT signal is
set to low state (output clock can be stopped by CKOUTDIV=0 in DFSDM_CHyCFGR1
register or by DFSDMEN=0 in DFSDM_CH0CFGR1 register). The output clock stopping is
performed:
• 4 system clocks after DFSDMEN is cleared (if CKOUTSRC=0)
• 1 system clock and 3 audio clocks after DFSDMEN is cleared (if CKOUTSRC=1)
Before changing CKOUTSRC the software has to wait for CKOUT being stopped to avoid
glitch on CKOUT pin. The output clock signal frequency must be in the range 0 - 20 MHz.

RM0438 Rev 7 871/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

SPI data input format operation

In SPI format, the data stream is sent in serial format through data and clock signals. Data
signal is always provided from DATINy pin. A clock signal can be provided externally from
CKINy pin or internally from a signal derived from the CKOUT signal source.
In case of external clock source selection (SPICKSEL[1:0]=0) data signal (on DATINy pin) is
sampled on rising or falling clock edge (of CKINy pin) according SITP[1:0] bits setting (in
DFSDM_CHyCFGR1 register).
Internal clock sources - see SPICKSEL[1:0] in DFSDM_CHyCFGR1 register:
• CKOUT signal:
– For connection to external Σ∆ modulator which uses directly its clock input (from
CKOUT) to generate its output serial communication clock.
– Sampling point: on rising/falling edge according SITP[1:0] setting.
• CKOUT/2 signal (generated on CKOUT rising edge):
– For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input rising edge).
– Sampling point: on each second CKOUT falling edge.
• CKOUT/2 signal (generated on CKOUT falling edge):
– For connection to external Σ∆ modulator which divides its clock input (from
CKOUT) by 2 to generate its output serial communication clock (and this output
clock change is active on each clock input falling edge).
– Sampling point: on each second CKOUT rising edge.
Note: An internal clock source can only be used when the external Σ∆ modulator uses CKOUT
signal as a clock input (to have synchronous clock and data operation).
Internal clock source usage can save CKINy pin connection (CKINy pins can be used for
other purpose).
The clock source signal frequency must be in the range 0 - 20 MHz for SPI coding and less
than fDFSDMCLK/4.

Manchester coded data input format operation

In Manchester coded format, the data stream is sent in serial format through DATINy pin
only. Decoded data and clock signal are recovered from serial stream after Manchester
decoding. There are two possible settings of Manchester codings (see SITP[1:0] bits in
DFSDM_CHyCFGR1 register):
• signal rising edge = log 0; signal falling edge = log 1
• signal rising edge = log 1; signal falling edge = log 0
The recovered clock signal frequency for Manchester coding must be in the range
0 - 10 MHz and less than fDFSDMCLK/6.
To correctly receive Manchester coded data, the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according formula:

( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK )

872/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Figure 180. Channel transceiver timing diagrams

CKINy (SPICKSEL=0)
SPI timing : SPICKSEL = 0

twl twh tr tf
tsu th

SITP = 00
DATINy

tsu th

SITP = 01

SPICKSEL=3
CKOUT

SPICKSEL=2
SPI timing : SPICKSEL = 1, 2, 3

SPICKSEL=1

twl twh tr tf
tsu th

SITP = 0
DATINy

tsu th

SITP = 1

SITP = 2
DATINy
Manchester timing

SITP = 3

recovered clock

recovered data 0 0 1 1 0
MS30766V3

RM0438 Rev 7 873/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Clock absence detection

Channels serial clock inputs can be checked for clock absence/presence to ensure the
correct operation of conversion and error reporting. Clock absence detection can be
enabled or disabled on each input channel y by bit CKABEN in DFSDM_CHyCFGR1
register. If enabled, then this clock absence detection is performed continuously on a given
channel. A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if
CKABIE=1) in case of an input clock error (see CKABF[3:0] in DFSDM_FLT0ISR register
and CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF
in DFSDM_FLT0ICR register), the clock absence flag is refreshed. Clock absence status bit
CKABF[y] is set also by hardware when corresponding channel y is disabled (if CHEN[y] = 0
then CKABF[y] is held in set state).
When a clock absence event has occurred, the data conversion (and/or analog watchdog
and short-circuit detector) provides incorrect data. The user should manage this event and
discard given data while a clock absence is reported.
The clock absence feature is available only when the system clock is used for the CKOUT
signal (CKOUTSRC=0 in DFSDM_CH0CFGR1 register).
When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register). The software sequence
concerning clock absence detection feature should be:
• Enable given channel by CHEN = 1
• Try to clear the clock absence flag (by CLRCKABF = 1) until the clock absence flag is
really cleared (CKABF = 0). At this time, the transceiver is synchronized (signal clock is
valid) and is able to receive data.
• Enable the clock absence feature CKABEN = 1 and the associated interrupt CKABIE =
1 to detect if the SPI clock is lost or Manchester data edges are missing.
If SPI data format is used, then the clock absence detection is based on the comparison of
an external input clock with an output clock generation (CKOUT signal). The external input
clock signal into the input channel must be changed at least once per 8 signal periods of
CKOUT signal (which is controlled by CKOUTDIV field in DFSDM_CH0CFGR1 register).

Figure 181. Clock absence timing diagram for SPI

max. 8 periods

CKOUT 2 0 1 2 3 4 5 6 7 0
SPI clock presence

restart counting
CKINy
timing

last clock change

CKABF[y]

error reported
MS30767V2

If Manchester data format is used, then the clock absence means that the clock recovery is
unable to perform from Manchester coded signal. For a correct clock recovery, it is first
necessary to receive data with 1 to 0 or 0 to 1 transition (see Figure 183 for Manchester
synchronization).

874/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

The detection of a clock absence in Manchester coding (after a first successful

synchronization) is based on changes comparison of coded serial data input signal with
output clock generation (CKOUT signal). There must be a voltage level change on DATINy
pin during 2 periods of CKOUT signal (which is controlled by CKOUTDIV bits in
DFSDM_CH0CFGR1 register). This condition also defines the minimum data rate to be able
to correctly recover the Manchester coded data and clock signals.
The maximum data rate of Manchester coded data must be less than the CKOUT signal.
So to correctly receive Manchester coded data, the CKOUTDIV divider must be set
according the formula:

( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK )

A clock absence flag is set (CKABF[y] = 1) and an interrupt can be invoked (if CKABIE=1) in
case of an input clock recovery error (see CKABF[3:0] in DFSDM_FLT0ISR register and
CKABEN in DFSDM_CHyCFGR1). After a clock absence flag clearing (by CLRCKABF in
DFSDM_FLT0ICR register), the clock absence flag is refreshed.

Figure 182. Clock absence timing diagram for Manchester coding

max. 2 periods

CKOUT 0 0 0 1 0

restart counting

SITP = 2
Manchester clock presence

DATINy

last data change

timing

SITP = 3

recovered clock

recovered data 0 0 1 ? ?

CKABF[y]

error reported
MS30768V2

RM0438 Rev 7 875/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Manchester/SPI code synchronization

The Manchester coded stream must be synchronized the first time after enabling the
channel (CHEN=1 in DFSDM_CHyCFGR1 register). The synchronization ends when a data
transition from 0 to 1 or from 1 to 0 (to be able to detect valid data edge) is received. The
end of the synchronization can be checked by polling CKABF[y]=0 for a given channel after
it has been cleared by CLRCKABF[y] in DFSDM_FLT0ICR, following the software sequence
detailed hereafter:
CKABF[y] flag is cleared by setting CLRCKABF[y] bit. If channel y is not yet synchronized
the hardware immediately set the CKABF[y] flag. Software is then reading back the
CKABF[y] flag and if it is set then perform again clearing of this flag by setting
CLRCKABF[y] bit. This software sequence (polling of CKABF[y] flag) continues until
CKABF[y] flag is set (signalizing that Manchester stream is synchronized). To be able to
synchronize/receive Manchester coded data the CKOUTDIV divider (in
DFSDM_CH0CFGR1 register) must be set with respect to expected Manchester data rate
according the formula below.

( ( CKOUTDIV + 1 ) × T SYSCLK ) < T Manchester clock < ( 2 × CKOUTDIV × T SYSCLK )

SPI coded stream is synchronized after first detection of clock input signal (valid
rising/falling edge).
Note: When the transceiver is not yet synchronized, the clock absence flag is set and cannot be
cleared by CLRCKABF[y] bit (in DFSDM_FLT0ICR register).

876/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Figure 183. First conversion for Manchester coding (Manchester synchronization)

SITP = 2
DATINy
Manchester timing

SITP = 3

recovered clock

data from
modulator 0 0 1 1 0

CHEN
real start of first conversion
first conversion
start trigger first data bit toggle - end of Manchester synchronization

recovered data ? ? 1 1 0

CKABF[y]

clearing of CKABF[y] flag by software polling

MS30769V2

External serial clock frequency measurement

The measuring of a channel serial clock input frequency provides a real data rate from an
external Σ∆ modulator, which is important for application purposes.
An external serial clock input frequency can be measured by a timer counting DFSDM
clocks (fDFSDMCLK) during one conversion duration. The counting starts at the first input
data clock after a conversion trigger (regular or injected) and finishes by last input data clock
before conversion ends (end of conversion flag is set). Each conversion duration (time
between first serial sample and last serial sample) is updated in counter CNVCNT[27:0] in
register DFSDM_FLTxCNVTIMR when the conversion finishes (JEOCF=1 or REOCF=1).
The user can then compute the data rate according to the digital filter settings (FORD,
FOSR, IOSR, FAST). The external serial frequency measurement is stopped only if the filter
is bypassed (FOSR=0, only integrator is active, CNVCNT[27:0]=0 in
DFSDM_FLTxCNVTIMR register).
In case of parallel data input (Section 26.4.6: Parallel data inputs) the measured frequency
is the average input data rate during one conversion.

RM0438 Rev 7 877/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Note: When conversion is interrupted (e.g. by disabling/enabling the selected channel) the
interruption time is also counted in CNVCNT[27:0]. Therefore it is recommended to not
interrupt the conversion for correct conversion duration result.
Conversion times:
injected conversion or regular conversion with FAST = 0 (or first conversion if
FAST=1):
for Sincx filters (x=1..5):
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
regular conversion with FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where:
• fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data
rate (in case of parallel data input)
• FOSR is the filter oversampling ratio: FOSR = FOSR[9:0]+1 (see DFSDM_FLTxFCR
register)
• IOSR is the integrator oversampling ratio: IOSR = IOSR[7:0]+1 (see DFSDM_FLTxFCR
register)
• FORD is the filter order: FORD = FORD[2:0] (see DFSDM_FLTxFCR register)

Channel offset setting

Each channel has its own offset setting (in register) which is finally subtracted from each
conversion result (injected or regular) from a given channel. Offset correction is performed
after the data right bit shift. The offset is stored as a 24-bit signed value in OFFSET[23:0]
field in DFSDM_CHyCFGR2 register.

Data right bit shift

To have the result aligned to a 24-bit value, each channel defines a number of right bit shifts
which will be applied on each conversion result (injected or regular) from a given channel.
The data bit shift number is stored in DTRBS[4:0] bits in DFSDM_CHyCFGR2 register.
The right bit-shift is rounding the result to nearest integer value. The sign of shifted result is
maintained, in order to have valid 24-bit signed format of result data.

Pulses skipper
Purpose of the pulses skipper is to implement delay line like behavior for given input
channel(s). Given number of samples from input serial data stream (serial stream only) can
be discarded before they enter into the filter. This data discarding is performed by skipping
given number of sampling input clock pulses (given serial data samples are then not
sampled by filter). The sampling clock is gated by pulses skipper function for given number
of clock pulses. When given clock pulses are skipped then the filtering continues for
following input data. With comparison to non skipped data stream this operation causes that

878/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

the final output sample (and next samples) from filter will be calculated from later input data.
This final sample then looks a bit in forward - because it is calculated from newer input
samples than the “non-skipped” sample. The final “skipped sample” is converted later
because the skipped input data samples must be replaced by followed input data samples.
The final data buffers behavior (skipped and non-skipped output data buffers comparison)
looks like the non-skipped data stream is a bit delayed - both data buffers will be phase
shifted.
Number of clock pulses to be skipped should be written into PLSSKP[5:0] field in
DFSDM_CHyDLYR register. Once PLSSKP[5:0] field is written the execution of pulses
skipping is started on given channel. PLSSKP[5:0] field can be read in order to check the
progress of pulses skipper. When PLSSKP[5:0]=0 means that pulses skipping has been
executed.
Up to 63 clock pulses can be skip with a single write operation into PLSSKP[5:0]. If more
pulses need to be skipped, then user has to write several times into the PLSSKP[5:0] field.
The application software should handle cumulative skipped clock number per each filter.

26.4.5 Configuring the input serial interface

The following parameters must be configured for the input serial interface:
• Output clock predivider. There is a programmable predivider to generate the output
clock from DFSDM clock (2 - 256). It is defined by CKOUTDIV[7:0] bits in
DFSDM_CH0CFGR1 register.
• Serial interface type and input clock phase. Selection of SPI or Manchester coding
and sampling edge of input clock. It is defined by SITP [1:0] bits in
DFSDM_CHyCFGR1 register.
• Input clock source. External source from CKINy pin or internal from CKOUT pin. It is
defined by SPICKSEL[1:0] field in DFSDM_CHyCFGR1 register.
• Final data right bit-shift. Defines the final data right bit shift to have the result aligned
to a 24-bit value. It is defined by DTRBS[4:0] in DFSDM_CHyCFGR2 register.
• Channel offset per channel. Defines the analog offset of a given serial channel (offset
of connected external Σ∆ modulator). It is defined by OFFSET[23:0] bits in
DFSDM_CHyCFGR2 register.
• short-circuit detector and clock absence per channel enable. To enable or disable
the short-circuit detector (by SCDEN bit) and the clock absence monitoring (by
CKABEN bit) on a given serial channel in register DFSDM_CHyCFGR1.
• Analog watchdog filter and short-circuit detector threshold settings. To configure
channel analog watchdog filter parameters and channel short-circuit detector
parameters. Configurations are defined in DFSDM_CHyAWSCDR register.

26.4.6 Parallel data inputs

Each input channel provides a register for 16-bit parallel data input (besides serial data
input). Each 16-bit parallel input can be sourced from internal data sources only:
• internal ADC results
• direct CPU/DMA writing.
The selection for using serial or parallel data input for a given channel is done by field
DATMPX[1:0] of DFSDM_CHyCFGR1 register. In DATMPX[1:0] is also defined the parallel
data source: internal ADC or direct write by CPU/DMA.

RM0438 Rev 7 879/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Each channel contains a 32-bit data input register DFSDM_CHyDATINR in which it can be
written a 16-bit data. Data are in 16-bit signed format. Those data can be used as input to
the digital filter which is accepting 16-bit parallel data.
If serial data input is selected (DATMPX[1:0] = 0), the DFSDM_CHyDATINR register is write
protected.

Input from internal ADC

In case of ADC data parallel input (DATMPX[1:0]=1) the ADC[y+1] result is assigned to
channel y input (ADC1 is filling DFSDM_CHDATIN0R register, ADC2 is filling
DFSDM_CHDATIN1R register, ... , ADC8 is filling DFSDM_CHDATIN7R register). End of
conversion event from ADC[y+1] causes update of channel y data (parallel data from
ADC[y+1] are put as next sample to digital filter). Data from ADC[y+1] is written into
DFSDM_CHyDATINR register (field INDAT0[15:0]) when end of conversion event occurred.
The setting of data packing mode (DATPACK[1:0] in the DFSDM_CHyCFGR1 register) has
no effect in case of ADC data input.
Note: Extension of ADC specification: in case the internal ADC is configured in interleaved mode
(e.g. ADC1 together with ADC2 - see ADC specification) then each result from ADC1 or
from ADC2 will come to the same 16-bit bus - to the bus of ADC1 - which is coming into
DFSDM channel 0 (fixed connection). So there will be double input data rate into DFSDM
channel 0 (even samples come from ADC1 and odd samples from ADC2). Channel 1
associated with ADC2 will be free.

Input from memory (direct CPU/DMA write)

The direct data write into DFSDM_CHyDATINR register by CPU or DMA (DATMPX[1:0]=2)
can be used as data input in order to process digital data streams from memory or
peripherals.
Data can be written by CPU or DMA into DFSDM_CHyDATINR register:
1. CPU data write:
Input data are written directly by CPU into DFSDM_CHyDATINR register.
2. DMA data write:
The DMA should be configured in memory-to-memory transfer mode to transfer data
from memory buffer into DFSDM_CHyDATINR register. The destination memory
address is the address of DFSDM_CHyDATINR register. Data are transferred at DMA
transfer speed from memory to DFSDM parallel input.
This DMA transfer is different from DMA used to read DFSDM conversion results. Both
DMA can be used at the same time - first DMA (configured as memory-to-memory
transfer) for input data writings and second DMA (configured as peripheral-to-memory
transfer) for data results reading.
The accesses to DFSDM_CHyDATINR can be either 16-bit or 32-bit wide, allowing to load
respectively one or two samples in one write operation. 32-bit input data register
(DFSDM_CHyDATINR) can be filled with one or two 16-bit data samples, depending on the
data packing operation mode defined in field DATPACK[1:0] of DFSDM_CHyCFGR1
register:
1. Standard mode (DATPACK[1:0]=0):
Only one sample is stored in field INDAT0[15:0] of DFSDM_CHyDATINR register which
is used as input data for channel y. The upper 16 bits (INDAT1[15:0]) are ignored and
write protected. The digital filter must perform one input sampling (from INDAT0[15:0])

880/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

to empty data register after it has been filled by CPU/DMA. This mode is used together
with 16-bit CPU/DMA access to DFSDM_CHyDATINR register to load one sample per
write operation.
2. Interleaved mode (DATPACK[1:0]=1):
DFSDM_CHyDATINR register is used as a two sample buffer. The first sample is
stored in INDAT0[15:0] and the second sample is stored in INDAT1[15:0]. The digital
filter must perform two input samplings from channel y to empty DFSDM_CHyDATINR
register. This mode is used together with 32-bit CPU/DMA access to
DFSDM_CHyDATINR register to load two samples per write operation.
3. Dual mode (DATPACK[1:0]=2):
Two samples are written into DFSDM_CHyDATINR register. The data INDAT0[15:0] is
for channel y, the data in INDAT1[15:0] is for channel y+1. The data in INDAT1[15:0] is
automatically copied INDAT0[15:0] of the following (y+1) channel data register
DFSDM_CH[y+1]DATINR). The digital filters must perform two samplings - one from
channel y and one from channel (y+1) - in order to empty DFSDM_CHyDATINR
registers.
Dual mode setting (DATPACK[1:0]=2) is available only on even channel numbers (y =
0, 2). If odd channel (y = 1, 3) is set to Dual mode then both INDAT0[15:0] and
INDAT1[15:0] parts are write protected for this channel. If even channel is set to Dual
mode then the following odd channel must be set into Standard mode
(DATPACK[1:0]=0) for correct cooperation with even channels.
See Figure 184 for DFSDM_CHyDATINR registers data modes and assignments of data
samples to channels.

Figure 184. DFSDM_CHyDATINR registers operation modes and assignment

Standard mode Interleaved mode Dual mode

31 16 15 0 31 16 15 0 31 16 15 0
Unused Ch0 (sample 0) Ch0 (sample 1) Ch0 (sample 0) Ch1 (sample 0) Ch0 (sample 0) y=0

Unused Ch1 (sample 0) Ch1 (sample 1) Ch1 (sample 0) Unused Ch1 (sample 0) y=1

Unused Ch2 (sample 0) Ch2 (sample 1) Ch2 (sample 0) Ch3 (sample 0) Ch2 (sample 0) y=2

Unused Ch3 (sample 0) Ch3 (sample 1) Ch3 (sample 0) Unused Ch3 (sample 0) y=3
MSv40123V1

The write into DFSDM_CHyDATINR register to load one or two samples must be performed
after the selected input channel (channel y) is enabled for data collection (starting
conversion for channel y). Otherwise written data are lost for next processing.
For example: for single conversion and interleaved mode, do not start writing pair of data
samples into DFSDM_CHyDATINR before the single conversion is started (any data
present in the DFSDM_CHyDATINR before starting a conversion is discarded).

26.4.7 Channel selection

There are 4 multiplexed channels which can be selected for conversion using the injected
channel group and/or using the regular channel.
The injected channel group is a selection of any or all of the 4 channels. JCHG[3:0] in the
DFSDM_FLTxJCHGR register selects the channels of the injected group, where JCHG[y]=1
means that channel y is selected.

RM0438 Rev 7 881/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Injected conversions can operate in scan mode (JSCAN=1) or single mode (JSCAN=0). In
scan mode, each of the selected channels is converted, one after another. The lowest
channel (channel 0, if selected) is converted first, followed immediately by the next higher
channel until all the channels selected by JCHG[3:0] have been converted. In single mode
(JSCAN=0), only one channel from the selected channels is converted, and the channel
selection is moved to the next channel. Writing to JCHG[3:0] if JSCAN=0 resets the channel
selection to the lowest selected channel.
Injected conversions can be launched by software or by a trigger. They are never
interrupted by regular conversions.
The regular channel is a selection of just one of the 4 channels. RCH[1:0] in the
DFSDM_FLTxCR1 register indicates the selected channel.
Regular conversions can be launched only by software (not by a trigger). A sequence of
continuous regular conversions is temporarily interrupted when an injected conversion is
requested.
Performing a conversion on a disabled channel (CHEN=0 in DFSDM_CHyCFGR1 register)
causes that the conversion will never end - because no input data is provided (with no clock
signal). In this case, it is necessary to enable a given channel (CHEN=1 in
DFSDM_CHyCFGR1 register) or to stop the conversion by DFEN=0 in DFSDM_FLTxCR1
register.

26.4.8 Digital filter configuration

DFSDM contains a Sincx type digital filter implementation. This Sincx filter performs an input
digital data stream filtering, which results in decreasing the output data rate (decimation)
and increasing the output data resolution. The Sincx digital filter is configurable in order to
reach the required output data rates and required output data resolution. The configurable
parameters are:
• Filter order/type: (see FORD[2:0] bits in DFSDM_FLTxFCR register):
– FastSinc
– Sinc1
– Sinc2
– Sinc3
– Sinc4
– Sinc5
• Filter oversampling/decimation ratio (see FOSR[9:0] bits in DFSDM_FLTxFCR
register):
– FOSR = 1-1024 - for FastSinc filter and Sincx filter x = FORD = 1..3
– FOSR = 1-215 - for Sincx filter x = FORD = 4
– FOSR = 1-73 - for Sincx filter x = FORD = 5
The filter has the following transfer function (impulse response in H domain):
x
 1 – z – FOSR
• Sincx filter type: H ( z ) =  ----------------------------
-
 1 – z–1 

2
 1 – z – FOSR – ( 2 ⋅ FOSR )
• FastSinc filter type: H ( z ) =  ----------------------------
- ⋅ ( 1 + z )
 1 – z–1 

882/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Figure 185. Example: Sinc3 filter response

Gain (dB)

Normalized frequency (fIN/fDATA )

MS30770V1

Table 202. Filter maximum output resolution (peak data values from filter output)
for some FOSR values
FOSR Sinc1 Sinc2 FastSinc Sinc3 Sinc4 Sinc5

x +/- x +/- x2 +/- 2x2 +/- x3 +/- x4 +/- x5

4 +/- 4 +/- 16 +/- 32 +/- 64 +/- 256 +/- 1024
8 +/- 8 +/- 64 +/- 128 +/- 512 +/- 4096 -
32 +/- 32 +/- 1024 +/- 2048 +/- 32768 +/- 1048576 +/- 33554432
64 +/- 64 +/- 4096 +/- 8192 +/- 262144 +/- 16777216 +/- 1073741824
128 +/- 128 +/- 16384 +/- 32768 +/- 2097152 +/- 268435456
256 +/- 256 +/- 65536 +/- 131072 +/- 16777216 Result can overflow on full scale
1024 +/- 1024 +/- 1048576 +/- 2097152 +/- 1073741824 input (> 32-bit signed integer)

For more information about Sinc filter type properties and usage, it is recommended to study
the theory about digital filters (more resources can be downloaded from internet).

26.4.9 Integrator unit

The integrator performs additional decimation and a resolution increase of data coming from
the digital filter. The integrator simply performs the sum of data from a digital filter for a given
number of data samples from a filter.
The integrator oversampling ratio parameter defines how many data counts will be summed
to one data output from the integrator. IOSR can be set in the range 1-256 (see IOSR[7:0]
bits description in DFSDM_FLTxFCR register).

RM0438 Rev 7 883/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Table 203. Integrator maximum output resolution (peak data values from integrator
output) for some IOSR values and FOSR = 256 and Sinc3 filter type (largest data)
IOSR Sinc1 Sinc2 FastSinc Sinc3 Sinc4 Sinc5

x +/- FOSR. x +/- FOSR2. x +/- 2.FOSR2. x +/- FOSR3. x +/- FOSR4. x +/- FOSR5. x
4 - - - +/- 67 108 864 - -
32 - - - +/- 536 870 912 - -
+/- 2 147 483
128 - - - - -
648
256 - - - +/- 232 - -

26.4.10 Analog watchdog

The analog watchdog purpose is to trigger an external signal (break or interrupt) when an
analog signal reaches or crosses given maximum and minimum threshold values. An
interrupt/event/break generation can then be invoked.
Each analog watchdog will supervise serial data receiver outputs (after the analog watchdog
filter on each channel) or data output register (current injected or regular conversion result)
according to AWFSEL bit setting (in DFSDM_FLTxCR1 register). The input channels to be
monitored or not by the analog watchdog x will be selected by AWDCH[3:0] in
DFSDM_FLTxCR2 register.
Analog watchdog conversions on input channels are independent from standard
conversions. In this case, the analog watchdog uses its own filters and signal processing on
each input channel independently from the main injected or regular conversions. Analog
watchdog conversions are performed in a continuous mode on the selected input channels
in order to watch channels also when main injected or regular conversions are paused
(RCIP = 0, JCIP = 0).
There are high and low threshold registers which are compared with given data values (set
by AWHT[23:0] bits in DFSDM_FLTxAWHTR register and by AWLT[23:0] bits in
DFSDM_FLTxAWLTR register).

884/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

There are 2 options for comparing the threshold registers with the data values
• Option1: in this case, the input data are taken from final output data register
(AWFSEL=0). This option is characterized by:
– high input data resolution (up to 24-bits)
– slow response time - inappropriate for fast response applications like overcurrent
detection
– for the comparison the final data are taken after bit shifting and offset data
correction
– final data are available only after main regular or injected conversions are
performed
– can be used in case of parallel input data source (DATMPX[1:0] ≠ 0 in
DFSDM_CHyCFGR1 register)
• Option2: in this case, the input data are taken from any serial data receivers output
(AWFSEL=1). This option is characterized by:
– input serial data are processed by dedicated analog watchdog Sincx channel
filters with configurable oversampling ratio (1..32) and filter order (1..3) (see
AWFOSR[4:0] and AWFORD[1:0] bits setting in DFSDM_CHyAWSCDR register)
– lower resolution (up to 16-bit)
– fast response time - appropriate for applications which require a fast response like
overcurrent/overvoltage detection)
– data are available in continuous mode independently from main regular or injected
conversions activity
In case of input channels monitoring (AWFSEL=1), the data for comparison to threshold is
taken from channels selected by AWDCH[3:0] field (DFSDM_FLTxCR2 register). Each of
the selected channels filter result is compared to one threshold value pair (AWHT[23:0] /
AWLT[23:0]). In this case, only higher 16 bits (AWHT[23:8] / AWLT[23:8]) define the 16-bit
threshold compared with the analog watchdog filter output because data coming from the
analog watchdog filter is up to a 16-bit resolution. Bits AWHT[7:0] / AWLT[7:0] are not taken
into comparison in this case (AWFSEL=1).
Parameters of the analog watchdog filter configuration for each input channel are set in
DFSDM_CHyAWSCDR register (filter order AWFORD[1:0] and filter oversampling ratio
AWFOSR[4:0]).
Each input channel has its own comparator which compares the analog watchdog data
(from analog watchdog filter) with analog watchdog threshold values (AWHT/AWLT). When
several channels are selected (field AWDCH[3:0] field of DFSDM_FLTxCR2 register),
several comparison requests may be received simultaneously. In this case, the channel
request with the lowest number is managed first and then continuing to higher selected
channels. For each channel, the result can be recorded in a separate flag (fields
AWHTF[3:0], AWLTF[3:0] of DFSDM_FLTxAWSR register). Each channel request is
executed in 8 DFSDM clock cycles. So, the bandwidth from each channel is limited to 8
DFSDM clock cycles (if AWDCH[3:0] = 0x0F). Because the maximum input channel
sampling clock frequency is the DFSDM clock frequency divided by 4, the configuration
AWFOSR = 0 (analog watchdog filter is bypassed) cannot be used for analog watchdog
feature at this input clock speed. Therefore user must properly configure the number of
watched channels and analog watchdog filter parameters with respect to input sampling
clock speed and DFSDM frequency.

RM0438 Rev 7 885/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Analog watchdog filter data for given channel y is available for reading by firmware on field
WDATA[15:0] in DFSDM_CHyWDATR register. That analog watchdog filter data is
converted continuously (if CHEN=1 in DFSDM_CHyCFGR1 register) with the data rate
given by the analog watchdog filter setting and the channel input clock frequency.
The analog watchdog filter conversion works like a regular Fast Continuous Conversion
without the intergator. The number of serial samples needed for one result from analog
watchdog filter output (at channel input clock frequency fCKIN):
first conversion:
for Sincx filters (x=1..5): number of samples = [FOSR * FORD + FORD + 1]
for FastSinc filter: number of samples = [FOSR * 4 + 2 + 1]
next conversions:
for Sincx and FastSinc filters: number of samples = [FOSR * IOSR]
where:
FOSR ....... filter oversampling ratio: FOSR = AWFOSR[4:0]+1 (see DFSDM_CHyAWSCDR
register)
FORD ....... the filter order: FORD = AWFORD[1:0] (see DFSDM_CHyAWSCDR register)
In case of output data register monitoring (AWFSEL=0), the comparison is done after a right
bit shift and an offset correction of final data (see OFFSET[23:0] and DTRBS[4:0] fields in
DFSDM_CHyCFGR2 register). A comparison is performed after each injected or regular
end of conversion for the channels selected by AWDCH[3:0] field (in DFSDM_FLTxCR2
register).
The status of an analog watchdog event is signalized in DFSDM_FLTxAWSR register where
a given event is latched. AWHTF[y]=1 flag signalizes crossing AWHT[23:0] value on
channel y. AWLTF[y]=1 flag signalizes crossing AWLT[23:0] value on channel y. Latched
events in DFSDM_FLTxAWSR register are cleared by writing ‘1’ into the corresponding
clearing bit CLRAWHTF[y] or CLRAWLTF[y] in DFSDM_FLTxAWCFR register.
The global status of an analog watchdog is signalized by the AWDF flag bit in
DFSDM_FLTxISR register (it is used for the fast detection of an interrupt source). AWDF=1
signalizes that at least one watchdog occurred (AWHTF[y]=1 or AWLTF[y]=1 for at least one
channel). AWDF bit is cleared when all AWHTF[3:0] and AWLTF[3:0] are cleared.
An analog watchdog event can be assigned to break output signal. There are four break
outputs to be assigned to a high or low threshold crossing event (dfsdm_break[3:0]). The
break signal assignment to a given analog watchdog event is done by BKAWH[3:0] and
BKAWL[3:0] fields in DFSDM_FLTxAWHTR and DFSDM_FLTxAWLTR register.

26.4.11 Short-circuit detector

The purpose of a short-circuit detector is to signalize with a very fast response time if an
analog signal reached saturated values (out of full scale ranges) and remained on this value
given time. This behavior can detect short-circuit or open circuit errors (e.g. overcurrent or
overvoltage). An interrupt/event/break generation can be invoked.
Input data into a short-circuit detector is taken from channel transceiver outputs.
There is an upcounting counter on each input channel which is counting consecutive 0’s or
1’s on serial data receiver outputs. A counter is restarted if there is a change in the data
stream received - 1 to 0 or 0 to 1 change of data signal. If this counter reaches a short-circuit
threshold register value (SCDT[7:0] bits in DFSDM_CHyAWSCDR register), then a short-

886/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

circuit event is invoked. Each input channel has its short-circuit detector. Any channel can
be selected to be continuously monitored by setting the SCDEN bit (in DFSDM_CHyCFGR1
register) and it has its own short-circuit detector settings (threshold value in SCDT[7:0] bits,
status bit SCDF[3:0], status clearing bits CLRSCDF[3:0]). Status flag SCDF[y] is cleared
also by hardware when corresponding channel y is disabled (CHEN[y] = 0).
On each channel, a short-circuit detector event can be assigned to break output signal
dfsdm_break[3:0]. There are four break outputs to be assigned to a short-circuit detector
event. The break signal assignment to a given channel short-circuit detector event is done
by BKSCD[3:0] field in DFSDM_CHyAWSCDR register.
Short circuit detector cannot be used in case of parallel input data channel selection
(DATMPX[1:0] ≠ 0 in DFSDM_CHyCFGR1 register).
Four break outputs are totally available (shared with the analog watchdog function).

26.4.12 Extreme detector

The purpose of an extremes detector is to collect the minimum and maximum values of final
output data words (peak to peak values).
If the output data word is higher than the value stored in the extremes detector maximum
register (EXMAX[23:0] bits in DFSDM_FLTxEXMAX register), then this register is updated
with the current output data word value and the channel from which the data is stored is in
EXMAXCH[1:0] bits (in DFSDM_FLTxEXMAX register) .
If the output data word is lower than the value stored in the extremes detector minimum
register (EXMIN[23:0] bits in DFSDM_FLTxEXMIN register), then this register is updated
with the current output data word value and the channel from which the data is stored is in
EXMINCH[1:0] bits (in DFSDM_FLTxEXMIN register).
The minimum and maximum register values can be refreshed by software (by reading given
DFSDM_FLTxEXMAX or DFSDM_FLTxEXMIN register). After refresh, the extremes
detector minimum data register DFSDM_FLTxEXMIN is filled with 0x7FFFFF (maximum
positive value) and the extremes detector maximum register DFSDM_FLTxEXMAX is filled
with 0x800000 (minimum negative value).
The extremes detector performs a comparison after a right bit shift and an offset data
correction. For each extremes detector, the input channels to be considered into computing
the extremes value are selected in EXCH[3:0] bits (in DFSDM_FLTxCR2 register).

26.4.13 Data unit block

The data unit block is the last block of the whole processing path: External Σ∆ modulators -
Serial transceivers - Sinc filter - Integrator - Data unit block.
The output data rate depends on the serial data stream rate, and filter and integrator
settings. The maximum output data rate is:
f CKIN
Datarate samples ⁄ s = ------------------------------------------------------------------------------------------------------- ...FAST = 0, Sincx filter
F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 )

f CKIN
Datarate samples ⁄ s = -------------------------------------------------------------------------------- ...FAST = 0, FastSinc filter
F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 )

RM0438 Rev 7 887/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

or
f CKIN
Datarate samples ⁄ s = ------------------------------- ...FAST = 1
F OSR ⋅ I OSR

Maximum output data rate in case of parallel data input:

f DATAIN_RATE
Datarate samples ⁄ s = ------------------------------------------------------------------------------------------------------- ...FAST = 0, Sincx filter
F OSR ⋅ ( I OSR – 1 + F ORD ) + ( F ORD + 1 )

or
f DATAIN_RATE
Datarate samples ⁄ s = -------------------------------------------------------------------------------- ...FAST = 0, FastSinc filter
F OSR ⋅ ( I OSR – 1 + 4 ) + ( 2 + 1 )

or
f DATAIN_RATE
Datarate samples ⁄ s = ------------------------------------ ...FAST=1 or any filter bypass case ( F OSR = 1 )
F OSR ⋅ I OSR

where: f DATAIN_RATE ...input data rate from ADC or from CPU/DMA

The right bit-shift of final data is performed in this module because the final data width is 24-
bit and data coming from the processing path can be up to 32 bits. This right bit-shift is
configurable in the range 0-31 bits for each selected input channel (see DTRBS[4:0] bits in
DFSDM_CHyCFGR2 register). The right bit-shift is rounding the result to nearest integer
value. The sign of shifted result is maintained - to have valid 24-bit signed format of result
data.
In the next step, an offset correction of the result is performed. The offset correction value
(OFFSET[23:0] stored in register DFSDM_CHyCFGR2) is subtracted from the output data
for a given channel. Data in the OFFSET[23:0] field is set by software by the appropriate
calibration routine.
Due to the fact that all operations in digital processing are performed on 32-bit signed
registers, the following conditions must be fulfilled not to overflow the result:
FOSR FORD . IOSR <= 231 ... for Sincx filters, x = 1..5)
2 . FOSR 2 . IOSR <= 231 ... for FastSinc filter)
Note: In case of filter and integrator bypass (IOSR[7:0]=0, FOSR[9:0]=0), the input data rate
(fDATAIN_RATE) must be limited to be able to read all output data:
fDATAIN_RATE ≤ fAPB
where fAPB is the bus frequency to which the DFSDM peripheral is connected.

26.4.14 Signed data format

Each DFSDM input serial channel can be connected to one external Σ∆ modulator. An
external Σ∆ modulator can have 2 differential inputs (positive and negative) which can be
used for a differential or single-ended signal measurement.
A Σ∆ modulator output is always assumed in a signed format (a data stream of zeros and
ones from a Σ∆ modulator represents values -1 and +1).

888/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Signed data format in registers: Data is in a signed format in registers for final output
data, analog watchdog, extremes detector, offset correction. The msb of output data word
represents the sign of value (two’s complement format).

26.4.15 Launching conversions

Injected conversions can be launched using the following methods:
• Software: writing ‘1’ to JSWSTART in the DFSDM_FLTxCR1 register.
• Trigger: JEXTSEL[4:0] selects the trigger signal while JEXTEN activates the trigger
and selects the active edge at the same time (see the DFSDM_FLTxCR1 register).
• Synchronous with DFSDM_FLT0 if JSYNC=1: for DFSDM_FLTx (x>0), an injected
conversion is automatically launched when in DFSDM_FLT0; the injected conversion is
started by software (JSWSTART=1 in DFSDM_FLT0CR2 register). Each injected
conversion in DFSDM_FLTx (x>0) is always executed according to its local
configuration settings (JSCAN, JCHG, etc.).
If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is
triggered, all of the selected channels in the injected group (JCHG[3:0] bits in
DFSDM_FLTxJCHGR register) are converted sequentially, starting with the lowest channel
(channel 0, if selected).
If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is
triggered, only one of the selected channels in the injected group (JCHG[3:0] bits in
DFSDM_FLTxJCHGR register) is converted and the channel selection is then moved to the
next selected channel. Writing to the JCHG[3:0] bits when JSCAN=0 sets the channel
selection to the lowest selected injected channel.
Only one injected conversion can be ongoing at a given time. Thus, any request to launch
an injected conversion is ignored if another request for an injected conversion has already
been issued but not yet completed.
Regular conversions can be launched using the following methods:
• Software: by writing ‘1’ to RSWSTART in the DFSDM_FLTxCR1 register.
• Synchronous with DFSDM_FLT0 if RSYNC=1: for DFSDM_FLTx (x>0), a regular
conversion is automatically launched when in DFSDM_FLT0; a regular conversion is
started by software (RSWSTART=1 in DFSDM_FLT0CR2 register). Each regular
conversion in DFSDM_FLTx (x>0) is always executed according to its local
configuration settings (RCONT, RCH, etc.).
Only one regular conversion can be pending or ongoing at a given time. Thus, any request
to launch a regular conversion is ignored if another request for a regular conversion has
already been issued but not yet completed. A regular conversion can be pending if it was
interrupted by an injected conversion or if it was started while an injected conversion was in
progress. This pending regular conversion is then delayed and is performed when all
injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit
in DFSDM_FLTxRDATAR register.

26.4.16 Continuous and fast continuous modes

Setting RCONT in the DFSDM_FLTxCR1 register causes regular conversions to execute in
continuous mode. RCONT=1 means that the channel selected by RCH[1:0] is converted
repeatedly after ‘1’ is written to RSWSTART.

RM0438 Rev 7 889/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

The regular conversions executing in continuous mode can be stopped by writing ‘0’ to
RCONT. After clearing RCONT, the on-going conversion is stopped immediately.
In continuous mode, the data rate can be increased by setting the FAST bit in the
DFSDM_FLTxCR1 register. In this case, the filter does not need to be refilled by new fresh
data if converting continuously from one channel because data inside the filter is valid from
previously sampled continuous data. The speed increase depends on the chosen filter
order. The first conversion in fast mode (FAST=1) after starting a continuous conversion by
RSWSTART=1 takes still full time (as when FAST=0), then each subsequent conversion is
finished in shorter intervals.
Conversion time in continuous mode:
if FAST = 0 (or first conversion if FAST=1):
for Sincx filters:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN
for FastSinc filter:
t = CNVCNT/fDFSDMCLK = [FOSR * (IOSR-1 + 4) + 2] / fCKIN
if FAST = 1 (except first conversion):
for Sincx and FastSinc filters:
t = CNVCNT/fDFSDMCLK = [FOSR * IOSR] / fCKIN
in case FOSR = FOSR[9:0]+1 = 1 (filter bypassed, only integrator active):
t = IOSR / fCKIN (... but CNVCNT=0)
Continuous mode is not available for injected conversions. Injected conversions can be
started by timer trigger to emulate the continuous mode with precise timing.
If a regular continuous conversion is in progress (RCONT=1) and if a write access to
DFSDM_FLTxCR1 register requesting regular continuous conversion (RCONT=1) is
performed, then regular continuous conversion is restarted from the next conversion cycle
(like new regular continuous conversion is applied for new channel selection - even if there
is no change in DFSDM_FLTxCR1 register).

26.4.17 Request precedence

An injected conversion has a higher precedence than a regular conversion. A regular
conversion which is already in progress is immediately interrupted by the request of an
injected conversion; this regular conversion is restarted after the injected conversion
finishes.
An injected conversion cannot be launched if another injected conversion is pending or
already in progress: any request to launch an injected conversion (either by JSWSTART or
by a trigger) is ignored as long as bit JCIP is ‘1’ (in the DFSDM_FLTxISR register).
Similarly, a regular conversion cannot be launched if another regular conversion is pending
or already in progress: any request to launch a regular conversion (using RSWSTART) is
ignored as long as bit RCIP is ‘1’ (in the DFSDM_FLTxISR register).
However, if an injected conversion is requested while a regular conversion is already in
progress, the regular conversion is immediately stopped and an injected conversion is
launched. The regular conversion is then restarted and this delayed restart is signalized in
bit RPEND.
Injected conversions have precedence over regular conversions in that a injected
conversion can temporarily interrupt a sequence of continuous regular conversions. When

890/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

the sequence of injected conversions finishes, the continuous regular conversions start
again if RCONT is still set (and RPEND bit will signalize the delayed start on the first regular
conversion result).
Precedence also matters when actions are initiated by the same write to DFSDM, or if
multiple actions are pending at the end of another action. For example, suppose that, while
an injected conversion is in process (JCIP=1), a single write operation to DFSDM_FLTxCR1
writes ‘1’ to RSWSTART, requesting a regular conversion. When the injected sequence
finishes, the precedence dictates that the regular conversion is performed next and its
delayed start is signalized in RPEND bit.

26.4.18 Power optimization in run mode

In order to reduce the consumption, the DFSDM filter and integrator are automatically put
into idle when not used by conversions (RCIP=0, JCIP=0).

26.5 DFSDM interrupts

In order to increase the CPU performance, a set of interrupts related to the CPU event
occurrence has been implemented:
• End of injected conversion interrupt:
– enabled by JEOCIE bit in DFSDM_FLTxCR2 register
– indicated in JEOCF bit in DFSDM_FLTxISR register
– cleared by reading DFSDM_FLTxJDATAR register (injected data)
– indication of which channel end of conversion occurred, reported in JDATACH[1:0]
bits in DFSDM_FLTxJDATAR register
• End of regular conversion interrupt:
– enabled by REOCIE bit in DFSDM_FLTxCR2 register
– indicated in REOCF bit in DFSDM_FLTxISR register
– cleared by reading DFSDM_FLTxRDATAR register (regular data)
– indication of which channel end of conversion occurred, reported in
RDATACH[1:0] bits in DFSDM_FLTxRDATAR register
• Data overrun interrupt for injected conversions:
– occurred when injected converted data were not read from DFSDM_FLTxJDATAR
register (by CPU or DMA) and were overwritten by a new injected conversion
– enabled by JOVRIE bit in DFSDM_FLTxCR2 register
– indicated in JOVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRJOVRF bit in DFSDM_FLTxICR register
• Data overrun interrupt for regular conversions:
– occurred when regular converted data were not read from DFSDM_FLTxRDATAR
register (by CPU or DMA) and were overwritten by a new regular conversion
– enabled by ROVRIE bit in DFSDM_FLTxCR2 register
– indicated in ROVRF bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRROVRF bit in DFSDM_FLTxICR register
• Analog watchdog interrupt:

RM0438 Rev 7 891/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

– occurred when converted data (output data or data from analog watchdog filter -
according to AWFSEL bit setting in DFSDM_FLTxCR1 register) crosses
over/under high/low thresholds in DFSDM_FLTxAWHTR / DFSDM_FLTxAWLTR
registers
– enabled by AWDIE bit in DFSDM_FLTxCR2 register (on selected channels
AWDCH[3:0])
– indicated in AWDF bit in DFSDM_FLTxISR register
– separate indication of high or low analog watchdog threshold error by AWHTF[3:0]
and AWLTF[3:0] fields in DFSDM_FLTxAWSR register
– cleared by writing ‘1’ into corresponding CLRAWHTF[3:0] or CLRAWLTF[3:0] bits
in DFSDM_FLTxAWCFR register
• Short-circuit detector interrupt:
– occurred when the number of stable data crosses over thresholds in
DFSDM_CHyAWSCDR register
– enabled by SCDIE bit in DFSDM_FLTxCR2 register (on channel selected by
SCDEN bi tin DFSDM_CHyCFGR1 register)
– indicated in SCDF[3:0] bits in DFSDM_FLTxISR register (which also reports the
channel on which the short-circuit detector event occurred)
– cleared by writing ‘1’ into the corresponding CLRSCDF[3:0] bit in
DFSDM_FLTxICR register
• Channel clock absence interrupt:
– occurred when there is clock absence on CKINy pin (see Clock absence detection
in Section 26.4.4: Serial channel transceivers)
– enabled by CKABIE bit in DFSDM_FLTxCR2 register (on channels selected by
CKABEN bit in DFSDM_CHyCFGR1 register)
– indicated in CKABF[y] bit in DFSDM_FLTxISR register
– cleared by writing ‘1’ into CLRCKABF[y] bit in DFSDM_FLTxICR register

Table 204. DFSDM interrupt requests

Event/Interrupt clearing Interrupt enable
Interrupt event Event flag
method control bit

End of injected conversion JEOCF reading DFSDM_FLTxJDATAR JEOCIE

End of regular conversion REOCF reading DFSDM_FLTxRDATAR REOCIE
Injected data overrun JOVRF writing CLRJOVRF = 1 JOVRIE
Regular data overrun ROVRF writing CLRROVRF = 1 ROVRIE
AWDF,
writing CLRAWHTF[3:0] = 1 AWDIE,
Analog watchdog AWHTF[3:0],
writing CLRAWLTF[3:0] = 1 (AWDCH[3:0])
AWLTF[3:0]
SCDIE,
short-circuit detector SCDF[3:0] writing CLRSCDF[3:0] = 1
(SCDEN)
CKABIE,
Channel clock absence CKABF[3:0] writing CLRCKABF[3:0] = 1
(CKABEN)

892/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

26.6 DFSDM DMA transfer

To decrease the CPU intervention, conversions can be transferred into memory using a
DMA transfer. A DMA transfer for injected conversions is enabled by setting bit JDMAEN=1
in DFSDM_FLTxCR1 register. A DMA transfer for regular conversions is enabled by setting
bit RDMAEN=1 in DFSDM_FLTxCR1 register.
Note: With a DMA transfer, the interrupt flag is automatically cleared at the end of the injected or
regular conversion (JEOCF or REOCF bit in DFSDM_FLTxISR register) because DMA is
reading DFSDM_FLTxJDATAR or DFSDM_FLTxRDATAR register.

26.7 DFSDM channel y registers (y=0..3)

Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register. Write access to DFSDM_CHyDATINR register can be either word access (32-bit)
or half-word access (16-bit).

26.7.1 DFSDM channel y configuration register (DFSDM_CHyCFGR1)

This register specifies the parameters used by channel y.
Address offset: 0x00 + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DFSDM CKOUT
Res. Res. Res. Res. Res. Res. CKOUTDIV[7:0]
EN SRC
rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CHIN CKAB
DATPACK[1:0] DATMPX[1:0] Res. Res. Res. CHEN SCDEN Res. SPICKSEL[1:0] SITP[1:0]
SEL EN

rw rw rw rw rw rw rw rw rw rw rw rw

Bit 31 DFSDMEN: Global enable for DFSDM interface

0: DFSDM interface disabled
1: DFSDM interface enabled
If DFSDM interface is enabled, then it is started to operate according to enabled y channels and
enabled x filters settings (CHEN bit in DFSDM_CHyCFGR1 and DFEN bit in DFSDM_FLTxCR1).
Data cleared by setting DFSDMEN=0:
–all registers DFSDM_FLTxISR are set to reset state (x = 0..3)
–all registers DFSDM_FLTxAWSR are set to reset state (x = 0..3)
Note: DFSDMEN is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bit 30 CKOUTSRC: Output serial clock source selection
0: Source for output clock is from system clock
1: Source for output clock is from audio clock
This value can be modified only when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
Note: CKOUTSRC is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bits 29:24 Reserved, must be kept at reset value.

RM0438 Rev 7 893/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bits 23:16 CKOUTDIV[7:0]: Output serial clock divider

0: Output clock generation is disabled (CKOUT signal is set to low state)
1- 255: Defines the division of system clock for the serial clock output for CKOUT signal in range 2 -
256 (Divider = CKOUTDIV+1).
CKOUTDIV also defines the threshold for a clock absence detection.
This value can only be modified when DFSDMEN=0 (in DFSDM_CH0CFGR1 register).
If DFSDMEN=0 (in DFSDM_CH0CFGR1 register) then CKOUT signal is set to low state (setting is
performed one DFSDM clock cycle after DFSDMEN=0).
Note: CKOUTDIV is present only in DFSDM_CH0CFGR1 register (channel y=0)
Bits 15:14 DATPACK[1:0]: Data packing mode in DFSDM_CHyDATINR register.
0: Standard: input data in DFSDM_CHyDATINR register are stored only in INDAT0[15:0]. To empty
DFSDM_CHyDATINR register one sample must be read by the DFSDM filter from channel y.
1: Interleaved: input data in DFSDM_CHyDATINR register are stored as two samples:
–first sample in INDAT0[15:0] (assigned to channel y)
–second sample INDAT1[15:0] (assigned to channel y)
To empty DFSDM_CHyDATINR register, two samples must be read by the digital filter from
channel y (INDAT0[15:0] part is read as first sample and then INDAT1[15:0] part is read as next
sample).
2: Dual: input data in DFSDM_CHyDATINR register are stored as two samples:
–first sample INDAT0[15:0] (assigned to channel y)
–second sample INDAT1[15:0] (assigned to channel y+1)
To empty DFSDM_CHyDATINR register first sample must be read by the digital filter from channel
y and second sample must be read by another digital filter from channel y+1. Dual mode is
available only on even channel numbers (y = 0, 2), for odd channel numbers (y = 1, 3)
DFSDM_CHyDATINR is write protected. If an even channel is set to dual mode then the following
odd channel must be set into standard mode (DATPACK[1:0]=0) for correct cooperation with even
channel.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 13:12 DATMPX[1:0]: Input data multiplexer for channel y
0: Data to channel y are taken from external serial inputs as 1-bit values. DFSDM_CHyDATINR
register is write protected.
1: Data to channel y are taken from internal analog to digital converter ADCy+1 output register
update as 16-bit values (if ADCy+1 is available). Data from ADCs are written into INDAT0[15:0]
part of DFSDM_CHyDATINR register.
2: Data to channel y are taken from internal DFSDM_CHyDATINR register by direct CPU/DMA write.
There can be written one or two 16-bit data samples according DATPACK[1:0] bit field setting.
3: Reserved
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).

Bits 11:9 Reserved, must be kept at reset value.

Bit 8 CHINSEL: Channel inputs selection
0: Channel inputs are taken from pins of the same channel y.
1: Channel inputs are taken from pins of the following channel (channel (y+1) modulo 8).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bit 7 CHEN: Channel y enable
0: Channel y disabled
1: Channel y enabled
If channel y is enabled, then serial data receiving is started according to the given channel setting.

894/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bit 6 CKABEN: Clock absence detector enable on channel y

0: Clock absence detector disabled on channel y
1: Clock absence detector enabled on channel y
Bit 5 SCDEN: Short-circuit detector enable on channel y
0: Input channel y will not be guarded by the short-circuit detector
1: Input channel y will be continuously guarded by the short-circuit detector
Bit 4 Reserved, must be kept at reset value.
Bits 3:2 SPICKSEL[1:0]: SPI clock select for channel y
0: clock coming from external CKINy input - sampling point according SITP[1:0]
1: clock coming from internal CKOUT output - sampling point according SITP[1:0]
2: clock coming from internal CKOUT - sampling point on each second CKOUT falling edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to
generate its output serial communication clock (and this output clock change is active on each
clock input rising edge).
3: clock coming from internal CKOUT output - sampling point on each second CKOUT rising edge.
For connection to external Σ∆ modulator which divides its clock input (from CKOUT) by 2 to
generate its output serial communication clock (and this output clock change is active on each
clock input falling edge).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 1:0 SITP[1:0]: Serial interface type for channel y
00: SPI with rising edge to strobe data
01: SPI with falling edge to strobe data
10: Manchester coded input on DATINy pin: rising edge = logic 0, falling edge = logic 1
11: Manchester coded input on DATINy pin: rising edge = logic 1, falling edge = logic 0
This value can only be modified when CHEN=0 (in DFSDM_CHyCFGR1 register).

26.7.2 DFSDM channel y configuration register (DFSDM_CHyCFGR2)

This register specifies the parameters used by channel y.
Address offset: 0x04 + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

OFFSET[23:8]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OFFSET[7:0] DTRBS[4:0] Res. Res. Res.

rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 895/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bits 31:8 OFFSET[23:0]: 24-bit calibration offset for channel y

For channel y, OFFSET is applied to the results of each conversion from this channel.
This value is set by software.
Bits 7:3 DTRBS[4:0]: Data right bit-shift for channel y
0-31: Defines the shift of the data result coming from the integrator - how many bit shifts to the right
will be performed to have final results. Bit-shift is performed before offset correction. The data shift is
rounding the result to nearest integer value. The sign of shifted result is maintained (to have valid
24-bit signed format of result data).
This value can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bits 2:0 Reserved, must be kept at reset value.

26.7.3 DFSDM channel y analog watchdog and short-circuit detector register

(DFSDM_CHyAWSCDR)
Short-circuit detector and analog watchdog settings for channel y.
Address offset: 0x08 + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. AWFORD[1:0] Res. AWFOSR[4:0]

rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BKSCD[3:0] Res. Res. Res. Res. SCDT[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:22 AWFORD[1:0]: Analog watchdog Sinc filter order on channel y
0: FastSinc filter type
1: Sinc1 filter type
2: Sinc2 filter type
3: Sinc3 filter type x
 1 – z – FOSR
Sincx filter type transfer function: H ( z ) =  ----------------------------
-
 1 – z –1 

2
 1 – z – FOSR – ( 2 ⋅ FOSR )
FastSinc filter type transfer function: H ( z ) =  ----------------------------
- ⋅ ( 1 + z )
 1 – z–1 
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Bit 21 Reserved, must be kept at reset value.
Bits 20:16 AWFOSR[4:0]: Analog watchdog filter oversampling ratio (decimation rate) on channel y
0 - 31: Defines the length of the Sinc type filter in the range 1 - 32 (AWFOSR + 1). This number is
also the decimation ratio of the analog data rate.
This bit can be modified only when CHEN=0 (in DFSDM_CHyCFGR1 register).
Note: If AWFOSR = 0 then the filter has no effect (filter bypass).

896/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bits 15:12 BKSCD[3:0]: Break signal assignment for short-circuit detector on channel y
BKSCD[i] = 0: Break i signal not assigned to short-circuit detector on channel y
BKSCD[i] = 1: Break i signal assigned to short-circuit detector on channel y
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:0 SCDT[7:0]: short-circuit detector threshold for channel y
These bits are written by software to define the threshold counter for the short-circuit detector. If this
value is reached, then a short-circuit detector event occurs on a given channel.

26.7.4 DFSDM channel y watchdog filter data register

(DFSDM_CHyWDATR)
This register contains the data resulting from the analog watchdog filter associated to the
input channel y.
Address offset: 0x0C + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 WDATA[15:0]: Input channel y watchdog data
Data converted by the analog watchdog filter for input channel y. This data is continuously converted
(no trigger) for this channel, with a limited resolution (OSR=1..32/sinc order = 1..3).

26.7.5 DFSDM channel y data input register (DFSDM_CHyDATINR)

This register contains 16-bit input data to be processed by DFSDM filter module. Write
access can be either word access (32-bit) or half-word access (16-bit).
Address offset: 0x10 + 0x20 * y, (y = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

INDAT1[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

INDAT0[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 897/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bits 31:16 INDAT1[15:0]: Input data for channel y or channel y+1

Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if
DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
INDAT0[15:0] is write protected (not used for input sample).
If DATPACK[1:0]=1 (interleaved mode)
Second channel y data sample is stored into INDAT1[15:0]. First channel y data sample is stored
into INDAT0[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y
data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: sample in INDAT1[15:0] is automatically copied into INDAT0[15:0] of
channel (y+1).
For odd y channels: INDAT1[15:0] is write protected.
See Section 26.4.6: Parallel data inputs for more details.
INDAT0[15:1] is in the16-bit signed format.
Bits 15:0 INDAT0[15:0]: Input data for channel y
Input parallel channel data to be processed by the digital filter if DATMPX[1:0]=1 or DATMPX[1:0]=2.
Data can be written by CPU/DMA (if DATMPX[1:0]=2) or directly by internal ADC (if
DATMPX[1:0]=1).
If DATPACK[1:0]=0 (standard mode)
Channel y data sample is stored into INDAT0[15:0].
If DATPACK[1:0]=1 (interleaved mode)
First channel y data sample is stored into INDAT0[15:0]. Second channel y data sample is stored
into INDAT1[15:0]. Both samples are read sequentially by DFSDM_FLTx filter as two channel y
data samples.
If DATPACK[1:0]=2 (dual mode).
For even y channels: Channel y data sample is stored into INDAT0[15:0].
For odd y channels: INDAT0[15:0] is write protected.
See Section 26.4.6: Parallel data inputs for more details.
INDAT0[15:0] is in the16-bit signed format.

26.7.6 DFSDM channel y delay register (DFSDM_CHyDLYR)

Address offset: 0x14 + 0x20 * y, (y = 0 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PLSSKP[5:0]

rw rw rw rw rw rw

898/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bits 31:6 Reserved, must be kept at reset value.

Bits 5:0 PLSSKP[5:0]: Pulses to skip for input data skipping function
0-63: Defines the number of serial input samples that will be skipped. Skipping is applied
immediately after writing to this field. Reading of PLSSKP[5:0] returns current value of pulses which
will be skipped. If PLSSKP[5:0]=0 then all required data samples were already skipped.
Note: User can update PLSSKP[5:0] also when PLSSKP[5:0] is not zero.

26.8 DFSDM filter x module registers (x=0..3)

Word access (32-bit) must be used for registers write access except DFSDM_CHyDATINR
register.

26.8.1 DFSDM filter x control register 1 (DFSDM_FLTxCR1)

Address offset: 0x100 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AWF RDMA RCON RSW
Res. FAST Res. Res. Res. RCH[1:0] Res. Res. Res. RSYNC Res.
SEL EN T START
rw rw rw rw rw rw rw rt_w1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JDMA JSW
Res. JEXTEN[1:0] JEXTSEL[4:0] Res. Res. JSCAN JSYNC Res. DFEN
EN START
rw rw rw rw rw rw rw rw rw rw rt_w1 rw

Bit 31 Reserved, must be kept at reset value.

Bit 30 AWFSEL: Analog watchdog fast mode select
0: Analog watchdog on data output value (after the digital filter). The comparison is done after offset
correction and shift
1: Analog watchdog on channel transceivers value (after watchdog filter)
Bit 29 FAST: Fast conversion mode selection for regular conversions
0: Fast conversion mode disabled
1: Fast conversion mode enabled
When converting a regular conversion in continuous mode, having enabled the fast mode causes
each conversion (except the first) to execute faster than in standard mode. This bit has no effect on
conversions which are not continuous.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
t = IOSR / fCKIN (... but CNVCNT=0)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input.
Bits 28:26 Reserved, must be kept at reset value.

RM0438 Rev 7 899/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bits 25:24 RCH[1:0]: Regular channel selection

0: Channel 0 is selected as the regular channel
1: Channel 1 is selected as the regular channel
...
3: Chanel 3 is selected as the regular channel
Writing this bit when RCIP=1 takes effect when the next regular conversion begins. This is
especially useful in continuous mode (when RCONT=1). It also affects regular conversions which
are pending (due to ongoing injected conversion).
Bits 23:22 Reserved, must be kept at reset value.
Bit 21 RDMAEN: DMA channel enabled to read data for the regular conversion
0: The DMA channel is not enabled to read regular data
1: The DMA channel is enabled to read regular data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 20 Reserved, must be kept at reset value.
Bit 19 RSYNC: Launch regular conversion synchronously with DFSDM_FLT0
0: Do not launch a regular conversion synchronously with DFSDM_FLT0
1: Launch a regular conversion in this DFSDM_FLTx at the very moment when a regular conversion
is launched in DFSDM_FLT0
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 18 RCONT: Continuous mode selection for regular conversions
0: The regular channel is converted just once for each conversion request
1: The regular channel is converted repeatedly after each conversion request
Writing ‘0’ to this bit while a continuous regular conversion is already in progress stops the
continuous mode immediately.

Bit 17 RSWSTART: Software start of a conversion on the regular channel

0: Writing ‘0’ has no effect
1: Writing ‘1’ makes a request to start a conversion on the regular channel and causes RCIP to
become ‘1’. If RCIP=1 already, writing to RSWSTART has no effect. Writing ‘1’ has no effect if
RSYNC=1.
This bit is always read as ‘0’.
Bits 16:15 Reserved, must be kept at reset value.
Bits 14:13 JEXTEN[1:0]: Trigger enable and trigger edge selection for injected conversions
00: Trigger detection is disabled
01: Each rising edge on the selected trigger makes a request to launch an injected conversion
10: Each falling edge on the selected trigger makes a request to launch an injected conversion
11: Both rising edges and falling edges on the selected trigger make requests to launch injected
conversions
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).

900/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bits 12:8 JEXTSEL[4:0]: Trigger signal selection for launching injected conversions
0x0-0x1F: Trigger inputs selected by the following table (internal or external trigger).
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Note: synchronous trigger has latency up to one fDFSDMCLK clock cycle (with deterministic jitter),
asynchronous trigger has latency 2-3 fDFSDMCLK clock cycles (with jitter up to 1 cycle).

DFSDM_FLTx
0x00 dfsdm_jtrg0
0x01 dfsdm_jtrg1
...
0x1E dfsdm_jtrg30
0x1F dfsdm_jtrg31
Refer to Table 200: DFSDM triggers connection.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 JDMAEN: DMA channel enabled to read data for the injected channel group
0: The DMA channel is not enabled to read injected data
1: The DMA channel is enabled to read injected data
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 4 JSCAN: Scanning conversion mode for injected conversions
0: One channel conversion is performed from the injected channel group and next the selected
channel from this group is selected.
1: The series of conversions for the injected group channels is executed, starting over with the
lowest selected channel.
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Writing JCHG if JSCAN=0 resets the channel selection to the lowest selected channel.
Bit 3 JSYNC: Launch an injected conversion synchronously with the DFSDM_FLT0 JSWSTART trigger
0: Do not launch an injected conversion synchronously with DFSDM_FLT0
1: Launch an injected conversion in this DFSDM_FLTx at the very moment when an injected
conversion is launched in DFSDM_FLT0 by its JSWSTART trigger
This bit can be modified only when DFEN=0 (DFSDM_FLTxCR1).
Bit 2 Reserved, must be kept at reset value.
Bit 1 JSWSTART: Start a conversion of the injected group of channels
0: Writing ‘0’ has no effect.
1: Writing ‘1’ makes a request to convert the channels in the injected conversion group, causing
JCIP to become ‘1’ at the same time. If JCIP=1 already, then writing to JSWSTART has no effect.
Writing ‘1’ has no effect if JSYNC=1.
This bit is always read as ‘0’.
Bit 0 DFEN: DFSDM_FLTx enable
0: DFSDM_FLTx is disabled. All conversions of given DFSDM_FLTx are stopped immediately and
all DFSDM_FLTx functions are stopped.
1: DFSDM_FLTx is enabled. If DFSDM_FLTx is enabled, then DFSDM_FLTx starts operating
according to its setting.
Data which are cleared by setting DFEN=0:
–register DFSDM_FLTxISR is set to the reset state
–register DFSDM_FLTxAWSR is set to the reset state

RM0438 Rev 7 901/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

26.8.2 DFSDM filter x control register 2 (DFSDM_FLTxCR2)

Address offset: 0x104 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AWDCH[3:0]

rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CKAB ROVR JOVR REOC JEOC
Res. Res. Res. Res. EXCH[3:0] Res. SCDIE AWDIE
IE IE IE IE IE
rw rw rw rw rw rw rw rw rw rw rw

Bits 31:20 Reserved, must be kept at reset value.

Bits 19:16 AWDCH[3:0]: Analog watchdog channel selection
These bits select the input channel to be guarded continuously by the analog watchdog.
AWDCH[y] = 0: Analog watchdog is disabled on channel y
AWDCH[y] = 1: Analog watchdog is enabled on channel y
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:8 EXCH[3:0]: Extremes detector channel selection
These bits select the input channels to be taken by the Extremes detector.
EXCH[y] = 0: Extremes detector does not accept data from channel y
EXCH[y] = 1: Extremes detector accepts data from channel y
Bit 7 Reserved, must be kept at reset value.
Bit 6 CKABIE: Clock absence interrupt enable
0: Detection of channel input clock absence interrupt is disabled
1: Detection of channel input clock absence interrupt is enabled
Please see the explanation of CKABF[3:0] in DFSDM_FLTxISR.
Note: CKABIE is present only in DFSDM_FLT0CR2 register (filter x=0)
Bit 5 SCDIE: Short-circuit detector interrupt enable
0: short-circuit detector interrupt is disabled
1: short-circuit detector interrupt is enabled
Please see the explanation of SCDF[3:0] in DFSDM_FLTxISR.
Note: SCDIE is present only in DFSDM_FLT0CR2 register (filter x=0)
Bit 4 AWDIE: Analog watchdog interrupt enable
0: Analog watchdog interrupt is disabled
1: Analog watchdog interrupt is enabled
Please see the explanation of AWDF in DFSDM_FLTxISR.
Bit 3 ROVRIE: Regular data overrun interrupt enable
0: Regular data overrun interrupt is disabled
1: Regular data overrun interrupt is enabled
Please see the explanation of ROVRF in DFSDM_FLTxISR.

902/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bit 2 JOVRIE: Injected data overrun interrupt enable

0: Injected data overrun interrupt is disabled
1: Injected data overrun interrupt is enabled
Please see the explanation of JOVRF in DFSDM_FLTxISR.
Bit 1 REOCIE: Regular end of conversion interrupt enable
0: Regular end of conversion interrupt is disabled
1: Regular end of conversion interrupt is enabled
Please see the explanation of REOCF in DFSDM_FLTxISR.
Bit 0 JEOCIE: Injected end of conversion interrupt enable
0: Injected end of conversion interrupt is disabled
1: Injected end of conversion interrupt is enabled
Please see the explanation of JEOCF in DFSDM_FLTxISR.

26.8.3 DFSDM filter x interrupt and status register (DFSDM_FLTxISR)

Address offset: 0x108 + 0x80 * x, (x = 0 to 3)
Reset value: 0x00FF 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. SCDF[3:0] Res. Res. Res. Res. CKABF[3:0]

r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. RCIP JCIP Res. Res. Res. Res. Res. Res. Res. Res. AWDF ROVRF JOVRF REOCF JEOCF

r r r r r r r

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 SCDF[3:0]: short-circuit detector flag
SDCF[y]=0: No short-circuit detector event occurred on channel y
SDCF[y]=1: The short-circuit detector counter reaches, on channel y, the value programmed in the
DFSDM_CHyAWSCDR registers
This bit is set by hardware. It can be cleared by software using the corresponding CLRSCDF[y] bit in
the DFSDM_FLTxICR register. SCDF[y] is cleared also by hardware when CHEN[y] = 0 (given
channel is disabled).
Note: SCDF[3:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 CKABF[3:0]: Clock absence flag
CKABF[y]=0: Clock signal on channel y is present.
CKABF[y]=1: Clock signal on channel y is not present.
Given y bit is set by hardware when clock absence is detected on channel y. It is held at
CKABF[y]=1 state by hardware when CHEN=0 (see DFSDM_CHyCFGR1 register). It is held at
CKABF[y]=1 state by hardware when the transceiver is not yet synchronized.It can be cleared by
software using the corresponding CLRCKABF[y] bit in the DFSDM_FLTxICR register.
Note: CKABF[3:0] is present only in DFSDM_FLT0ISR register (filter x=0)
Bit 15 Reserved, must be kept at reset value.

RM0438 Rev 7 903/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bit 14 RCIP: Regular conversion in progress status

0: No request to convert the regular channel has been issued
1: The conversion of the regular channel is in progress or a request for a regular conversion is
pending
A request to start a regular conversion is ignored when RCIP=1.
Bit 13 JCIP: Injected conversion in progress status
0: No request to convert the injected channel group (neither by software nor by trigger) has been
issued
1: The conversion of the injected channel group is in progress or a request for a injected conversion
is pending, due either to ‘1’ being written to JSWSTART or to a trigger detection
A request to start an injected conversion is ignored when JCIP=1.
Bits 12:5 Reserved, must be kept at reset value.
Bit 4 AWDF: Analog watchdog
0: No Analog watchdog event occurred
1: The analog watchdog block detected voltage which crosses the value programmed in the
DFSDM_FLTxAWLTR or DFSDM_FLTxAWHTR registers.
This bit is set by hardware. It is cleared by software by clearing all source flag bits AWHTF[3:0] and
AWLTF[3:0] in DFSDM_FLTxAWSR register (by writing ‘1’ into the clear bits in
DFSDM_FLTxAWCFR register).
Bit 3 ROVRF: Regular conversion overrun flag
0: No regular conversion overrun has occurred
1: A regular conversion overrun has occurred, which means that a regular conversion finished while
REOCF was already ‘1’. RDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRROVRF bit in the
DFSDM_FLTxICR register.
Bit 2 JOVRF: Injected conversion overrun flag
0: No injected conversion overrun has occurred
1: An injected conversion overrun has occurred, which means that an injected conversion finished
while JEOCF was already ‘1’. JDATAR is not affected by overruns
This bit is set by hardware. It can be cleared by software using the CLRJOVRF bit in the
DFSDM_FLTxICR register.
Bit 1 REOCF: End of regular conversion flag
0: No regular conversion has completed
1: A regular conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxRDATAR.
Bit 0 JEOCF: End of injected conversion flag
0: No injected conversion has completed
1: An injected conversion has completed and its data may be read
This bit is set by hardware. It is cleared when the software or DMA reads DFSDM_FLTxJDATAR.

Note: For each of the flag bits, an interrupt can be enabled by setting the corresponding bit in
DFSDM_FLTxCR2. If an interrupt is called, the flag must be cleared before exiting the
interrupt service routine.
All the bits of DFSDM_FLTxISR are automatically reset when DFEN=0.

904/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

26.8.4 DFSDM filter x interrupt flag clear register (DFSDM_FLTxICR)

Address offset: 0x10C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. CLRSCDF[3:0] Res. Res. Res. Res. CLRCKABF[3:0]

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLRR CLRJ
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
OVRF OVRF
rc_w1 rc_w1

Bits 31:28 Reserved, must be kept at reset value.

Bits 27:24 CLRSCDF[3:0]: Clear the short-circuit detector flag
CLRSCDF[y]=0: Writing ‘0’ has no effect
CLRSCDF[y]=1: Writing ‘1’ to position y clears the corresponding SCDF[y] bit in the
DFSDM_FLTxISR register
Note: CLRSCDF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0)
Bits 23:20 Reserved, must be kept at reset value.
Bits 19:16 CLRCKABF[3:0]: Clear the clock absence flag
CLRCKABF[y]=0: Writing ‘0’ has no effect
CLRCKABF[y]=1: Writing ‘1’ to position y clears the corresponding CKABF[y] bit in the
DFSDM_FLTxISR register. When the transceiver is not yet synchronized, the clock absence flag is
set and cannot be cleared by CLRCKABF[y].
Note: CLRCKABF[3:0] is present only in DFSDM_FLT0ICR register (filter x=0)
Bits 15:4 Reserved, must be kept at reset value.
Bit 3 CLRROVRF: Clear the regular conversion overrun flag
0: Writing ‘0’ has no effect
1: Writing ‘1’ clears the ROVRF bit in the DFSDM_FLTxISR register
Bit 2 CLRJOVRF: Clear the injected conversion overrun flag
0: Writing ‘0’ has no effect
1: Writing ‘1’ clears the JOVRF bit in the DFSDM_FLTxISR register
Bits 1:0 Reserved, must be kept at reset value.

Note: The bits of DFSDM_FLTxICR are always read as ‘0’.

RM0438 Rev 7 905/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

26.8.5 DFSDM filter x injected channel group selection register

(DFSDM_FLTxJCHGR)
Address offset: 0x110 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. JCHG[3:0]

rw rw rw rw

Bits 31:4 Reserved, must be kept at reset value.

Bits 3:0 JCHG[3:0]: Injected channel group selection
JCHG[y]=0: channel y is not part of the injected group
JCHG[y]=1: channel y is part of the injected group
If JSCAN=1, each of the selected channels is converted, one after another. The lowest channel
(channel 0, if selected) is converted first and the sequence ends at the highest selected channel.
If JSCAN=0, then only one channel is converted from the selected channels, and the channel
selection is moved to the next channel. Writing JCHG, if JSCAN=0, resets the channel selection to
the lowest selected channel.
At least one channel must always be selected for the injected group. Writes causing all JCHG bits to
be zero are ignored.

26.8.6 DFSDM filter x control register (DFSDM_FLTxFCR)

Address offset: 0x114 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FORD[2:0] Res. Res. Res. FOSR[9:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. IOSR[7:0]

rw rw rw rw rw rw rw rw

906/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bits 31:29 FORD[2:0]: Sinc filter order

0: FastSinc filter type
1: Sinc1 filter type
2: Sinc2 filter type
3: Sinc3 filter type
4: Sinc4 filter type
5: Sinc5 filter type
6-7: Reserved x
 1 – z –FOSR
Sincx filter type transfer function: H ( z ) =  ----------------------------
-
 1 – z –1 

2
 1 – z –FOSR
FastSinc filter type transfer function: - ⋅ ( 1 + z –( 2 ⋅ FOSR ) )
H ( z ) =  ----------------------------
 1 – z –1 
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1).
Bits 28:26 Reserved, must be kept at reset value.
Bits 25:16 FOSR[9:0]: Sinc filter oversampling ratio (decimation rate)
0 - 1023: Defines the length of the Sinc type filter in the range 1 - 1024 (FOSR = FOSR[9:0] +1). This
number is also the decimation ratio of the output data rate from filter.
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If FOSR = 0, then the filter has no effect (filter bypass).
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 IOSR[7:0]: Integrator oversampling ratio (averaging length)
0- 255: The length of the Integrator in the range 1 - 256 (IOSR + 1). Defines how many samples
from Sinc filter will be summed into one output data sample from the integrator. The output data rate
from the integrator will be decreased by this number (additional data decimation ratio).
This bit can only be modified when DFEN=0 (DFSDM_FLTxCR1)
Note: If IOSR = 0, then the Integrator has no effect (Integrator bypass).

26.8.7 DFSDM filter x data register for injected group

(DFSDM_FLTxJDATAR)
Address offset: 0x118 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

JDATA[23:8]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JDATA[7:0] Res. Res. Res. Res. Res. Res. JDATACH[1:0]

r r r r r r r r r r

RM0438 Rev 7 907/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bits 31:8 JDATA[23:0]: Injected group conversion data

When each conversion of a channel in the injected group finishes, its resulting data is stored in this
field. The data is valid when JEOCF=1. Reading this register clears the corresponding JEOCF.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 JDATACH[1:0]: Injected channel most recently converted
When each conversion of a channel in the injected group finishes, JDATACH[1:0] is updated to
indicate which channel was converted. Thus, JDATA[23:0] holds the data that corresponds to the
channel indicated by JDATACH[1:0].

Note: DMA may be used to read the data from this register. Half-word accesses may be used to
read only the MSBs of conversion data.
Reading this register also clears JEOCF in DFSDM_FLTxISR. Thus, the firmware must not
read this register if DMA is activated to read data from this register.

26.8.8 DFSDM filter x data register for the regular channel

(DFSDM_FLTxRDATAR)
Address offset: 0x11C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RDATA[23:8]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RDATA[7:0] Res. Res. Res. RPEND Res. Res. RDATACH[1:0]

r r r r r r r r r r r

Bits 31:8 RDATA[23:0]: Regular channel conversion data

When each regular conversion finishes, its data is stored in this register. The data is valid when
REOCF=1. Reading this register clears the corresponding REOCF.
Bits 7:5 Reserved, must be kept at reset value.
Bit 4 RPEND: Regular channel pending data
Regular data in RDATA[23:0] was delayed due to an injected channel trigger during the conversion
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 RDATACH[1:0]: Regular channel most recently converted
When each regular conversion finishes, RDATACH[1:0] is updated to indicate which channel was
converted (because regular channel selection RCH[1:0] in DFSDM_FLTxCR1 register can be
updated during regular conversion). Thus RDATA[23:0] holds the data that corresponds to the
channel indicated by RDATACH[1:0].

Note: Half-word accesses may be used to read only the MSBs of conversion data.
Reading this register also clears REOCF in DFSDM_FLTxISR.

908/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

26.8.9 DFSDM filter x analog watchdog high threshold register

(DFSDM_FLTxAWHTR)
Address offset: 0x120 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AWHT[23:8]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWHT[7:0] Res. Res. Res. Res. BKAWH[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:8 AWHT[23:0]: Analog watchdog high threshold

These bits are written by software to define the high threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), the higher 16 bits (AWHT[23:8]) define the
16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWHT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWH[3:0]: Break signal assignment to analog watchdog high threshold event
BKAWH[i] = 0: Break i signal is not assigned to an analog watchdog high threshold event
BKAWH[i] = 1: Break i signal is assigned to an analog watchdog high threshold event

26.8.10 DFSDM filter x analog watchdog low threshold register

(DFSDM_FLTxAWLTR)
Address offset: 0x124 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AWLT[23:8]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

AWLT[7:0] Res. Res. Res. Res. BKAWL[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 909/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

Bits 31:8 AWLT[23:0]: Analog watchdog low threshold

These bits are written by software to define the low threshold for the analog watchdog.
Note: In case channel transceivers monitor (AWFSEL=1), only the higher 16 bits (AWLT[23:8]) define
the 16-bit threshold as compared with the analog watchdog filter output (because data coming
from the analog watchdog filter are up to a 16-bit resolution). Bits AWLT[7:0] are not taken into
comparison in this case.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 BKAWL[3:0]: Break signal assignment to analog watchdog low threshold event
BKAWL[i] = 0: Break i signal is not assigned to an analog watchdog low threshold event
BKAWL[i] = 1: Break i signal is assigned to an analog watchdog low threshold event

26.8.11 DFSDM filter x analog watchdog status register

(DFSDM_FLTxAWSR)
Address offset: 0x128 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. AWHTF[3:0] Res. Res. Res. Res. AWLTF[3:0]

r r r r r r r r

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:8 AWHTF[3:0]: Analog watchdog high threshold flag
AWHTF[y]=1 indicates a high threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWHTF[y] bit in the DFSDM_FLTxAWCFR register.
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 AWLTF[3:0]: Analog watchdog low threshold flag
AWLTF[y]=1 indicates a low threshold error on channel y. It is set by hardware. It can be cleared by
software using the corresponding CLRAWLTF[y] bit in the DFSDM_FLTxAWCFR register.

Note: All the bits of DFSDM_FLTxAWSR are automatically reset when DFEN=0.

910/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

26.8.12 DFSDM filter x analog watchdog clear flag register

(DFSDM_FLTxAWCFR)
Address offset: 0x12C + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. CLRAWHTF[3:0] Res. Res. Res. Res. CLRAWLTF[3:0]

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:12 Reserved, must be kept at reset value.

Bits 11:8 CLRAWHTF[3:0]: Clear the analog watchdog high threshold flag
CLRAWHTF[y]=0: Writing ‘0’ has no effect
CLRAWHTF[y]=1: Writing ‘1’ to position y clears the corresponding AWHTF[y] bit in the
DFSDM_FLTxAWSR register
Bits 7:4 Reserved, must be kept at reset value.
Bits 3:0 CLRAWLTF[3:0]: Clear the analog watchdog low threshold flag
CLRAWLTF[y]=0: Writing ‘0’ has no effect
CLRAWLTF[y]=1: Writing ‘1’ to position y clears the corresponding AWLTF[y] bit in the
DFSDM_FLTxAWSR register

26.8.13 DFSDM filter x extremes detector maximum register

(DFSDM_FLTxEXMAX)
Address offset: 0x130 + 0x80 * x, (x = 0 to 3)
Reset value: 0x8000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXMAX[23:8]

rs_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXMAX[7:0] Res. Res. Res. Res. Res. Res. EXMAXCH[1:0]

rc_r rc_r rc_r rc_r rc_r rc_r rc_r rc_r r r

Bits 31:8 EXMAX[23:0]: Extremes detector maximum value

These bits are set by hardware and indicate the highest value converted by DFSDM_FLTx.
EXMAX[23:0] bits are reset to value (0x800000) by reading of this register.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 EXMAXCH[1:0]: Extremes detector maximum data channel.
These bits contains information about the channel on which the data is stored into EXMAX[23:0].
Bits are cleared by reading of this register.

RM0438 Rev 7 911/2194

920
Digital filter for sigma delta modulators (DFSDM) RM0438

26.8.14 DFSDM filter x extremes detector minimum register

(DFSDM_FLTxEXMIN)
Address offset: 0x134 + 0x80 * x, (x = 0 to 3)
Reset value: 0x7FFF FF00

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

EXMIN[23:8]

rc_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXMIN[7:0] Res. Res. Res. Res. Res. Res. EXMINCH[1:0]

rs_r rs_r rs_r rs_r rs_r rs_r rs_r rs_r r r

Bits 31:8 EXMIN[23:0]: Extremes detector minimum value

These bits are set by hardware and indicate the lowest value converted by DFSDM_FLTx.
EXMIN[23:0] bits are reset to value (0x7FFFFF) by reading of this register.
Bits 7:2 Reserved, must be kept at reset value.
Bits 1:0 EXMINCH[1:0]: Extremes detector minimum data channel
These bits contain information about the channel on which the data is stored into EXMIN[23:0]. Bits
are cleared by reading of this register.

26.8.15 DFSDM filter x conversion timer register (DFSDM_FLTxCNVTIMR)

Address offset: 0x138 + 0x80 * x, (x = 0 to 3)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CNVCNT[27:12]

r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNVCNT[11:0] Res. Res. Res. Res.

r r r r r r r r r r r r

912/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Bits 31:4 CNVCNT[27:0]: 28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDMCLK
The timer has an input clock from DFSDM clock (system clock fDFSDMCLK). Conversion time
measurement is started on each conversion start and stopped when conversion finishes (interval
between first and last serial sample). Only in case of filter bypass (FOSR[9:0] = 0) is the conversion
time measurement stopped and CNVCNT[27:0] = 0. The counted time is:
if FAST=0 (or first conversion in continuous mode if FAST=1):
t = [FOSR * (IOSR-1 + FORD) + FORD] / fCKIN..... for Sincx filters
t = [FOSR * (IOSR-1 + 4) + 2] / fCKIN..... for FastSinc filter
if FAST=1 in continuous mode (except first conversion):
t = [FOSR * IOSR] / fCKIN
in case if FOSR = FOSR[9:0]+1 = 1 (filter bypassed, active only integrator):
CNVCNT = 0 (counting is stopped, conversion time: t = IOSR / fCKIN)
where: fCKIN is the channel input clock frequency (on given channel CKINy pin) or input data rate in
case of parallel data input (from internal ADC or from CPU/DMA write)
Note: When conversion is interrupted (e.g. by disable/enable selected channel) the timer counts also
this interruption time.
Bits 3:0 Reserved, must be kept at reset value.

26.8.16 DFSDM register map

The following table summarizes the DFSDM registers.

Table 205. DFSDM register map and reset values

Register
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
DATPACK[1:0]

DATMPX[1:0]
CKOUTSRC
DFSDMEN

SPICKSEL
CHINSEL

SITP[1:0]
CKABEN
SCDEN
CHEN
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.

Res.

[1:0]
CKOUTDIV[7:0]
0x00 CH0CFGR1

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
OFFSET[23:0] DTRBS[4:0]
0x04 CH0CFGR2
reset value 0 0
AWFORD

DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.
Res.
Res.
[1:0]

AWFOSR[4:0] BKSCD[3:0] SCDT[7:0]

0x08 CH0AWSCDR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

WDATA[15:0]
0x0C CH0WDATR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
INDAT1[15:0] INDAT0[15:0]
0x10 CH0DATINR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

PLSSKP[5:0]
0x14 CH0DLYR
reset value 0 0 0 0 0 0
0x18 -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x1C

RM0438 Rev 7 913/2194

920
 0x54
0x50
0x48
0x44
0x40
0x34
0x30
0x28
0x24
0x20

0x5C
0x4C
0x3C
0x2C

0x58 -
0x38 -
Offset

914/2194
name

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved
Reserved

CH2DLYR
CH1DLYR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

CH2CFGR2
CH2CFGR1
CH1CFGR2
CH1CFGR1

CH2WDATR
CH1WDATR

CH2DATINR
CH1DATINR

CH2AWSCDR
CH1AWSCDR

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 30

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 29

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 25

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 23

AWFORD[1:0] AWFORD[1:0]

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

INDAT1[15:0]
INDAT1[15:0]
22

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 20

Digital filter for sigma delta modulators (DFSDM)

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 19

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

OFFSET[23:0]
OFFSET[23:0]

18

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res.

RM0438 Rev 7
17

AWFOSR[4:0]
AWFOSR[4:0]

0
0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 16

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 15

DATPACK[1:0] DATPACK[1:0]

0
0

0
0
0
0
0
0
0
0

Res. Res. Res. Res. 14

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 13

DATMPX[1:0] DATMPX[1:0]

BKSCD[3:0]
BKSCD[3:0]

0
0
0
0

0
0
0
0
0
0

Res. Res. Res. Res. 12

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. Res. 9

0
0
0
0

0
0
0
0

Res. Res. Res. CHINSEL Res. Res. Res. CHINSEL 8

Table 205. DFSDM register map and reset values (continued)

0
0
0
0

0
0
0
0
0
0

Res. Res. CHEN Res. Res. CHEN 7

0
0
0
0

0
0
0
0
0
0

Res. Res. CKABEN Res. Res. CKABEN

WDATA[15:0]
WDATA[15:0]

INDAT0[15:0]
INDAT0[15:0]

0
0
0
0

0
0
0
0
0
0

0
0

Res. SCDEN Res. SCDEN 5

0
0
0
0

0
0
0
0

0
0

Res. Res. Res. Res. 4

DTRBS[4:0]
DTRBS[4:0]

0
0
0
0

0
0

0
0
0
0

0
0

Res. Res. SPICKSEL 3

SPICKSEL[1:0]

SCDT[7:0]
SCDT[7:0]

[1:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 2

0
0

0
0
0
0

0
0
0
0

PLSSKP[5:0]
PLSSKP[5:0]

Res. Res. Res. Res. 1

SITP[1:0] SITP[1:0]

0
0

0
0
0
0

0
0
0
0

Res. Res. Res. Res. 0

RM0438
 0x74
0x70
0x68
0x64
0x60

0x6C

0xFC

0x114
0x110
0x108
0x104
0x100
0x78 -

0x10C
Offset
RM0438

name

FLT0ISR

FLT0ICR

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved

FLT0CR2
FLT0CR1

FLT0FCR
CH3DLYR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

CH3CFGR2
CH3CFGR1

CH3WDATR

CH3DATINR

FLT0JCHGR
CH3AWSCDR

0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
FORD[2:0] Res. Res. Res. Res. AWFSEL Res. Res. Res. Res. Res. 30

0
0
0
0
Res. Res. Res. Res. FAST Res. Res. Res. Res. Res. 29

0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
Res. Res. Res. Res. Res. Res. Res. Res. Res. 26

[3:0]

0
0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. 25
RCH[1:0]

SCDF[3:0]

CLRSCDF

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 24

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 23

AWFORD[1:0]

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res.

INDAT1[15:0]
22

0
0
0
0

Res. Res. Res. Res. RDMAEN Res. Res. Res. Res. Res. 21

0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. 20

FOSR[9:0]

0
0
1
0
0
0
0
0

Res. RSYNC Res. Res. Res. Res. 19

0
0
1
0
0
0
0
0

Res. RCONT Res. Res. Res. Res.

OFFSET[23:0]

18

[3:0]

0
0
1
0
0
0
0
0

Res. RSW START Res. Res. Res. Res.

RM0438 Rev 7
17
AWFOSR[4:0]

CKABF[3:0]

CLRCKABF

0
0
1
0
0
0
0

AWDCH[3:0]
Res. Res. Res. Res. Res. Res. 16

0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 15

DATPACK[1:0]

0
0
0
0
0
0
0

Res. Res. Res. RCIP Res. Res. Res. 14

JEXTEN[1:0]

0
0
0
0

0
0
0

Res. Res. Res. JCIP Res. Res. Res. 13

DATMPX[1:0]
BKSCD[3:0]

0
0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. 12

0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 11

0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 10

0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 9

JEXTSEL[4:0]

EXCH[3:0]
0

0
0
0

0
0

Res. Res. Res. Res. Res. Res. Res. CHINSEL 8

Table 205. DFSDM register map and reset values (continued)

0
0
0

0
0
0

Res. Res. Res. Res. Res. Res. Res. CHEN 7

0
0
0

0
0
0
0

Res. Res. Res. CKABIE Res. Res. Res. CKABEN

WDATA[15:0]

INDAT0[15:0]

0
0
0
0

0
0
0
0

Res. Res. Res. SCDIE JDMAEN Res. SCDEN 5

0
0
0
0

0
0
0
0

Res. Res. AWDF AWDIE JSCAN Res. Res. 4

DTRBS[4:0]

0
0
0

0
0
0
0
0
0

0
0

0
CLR ROVRF ROVRF ROVRIE JSYNC Res. 3
SPICKSEL[1:0]

IOSR[7:0]
SCDT[7:0]

0
0

0
0
0
0
0
0

0
0

CLR JOVRF JOVRF JOVRIE Res. Res. Res. 2

0
0
0

0
0
0
0
0

0
0
PLSSKP[5:0]

Res. REOCF REOCIE JSW START Res. Res. 1

SITP[1:0]

JCHG[3:0]

0
0
0

0
0
0
0
0

1
0

Res. JEOCF JEOCIE DFEN Res. Res. 0

Digital filter for sigma delta modulators (DFSDM)

915/2194
920
Digital filter for sigma delta modulators (DFSDM) RM0438

Table 205. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

JDATACH [1:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
Res.
JDATA[23:0]
0x118 FLT0JDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDATACH[1:0]
RPEND
DFSDM_

Res.
Res.
Res.

Res.
Res.
RDATA[23:0]
0x11C FLT0RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWHT[23:0] BKAWH[3:0]
0x120 FLT0AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWLT[23:0] BKAWL[3:0]
0x124 FLT0AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
AWHTF[3:0] AWLTF[3:0]
0x128 FLT0AWSR
reset value 0 0 0 0 0 0 0 0
DFSDM_ CLRAWHTF CLRAWLTF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
0x12C FLT0AWCFR [3:0] [3:0]
reset value 0 0 0 0 0 0 0 0

EXMAXCH[1:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
Res.
EXMAX[23:0]
0x130 FLT0EXMAX

reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXMINCH[1:0]
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
FLT0EXMIN EXMIN[23:0]
0x134

reset value 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
DFSDM_
Res.
Res.
Res.
Res.

CNVCNT[27:0]
0x138 FLT0CNVTIMR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x13C -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RSW START Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Reserved
0x17C
JEXTEN[1:0]

JSW START
RDMAEN
RCH[1:0]

JDMAEN
AWFSEL

RCONT
RSYNC

JSCAN
JSYNC

DFEN

DFSDM_
FAST
Res.

Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.

Res.
Res.

Res.

JEXTSEL[4:0]
0x180 FLT1CR1

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
REOCIE
ROVRIE
JOVRIE

JEOCIE
AWDIE

DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

Res.
Res.
Res.

AWDCH[3:0] EXCH[3:0]
0x184 FLT1CR2

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0

916/2194 RM0438 Rev 7

RM0438 Digital filter for sigma delta modulators (DFSDM)

Table 205. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

ROVRF

REOCF
JOVRF

JEOCF
AWDF
DFSDM_

RCIP
JCIP
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x188 FLT1ISR

reset value 0 0 0 0 0 0 0

CLR ROVRF
CLR JOVRF
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
0x18C FLT1ICR

reset value 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
JCHG[3:0]
0x190 FLT1JCHGR
reset value 0 0 0 1
FORD[2:0]

DFSDM_
Res.
Res.
Res.

Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FOSR[9:0] IOSR[7:0]
0x194 FLT1FCR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JDATACH[1:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
Res.
JDATA[23:0]
0x198 FLT1JDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RDATACH[1:0]
RPEND
DFSDM_

Res.
Res.
Res.

Res.
Res.
RDATA[23:0]
0x19C FLT1RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
AWHT[23:0] BKAWH[3:0]
0x1A0 FLT1AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.

AWLT[23:0] BKAWL[3:0]
0x1A4 FLT1AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

AWHTF[3:0] AWLTF[3:0]
0x1A8 FLT1AWSR
reset value 0 0 0 0 0 0 0 0
DFSDM_ CLRAWHTF CLRAWLTF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.

0x1AC FLT1AWCFR [3:0] [3:0]

reset value 0 0 0 0 0 0 0 0
EXMAXCH[1:0]

DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.

EXMAX[23:0]
0x1B0 FLT1EXMAX

reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EXMINCH[1:0]

DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.

FLT1EXMIN EXMIN[23:0]
0x1B4

reset value 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0

RM0438 Rev 7 917/2194

920
 0x228
0x224
0x220
0x218
0x214
0x210
0x208
0x204
0x200
0x1B8

0x21C
0x20C
0x1FC
0x1BC -
Offset

918/2194
name

DFDM_

FLT2ISR

FLT2ICR

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved

FLT2CR2
FLT2CR1

FLT2FCR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

FLT2AWSR
FLT2AWLTR
FLT2JCHGR

FLT2AWHTR
FLT2JDATAR

FLT2RDATAR
FLT1CNVTIMR

0
0
0
0
0
Res. Res. Res. Res. Res. Res. Res. 0 31

0
0
0
0
0
0
0
Res. FORD[2:0] Res. Res. Res. Res. AWFSEL Res. 30

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. FAST Res. 29

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 25

RCH[1:0]

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. 24

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
0
0
0

Res. Res. Res. Res. Res. RDMAEN Res. 21

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 20

Digital filter for sigma delta modulators (DFSDM)

FOSR[9:0]

0
0
0
0
0
0
0
0

Res. Res. Res. Res. RSYNC Res. 19

AWLT[23:0]
AWHT[23:0]
JDATA[23:0]

0
0
0
0
0
0
0
0

RDATA[23:0]
Res. Res. Res. Res. RCONT Res. 18

0
0
0
0
0
0
0
0

Res. Res. Res. Res. RSW START Res.

RM0438 Rev 7
17

0
0
0
0
0
0
0

AWDCH[3:0]

Res. Res. Res. Res. Res. Res. 16

CNVCNT[27:0]

0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. 15

0
0
0
0
0

0
0

Res. Res. Res. Res. RCIP Res. Res. 14

JEXTEN[1:0]

0
0
0
0
0

0
0

Res. Res. Res. Res. JCIP Res. Res. 13

0
0
0
0
0
0

Res. Res. Res. Res. Res. Res. Res. 12

0
0
0
0
0

0
0
0

Res. Res. Res. Res. Res. 11

0
0
0
0
0

0
0
0

Res. Res. Res. Res. Res. 10

0
0
0
0
0

0
0
0

Res. Res. Res. Res. Res. 9

JEXTSEL[4:0]

EXCH[3:0]

AWHTF[3:0]
0
0
0
0
0

0
0
0

Res. Res. Res. Res. Res. 8

Table 205. DFSDM register map and reset values (continued)

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

0
0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. JDMAEN Res. 5

0
0
0
0
0

Res. Res. Res. RPEND Res. Res. Res. AWDF AWDIE JSCAN Res. 4

0
0
0
0
0

0
0
0
0

Res. Res. CLR ROVRF ROVRF ROVRIE JSYNC Res. Res. 3

IOSR[7:0]

0
0
0

0
0
0

0
0

Res. Res. CLR JOVRF JOVRF JOVRIE Res. Res. Res. 2

0
0
0
0
0

0
0
0
0

Res. REOCF REOCIE JSW START Res. Res. 1

RDATACH[1:0] JDATACH[1:0]
JCHG[3:0]

AWLTF[3:0]
BKAWL[3:0]

0
0
0
0
0

0
0
0
0

BKAWH[3:0]
Res. JEOCF JEOCIE DFEN Res. Res. 0
RM0438
 0x298
0x294
0x290
0x288
0x284
0x280
0x238
0x234
0x230

0x28C
0x27C
0x22C

0x23C -
Offset
RM0438

name

FLT3ISR

FLT3ICR

DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_
DFSDM_

Reserved

FLT3CR2
FLT3CR1

FLT3FCR

reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
reset value
Register

FLT2EXMIN

FLT3JCHGR
FLT2EXMAX
FLT2AWCFR

FLT3JDATAR
FLT2CNVTIMR

0
0
0
0
1
Res. Res. Res. Res. Res. Res. Res. 31

0
0
0
0
1
0
FORD[2:0] Res. Res. Res. Res. AWFSEL Res. Res. 30

0
0
0
0
1
0
Res. Res. Res. Res. FAST Res. Res. 29

0
0
1
0
Res. Res. Res. Res. Res. Res. Res. Res. 28

0
0
1
0
Res. Res. Res. Res. Res. Res. Res. Res. 27

0
0
1
0
Res. Res. Res. Res. Res. Res. Res. Res. 26

0
0
0
0
1
0
Res. Res. Res. Res. Res. Res. 25
RCH[1:0]

0
0
0
0
1
0

Res. Res. Res. Res. Res. Res. 24

0
0
0
1
0

Res. Res. Res. Res. Res. Res. Res. 23

0
0
0
1
0

Res. Res. Res. Res. Res. Res. Res. 22

0
0
0
0
1
0

Res. Res. Res. Res. RDMAEN Res. Res. 21

0
0
0
1
0

Res. Res. Res. Res. Res. Res. Res. 20

FOSR[9:0]

0
0
0
0
0
1
0

Res. Res. Res. RSYNC Res. Res. 19

JDATA[23:0]

0
0
0
0
0
1
0

EXMIN[23:0]

Res. Res. Res. RCONT Res. Res.

EXMAX[23:0]

18

0
0
0
0
0
1
0

Res. Res. Res. RSW START Res. Res.

RM0438 Rev 7
17

0
0
0
0
1
0

AWDCH[3:0]
Res. Res. Res. Res. Res. Res. 16
CNVCNT[27:0]

0
0
1
0

Res. Res. Res. Res. Res. Res. Res. Res. 15

0
0
1
0

0
0
Res. Res. Res. RCIP Res. Res. Res. 14
JEXTEN[1:0]

0
0
1
0

0
0
Res. Res. Res. JCIP Res. Res. Res. 13

0
0
0
1
0

Res. Res. Res. Res. Res. Res. Res. 12

0
0
1
0

0
0
0

Res. Res. Res. Res. Res. 11

0
0
1
0

0
0
0

Res. Res. Res. Res. Res. 10

[3:0]

0
0
1
0

0
0
0

Res. Res. Res. Res. Res. 9

JEXTSEL[4:0]

EXCH[3:0]
CLRAWHTF

0
0
1
0

0
0
0

Res. Res. Res. Res. Res. 8

Table 205. DFSDM register map and reset values (continued)

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 7

0
0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 6

0
0
0

Res. Res. Res. Res. Res. JDMAEN Res. Res. Res. Res. 5

0
0
0
0

0
Res. Res. Res. AWDF AWDIE JSCAN Res. Res. Res. Res. 4

0
0
0

0
0
0
0

Res. CLR ROVRF ROVRF ROVRIE JSYNC Res. Res. Res. Res. 3

IOSR[7:0]

0
0
0

0
0
0

Res. CLR JOVRF JOVRF JOVRIE Res. Res. Res. Res. Res. 2
[3:0]

0
0
0
0
0
0
0

0
0

Res. REOCF REOCIE JSW START Res. Res. 1

JDATACH[1:0] EXMINCH[1:0] EXMAXCH[1:0]

JCHG[3:0]
CLRAWLTF

0
0
0
0
0
0
0

1
0

Res. JEOCF JEOCIE DFEN Res. Res. 0

Digital filter for sigma delta modulators (DFSDM)

919/2194
920
Digital filter for sigma delta modulators (DFSDM) RM0438

Table 205. DFSDM register map and reset values (continued)

Register
Offset

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

RDATACH[1:0]
RPEND
DFSDM_

Res.
Res.
Res.

Res.
Res.
RDATA[23:0]
0x29C FLT3RDATAR

reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWHT[23:0] BKAWH[3:0]
0x2A0 FLT3AWHTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_

Res.
Res.
Res.
Res.
AWLT[23:0] BKAWL[3:0]
0x2A4 FLT3AWLTR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSDM_
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
AWHTF[3:0] AWLTF[3:0]
0x2A8 FLT3AWSR
reset value 0 0 0 0 0 0 0 0
DFSDM_ CLRAWHTF CLRAWLTF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
Res.
0x2AC FLT3AWCFR [3:0] [3:0]
reset value 0 0 0 0 0 0 0 0

EXMAXCH[1:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
Res.
EXMAX[23:0]
0x2B0 FLT3EXMAX

reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXMINCH[1:0]
DFSDM_

Res.
Res.
Res.
Res.
Res.
Res.
FLT3EXMIN EXMIN[23:0]
0x2B4

reset value 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
DFSDM_

Res.
Res.
Res.
Res.
CNVCNT[27:0]
0x2B8 FLT3CNVTIMR
reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x2BC -
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
0x3FC

Refer to Section 2.3 on page 87 for the register boundary addresses.

920/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27 Touch sensing controller (TSC)

27.1 Introduction
The touch sensing controller provides a simple solution for adding capacitive sensing
functionality to any application. Capacitive sensing technology is able to detect finger
presence near an electrode that is protected from direct touch by a dielectric (for example
glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is
measured using a proven implementation based on a surface charge transfer acquisition
principle.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library, which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.

27.2 TSC main features

The touch sensing controller has the following main features:
• Proven and robust surface charge transfer acquisition principle
• Supports up to 24 capacitive sensing channels
• Up to 8 capacitive sensing channels can be acquired in parallel offering a very good
response time
• Spread spectrum feature to improve system robustness in noisy environments
• Full hardware management of the charge transfer acquisition sequence
• Programmable charge transfer frequency
• Programmable sampling capacitor I/O pin
• Programmable channel I/O pin
• Programmable max count value to avoid long acquisition when a channel is faulty
• Dedicated end of acquisition and max count error flags with interrupt capability
• One sampling capacitor for up to 3 capacitive sensing channels to reduce the system
components
• Compatible with proximity, touchkey, linear and rotary touch sensor implementation
• Designed to operate with STMTouch touch sensing firmware library
Note: The number of capacitive sensing channels is dependent on the size of the packages and
subject to IO availability.

RM0438 Rev 7 921/2194

939
Touch sensing controller (TSC) RM0438

27.3 TSC functional description

27.3.1 TSC block diagram

The block diagram of the touch sensing controller is shown in Figure 186.

Figure 186. TSC block diagram

SYNC

Pulse generator G1_IO1

fHCLK Clock G1_IO2
prescalers
G1_IO3
Spread spectrum
G1_IO4
G2_IO1
G2_IO2
I/O control G2_IO3
Group counters logic
G2_IO4

TSC_IOG1CR

TSC_IOG2CR

Gx_IO1
Gx_IO2
Gx_IO3
TSC_IOGxCR
Gx_IO4

MS30929V1

27.3.2 Surface charge transfer acquisition overview

The surface charge transfer acquisition is a proven, robust and efficient way to measure a
capacitance. It uses a minimum number of external components to operate with a single
ended electrode type. This acquisition is designed around an analog I/O group composed of
up to four GPIOs (see Figure 187). Several analog I/O groups are available to allow the
acquisition of several capacitive sensing channels simultaneously and to support a larger
number of capacitive sensing channels. Within a same analog I/O group, the acquisition of
the capacitive sensing channels is sequential.
One of the GPIOs is dedicated to the sampling capacitor CS. Only one sampling capacitor
I/O per analog I/O group must be enabled at a time.
The remaining GPIOs are dedicated to the electrodes and are commonly called channels.
For some specific needs (such as proximity detection), it is possible to simultaneously
enable more than one channel per analog I/O group.

922/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

Figure 187. Surface charge transfer analog I/O group structure

Electrode 1 Analog
RS1 I/O group
G1_IO1

CX1

G1_IO2
CS

Electrode 2
RS2
G1_IO3

CX2

Electrode 3 RS3
G1_IO4

CX3

MS30930V1

Note: Gx_IOy where x is the analog I/O group number and y the GPIO number within the selected
group.
The surface charge transfer acquisition principle consists of charging an electrode
capacitance (CX) and transferring a part of the accumulated charge into a sampling
capacitor (CS). This sequence is repeated until the voltage across CS reaches a given
threshold (VIH in our case). The number of charge transfers required to reach the threshold
is a direct representation of the size of the electrode capacitance.
Table 206 details the charge transfer acquisition sequence of the capacitive sensing
channel 1. States 3 to 7 are repeated until the voltage across CS reaches the given
threshold. The same sequence applies to the acquisition of the other channels. The
electrode serial resistor RS improves the ESD immunity of the solution.

RM0438 Rev 7 923/2194

939
Touch sensing controller (TSC) RM0438

Table 206. Acquisition sequence summary

G1_IO1 G1_IO2 G1_IO3 G1_IO4
State State description
(channel) (sampling) (channel) (channel)

Output open-
Input floating
drain low with Input floating with analog switch Discharge all CX and
#1 with analog
analog switch closed CS
switch closed
closed
#2 Input floating Dead time
Output push-
#3 Input floating Charge CX1
pull high
#4 Input floating Dead time
Input floating with analog switch Charge transfer from
#5 Input floating
closed CX1 to CS
#6 Input floating Dead time
#7 Input floating Measure CS voltage

The voltage variation over the time on the sampling capacitor CS is detailed below:

Figure 188. Sampling capacitor voltage variation

VCS

VDD

Threshold =VIH

t
Burst duration
MS30931V1

27.3.3 Reset and clocks

The TSC clock source is the AHB clock (HCLK). Two programmable prescalers are used to
generate the pulse generator and the spread spectrum internal clocks:
• The pulse generator clock (PGCLK) is defined using the PGPSC[2:0] bits of the
TSC_CR register
• The spread spectrum clock (SSCLK) is defined using the SSPSC bit of the TSC_CR
register
The Reset and Clock Controller (RCC) provides dedicated bits to enable the touch sensing
controller clock and to reset this peripheral. For more information, refer to Section 9: Reset
and clock control (RCC).

924/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27.3.4 Charge transfer acquisition sequence

An example of a charge transfer acquisition sequence is detailed in Figure 189.

Figure 189. Charge transfer acquisition sequence

Charge transfer frequency

CLK_AHB

CX HiZ

CS HiZ

Spread spectrum state

Dead time state

Dead time state

Dead time state

Dead time state

Dead time state

CS reading

CS reading
Pulse low
Pulse high
Discharge state (charge Pulse high Pulse low
State CX and CS
state
transfer from state state
(charge of CX)
CX to CS)

t
MSv30932V3

For higher flexibility, the charge transfer frequency is fully configurable. Both the pulse high
state (charge of CX) and the pulse low state (transfer of charge from CX to CS) duration can
be defined using the CTPH[3:0] and CTPL[3:0] bits in the TSC_CR register. The standard
range for the pulse high and low states duration is 500 ns to 2 µs. To ensure a correct
measurement of the electrode capacitance, the pulse high state duration must be set to
ensure that CX is always fully charged.
A dead time where both the sampling capacitor I/O and the channel I/O are in input floating
state is inserted between the pulse high and low states to ensure an optimum charge
transfer acquisition sequence. This state duration is 1 periods of HCLK.
At the end of the pulse high state and if the spread spectrum feature is enabled, a variable
number of periods of the SSCLK clock are added.
The reading of the sampling capacitor I/O, to determine if the voltage across CS has
reached the given threshold, is performed at the end of the pulse low state.
Note: The following TSC control register configurations are forbidden:
• bits PGPSC are set to ‘000’ and bits CTPL are set to ‘0000’
• bits PGPSC are set to ‘000’ and bits CTPL are set to ‘0001’
• bits PGPSC are set to ‘001’ and bits CTPL are set to ‘0000’

RM0438 Rev 7 925/2194

939
Touch sensing controller (TSC) RM0438

27.3.5 Spread spectrum feature

The spread spectrum feature allows to generate a variation of the charge transfer
frequency. This is done to improve the robustness of the charge transfer acquisition in noisy
environments and also to reduce the induced emission. The maximum frequency variation
is in the range of 10% to 50% of the nominal charge transfer period. For instance, for a
nominal charge transfer frequency of 250 kHz (4 µs), the typical spread spectrum deviation
is 10% (400 ns) which leads to a minimum charge transfer frequency of ~227 kHz.
In practice, the spread spectrum consists of adding a variable number of SSCLK periods to
the pulse high state using the principle shown below:

Figure 190. Spread spectrum variation principle

Deviation value

(SSD +1)

1
0 n-1 n n+1
Number of pulses
MS30933V1

The table below details the maximum frequency deviation with different HCLK settings:

Table 207. Spread spectrum deviation versus AHB clock frequency

fHCLK Spread spectrum step Maximum spread spectrum deviation

24 MHz 41.6 ns 10666.6 ns

48 MHz 20.8 ns 5333.3 ns
80 MHz 12.5 ns 3205.1 ns
110 MHz 9.09 ns 2327.3 ns

The spread spectrum feature can be disabled/enabled using the SSE bit in the TSC_CR
register. The frequency deviation is also configurable to accommodate the device HCLK
clock frequency and the selected charge transfer frequency through the SSPSC and
SSD[6:0] bits in the TSC_CR register.

27.3.6 Max count error

The max count error prevents long acquisition times resulting from a faulty capacitive
sensing channel. It consists of specifying a maximum count value for the analog I/O group
counters. This maximum count value is specified using the MCV[2:0] bits in the TSC_CR
register. As soon as an acquisition group counter reaches this maximum value, the ongoing
acquisition is stopped and the end of acquisition (EOAF bit) and max count error (MCEF bit)
flags are both set. An interrupt can also be generated if the corresponding end of acquisition
(EOAIE bit) or/and max count error (MCEIE bit) interrupt enable bits are set.

926/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27.3.7 Sampling capacitor I/O and channel I/O mode selection

To allow the GPIOs to be controlled by the touch sensing controller, the corresponding
alternate function must be enabled through the standard GPIO registers and the GPIOxAFR
registers.
The GPIOs modes controlled by the TSC are defined using the TSC_IOSCR and
TSC_IOCCR register.
When there is no ongoing acquisition, all the I/Os controlled by the touch sensing controller
are in default state. While an acquisition is ongoing, only unused I/Os (neither defined as
sampling capacitor I/O nor as channel I/O) are in default state. The IODEF bit in the
TSC_CR register defines the configuration of the I/Os which are in default state. The table
below summarizes the configuration of the I/O depending on its mode.

Table 208. I/O state depending on its mode and IODEF bit value
Sampling
Acquisition Unused I/O Channel I/O
IODEF bit capacitor I/O
status mode mode
mode

0 Output push-pull Output push-pull Output push-pull

No
(output push-pull low) low low low
0 Output push-pull
Ongoing - -
(output push-pull low) low
1
No Input floating Input floating Input floating
(input floating)
1
Ongoing Input floating - -
(input floating)

Unused I/O mode

An unused I/O corresponds to a GPIO controlled by the TSC peripheral but not defined as
an electrode I/O nor as a sampling capacitor I/O.
Sampling capacitor I/O mode
To allow the control of the sampling capacitor I/O by the TSC peripheral, the corresponding
GPIO must be first set to alternate output open drain mode and then the corresponding
Gx_IOy bit in the TSC_IOSCR register must be set.
Only one sampling capacitor per analog I/O group must be enabled at a time.
Channel I/O mode
To allow the control of the channel I/O by the TSC peripheral, the corresponding GPIO must
be first set to alternate output push-pull mode and the corresponding Gx_IOy bit in the
TSC_IOCCR register must be set.
For proximity detection where a higher equivalent electrode surface is required or to speed-
up the acquisition process, it is possible to enable and simultaneously acquire several
channels belonging to the same analog I/O group.
Note: During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR or TSC_IOCCR bit is set, the corresponding GPIO
analog switch is automatically controlled by the touch sensing controller.

RM0438 Rev 7 927/2194

939
Touch sensing controller (TSC) RM0438

27.3.8 Acquisition mode

The touch sensing controller offers two acquisition modes:
• Normal acquisition mode: the acquisition starts as soon as the START bit in the
TSC_CR register is set.
• Synchronized acquisition mode: the acquisition is enabled by setting the START bit in
the TSC_CR register but only starts upon the detection of a falling edge or a rising
edge and high level on the SYNC input pin. This mode is useful for synchronizing the
capacitive sensing channels acquisition with an external signal without additional CPU
load.
The GxE bits in the TSC_IOGCSR registers specify which analog I/O groups are enabled
(corresponding counter is counting). The CS voltage of a disabled analog I/O group is not
monitored and this group does not participate in the triggering of the end of acquisition flag.
However, if the disabled analog I/O group contains some channels, they are pulsed.
When the CS voltage of an enabled analog I/O group reaches the given threshold, the
corresponding GxS bit of the TSC_IOGCSR register is set. When the acquisition of all
enabled analog I/O groups is complete (all GxS bits of all enabled analog I/O groups are
set), the EOAF flag in the TSC_ISR register is set. An interrupt request is generated if the
EOAIE bit in the TSC_IER register is set.
In the case that a max count error is detected, the ongoing acquisition is stopped and both
the EOAF and MCEF flags in the TSC_ISR register are set. Interrupt requests can be
generated for both events if the corresponding bits (EOAIE and MCEIE bits of the TSCIER
register) are set. Note that when the max count error is detected the remaining GxS bits in
the enabled analog I/O groups are not set.
To clear the interrupt flags, the corresponding EOAIC and MCEIC bits in the TSC_ICR
register must be set.
The analog I/O group counters are cleared when a new acquisition is started. They are
updated with the number of charge transfer cycles generated on the corresponding
channel(s) upon the completion of the acquisition.

27.3.9 I/O hysteresis and analog switch control

In order to offer a higher flexibility, the touch sensing controller also allows to take the
control of the Schmitt trigger hysteresis and analog switch of each Gx_IOy. This control is
available whatever the I/O control mode is (controlled by standard GPIO registers or other
peripherals) assuming that the touch sensing controller is enabled. This may be useful to
perform a different acquisition sequence or for other purposes.
In order to improve the system immunity, the Schmitt trigger hysteresis of the GPIOs
controlled by the TSC must be disabled by resetting the corresponding Gx_IOy bit in the
TSC_IOHCR register.

928/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27.4 TSC low-power modes

Table 209. Effect of low-power modes on TSC
Mode Description

Sleep No effect. Peripheral interrupts cause the device to exit Sleep mode.
Low power run No effect.
Low power sleep No effect. Peripheral interrupts cause the device to exit Low-power sleep mode.
Stop 0 / Stop 1
Peripheral registers content is kept.
Stop 2
Standby Powered-down. The peripheral must be reinitialized after exiting Standby or
Shutdown Shutdown mode.

27.5 TSC interrupts

Table 210. Interrupt control bits
Enable Clear flag Exit the Exit the Exit the
Interrupt event Event flag
control bit bit Sleep mode Stop mode Standby mode

End of acquisition EOAIE EOAIF EOAIC Yes No No

Max count error MCEIE MCEIF MCEIC Yes No No

RM0438 Rev 7 929/2194

939
Touch sensing controller (TSC) RM0438

27.6 TSC registers

Refer to Section 1.2 on page 76 of the reference manual for a list of abbreviations used in
register descriptions.
The peripheral registers can be accessed by words (32-bit).

27.6.1 TSC control register (TSC_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CTPH[3:0] CTPL[3:0] SSD[6:0] SSE
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SYNC
SSPSC PGPSC[2:0] Res. Res. Res. Res. MCV[2:0] IODEF AM START TSCE
POL
rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 CTPH[3:0]: Charge transfer pulse high

These bits are set and cleared by software. They define the duration of the high state of the
charge transfer pulse (charge of CX).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK
Note: These bits must not be modified when an acquisition is ongoing.
Bits 27:24 CTPL[3:0]: Charge transfer pulse low
These bits are set and cleared by software. They define the duration of the low state of the
charge transfer pulse (transfer of charge from CX to CS).
0000: 1x tPGCLK
0001: 2x tPGCLK
...
1111: 16x tPGCLK
Note: These bits must not be modified when an acquisition is ongoing.
Note: Some configurations are forbidden. Refer to the Section 27.3.4: Charge transfer
acquisition sequence for details.
Bits 23:17 SSD[6:0]: Spread spectrum deviation
These bits are set and cleared by software. They define the spread spectrum deviation which
consists in adding a variable number of periods of the SSCLK clock to the charge transfer
pulse high state.
0000000: 1x tSSCLK
0000001: 2x tSSCLK
...
1111111: 128x tSSCLK
Note: These bits must not be modified when an acquisition is ongoing.

930/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

Bit 16 SSE: Spread spectrum enable

This bit is set and cleared by software to enable/disable the spread spectrum feature.
0: Spread spectrum disabled
1: Spread spectrum enabled
Note: This bit must not be modified when an acquisition is ongoing.
Bit 15 SSPSC: Spread spectrum prescaler
This bit is set and cleared by software. It selects the AHB clock divider used to generate the
spread spectrum clock (SSCLK).
0: fHCLK
1: fHCLK /2
Note: This bit must not be modified when an acquisition is ongoing.
Bits 14:12 PGPSC[2:0]: Pulse generator prescaler
These bits are set and cleared by software.They select the AHB clock divider used to
generate the pulse generator clock (PGCLK).
000: fHCLK
001: fHCLK /2
010: fHCLK /4
011: fHCLK /8
100: fHCLK /16
101: fHCLK /32
110: fHCLK /64
111: fHCLK /128
Note: These bits must not be modified when an acquisition is ongoing.
Note: Some configurations are forbidden. Refer to the Section 27.3.4: Charge transfer
acquisition sequence for details.
Bits 11:8 Reserved, must be kept at reset value.
Bits 7:5 MCV[2:0]: Max count value
These bits are set and cleared by software. They define the maximum number of charge
transfer pulses that can be generated before a max count error is generated.
000: 255
001: 511
010: 1023
011: 2047
100: 4095
101: 8191
110: 16383
111: reserved
Note: These bits must not be modified when an acquisition is ongoing.
Bit 4 IODEF: I/O Default mode
This bit is set and cleared by software. It defines the configuration of all the TSC I/Os when
there is no ongoing acquisition. When there is an ongoing acquisition, it defines the
configuration of all unused I/Os (not defined as sampling capacitor I/O or as channel I/O).
0: I/Os are forced to output push-pull low
1: I/Os are in input floating
Note: This bit must not be modified when an acquisition is ongoing.
Bit 3 SYNCPOL: Synchronization pin polarity
This bit is set and cleared by software to select the polarity of the synchronization input pin.
0: Falling edge only
1: Rising edge and high level

RM0438 Rev 7 931/2194

939
Touch sensing controller (TSC) RM0438

Bit 2 AM: Acquisition mode

This bit is set and cleared by software to select the acquisition mode.
0: Normal acquisition mode (acquisition starts as soon as START bit is set)
1: Synchronized acquisition mode (acquisition starts if START bit is set and when the
selected signal is detected on the SYNC input pin)
Note: This bit must not be modified when an acquisition is ongoing.
Bit 1 START: Start a new acquisition
This bit is set by software to start a new acquisition. It is cleared by hardware as soon as the
acquisition is complete or by software to cancel the ongoing acquisition.
0: Acquisition not started
1: Start a new acquisition
Bit 0 TSCE: Touch sensing controller enable
This bit is set and cleared by software to enable/disable the touch sensing controller.
0: Touch sensing controller disabled
1: Touch sensing controller enabled
Note: When the touch sensing controller is disabled, TSC registers settings have no effect.

27.6.2 TSC interrupt enable register (TSC_IER)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEIE EOAIE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 MCEIE: Max count error interrupt enable
This bit is set and cleared by software to enable/disable the max count error interrupt.
0: Max count error interrupt disabled
1: Max count error interrupt enabled
Bit 0 EOAIE: End of acquisition interrupt enable
This bit is set and cleared by software to enable/disable the end of acquisition interrupt.
0: End of acquisition interrupt disabled
1: End of acquisition interrupt enabled

932/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27.6.3 TSC interrupt clear register (TSC_ICR)

Address offset: 0x08
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEIC EOAIC
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 MCEIC: Max count error interrupt clear
This bit is set by software to clear the max count error flag and it is cleared by hardware
when the flag is reset. Writing a ‘0’ has no effect.
0: No effect
1: Clears the corresponding MCEF of the TSC_ISR register
Bit 0 EOAIC: End of acquisition interrupt clear
This bit is set by software to clear the end of acquisition flag and it is cleared by hardware
when the flag is reset. Writing a ‘0’ has no effect.
0: No effect
1: Clears the corresponding EOAF of the TSC_ISR register

RM0438 Rev 7 933/2194

939
Touch sensing controller (TSC) RM0438

27.6.4 TSC interrupt status register (TSC_ISR)

Address offset: 0x0C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. MCEF EOAF
r r

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 MCEF: Max count error flag
This bit is set by hardware as soon as an analog I/O group counter reaches the max count
value specified. It is cleared by software writing 1 to the bit MCEIC of the TSC_ICR register.
0: No max count error (MCE) detected
1: Max count error (MCE) detected
Bit 0 EOAF: End of acquisition flag
This bit is set by hardware when the acquisition of all enabled group is complete (all GxS bits
of all enabled analog I/O groups are set or when a max count error is detected). It is cleared
by software writing 1 to the bit EOAIC of the TSC_ICR register.
0: Acquisition is ongoing or not started
1: Acquisition is complete

27.6.5 TSC I/O hysteresis control register (TSC_IOHCR)

Address offset: 0x10
Reset value: 0xFFFF FFFF

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Gx_IOy: Gx_IOy Schmitt trigger hysteresis mode

These bits are set and cleared by software to enable/disable the Gx_IOy Schmitt trigger
hysteresis.
0: Gx_IOy Schmitt trigger hysteresis disabled
1: Gx_IOy Schmitt trigger hysteresis enabled
Note: These bits control the I/O Schmitt trigger hysteresis whatever the I/O control mode is
(even if controlled by standard GPIO registers).

934/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27.6.6 TSC I/O analog switch control register (TSC_IOASCR)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Gx_IOy: Gx_IOy analog switch enable

These bits are set and cleared by software to enable/disable the Gx_IOy analog switch.
0: Gx_IOy analog switch disabled (opened)
1: Gx_IOy analog switch enabled (closed)
Note: These bits control the I/O analog switch whatever the I/O control mode is (even if
controlled by standard GPIO registers).

27.6.7 TSC I/O sampling control register (TSC_IOSCR)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Gx_IOy: Gx_IOy sampling mode

These bits are set and cleared by software to configure the Gx_IOy as a sampling capacitor
I/O. Only one I/O per analog I/O group must be defined as sampling capacitor.
0: Gx_IOy unused
1: Gx_IOy used as sampling capacitor
Note: These bits must not be modified when an acquisition is ongoing.
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOSCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.

RM0438 Rev 7 935/2194

939
Touch sensing controller (TSC) RM0438

27.6.8 TSC I/O channel control register (TSC_IOCCR)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G8_IO4 G8_IO3 G8_IO2 G8_IO1 G7_IO4 G7_IO3 G7_IO2 G7_IO1 G6_IO4 G6_IO3 G6_IO2 G6_IO1 G5_IO4 G5_IO3 G5_IO2 G5_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
G4_IO4 G4_IO3 G4_IO2 G4_IO1 G3_IO4 G3_IO3 G3_IO2 G3_IO1 G2_IO4 G2_IO3 G2_IO2 G2_IO1 G1_IO4 G1_IO3 G1_IO2 G1_IO1
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 Gx_IOy: Gx_IOy channel mode

These bits are set and cleared by software to configure the Gx_IOy as a channel I/O.
0: Gx_IOy unused
1: Gx_IOy used as channel
Note: These bits must not be modified when an acquisition is ongoing.
During the acquisition phase and even if the TSC peripheral alternate function is not
enabled, as soon as the TSC_IOCCR bit is set, the corresponding GPIO analog switch
is automatically controlled by the touch sensing controller.

27.6.9 TSC I/O group control status register (TSC_IOGCSR)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. G8S G7S G6S G5S G4S G3S G2S G1S
r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. G8E G7E G6E G5E G4E G3E G2E G1E
rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:16 GxS: Analog I/O group x status
These bits are set by hardware when the acquisition on the corresponding enabled analog
I/O group x is complete. They are cleared by hardware when a new acquisition is started.
0: Acquisition on analog I/O group x is ongoing or not started
1: Acquisition on analog I/O group x is complete
Note: When a max count error is detected the remaining GxS bits of the enabled analog I/O
groups are not set.
Bits 15:8 Reserved, must be kept at reset value.
Bits 7:0 GxE: Analog I/O group x enable
These bits are set and cleared by software to enable/disable the acquisition (counter is
counting) on the corresponding analog I/O group x.
0: Acquisition on analog I/O group x disabled
1: Acquisition on analog I/O group x enabled

936/2194 RM0438 Rev 7

RM0438 Touch sensing controller (TSC)

27.6.10 TSC I/O group x counter register (TSC_IOGxCR)

x represents the analog I/O group number.
Address offset: 0x30 + 0x04 * x, (x = 1..8)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. CNT[13:0]

r r r r r r r r r r r r r r

Bits 31:14 Reserved, must be kept at reset value.

Bits 13:0 CNT[13:0]: Counter value
These bits represent the number of charge transfer cycles generated on the analog I/O
group x to complete its acquisition (voltage across CS has reached the threshold).

RM0438 Rev 7 937/2194

939
 0x0038
0x0034
0x0030
0x0028
0x0020
0x0018
0x0010
0x0008
0x0004
0x0000

0x0024
0x0014

0x002C
0x001C
0x000C
Offset

938/2194
27.6.11

TSC_CR

TSC_ISR
TSC_IER

TSC_ICR
Register

Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value
Reset value

TSC_IOSCR

TSC_IOCCR
TSC_IOHCR

TSC_IOG2CR
TSC_IOG1CR
TSC_IOASCR

TSC_IOGCSR
0
0
0
1
0
Res. Res. Res. G8_IO4 G8_IO4 G8_IO4 G8_IO4 Res. Res. Res. 31

0
0
0
1
0
Res. Res. Res. G8_IO3 G8_IO3 G8_IO3 G8_IO3 Res. Res. Res. 30

0
0
0
1
0
Res. Res. Res. G8_IO2 G8_IO2 G8_IO2 G8_IO2 Res. Res. Res. 29
CTPH[3:0]

0
0
0
1
0
Res. Res. Res. G8_IO1 G8_IO1 G8_IO1 G8_IO1 Res. Res. Res. 28

0
0
0
1
Res. Res. Res. G7_IO4 G7_IO4 G7_IO4 G7_IO4 Res. Res. Res. 0
Touch sensing controller (TSC)

27
TSC register map

0
0
0
1
0
Res. Res. Res. G7_IO3 G7_IO3 G7_IO3 G7_IO3 Res. Res. Res. 26

0
0
0
1
0

Res. Res. Res. G7_IO2 G7_IO2 G7_IO2 G7_IO2 Res. Res. Res. 25
CTPL[3:0]

0
0
0
1
0

Res. Res. Res. G7_IO1 G7_IO1 G7_IO1 G7_IO1 Res. Res. Res. 24

0
0
0
0
1
0

Res. Res. G8S G6_IO4 G6_IO4 G6_IO4 G6_IO4 Res. Res. Res. 23

0
0
0
0
1
0

Res. Res. G7S G6_IO3 G6_IO3 G6_IO3 G6_IO3 Res. Res. Res. 22

0
0
0
0
1
0

Res. Res. G6S G6_IO2 G6_IO2 G6_IO2 G6_IO2 Res. Res. Res. 21

0
0
0
0
1
0

Res. Res. G5S G6_IO1 G6_IO1 G6_IO1 G6_IO1 Res. Res. Res. 20

0
0
0
0
1
0
SSD[6:0]

Res. Res. G4S G5_IO4 G5_IO4 G5_IO4 G5_IO4 Res. Res. Res. 19

0
0
0
0
1
0

Res. Res. G3S G5_IO3 G5_IO3 G5_IO3 G5_IO3 Res. Res. Res. 18

RM0438 Rev 7
0
0
0
0
1
0

Reserved
Reserved

Reserved
Reserved
Res. Res. G2S G5_IO2 G5_IO2 G5_IO2 G5_IO2 Res. Res. Res. 17

0
0
0
0
1
0

Res. Res. G1S G5_IO1 G5_IO1 G5_IO1 G5_IO1 Res. Res. Res. SSE 16

0
0
0
1
0

Res. Res. Res. G4_IO4 G4_IO4 G4_IO4 G4_IO4 Res. Res. Res. SSPSC 15

0
0
0
1
0

Res. Res. Res. G4_IO3 G4_IO3 G4_IO3 G4_IO3 Res. Res. Res. 14

0
0
0
1
0

0
0
Res. G4_IO2 G4_IO2 G4_IO2 G4_IO2 Res. Res. Res. PGPSC[2:0] 13

0
0
0
1
0

0
0
Res. G4_IO1 G4_IO1 G4_IO1 G4_IO1 Res. Res. Res. 12

0
0
0
1

0
0
Res. G3_IO4 G3_IO4 G3_IO4 G3_IO4 Res. Res. Res. Res. 11
Table 211. TSC register map and reset values

0
0
0
1

0
0
Res. G3_IO3 G3_IO3 G3_IO3 G3_IO3 Res. Res. Res. Res. 10

0
0
0
1

0
0
Res. G3_IO2 G3_IO2 G3_IO2 G3_IO2 Res. Res. Res. Res. 9

0
0
0
1

0
0
Res. G3_IO1 G3_IO1 G3_IO1 G3_IO1 Res. Res. Res. Res. 8

0
0
0
1
0

0
0
0
G8E G2_IO4 G2_IO4 G2_IO4 G2_IO4 Res. Res. Res. 7

0
0
0
1
0

0
0
0
G7E G2_IO3 G2_IO3 G2_IO3 G2_IO3 Res. Res. Res. 6
[2:0]
MCV

CNT[13:0]
CNT[13:0]
0
0
0
1
0

0
0
0
G6E G2_IO2 G2_IO2 G2_IO2 G2_IO2 Res. Res. Res. 5

0
0
0
1
0

0
0
0
G5E G2_IO1 G2_IO1 G2_IO1 G2_IO1 Res. Res. Res. IODEF 4

0
0
0
1
0

0
0
0
G4E G1_IO4 G1_IO4 G1_IO4 G1_IO4 Res. Res. Res. SYNCPOL 3

0
0
0
1
0

0
0
0
G3E G1_IO3 G1_IO3 G1_IO3 G1_IO3 Res. Res. Res. AM 2

0
0
0
1
0

0
0
0
0
0
0

G2E G1_IO2 G1_IO2 G1_IO2 G1_IO2 MCEF MCEIC MCEIE START 1

0
0
0
1
0

0
0
0
0
0
0

G1E G1_IO1 G1_IO1 G1_IO1 G1_IO1 EOAF EOAIC EOAIE TSCE 0

RM0438
RM0438 Touch sensing controller (TSC)

Table 211. TSC register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG3CR CNT[13:0]
0x003C
Reset value Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG4CR CNT[13:0]
0x0040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG5CR CNT[13:0]
0x0044
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG6CR CNT[13:0]
0x0048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG7CR CNT[13:0]
0x004C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TSC_IOG8CR CNT[13:0]
0x0050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

RM0438 Rev 7 939/2194

939
True random number generator (RNG) RM0438

28 True random number generator (RNG)

28.1 Introduction
The RNG is a true random number generator that provides full entropy outputs to the
application as 32-bit samples. It is composed of a live entropy source (analog) and an
internal conditioning component.
The RNG is a NIST SP 800-90B compliant entropy source that can be used to construct a
non-deterministic random bit generator (NDRBG).
The RNG true random number generator has been pre-certified NIST SP800-90B. It has
also been tested using German BSI statistical tests of AIS-31 (T0 to T8).

28.2 RNG main features

• The RNG delivers 32-bit true random numbers, produced by an analog entropy source
conditioned by a NIST SP800-90B approved conditioning stage.
• It can be used as entropy source to construct a non-deterministic random bit generator
(NDRBG).
• It produces four 32-bit random samples every 412 AHB clock cycles if fAHB < 77 MHz
(256 RNG clock cycles otherwise).
• It embeds start-up and NIST SP800-90B approved continuous health tests (repetition
count and adaptive proportion tests), associated with specific error management
• It can be disabled to reduce power consumption, or enabled with an automatic low
power mode (default configuration).
• It has an AMBA AHB slave peripheral, accessible through 32-bit word single accesses
only (else an AHB bus error is generated, and the write accesses are ignored).

940/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

28.3 RNG functional description

28.3.1 RNG block diagram

Figure 191 shows the RNG block diagram.

Figure 191. RNG block diagram

True RNG
rng_it Conditioning logic
Banked Registers CONDRST

128-bit data output

control RNG_CR
32-bit AHB bus

4x32-bit
FIFO
data RNG_DR
AHB
status RNG_SR
interface

Alarms
Fault detection
Clock checker
rng_hclk AHB clock domain
Health tests
1-bit

rng_clk Post-processing (optional)

DIV

RNG clock domain

Sampling (x N) + XOR

Analog Analog ... Analog

noise noise noise
en_osc source 1 source 2 source N
Analog noise source

MSv42098V2

28.3.2 RNG internal signals

Table 212 describes a list of useful-to-know internal signals available at the RNG level, not
at the STM32 product level (on pads).

Table 212. RNG internal input/output signals

Signal name Signal type Description

rng_it Digital output RNG global interrupt request

rng_hclk Digital input AHB clock
rng_clk Digital input RNG dedicated clock, asynchronous to rng_hclk

RM0438 Rev 7 941/2194

955
True random number generator (RNG) RM0438

28.3.3 Random number generation

The true random number generator (RNG) delivers truly random data through its AHB
interface at deterministic intervals.
Within its boundary RNG integrates all the required NIST components depicted on
Figure 192. Those components are an analog noise source, a digitization stage, a
conditioning algorithm, a health monitoring block and two interfaces that are used to interact
with the entropy source: GetEntropy and HealthTest.

Figure 192. NIST SP800-90B entropy source model

Error
message Output
(GetEntropy)
(HealthTest)

Conditioning
Heath (optional)
tests
Raw data

Post-processing
(optional)

Digitization

Noise Source

Entropy source

MSv44200V2

The components pictured above are detailed hereafter:

Noise source
The noise source is the component that contains the non-deterministic, entropy-providing
activity that is ultimately responsible for the uncertainty associated with the bitstring output
by the entropy source. This noise source provides 1-bit samples. It is composed of:
• Multiple analog noise sources (x6), each based on three XORed free-running ring
oscillator outputs. It is possible to disable those analog oscillators to save power, as
described in Section 28.3.8: RNG low-power usage.
• The XORing of the 6 noise sources into a single analog output.
• A sampling stage of this output clocked by a dedicated clock input (rng_clk with
integrated divider), delivering a 1-bit raw data output.
This noise source sampling is independent to the AHB interface clock frequency (rng_hclk),
with a possibility for the software to decrease the sampling frequency by using the
integrated divider.
Note: In Section 28.6: RNG entropy source validation recommended RNG clock frequencies and
associated divider value are given.

942/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

Post processing
In NIST configuration no post-processing is applied to sampled noise source. In non-NIST
configuration B (as defined in Section 28.6.2) a normalization debiasing is applied, i.e. half
of the bits are taken from the sampled noise source, half of the bits are taken from inverted
sampled noise source.

Conditioning
The conditioning component in the RNG is a deterministic function that increases the
entropy rate of the resulting fixed-length bitstrings output (128-bit). The NIST SP800-90B
target is full entropy on the output (i.e. 128-bit).
The times required between two random number generations, and between the RNG
initialization and availability of first sample are described in Section 28.5: RNG processing
time.

Output buffer
A data output buffer can store up to four 32-bit words that have been output from the
conditioning component. When four words have been read from the output FIFO through
the RNG_DR register, the content of the 128-bit conditioning output register is pushed into
the output FIFO, and a new conditioning round is automatically started. Four new words are
added to the conditioning output register after a number of clock cycles specified in
Section 28.5: RNG processing time.
Whenever a random number is available through the RNG_DR register the DRDY flag
transitions from “0” to “1”. This flag remains high until output buffer becomes empty after
reading four words from the RNG_DR register.
Note: When interrupts are enabled an interrupt is generated when this data ready flag transitions
from “0” to “1”. Interrupt is then cleared automatically by the RNG as explained above.

RM0438 Rev 7 943/2194

955
True random number generator (RNG) RM0438

Health checks
This component ensures that the entire entropy source (with its noise source) starts then
operates as expected, obtaining assurance that failures are caught quickly and with a high
probability and reliability.
The RNG implements the following health check features in accordance with NIST SP800-
90B. The described thresholds correspond to the value recommended for register
RNG_HTCR (in Section 28.6.2).
1. Start-up health tests, performed after reset and before the first use of the RNG as
entropy source
– Adaptive proportion test running on one 1024 bit windows: the RNG verifies that
the first bit on the outputs of the noise source is not repeated more than 691 times.
– Known-answer tests, to verify the conditioning stage.
– Repetition count test, flagging an error when the noise source has provided more
than 40 consecutive bits at a constant value (“0” or “1”)
2. Continuous health tests, running indefinitely on the outputs of the noise source
– Repetition count test, similar to the one running in start-up tests
– Adaptive proportion test running on 1024 consecutive samples, like during start-up
health tests.
3. Vendor specific continuous tests
– Transition count test, flagging an error when the noise source has delivered more
than 32 consecutive occurrence of two bits patterns (“01” or “10”).
– Real-time “too slow” sampling clock detector, flagging an error when one RNG
clock cycle (before divider) is smaller than AHB clock cycle divided by 32.
4. On-demand test of digitized noise source (raw data)
– Supported by restarting the entropy source and re-running the startup tests (see
software reset sequence in Section 28.3.4: RNG initialization). Other kinds of on-
demand testing (software based) are not supported.
The CECS and SECS status bits in the RNG_SR register indicate when an error condition is
detected, as detailed in Section 28.3.7: Error management.
Note: An interrupt can be generated when an error is detected.
Above health test thresholds are modified by changing value in RNG_HTCR register. See
Section 28.6: RNG entropy source validation for details.

944/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

28.3.4 RNG initialization

The RNG simplified state machine is pictured on Figure 193
After enabling the RNG (RNGEN=1 in RNG_CR) the following chain of events occurs:
1. The analog noise source is enabled, and by default the RNG waits 16 cycles of RNG
clock cycles (before divider) before starting to sample analog output and filling 128-bit
conditioning shift register.
2. The conditioning hardware initializes, automatically triggering start-up behavior test on
the raw data samples and known-answer tests.
3. When start-up health tests are completed. During this time three 128-bit noise source
samples are used.
4. The conditioning stage internal input data buffer is filled again with 128-bit and a
number of conditioning rounds defined by the RNG configuration (NIST or non-NIST) is
performed. The output buffer is then filled with the post processing result.
5. The output buffer is refilled automatically according to the RNG usage.
The associated initialization time can be found in Section 28.5: RNG processing time.

Figure 193. RNG initialization overview

Wait for noise

source Software reset

2
Software reset

Start-up heath tests Error state

start-up test(s)
not OK
3

Conditioning keys continuous test(s)

init not OK

Generate samples

MSv44204V2

RM0438 Rev 7 945/2194

955
True random number generator (RNG) RM0438

Figure 193 also highlights a possible software reset sequence, implemented by:
a) Writing bits RNGEN=0 and CONDRST=1 in the RNG_CR register with the same
RNG configuration and a new CLKDIV if needed.
b) Then writing RNGEN=1 and CONDRST=0 in the RNG_CR register.
c) Wait for random number to be ready, after initialization completes
Note: When RNG peripheral is reset through RCC (hardware reset) the RNG configuration for
optimal randomness is lost in RNG registers. Software reset with CONFIGLOCK set
preserves the RNG configuration.

28.3.5 RNG operation

Normal operations
To run the RNG using interrupts the following steps are recommended:
1. Consult the Section 28.6: RNG entropy source validation on page 949 and verify if a
specific RNG configuration is required for your application.
– If it is the case, write in the RNG_CR register the bit CONDRST=“1” together with
the correct RNG configuration. Then perform a second write to the RNG_CR
register with the bit CONDRST=“0”, the interrupt enable bit IE=”1” and the RNG
enable bit RNGEN=“1”.
– If it is not the case perform a write to the RNG_CR register with the interrupt
enable bit IE=”1” and the RNG enable bit RNGEN=“1”.
2. An interrupt is now generated when a random number is ready or when an error
occurs. Therefore at each interrupt, check that:
– No error occurred. The SEIS and CEIS bits should be set to 0 in the RNG_SR
register.
– A random number is ready. The DRDY bit must be set to 1 in the RNG_SR
register.
– If above two conditions are true the content of the RNG_DR register can be read
up to four consecutive times. If valid data is available in the conditioning output
buffer, four additional words can be read by the application (in this case the DRDY
bit is still high). If one or both of above conditions are false, the RNG_DR register
must not be read. If an error occurred error recovery sequence described in
Section 28.3.7 must be used.
To run the RNG in polling mode following steps are recommended:
1. Consult the Section 28.6: RNG entropy source validation on page 949 and verify if a
specific RNG configuration is required for your application.
– If it is the case write in the RNG_CR register the bit CONDRST=“1” together with
the correction RNG configuration. Then perform a second write to the RNG_CR
register with the bit CONDRST=“0” and the RNG enable bit RNGEN=“1”.
– If it is not the case only enable the RNG by setting the RNGEN bit to “1” in the
RNG_CR register.
2. Read the RNG_SR register and check that:
– No error occurred (the SEIS and CEIS bits should be set to 0)
– A random number is ready (the DRDY bit should be set to 1)
3. If above conditions are true read the content of the RNG_DR register up to four
consecutive times. If valid data is available in the conditioning output buffer four

946/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

additional words can be read by the application (in this case the DRDY bit is still high).
If one or both of above conditions are false, the RNG_DR register must not be read. If
an error occurred error recovery sequence described in Section 28.3.7 must be used.
Note: When data is not ready (DRDY=”0”) RNG_DR returns zero.
It is recommended to always verify that RNG_DR is different from zero. Because when it is
the case a seed error occurred between RNG_SR polling and RND_DR output reading (rare
event).
If the random number generation period is a concern to the application and if NIST
compliance is not required it is possible to select a faster RNG configuration by using the
RNG configuration “B”, described in Section 28.6: RNG entropy source validation. The gain
in random number generation speed is summarized in Section 28.5: RNG processing time.

Low-power operations
If the power consumption is a concern to the application, low-power strategies can be used,
as described in Section 28.3.8: RNG low-power usage.

Software post-processing
No specific software post-processing/conditioning is expected to meet the AIS-31 or NIST
SP800-90B approvals.
Built-in health check functions are described in Section 28.3.3: Random number generation.

28.3.6 RNG clocking

The RNG runs on two different clocks: the AHB bus clock and a dedicated RNG clock.
The AHB clock is used to clock the AHB banked registers and conditioning component. The
RNG clock, coupled with a programmable divider (see CLKDIV bitfield in the RNG_CR
register) is used for noise source sampling. Recommended clock configurations are detailed
in Section 28.6: RNG entropy source validation.
Note: When the CED bit in the RNG_CR register is set to “0”, the RNG clock frequency before
internal divider should be higher than AHB clock frequency divided by 32, otherwise the
clock checker always flags a clock error (CECS=1 in the RNG_SR register).
See Section 28.3.1: RNG block diagram for details (AHB and RNG clock domains).

28.3.7 Error management

In parallel to random number generation an health check block verifies the correct noise
source behavior and the frequency of the RNG source clock as detailed in this section.
Associated error state is also described.

Clock error detection

When the clock error detection is enabled (CED = 0) and if the RNG clock frequency is too
low, the RNG sets to “1” both the CEIS and CECS bits to indicate that a clock error
occurred. In this case, the application should check that the RNG clock is configured
correctly (see Section 28.3.6: RNG clocking) and then it must clear the CEIS bit interrupt
flag. The CECS bit is automatically cleared when clocking condition is normal.
Note: The clock error has no impact on generated random numbers, i.e. application can still read
RNG_DR register.

RM0438 Rev 7 947/2194

955
True random number generator (RNG) RM0438

CEIS is set only when CECS is set to “1” by RNG.

Noise source error detection

When a noise source (or seed) error occurs, the RNG stops generating random numbers
and sets to “1” both SEIS and SECS bits to indicate that a seed error occurred. If a value is
available in the RNG_DR register, it must not be used as it may not have enough entropy.
The following sequence must be used to fully recover from a seed error:
1. Software reset by writing CONDRST at 1 and at 0 (see bitfield description for details).
2. wait for CONDRST to be cleared in the RNG_CR register, then confirm that SEIS is
cleared in the RNG_SR register.
3. wait for SECS to be cleared by RNG. The random number generation is now back to
normal.

28.3.8 RNG low-power usage

If power consumption is a concern, the RNG can be disabled as soon as the DRDY bit is set
to “1” by setting the RNGEN bit to “0” in the RNG_CR register. As the post-processing logic
and the output buffer remain operational while RNGEN=’0’ following features are available
to software:
• If there are valid words in the output buffer four random numbers can still be read from
the RNG_DR register.
• If there are valid bits in the conditioning output internal register four additional random
numbers can be still be read from the RNG_DR register. If it is not the case RNG must
be re-enabled by the application until the expected new noise source bits threshold is
reached (128-bit in NIST mode) and a complete conditioning round has been done.
Four new random words are then available only if the expected number of conditioning
round has been reached (two if NISTC=0). The overall time can be found in
Section 28.5: RNG processing time on page 949.
When disabling the RNG the user deactivates all the analog seed generators, whose power
consumption is given in the datasheet electrical characteristics section. The user also gates
all the logic clocked by the RNG clock. Note that this strategy is adding latency before a
random sample is available on the RNG_DR register, because of the RNG initialization time.
If the RNG block is disabled during initialization (i.e. well before the DRDY bit rises for the
first time), the initialization sequence resumes from where it was stopped when RNGEN bit
is set to “1”, unless the application resets the conditioning logic using CONDRST bit in the
RNG_CR register.

28.4 RNG interrupts

In the RNG an interrupt can be produced on the following events:
• Data ready flag
• Seed error, see Section 28.3.7: Error management
• Clock error, see Section 28.3.7: Error management
Dedicated interrupt enable control bits are available as shown in Table 213.

948/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

Table 213. RNG interrupt requests

Interrupt acronym Interrupt event Event flag Enable control bit Interrupt clear method

Data ready flag DRDY IE None (automatic)

Write 0 to SEIS or write
RNG Seed error flag SEIS IE
CONDRST to 1 then to 0
Clock error flag CEIS IE Write 0 to CEIS

The user can enable or disable the above interrupt sources individually by changing the
mask bits or the general interrupt control bit IE in the RNG_CR register. The status of the
individual interrupt sources can be read from the RNG_SR register.
Note: Interrupts are generated only when RNG is enabled.

28.5 RNG processing time

In NIST compliant configuration, the time between two sets of four 32-bit data is either:
• 412 AHB cycles if fAHB < fthreshold (conditioning stage is limiting), or
• 256 RNG cycles fAHB ≥ fthreshold (noise source stage is limiting).
With fthreshold = 1.6 x fAHB, e.g. 77 MHz if fRNG= 48 MHz.
Note: When CLKDIV is different from zero, fRNG must take into account the internal divider ratio.

28.6 RNG entropy source validation

28.6.1 Introduction
In order to assess the amount of entropy available from the RNG, STMicroelectronics has
tested the peripheral using German BSI AIS-31 statistical tests (T0 to T8), and NIST SP800-
90B test suite. The results can be provided on demand or the customer can reproduce the
tests.

28.6.2 Validation conditions

STMicroelectronics has tested the RNG true random number generator in the following
conditions:
• RNG clock rng_clk= 48 MHz
• RNG configurations described in Table 214. Note that only configuration A can be
certified NIST SP800-90B.

Table 214. RNG configurations

RNG_CR bits
Nb
RNG RNG_HTCR
loop
Config NISTC RNG_CONFIG1 CLKDIV RNG_CONFIG2 RNG_CONFIG3 CED register(1)
(N)
bit [5:0] [3:0] [2:0] [3:0] bit

A 0 0x0F 0x0 0x0 0xD 0 2 0x0000

B 1 0x18 0x0 0x0 0x0 0 2 A2B3

RM0438 Rev 7 949/2194

955
True random number generator (RNG) RM0438

1. When writing this register magic number 0x17590ABC must be written immediately before the indicated value

28.6.3 Data collection

In order to run statistical tests it is required to collect samples from the entropy source at raw
data level as well as at the output of the entropy source. For details on data collection and
the running of statistical test suites refer to “STM32 microcontrollers random number
generation validation using NIST statistical test suite” application note (AN4230) available
from www.st.com.
Contact STMicroelectronics if above samples need to be retrieved for your product.

950/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

28.7 RNG registers

The RNG is associated with a control register, a data register and a status register.

28.7.1 RNG control register (RNG_CR)

Address offset: 0x000
Reset value: 0x0080 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CONFI COND
Res. Res. Res. Res. RNG_CONFIG1[5:0] CLKDIV[3:0]
GLOCK RST
rs rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNG_CONFIG2[2:0] NISTC RNG_CONFIG3[3:0] Res. Res. CED Res. IE RNGEN Res. Res.
rw rw rw rw rw rw rw rw rw rw rw

Bit 31 CONFIGLOCK: RNG Config Lock

0: Writes to the RNG_CR configuration bits [29:4] are allowed.
1: Writes to the RNG_CR configuration bits [29:4] are ignored until the next RNG reset.
This bitfield is set once: if this bit is set it can only be reset to 0 if RNG is reset.
Bit 30 CONDRST: Conditioning soft reset
Write 1 and then write 0 to reset the conditioning logic, clear all the FIFOs and start a new
RNG initialization process, with RNG_SR cleared. Registers RNG_CR and RNG_NSCR are
not changed by CONDRST.
This bit must be set to 1 in the same access that set any configuration bits [29:4]. In other
words, when CONDRST bit is set to 1 correct configuration in bits [29:4] must also be
written.
When CONDRST is set to 0 by software its value goes to 0 when the reset process is done.
It takes about 2 AHB clock cycles + 2 RNG clock cycles.
Bits 29:26 Reserved, must be kept at reset value.
Bits 25:20 RNG_CONFIG1[5:0]: RNG configuration 1
Reserved to the RNG configuration (bitfield 1). Must be initialized using the recommended
value documented in Section 28.6: RNG entropy source validation.
Writing any bit of RNG_CONFIG1 is taken into account only if CONDRST bit is set to 1 in the
same access, while CONFIGLOCK remains at 0. Writing to this bit is ignored if
CONFIGLOCK=1.
Bits 19:16 CLKDIV[3:0]: Clock divider factor
This value used to configure an internal programmable divider (from 1 to 16) acting on the
incoming RNG clock. These bits can be written only when the core is disabled (RNGEN=0).
0x0: internal RNG clock after divider is similar to incoming RNG clock.
0x1: two RNG clock cycles per internal RNG clock.
...
0xF: 215 RNG clock cycles per internal clock, e.g. an incoming 48MHz RNG clock becomes
a 1.5 kHz internal RNG clock.
Writing these bits is taken into account only if CONDRST bit is set to 1 in the same access,
while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK=1.
Bits 15:13 RNG_CONFIG2[2:0]: RNG configuration 2
Reserved to the RNG configuration (bitfield 2). Refer to RNG_CONFIG1 bitfield for details.

RM0438 Rev 7 951/2194

955
True random number generator (RNG) RM0438

Bit 12 NISTC: Non NIST compliant

0: Hardware default values for NIST compliant RNG. In this configuration per 128-bit output
two conditioning loops are performed and 256 bits of noise source are used.
1: Custom values for NIST compliant RNG. See Section 28.6: RNG entropy source
validation for
proposed configuration.
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access, while
CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK=1.
Bits 11:8 RNG_CONFIG3[3:0]: RNG configuration 3
Reserved to the RNG configuration (bitfield 3). Refer to RNG_CONFIG1 bitfield for details.
If NISTC bit is cleared in this register RNG_CONFIG3 bitfield values are ignored by RNG.
Bit 7 Reserved, must be kept at reset value.
Bit 6 Reserved, must be kept at reset value.
Bit 5 CED: Clock error detection
0: Clock error detection is enable
1: Clock error detection is disable
The clock error detection cannot be enabled nor disabled on-the-fly when the RNG is
enabled, i.e. to enable or disable CED the RNG must be disabled.
Writing this bit is taken into account only if CONDRST bit is set to 1 in the same access,
while CONFIGLOCK remains at 0. Writing to this bit is ignored if CONFIGLOCK=1.
Bit 4 Reserved, must be kept at reset value.
Bit 3 IE: Interrupt Enable
0: RNG Interrupt is disabled
1: RNG Interrupt is enabled. An interrupt is pending as soon as DRDY=’1’, SEIS=’1’ or
CEIS=1 in the RNG_SR register.
Bit 2 RNGEN: True random number generator enable
0: True random number generator is disabled. Analog noise sources are powered off and
logic clocked by the RNG clock is gated.
1: True random number generator is enabled.
Bits 1:0 Reserved, must be kept at reset value.

952/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

28.7.2 RNG status register (RNG_SR)

Address offset: 0x004
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. SEIS CEIS Res. Res. SECS CECS DRDY
rc_w0 rc_w0 r r r

Bits 31:7 Reserved, must be kept at reset value.

Bit 6 SEIS: Seed error interrupt status
This bit is set at the same time as SECS. It is cleared by writing 0 (unless CONDRST is
used). Writing 1 has no effect.
0: No faulty sequence detected
1: At least one faulty sequence has been detected. See SECS bit description for details.
An interrupt is pending if IE = 1 in the RNG_CR register.
Bit 5 CEIS: Clock error interrupt status
This bit is set at the same time as CECS. It is cleared by writing 0. Writing 1 has no effect.
0: The RNG clock is correct (fRNGCLK> fHCLK/32)
1: The RNG clock before internal divider has been detected too slow (fRNGCLK< fHCLK/32)
An interrupt is pending if IE = 1 in the RNG_CR register.
Bits 4:3 Reserved, must be kept at reset value.
Bit 2 SECS: Seed error current status
0: No faulty sequence has currently been detected. If the SEIS bit is set, this means that a
faulty sequence was detected and the situation has been recovered.
1: At least one of the following faulty sequence has been detected:
– Run-time repetition count test failed (noise source has provided more than 24
consecutive bits at a constant value 0” or 1”, or more than 32 consecutive
occurrence of two bits patterns 01” or 10”)
– Start-up or continuous adaptive proportion test on noise source failed.
– Start-up post-processing/conditioning sanity check failed.

Bit 1 CECS: Clock error current status

0: The RNG clock is correct (fRNGCLK> fHCLK/32). If the CEIS bit is set, this means that a
slow clock was detected and the situation has been recovered.
1: The RNG clock is too slow (fRNGCLK< fHCLK/32).
Note: CECS bit is valid only if the CED bit in the RNG_CR register is set to 0.
Bit 0 DRDY: Data Ready
0: The RNG_DR register is not yet valid, no random data is available.
1: The RNG_DR register contains valid random data.
Once the output buffer becomes empty (after reading the RNG_DR register), this bit returns
to 0 until a new random value is generated.
Note: The DRDY bit can rise when the peripheral is disabled (RNGEN=0 in the RNG_CR
register).
If IE=1 in the RNG_CR register, an interrupt is generated when DRDY=1.

RM0438 Rev 7 953/2194

955
True random number generator (RNG) RM0438

28.7.3 RNG data register (RNG_DR)

Address offset: 0x008
Reset value: 0x0000 0000
The RNG_DR register is a read-only register that delivers a 32-bit random value when read.
The content of this register is valid when DRDY=1 and value is not 0x0, even if RNGEN=0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RNDATA[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RNDATA[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 RNDATA[31:0]: Random data

32-bit random data which are valid when DRDY=1. When DRDY=0 RNDATA value is zero.
It is recommended to always verify that RNG_DR is different from zero. Because when it is
the case a seed error occurred between RNG_SR polling and RND_DR output reading
(rare event).

28.7.4 RNG health test control register (RNG_HTCR)

Address offset: 0x010
Reset value: 0x000C AA74
Writing in RNG_HTCR is taken into account only if CONDRST bit is set, and CONFIGLOCK
bit is cleared in RNG_CR. Writing to this register is ignored if CONFIGLOCK=1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HTCFG[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HTCFG[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 HTCFG[31:0]: health test configuration

This configuration is used by RNG to configure the health tests. See Section 28.6: RNG
entropy source validation for the recommended value.
Note: The RNG behavior, including the read to this register, is not guaranteed if a different
value from the recommended value is written.
When reading or writing this register magic number; 0x17590ABC must be written
immediately before to RNG_HTCR register.

954/2194 RM0438 Rev 7

RM0438 True random number generator (RNG)

28.7.5 RNG register map

Table 215 gives the RNG register map and reset values.

Table 215. RNG register map and reset map

Offset Register name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
CONFIGLOCK
CONDRST
RNG_C RNG_CO

RNGEN
NISTC
RNG_CONFIG1 .CLKDIV

CED
Res.
Res.
Res.
Res.

Res.
Res.

Res.

Res.
Res.
RNG_CR ONFIG NFIG3

IE
0x000 [5:0] [3:0]
2[2:0] [3:0]

Reset value 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DRDY
CECS
SECS
CEIS
SEIS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
RNG_SR
0x004
Reset value 0 0 0 0 0
RNG_DR RNDATA[31:0]
0x008
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RNG_HTCR HTCFG[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 0 0

Refer to Section 2.3 for the register boundary addresses.

RM0438 Rev 7 955/2194

955
AES hardware accelerator (AES) RM0438

29 AES hardware accelerator (AES)

29.1 Introduction
The AES hardware accelerator (AES) encrypts or decrypts data, using an algorithm and
implementation fully compliant with the advanced encryption standard (AES) defined in
Federal information processing standards (FIPS) publication 197.
The peripheral supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key
sizes of 128 or 256 bits.
AES is an AMBA AHB slave peripheral accessible through 32-bit single accesses only.
Other access types generate an AHB error, and other than 32-bit writes may corrupt the
register content.
The peripheral supports DMA single transfers for incoming and outgoing data (two DMA
channels required).

29.2 AES main features

• Compliance with NIST “Advanced encryption standard (AES), FIPS publication 197”
from November 2001
• 128-bit data block processing
• Support for cipher key lengths of 128-bit and 256-bit
• Encryption and decryption with multiple chaining modes:
– Electronic codebook (ECB) mode
– Cipher block chaining (CBC) mode
– Counter (CTR) mode
– Galois counter mode (GCM)
– Galois message authentication code (GMAC) mode
– Counter with CBC-MAC (CCM) mode
• 51 or 75 clock cycle latency in ECB mode for processing one 128-bit block of data with,
respectively, 128-bit or 256-bit key
• Integrated round key scheduler to compute the last round key for ECB/CBC decryption
• AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
• 256-bit write-only register for storing the cryptographic key (eight 32-bit registers)
• 128-bit register for storing initialization vector (four 32-bit registers)
• 32-bit buffer for data input and output
• Automatic data flow control with support of single-transfer direct memory access (DMA)
using two channels (one for incoming data, one for processed data)
• Data-swapping logic to support 1-, 8-, 16- or 32-bit data
• Possibility for software to suspend a message if AES needs to process another
message with a higher priority, then resume the original message

956/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.3 AES implementation

The devices have one AES peripheral.

29.4 AES functional description

29.4.1 AES block diagram

Figure 194 shows the block diagram of AES.

Figure 194. AES block diagram

AES 32-bit
access Banked registers

32-bit key AES_KEYRx KEY

AHB bus IV, counter AES_IVRx IVI

status AES_SR
AHB
interface control AES_CR
swap AES
aes_hclk
data in AES_DINR DIN Core
(AEA)
data out AES_DOUTR DOUT

AES_SUSPRx Save / Restore

aes_in_dma DMA
aes_out_dma interface Control Logic

IRQ
aes_it
interface

MSv42154V1

29.4.2 AES internal signals

Table 216 describes the user relevant internal signals interfacing the AES peripheral.

Table 216. AES internal input/output signals

Signal name Signal type Description

aes_hclk Input AHB bus clock

aes_it Output AES interrupt request
aes_in_dma Input/Output Input DMA single request/acknowledge
aes_out_dma Input/Output Output DMA single request/acknowledge

RM0438 Rev 7 957/2194

1004
AES hardware accelerator (AES) RM0438

29.4.3 AES cryptographic core

Overview
The AES cryptographic core consists of the following components:
• AES core algorithm (AEA)
• multiplier over a binary Galois field (GF2mul)
• key input
• initialization vector (IV) input
• chaining algorithm logic (XOR, feedback/counter, mask)
The AES core works on 128-bit data blocks (four words) with 128-bit or 256-bit key length.
Depending on the chaining mode, the AES requires zero or one 128-bit initialization vector
IV.
The AES features the following modes of operation:
• Mode 1:
Plaintext encryption using a key stored in the AES_KEYRx registers
• Mode 2:
ECB or CBC decryption key preparation. It must be used prior to selecting Mode 3 with
ECB or CBC chaining modes. The key prepared for decryption is stored automatically
in the AES_KEYRx registers. Now the AES peripheral is ready to switch to Mode 3 for
executing data decryption.
• Mode 3:
Ciphertext decryption using a key stored in the AES_KEYRx registers. When ECB and
CBC chaining modes are selected, the key must be prepared beforehand, through
Mode 2.
Note: Mode 2 is only used when performing ECB and CBC decryption.
The operating mode is selected by programming the MODE[1:0] bitfield of the AES_CR
register. It may be done only when the AES peripheral is disabled.

Typical data processing

Typical usage of the AES is described in Section 29.4.4: AES procedure to perform a cipher
operation on page 963.
Note: The outputs of the intermediate AEA stages are never revealed outside the cryptographic
boundary, with the exclusion of the IVI bitfield.

Chaining modes
The following chaining modes are supported by AES, selected through the CHMOD[2:0]
bitfield of the AES_CR register:
• Electronic code book (ECB)
• Cipher block chaining (CBC)
• Counter (CTR)
• Galois counter mode (GCM)
• Galois message authentication code (GMAC)
• Counter with CBC-MAC (CCM)

958/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Note: The chaining mode may be changed only when AES is disabled (bit EN of the AES_CR
register cleared).
Principle of each AES chaining mode is provided in the following subsections.
Detailed information is in dedicated sections, starting from Section 29.4.8: AES basic
chaining modes (ECB, CBC).

Electronic codebook (ECB) mode

Figure 195. ECB encryption and decryption principle

Encryption
Plaintext block 1 Plaintext block 2 Plaintext block 3

key key key

Encrypt Encrypt Encrypt

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Decryption
Plaintext block 1 Plaintext block 2 Plaintext block 3

Legend key key key

Decrypt Decrypt Decrypt
input

output
key
scheduling Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42140V1

ECB is the simplest mode of operation. There are no chaining operations, and no special
initialization stage. The message is divided into blocks and each block is encrypted or
decrypted separately.
Note: For decryption, a special key scheduling is required before processing the first block.

RM0438 Rev 7 959/2194

1004
AES hardware accelerator (AES) RM0438

Cipher block chaining (CBC) mode

Figure 196. CBC encryption and decryption principle

Encryption
Plaintext block 1 Plaintext block 2 Plaintext block 3

initialization
vector

key key key

Encrypt Encrypt Encrypt

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Decryption
Plaintext block 1 Plaintext block 2 Plaintext block 3
initialization
vector
Legend key key key
Decrypt Decrypt Decrypt
input

output
key
scheduling Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42141V1

In CBC mode the output of each block chains with the input of the following block. To make
each message unique, an initialization vector is used during the first block processing.
Note: For decryption, a special key scheduling is required before processing the first block.

960/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Counter (CTR) mode

Figure 197. CTR encryption and decryption principle

Encryption
Counter +1 Counter +1 Counter

value value + 1 value + 2

key key key

Encrypt Encrypt Encrypt

Plaintext block 1 Plaintext block 2 Plaintext block 3

Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Decryption
Counter +1 Counter +1 Counter

value value + 1 value + 2

Legend key key key

Decrypt Decrypt Decrypt
input

output
Plaintext block 1 Plaintext block 2 Plaintext block 3
XOR
Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

MSv42142V1

The CTR mode uses the AES core to generate a key stream. The keys are then XORed
with the plaintext to obtain the ciphertext as specified in NIST Special Publication 800-38A,
Recommendation for Block Cipher Modes of Operation.
Note: Unlike with ECB and CBC modes, no key scheduling is required for the CTR decryption,
since in this chaining scheme the AES core is always used in encryption mode for producing
the key stream, or counter blocks.

RM0438 Rev 7 961/2194

1004
AES hardware accelerator (AES) RM0438

Galois/counter mode (GCM)

Figure 198. GCM encryption and authentication principle

Initialization Counter +1 Counter +1 Counter

vector
value value + 1 value + 2

key Init key key key

Encrypt Encrypt Encrypt
(Encrypt)

Plaintext block 1 Plaintext block 2 Plaintext block 3

H Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

Legend

input GF2mul GF2mul GF2mul

output

XOR
Final TAG

MSv42143V1

In Galois/counter mode (GCM), the plaintext message is encrypted while a message

authentication code (MAC) is computed in parallel, thus generating the corresponding
ciphertext and its MAC (also known as authentication tag). It is defined in NIST Special
Publication 800-38D, Recommendation for Block Cipher Modes of Operation -
Galois/Counter Mode (GCM) and GMAC.
GCM mode is based on AES in counter mode for confidentiality. It uses a multiplier over a
fixed finite field for computing the message authentication code. It requires an initial value
and a particular 128-bit block at the end of the message.

Galois message authentication code (GMAC) principle

Figure 199. GMAC authentication principle

Initialization
vector

key Plaintext block 1 Plaintext block 2 Plaintext block 3

Init
(Encrypt)

H GF2mul GF2mul GF2mul

Legend

input

output
Final TAG
XOR
MSv42144V1

Galois message authentication code (GMAC) allows authenticating a message and

generating the corresponding message authentication code (MAC). It is defined in NIST
Special Publication 800-38D, Recommendation for Block Cipher Modes of Operation -
Galois/Counter Mode (GCM) and GMAC.

962/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

GMAC is similar to GCM, except that it is applied on a message composed only by plaintext
authenticated data (that is, only header, no payload).

Counter with CBC-MAC (CCM) principle

Figure 200. CCM encryption and authentication principle

B0 Count 1 +1 Count 2 +1 Count 3

key Init key key key

Encrypt Encrypt Encrypt
(Encrypt)

Plaintext block 1 Plaintext block 2 Plaintext block 3

Initialization Ciphertext block 1 Ciphertext block 2 Ciphertext block 3

vector

Legend
key
input Encrypt Encrypt Encrypt

output

XOR
Final TAG

MSv42145V1

In Counter with cipher block chaining-message authentication code (CCM) mode, the
plaintext message is encrypted while a message authentication code (MAC) is computed in
parallel, thus generating the corresponding ciphertext and the corresponding MAC (also
known as tag). It is described by NIST in Special Publication 800-38C, Recommendation for
Block Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality.
CCM mode is based on AES in counter mode for confidentiality and it uses CBC for
computing the message authentication code. It requires an initial value.
Like GCM, the CCM chaining mode can be applied on a message composed only by
plaintext authenticated data (that is, only header, no payload). Note that this way of using
CCM is not called CMAC (it is not similar to GCM/GMAC), and its usage is not
recommended by NIST.

29.4.4 AES procedure to perform a cipher operation

Introduction
A typical cipher operation is explained below. Detailed information is provided in sections
starting from Section 29.4.8: AES basic chaining modes (ECB, CBC).

RM0438 Rev 7 963/2194

1004
AES hardware accelerator (AES) RM0438

Initialization of AES
To initialize AES, first disable it by clearing the EN bit of the AES_CR register. Then perform
the following steps in any order:
• Configure the AES mode, by programming the MODE[1:0] bitfield of the AES_CR
register.
– For encryption, select Mode 1 (MODE[1:0] = 00).
– For decryption, select Mode 3 (MODE[1:0] = 10), unless ECB or CBC chaining
modes are used. In this latter case, perform an initial key derivation of the
encryption key, as described in Section 29.4.5: AES decryption round key
preparation.
• Select the chaining mode, by programming the CHMOD[2:0] bitfield of the AES_CR
register.
• Configure the data type (1-, 8-, 16- or 32-bit), with the DATATYPE[1:0] bitfield in the
AES_CR register.
• When it is required (for example in CBC or CTR chaining modes), write the initialization
vector into the AES_IVRx registers.
• Configure the key size (128-bit or 256-bit), with the KEYSIZE bitfield of the AES_CR
register.
• Write a symmetric key into the AES_KEYRx registers (4 or 8 registers depending on
the key size).

Data append
This section describes different ways of appending data for processing, where the size of
data to process is not a multiple of 128 bits.
For ECB or CBC mode, refer to Section 29.4.6: AES ciphertext stealing and data padding.
The last block management in these cases is more complex than in the sequence described
in this section.
Data append through polling
This method uses flag polling to control the data append through the following sequence:
1. Enable the AES peripheral by setting the EN bit of the AES_CR register.
2. Repeat the following sub-sequence until the payload is entirely processed:
a) Write four input data words into the AES_DINR register.
b) Wait until the status flag CCF is set in the AES_SR, then read the four data words
from the AES_DOUTR register.
c) Clear the CCF flag, by setting the CCFC bit of the AES_CR register.
d) If the data block just processed is the second-last block of the message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros and, in case of GCM payload encryption or
CCM payload decryption, specify the number of non-valid bytes, using the NPBLB
bitfield of the AES_CR register, for AES to compute a correct tag;.
3. As it is the last block, discard the data that is not part of the data, then disable the AES
peripheral by clearing the EN bit of the AES_CR register.
Note: Up to three wait cycles are automatically inserted between two consecutive writes to the
AES_DINR register, to allow sending the key to the AES processor.
NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.

964/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Data append using interrupt

The method uses interrupt from the AES peripheral to control the data append, through the
following sequence:
1. Enable interrupts from AES by setting the CCFIE bit of the AES_CR register.
2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. Write first four input data words into the AES_DINR register.
4. Handle the data in the AES interrupt service routine, upon interrupt:
a) Read four output data words from the AES_DOUTR register.
b) Clear the CCF flag and thus the pending interrupt, by setting the CCFC bit of the
AES_CR register.
c) If the data block just processed is the second-last block of an message and the
significant data in the last block to process is inferior to 128 bits, pad the
remainder of the last block with zeros and, in case of GCM payload encryption or
CCM payload decryption, specify the number of non-valid bytes, using the NPBLB
bitfield of the AES_CR register, for AES to compute a correct tag;. Then proceed
with point 4e).
d) If the data block just processed is the last block of the message, discard the data
that is not part of the data, then disable the AES peripheral by clearing the EN bit
of the AES_CR register and quit the interrupt service routine.
e) Write next four input data words into the AES_DINR register and quit the interrupt
service routine.
Note: AES is tolerant of delays between consecutive read or write operations, which allows, for
example, an interrupt from another peripheral to be served between two AES computations.
NPBLB bits are not used in header phase of GCM, GMAC and CCM chaining modes.
Data append using DMA
With this method, all the transfers and processing are managed by DMA and AES. To use
the method, proceed as follows:
1. Prepare the last four-word data block (if the data to process does not fill it completely),
by padding the remainder of the block with zeros.
2. Configure the DMA controller so as to transfer the data to process from the memory to
the AES peripheral input and the processed data from the AES peripheral output to the
memory, as described in Section 29.4.16: AES DMA interface. Configure the DMA
controller so as to generate an interrupt on transfer completion. In case of GCM
payload encryption or CCM payload decryption, DMA transfer must not include the
last four-word block if padded with zeros. The sequence described in Data append
through polling must be used instead for this last block, because NPBLB bits must be
setup before processing the block, for AES to compute a correct tag.
3. Enable the AES peripheral by setting the EN bit of the AES_CR register
4. Enable DMA requests by setting the DMAINEN and DMAOUTEN bits of the AES_CR
register.
5. Upon DMA interrupt indicating the transfer completion, get the AES-processed data
from the memory.
Note: The CCF flag has no use with this method, because the reading of the AES_DOUTR
register is managed by DMA automatically, without any software action, at the end of the
computation phase.
NPBLB bits are not used in header phase of GCM, GMAC, and CCM chaining modes.

RM0438 Rev 7 965/2194

1004
AES hardware accelerator (AES) RM0438

29.4.5 AES decryption round key preparation

Internal key schedule is used to generate AES round keys. In AES encryption, the round 0
key is the one stored in the key registers. AES decryption must start using the last round
key. As the encryption key is stored in memory, a special key scheduling must be performed
to obtain the decryption key. This key scheduling is only required for AES decryption in ECB
and CBC modes.
Recommended method is to select the Mode 2 by setting to 01 the MODE[1:0] bitfield of the
AES_CR (key process only), then proceed with the decryption by setting MODE[1:0] to 10
(Mode 3, decryption only). Mode 2 usage is described below:
1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. Select Mode 2 by setting to 01 the MODE[1:0] bitfield of the AES_CR. The
CHMOD[2:0] bitfield is not significant in this case because this key derivation mode is
independent of the chaining algorithm selected.
3. Set key length to 128 or 256 bits, via KEYSIZE bit of AES_CR register.
4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Writes to the
AES_IVRx registers have no effect.
5. Enable the AES peripheral, by setting the EN bit of the AES_CR register.
6. Wait until the CCF flag is set in the AES_SR register.
7. Clear the CCF flag. Derived key is available in AES core, ready to use for decryption.
Note: The AES is disabled by hardware when the derivation key is available.
To restart a derivation key computation, repeat steps 4, 5, 6, and 7.
Note: The operation of the key preparation lasts 59 or 82 clock cycles, depending on the key size
(128- or 256-bit).

29.4.6 AES ciphertext stealing and data padding

When using AES in ECB or CBC modes to manage messages the size of which is not a
multiple of the block size (128 bits), ciphertext stealing techniques are used, such as those
described in NIST Special Publication 800-38A, Recommendation for Block Cipher Modes
of Operation: Three Variants of Ciphertext Stealing for CBC Mode. Since the AES peripheral
does not support such techniques, the application must complete the last block of input data
using data from the second last block.
Note: Ciphertext stealing techniques are not documented in this reference manual.
Similarly, when AES is used in other modes than ECB or CBC, an incomplete input data
block (that is, block with input data shorter than 128 bits) must be padded with zeros prior to
encryption (that is, extra bits must be appended to the trailing end of the data string). After
decryption, the extra bits must be discarded. As AES does not implement automatic data
padding operation to the last block, the application must follow the recommendation given
in Section 29.4.4: AES procedure to perform a cipher operation on page 963 to manage
messages the size of which is not a multiple of 128 bits.
Note: Padding data are swapped in a similar way as normal data, according to the
DATATYPE[1:0] field of the AES_CR register (see Section 29.4.13: AES data registers and
data swapping for details).

966/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.4.7 AES task suspend and resume

A message can be suspended if another message with a higher priority must be processed.
When this highest priority message is sent, the suspended message can resume in both
encryption or decryption mode.
Suspend/resume operations do not break the chaining operation and the message
processing can resume as soon as AES is enabled again to receive the next data block.
Figure 201 gives an example of suspend/resume operation: Message 1 is suspended in
order to send a shorter and higher-priority Message 2.

Figure 201. Example of suspend mode management

Message 1 Message 2

128-bit block 1

New higher-priority 128-bit block 2

message 2 to be
AES suspend
processed
sequence
128-bit block 3

128-bit block 1

128-bit block 2
128-bit block 4

AES resume
128-bit block 5
sequence

128-bit block 6

...
MSv42148V1

A detailed description of suspend/resume operations is in the sections dedicated to each

AES mode.

29.4.8 AES basic chaining modes (ECB, CBC)

Overview
This section gives a brief explanation of the four basic operation modes provided by the
AES core: ECB encryption, ECB decryption, CBC encryption and CBC decryption. For
detailed information, refer to the FIPS publication 197 from November 26, 2001.

RM0438 Rev 7 967/2194

1004
AES hardware accelerator (AES) RM0438

Figure 202 illustrates the electronic codebook (ECB) encryption.

Figure 202. ECB encryption

Block 1 Block 2
AES_DINR (plaintext P1) AES_DINR (plaintext P2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt

O1 O2
Legend Swap AES core Swap
DATATYPE[1:0] management DATATYPE[1:0] management
input

output AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)

MSv19105V2

In ECB encrypt mode, the 128-bit plaintext input data block Px in the AES_DINR register
first goes through bit/byte/half-word swapping. The swap result Ix is processed with the AES
core set in encrypt mode, using a 128- or 256-bit key. The encryption result Ox goes through
bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit ciphertext
output data block Cx. The ECB encryption continues in this way until the last complete
plaintext block is encrypted.
Figure 203 illustrates the electronic codebook (ECB) decryption.

Figure 203. ECB decryption

Block 1 Block 2
AES_DINR (ciphertext C1) AES_DINR (ciphertext C2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Decrypt Decrypt

O1 O2
Legend Swap Swap
DATATYPE[1:0] management DATATYPE[1:0] management
input

output
AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)
MSv19106V2

To perform an AES decryption in the ECB mode, the secret key has to be prepared by
collecting the last-round encryption key (which requires to first execute the complete key
schedule for encryption), and using it as the first-round key for the decryption of the
ciphertext. This preparation is supported by the AES core.
In ECB decrypt mode, the 128-bit ciphertext input data block C1 in the AES_DINR register
first goes through bit/byte/half-word swapping. The keying sequence is reversed compared
to that of the ECB encryption. The swap result I1 is processed with the AES core set in
decrypt mode, using the formerly prepared decryption key. The decryption result goes
through bit/byte/half-word swapping, then is stored in the AES_DOUTR register as 128-bit
plaintext output data block P1. The ECB decryption continues in this way until the last
complete ciphertext block is decrypted.

968/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Figure 204 illustrates the cipher block chaining (CBC) encryption.

Figure 204. CBC encryption

Block 1 Block 2
AES_DINR (plaintext P1) AES_DINR (plaintext P2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management
AES_IVRx (init. vector)
P1' P2'
IVI
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Block cipher Block cipher
encryption encryption
O1 O2
Legend
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
input management management

output
AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)
XOR
MSv19107V2

In CBC encrypt mode, the first plaintext input block, after bit/byte/half-word swapping (P1’),
is XOR-ed with a 128-bit IVI bitfield (initialization vector and counter), producing the I1 input
data for encrypt with the AES core, using a 128- or 256-bit key. The resulting 128-bit output
block O1, after swapping operation, is used as ciphertext C1. The O1 data is then XOR-ed
with the second-block plaintext data P2’ to produce the I2 input data for the AES core to
produce the second block of ciphertext data. The chaining of data blocks continues in this
way until the last plaintext block in the message is encrypted.
If the message size is not a multiple of 128 bits, the final partial data block is encrypted in
the way explained in Section 29.4.6: AES ciphertext stealing and data padding.
Figure 205 illustrates the cipher block chaining (CBC) decryption.

Figure 205. CBC decryption

Block 1 Block 2
AES_DINR (ciphertext C1) AES_DINR (ciphertext C2)

DATATYPE[1:0] Swap DATATYPE[1:0] Swap

management management

I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Decrypt Decrypt

AES_IVRx (IV) O1 O2
IVI
P1' P2'
Legend
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
management management
input

output
AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)
XOR
MSv19104V2

In CBC decrypt mode, like in ECB decrypt mode, the secret key must be prepared to
perform an AES decryption.
After the key preparation process, the decryption goes as follows: the first 128-bit ciphertext
block (after the swap operation) is used directly as the AES core input block I1 for decrypt
operation, using the 128-bit or 256-bit key. Its output O1 is XOR-ed with the 128-bit IVI field
(that must be identical to that used during encryption) to produce the first plaintext block P1.

RM0438 Rev 7 969/2194

1004
AES hardware accelerator (AES) RM0438

The second ciphertext block is processed in the same way as the first block, except that the
I1 data from the first block is used in place of the initialization vector.
The decryption continues in this way until the last complete ciphertext block is decrypted.
If the message size is not a multiple of 128 bits, the final partial data block is decrypted in
the way explained in Section 29.4.6: AES ciphertext stealing and data padding.
For more information on data swapping, refer to Section 29.4.13: AES data registers and
data swapping.

ECB/CBC encryption sequence

The sequence of events to perform an ECB/CBC encryption (more detail in Section 29.4.4):
1. Disable the AES peripheral by clearing the EN bit of the AES_CR register.
2. Select the Mode 1 by setting to 00 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR
register to 000 or 001, respectively. Data type can also be defined, using
DATATYPE[1:0] bitfield.
3. Select 128- or 256-bit key length through the KEYSIZE bit of the AES_CR register.
4. Write the AES_KEYRx registers (128 or 256 bits) with encryption key. Fill the
AES_IVRx registers with the initialization vector data if CBC mode has been selected.
5. Enable the AES peripheral by setting the EN bit of the AES_CR register.
6. Write the AES_DINR register four times to input the plaintext (MSB first), as shown in
Figure 206.
7. Wait until the CCF flag is set in the AES_SR register.
8. Read the AES_DOUTR register four times to get the ciphertext (MSB first) as shown in
Figure 206. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
9. Repeat steps 6-7-8 to process all the blocks with the same encryption key.

Figure 206. ECB/CBC encryption (Mode 1)

WR WR WR WR RD RD RD RD
Wait until flag CCF = 1
PT3 PT2 PT1 PT0 CT3 CT2 CT1 CT0
MSB LSB MSB LSB

Input phase Computation phase Output phase

4 write operations into 4 read operations of
AES_DINR[31:0] AES_DOUTR[31:0]

PT = plaintext = 4 words (PT3, … , PT0)

CT = ciphertext = 4 words (CT3, … , CT0)
MS18936V3

ECB/CBC decryption sequence

The sequence of events to perform an AES ECB/CBC decryption is as follows (More detail
in Section 29.4.4).
1. Follow the steps described in Section 29.4.5: AES decryption round key preparation, in
order to prepare the decryption key in AES core.
2. Select the Mode 3 by setting to 10 the MODE[1:0] bitfield of the AES_CR register and
select ECB or CBC chaining mode by setting the CHMOD[2:0] bitfield of the AES_CR

970/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

register to 000 or 001, respectively. Data type can also be defined, using
DATATYPE[1:0] bitfield. KEYSIZE bitfield must be kept as-is.
3. Write the AES_IVRx registers with the initialization vector (required in CBC mode only).
4. Enable AES by setting the EN bit of the AES_CR register.
5. Write the AES_DINR register four times to input the cipher text (MSB first), as shown in
Figure 207.
6. Wait until the CCF flag is set in the AES_SR register.
7. Read the AES_DOUTR register four times to get the plain text (MSB first), as shown in
Figure 207. Then clear the CCF flag by setting the CCFC bit of the AES_CR register.
8. Repeat steps 5-6-7 to process all the blocks encrypted with the same key.

Figure 207. ECB/CBC decryption (Mode 3)

WR WR WR WR RD RD RD RD
Wait until flag CCF = 1
CT3 CT2 CT1 CT0 PT3 PT2 PT1 PT0
MSB LSB MSB LSB

Input phase Computation phase Output phase

4 write operations into 4 read operations from
AES_DINR[31:0] AES_DOUTR[31:0]

PT = plaintext = 4 words (PT3, … , PT0)

CT = ciphertext = 4 words (CT3, … , CT0)
MS18938V3

Suspend/resume operations in ECB/CBC modes

To suspend the processing of a message, proceed as follows:
1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register.
2. If DMA is not used, read four times the AES_DOUTR register to save the last
processed block. If DMA is used, wait until the CCF flag is set in the AES_SR register
then stop the DMA transfers from the OUT FIFO by clearing the DMAOUTEN bit of the
AES_CR register.
3. If DMA is not used, poll the CCF flag of the AES_SR register until it becomes 1
(computation completed).
4. Clear the CCF flag by setting the CCFC bit of the AES_CR register.
5. Save initialization vector registers (only required in CBC mode as AES_IVRx registers
are altered during the data processing).
6. Disable the AES peripheral by clearing the bit EN of the AES_CR register.
7. Save the AES_CR register and clear the key registers if they are not needed, to
process the higher priority message.
8. If DMA is used, save the DMA controller status (pointers for IN and OUT data transfers,
number of remaining bytes, and so on).

RM0438 Rev 7 971/2194

1004
AES hardware accelerator (AES) RM0438

To resume the processing of a message, proceed as follows:

1. If DMA is used, configure the DMA controller so as to complete the rest of the FIFO IN
and FIFO OUT transfers.
2. Ensure that AES is disabled (the EN bit of the AES_CR must be 0).
3. Restore AES_CR register (with correct KEYSIZE) then restore AES_KEYRx registers.
4. Prepare the decryption key as described in Section 29.4.5: AES decryption round key
preparation (only required for ECB or CBC decryption).
5. Restore AES_IVRx registers using the saved configuration (only required in CBC
mode).
6. Enable the AES peripheral by setting the EN bit of the AES_CR register.
7. If DMA is used, enable AES DMA transfers by setting the DMAINEN and DMAOUTEN
bits of the AES_CR register.

29.4.9 AES counter (CTR) mode

Overview
The counter mode (CTR) uses AES as a key-stream generator. The generated keys are
then XOR-ed with the plaintext to obtain the ciphertext.
CTR chaining is defined in NIST Special Publication 800-38A, Recommendation for Block
Cipher Modes of Operation. A typical message construction in CTR mode is given in
Figure 208.

Figure 208. Message construction in CTR mode

16-byte boundaries

Zero
ICB Ciphertext (C) 0 padding
decrypt

4-byte boundaries
Plaintext (P)
Initialization vector (IV) Counter

MSv42156V1

The structure of this message is:

• A 16-byte initial counter block (ICB), composed of two distinct fields:
– Initialization vector (IV): a 96-bit value that must be unique for each encryption
cycle with a given key.
– Counter: a 32-bit big-endian integer that is incremented each time a block
processing is completed. The initial value of the counter must be set to 1.
• The plaintext P is encrypted as ciphertext C, with a known length. This length can be
non-multiple of 16 bytes, in which case a plaintext padding is required.

972/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

CTR encryption and decryption

Figure 209 and Figure 210 describe the CTR encryption and decryption process,
respectively, as implemented in the AES peripheral. The CTR mode is selected by writing
010 to the CHMOD[2:0] bitfield of AES_CR register.

Figure 209. CTR encryption

Block 1 Block 2
AES_IVRx AES_IVRx
Nonce + 32-bit counter Nonce + 32-bit counter (+1)
Counter
increment (+1)
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt

AES_DINR (plaintext P1) O1 AES_DINR (plaintext P2) O2

Swap DATATYPE[1:0] Swap DATATYPE[1:0]

management management
P1' P2'
Legend C1' C2'
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
input management management
output
AES_DOUTR (ciphertext C1) AES_DOUTR (ciphertext C2)
XOR
MSv19102V3

Figure 210. CTR decryption

Block 1 Block 2
AES_IVRx AES_IVRx
Nonce + 32-bit counter Nonce + 32-bit counter (+1)
Counter
increment (+1)
I1 I2
AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt

AES_DINR (ciphertext C1) O1 AES_DINR (ciphertext C2) O2

Swap DATATYPE[1:0] Swap DATATYPE[1:0]

management management
C1' C2'
Legend P1' P2'
DATATYPE[1:0] Swap DATATYPE[1:0] Swap
input management management

output
AES_DOUTR (plaintext P1) AES_DOUTR (plaintext P2)
XOR
MSv18942V2

In CTR mode, the cryptographic core output (also called keystream) Ox is XOR-ed with
relevant input block (Px' for encryption, Cx' for decryption), to produce the correct output
block (Cx' for encryption, Px' for decryption). Initialization vectors in AES must be initialized
as shown in Table 217.

Table 217. CTR mode initialization vector definition

AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

Nonce[31:0] Nonce[63:32] Nonce[95:64] 32-bit counter = 0x0001

RM0438 Rev 7 973/2194

1004
AES hardware accelerator (AES) RM0438

Unlike in CBC mode that uses the AES_IVRx registers only once when processing the first
data block, in CTR mode AES_IVRx registers are used for processing each data block, and
the AES peripheral increments the counter bits of the initialization vector (leaving the nonce
bits unchanged).
CTR decryption does not differ from CTR encryption, since the core always encrypts the
current counter block to produce the key stream that is then XOR-ed with the plaintext (CTR
encryption) or ciphertext (CTR decryption) input. In CTR mode, the MODE[1:0] bitfield
setting 01 (key derivation) is forbidden and all the other settings default to encryption mode.
The sequence of events to perform an encryption or a decryption in CTR chaining mode:
1. Ensure that AES is disabled (the EN bit of the AES_CR must be 0).
2. Select CTR chaining mode by setting to 010 the CHMOD[2:0] bitfield of the AES_CR
register. Set MODE[1:0] bitfield to any value other than 01.
3. Initialize the AES_KEYRx registers, and load the AES_IVRx registers as described in
Table 217.
4. Set the EN bit of the AES_CR register, to start encrypting the current counter (EN is
automatically reset when the calculation finishes).
5. If it is the last block, pad the data with zeros to have a complete block, if needed.
6. Append data in AES, and read the result. The three possible scenarios are described in
Section 29.4.4: AES procedure to perform a cipher operation.
7. Repeat the previous step till the second-last block is processed. For the last block,
apply the two previous steps and discard the bits that are not part of the payload (if the
size of the significant data in the last input block is less than 16 bytes).

Suspend/resume operations in CTR mode

Like for the CBC mode, it is possible to interrupt a message to send a higher priority
message, and resume the message that was interrupted. Detailed CBC suspend/resume
sequence is described in Section 29.4.8: AES basic chaining modes (ECB, CBC).
Note: Like for CBC mode, the AES_IVRx registers must be reloaded during the resume operation.

29.4.10 AES Galois/counter mode (GCM)

Overview
The AES Galois/counter mode (GCM) allows encrypting and authenticating a plaintext
message into the corresponding ciphertext and tag (also known as message authentication
code). To ensure confidentiality, GCM algorithm is based on AES counter mode. It uses a
multiplier over a fixed finite field to generate the tag.
GCM chaining is defined in NIST Special Publication 800-38D, Recommendation for Block
Cipher Modes of Operation - Galois/Counter Mode (GCM) and GMAC. A typical message
construction in GCM mode is given in Figure 211.

974/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Figure 211. Message construction in GCM

[Len(A)]64 [Len(C)]64

Len(A) Len(P) = Len(C)

16-byte
boundaries
Additional authenticated data Last
ICB (AAD) 0 Plaintext (P) 0 block

encrypt
authenticate

authenticate
4-byte boundaries
Authenticated & encrypted ciphertext (C) 0
Initialization vector (IV) Counter

auth.
Authentication tag (T)
Zero padding / zeroed bits
MSv42157V1

The message has the following structure:

• 16-byte initial counter block (ICB), composed of two distinct fields:
– Initialization vector (IV): a 96-bit value that must be unique for each encryption
cycle with a given key. Note that the GCM standard supports IVs with less than 96
bits, but in this case strict rules apply.
– Counter: a 32-bit big-endian integer that is incremented each time a block
processing is completed. According to NIST specification, the counter value is 0x2
when processing the first block of payload.
• Authenticated header AAD (also knows as additional authentication data) has a
known length Len(A) that may be a non-multiple of 16 bytes, and must not exceed
264 – 1 bits. This part of the message is only authenticated, not encrypted.
• Plaintext message P is both authenticated and encrypted as ciphertext C, with a
known length Len(P) that may be non-multiple of 16 bytes, and cannot exceed 232 - 2
128-bit blocks.
• Last block contains the AAD header length (bits [32:63]) and the payload length (bits
[96:127]) information, as shown in Table 218.
The GCM standard specifies that ciphertext C has the same bit length as the plaintext P.
When a part of the message (AAD or P) has a length that is a non-multiple of 16-bytes a
special padding scheme is required.

Table 218. GCM last block definition

Endianness Bit[0] ---------- Bit[31] Bit[32]---------- Bit[63] Bit[64] -------- Bit[95] Bit[96] --------- Bit[127]

Input data 0x0 AAD length[31:0] 0x0 Payload length[31:0]

RM0438 Rev 7 975/2194

1004
AES hardware accelerator (AES) RM0438

GCM processing
Figure 212 describes the GCM implementation in the AES peripheral. The GCM is selected
by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

Figure 212. GCM authenticated encryption

(3) Payload
Block 1 Block n
AES_IVRx
ICB + (32-bit counter = 0x02) AES_IVRx
(1) Init Counter CBn
increment (+1)
AES_KEYRx (KEY) CB1 CBn
[0]128 AES_KEYRx (KEY) AES_KEYRx (KEY)
Encrypt Encrypt
Encrypt
AES_DINR (plaintext P1) AES_DINR (plaintext Pn)

H
Swap DATATYPE Swap DATATYPE
management [1:0] management [1:0]

DATATYPE Swap Swap

(2) Header [1:0] DATATYPE[1:0]
management management
AES_DINR (AAD 0) AES_DINR (AAD i)
AES_DOUTR
AES_DOUTR (ciphertext Cn)
Swap Swap (ciphertext C1)
management DATATYPE management
[1:0]
H GF2mul H GF2mul

H GF2mul H GF2mul (4) Final AES_DINR

Len(A)64 || Len(C)64

H GF2mul
AES_IVRx
Legend (IV + 32-bit counter (= 0x0))
S
input Encrypt
output

XOR AES_DOUTR
AES_KEYRx (key) (Authentication TAG T)

MSv42149V1

The mechanism for the confidentiality of the plaintext in GCM mode is similar to that in the
Counter mode, with a particular increment function (denoted 32-bit increment) that
generates the sequence of input counter blocks.
AES_IVRx registers keeping the counter block of data are used for processing each data
block. The AES peripheral automatically increments the Counter[31:0] bitfield. The first
counter block (CB1) is derived from the initial counter block ICB by the application software
(see Table 219).

Table 219. GCM mode IVI bitfield initialization

Register AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

Input data ICB[31:0] ICB[63:32] ICB[95:64] Counter[31:0] = 0x2

Note: In this mode, the setting 01 of the MODE[1:0] bitfield (key derivation) is forbidden.

976/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

The authentication mechanism in GCM mode is based on a hash function called GF2mul
that performs multiplication by a fixed parameter, called hash subkey (H), within a binary
Galois field.
A GCM message is processed through the following phases, further described in next
subsections:
• Init phase: AES prepares the GCM hash subkey (H).
• Header phase: AES processes the additional authenticated data (AAD), with hash
computation only.
• Payload phase: AES processes the plaintext (P) with hash computation, counter block
encryption and data XOR-ing. It operates in a similar way for ciphertext (C).
• Final phase: AES generates the authenticated tag (T) using the last block of the
message.
GCM init phase
During this first step, the GCM hash subkey (H) is calculated and saved internally, to be
used for processing all the blocks. The recommended sequence is:
1. Ensure that AES is disabled (the EN bit of the AES_CR must be 0).
2. Select GCM chaining mode, by setting to 011 the CHMOD[2:0] bitfield of the AES_CR
register, and optionally, set the DATATYPE[1:0] bitfield.
3. Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR
register.
4. Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is
only used in payload phase, it is recommended to set it in the Init phase and keep it
unchanged in all subsequent phases.
5. Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with
the information as defined in Table 219.
6. Start the calculation of the hash key, by setting to 1 the EN bit of the AES_CR register
(EN is automatically reset when the calculation finishes).
7. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting
to 1. Alternatively, use the corresponding interrupt.
8. Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR
register.
GCM header phase
This phase coming after the GCM Init phase must be completed before the payload phase.
The sequence to execute, identical for encryption and decryption, is:
1. Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR
register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. If it is the last block and the AAD size in the block is inferior to 128 bits, pad the
remainder of the block with zeros. Then append the data block into AES in one of ways
described in Section 29.4.4: AES procedure to perform a cipher operation. No data is
read during this phase.
4. Repeat the step 3 until the last additional authenticated data block is processed.
Note: The header phase can be skipped if there is no AAD, that is, Len(A) = 0.

RM0438 Rev 7 977/2194

1004
AES hardware accelerator (AES) RM0438

GCM payload phase

This phase, identical for encryption and decryption, is executed after the GCM header
phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR
register. The sequence to execute is:
1. Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR
register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. If the header phase was skipped, enable the AES peripheral by setting the EN bit of the
AES_CR register.
3. If it is the last block and the plaintext (encryption) or ciphertext (decryption) size in the
block is inferior to 128 bits, pad the remainder of the block with zeros.
4. Append the data block into AES in one of ways described in Section 29.4.4: AES
procedure to perform a cipher operation on page 963, and read the result.
5. Repeat the previous step till the second-last plaintext block is encrypted or till the last
block of ciphertext is decrypted. For the last block of plaintext (encryption only),
execute the two previous steps. For the last block, discard the bits that are not part of
the payload when the last block size is less than 16 bytes.
Note: The payload phase can be skipped if there is no payload data, that is, Len(C) = 0 (see
GMAC mode).
GCM final phase
In this last phase, the AES peripheral generates the GCM authentication tag and stores it in
the AES_DOUTR register. The sequence to execute is:

1. Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR
register.
2. Compose the data of the block, by concatenating the AAD bit length and the payload
bit length, as shown in Table 218. Write the block into the AES_DINR register.
3. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting
to 1.
4. Get the GCM authentication tag, by reading the AES_DOUTR register four times.
5. Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR
register.
6. Disable the AES peripheral, by clearing the bit EN of the AES_CR register. If it is an
authenticated decryption, compare the generated tag with the expected tag passed
with the message.

Note: In the final phase, data is written to AES_DINR normally (no swapping), while swapping is
applied to tag data read from AES_DOUTR.
When transiting from the header or the payload phase to the final phase, the AES peripheral
must not be disabled, otherwise the result is wrong.

978/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Suspend/resume operations in GCM mode

To suspend the processing of a message, proceed as follows:

1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register. If DMA is not used, make sure that the current computation
is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
2. In the payload phase, if DMA is not used, read four times the AES_DOUTR register to
save the last-processed block. If DMA is used, wait until the CCF flag is set in the
AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the
DMAOUTEN bit of the AES_CR register.
3. Clear the CCF flag of the AES_SR register, by setting the CCFC bit of the AES_CR
register.
4. Save the AES_SUSPxR registers in the memory, where x is from 0 to 7.
5. In the payload phase, save the AES_IVRx registers as, during the data processing,
they changed from their initial values. In the header phase, this step is not required.
6. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.
7. Save the current AES configuration in the memory, excluding the initialization vector
registers AES_IVRx. Key registers do not need to be saved as the original key value is
known by the application.
8. If DMA is used, save the DMA controller status (pointers for IN data transfers, number
of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers
must also be saved.
To resume the processing of a message, proceed as follows:
1. If DMA is used, configure the DMA controller in order to complete the rest of the FIFO
IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be
configured in the DMA controller.
2. Ensure that the AES peripheral is disabled (the EN bit of the AES_CR register must be
0).
3. Write the suspend register values, previously saved in the memory, back into their
corresponding AES_SUSPxR registers, where x is from 0 to 7.
4. In the payload phase, write the initialization vector register values, previously saved in
the memory, back into their corresponding AES_IVRx registers. In the header phase,
write initial setting values back into the AES_IVRx registers.
5. Restore the initial setting values in the AES_CR and AES_KEYRx registers.
6. Enable the AES peripheral by setting the EN bit of the AES_CR register.
If DMA is used, enable AES DMA requests by setting the DMAINEN bit (and DMAOUTEN
bit if in payload phase) of the AES_CR register.

29.4.11 AES Galois message authentication code (GMAC)

Overview
The Galois message authentication code (GMAC) allows the authentication of a plaintext,
generating the corresponding tag information (also known as message authentication
code). It is based on GCM algorithm, as defined in NIST Special Publication 800-38D,
Recommendation for Block Cipher Modes of Operation - Galois/Counter Mode (GCM) and
GMAC.

RM0438 Rev 7 979/2194

1004
AES hardware accelerator (AES) RM0438

A typical message construction for GMAC is given in Figure 213.

Figure 213. Message construction in GMAC mode

[Len(A)]64 [0]64

Len(A)
16-byte
boundaries
Last
ICB Authenticated data 0 block

auth.
4-byte boundaries
Authentication tag (T)
Initialization vector (IV) Counter

Zero padding
MSv42158V2

AES GMAC processing

Figure 214 describes the GMAC mode implementation in the AES peripheral. This mode is
selected by writing 011 to the CHMOD[2:0] bitfield of the AES_CR register.

Figure 214. GMAC authentication mode

(1) Init (4) Final

[0]128 AES_IVRx
AES_KEYRx (KEY) IV + 32-bit counter (= 0x0)
Encrypt

AES_KEYRx (KEY)
H
Encrypt
(2) Header
AES_DINR AES_DINR AES_DINR
(message block 1) (message block n) len(A)64 || [0]64

Swap Swap
management DATATYPE management
[1:0]
H GF2mul

S
H GF2mul H GF2mul

Legend

input AES_DOUTR
(authentication tag T)
output

XOR
MSv42150V2

The GMAC algorithm corresponds to the GCM algorithm applied on a message only
containing a header. As a consequence, all steps and settings are the same as with the
GCM, except that the payload phase is omitted.

Suspend/resume operations in GMAC

In GMAC mode, the sequence described for the GCM applies except that only the header
phase can be interrupted.

980/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.4.12 AES counter with CBC-MAC (CCM)

Overview
The AES counter with cipher block chaining-message authentication code (CCM)
algorithm allows encryption and authentication of plaintext, generating the corresponding
ciphertext and tag (also known as message authentication code). To ensure confidentiality,
the CCM algorithm is based on AES in counter mode. It uses cipher block chaining
technique to generate the message authentication code. This is commonly called CBC-
MAC.
Note: NIST does not approve this CBC-MAC as an authentication mode outside the context of the
CCM specification.
CCM chaining is specified in NIST Special Publication 800-38C, Recommendation for Block
Cipher Modes of Operation - The CCM Mode for Authentication and Confidentiality. A typical
message construction for CCM is given in Figure 215.

Figure 215. Message construction in CCM mode

Len(C)
Len(A) Len(P) Len(T)
16-byte
boundaries
[a]32 Enc
B0 [a]16 Associated data (A) 0 Plaintext (P)
encrypt 0 (T)
authenticate

4-byte boundaries
Authenticated & encrypted ciphertext (C)
flags Nonce (N) Q

Len(N) MAC (T) Decrypt and compare

Zero padding
MSv42159V2

The structure of the message is:

• 16-byte first authentication block (B0), composed of three distinct fields:
– Q: a bit string representation of the octet length of P (Len(P))
– Nonce (N): a single-use value (that is, a new nonce must be assigned to each
new communication) of Len(N) size. The sum Len(N) + Len(P) must be equal to
15 bytes.
– Flags: most significant octet containing four flags for control information, as
specified by the standard. It contains two 3-bit strings to encode the values t (MAC
length expressed in bytes) and Q (plaintext length such that Len(P) < 28q bytes).
The counter blocks range associated to Q is equal to 28Q-4, that is, if the maximum
value of Q is 8, the counter blocks used in cipher must be on 60 bits.
• 16-byte blocks (B) associated to the Associated Data (A).
This part of the message is only authenticated, not encrypted. This section has a
known length Len(A) that can be a non-multiple of 16 bytes (see Figure 215). The

RM0438 Rev 7 981/2194

1004
AES hardware accelerator (AES) RM0438

standard also states that, on MSB bits of the first message block (B1), the associated
data length expressed in bytes (a) must be encoded as follows:
– If 0 < a < 216 - 28, then it is encoded as [a]16, that is, on two bytes.
– If 216 - 28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, that is, on six bytes.
– If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, that is, on ten bytes.
• 16-byte blocks (B) associated to the plaintext message P, which is both authenticated
and encrypted as ciphertext C, with a known length Len(P). This length can be a non-
multiple of 16 bytes (see Figure 215).
• Encrypted MAC (T) of length Len(T) appended to the ciphertext C of overall length
Len(C).
When a part of the message (A or P) has a length that is a non-multiple of 16-bytes, a
special padding scheme is required.
Note: CCM chaining mode can also be used with associated data only (that is, no payload).
As an example, the C.1 section in NIST Special Publication 800-38C gives the following
values (hexadecimal numbers):
N: 10111213 141516 (Len(N)= 56 bits or 7 bytes)
A: 00010203 04050607 (Len(A)= 64 bits or 8 bytes)
P: 20212223 (Len(P)= 32 bits or 4 bytes)
T: 6084341B (Len(T)= 32 bits or t = 4)
B0: 4F101112 13141516 00000000 00000004
B1: 00080001 02030405 06070000 00000000
B2: 20212223 00000000 00000000 00000000
CTR0: 0710111213 141516 00000000 00000000
CTR1: 0710111213 141516 00000000 00000001
Generation of formatted input data blocks Bx (especially B0 and B1) must be managed by
the application.

982/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

CCM processing
Figure 216 describes the CCM implementation within the AES peripheral (encryption
example). This mode is selected by writing 100 into the CHMOD[2:0] bitfield of the AES_CR
register.

Figure 216. CCM mode authenticated encryption

Block 1 (3) Payload Block m
(1) Init
AES_IVRx (CTR0) AES_IVRx (CTR1) AES_IVRx (CTRm)
Counter Counter
mask increment (+1) increment (+1)

AES_IVRx (First block B0) AES_KEYRx (KEY) AES_KEYRx (KEY)

Encrypt Encrypt

AES_DINR (plaintext P1) AES_DINR (plaintext

Encrypt last block Pm )
S1 Sm
Swap DATATYPE DATATYPE
management [1:0] Swap
management [1:0]
AES_KEYRx (KEY)
DATATYPE
(2) Header [1:0]
Swap DATATYPE Swap
management [1:0] management
AES_DINR (associated AES_DINR (associated
data block B1) data last block Bu)

AES_DOUTR (ciphertext C1) AES_DOUTR

Swap Swap (ciphertext last block Cm)
management management
DATATYPE[1:0] Bu+1 Br
DATATYPE[1:0]

AES_KEYRx (KEY)
Encrypt Encrypt Encrypt Encrypt

AES_DINR (CTR0)
AES_KEYRx (KEY) AES_KEYRx (KEY) AES_KEYRx (KEY)
MAC (T)
S0
Legend Encrypt

input
AES_DOUTR
output (EncTAG)
AES_KEYRx (KEY)
XOR (4) Final
MSv42152V2

The data input to the generation-encryption process are a valid nonce, a valid payload
string, and a valid associated data string, all properly formatted. The CBC chaining
mechanism is applied to the formatted plaintext data to generate a MAC, with a known
length. Counter mode encryption that requires a sufficiently long sequence of counter blocks
as input, is applied to the payload string and separately to the MAC. The resulting ciphertext
C is the output of the generation-encryption process on plaintext P.
AES_IVRx registers are used for processing each data block, AES automatically
incrementing the CTR counter with a bit length defined by the first block B0. Table 220
shows how the application must load the B0 data.
Note: The AES peripheral in CCM mode supports counters up to 64 bits, as specified by NIST.

Table 220. Initialization of AES_IVRx registers in CCM mode

Register AES_IVR3[31:0] AES_IVR2[31:0] AES_IVR1[31:0] AES_IVR0[31:0]

Input data B0[31:0] B0[63:32] B0[95:64] B0[127:96]

RM0438 Rev 7 983/2194

1004
AES hardware accelerator (AES) RM0438

Note: In this mode, the setting 01 of the MODE[1:0] bitfield (key derivation) is forbidden.

A CCM message is processed through the following phases, further described in next
subsections:
• Init phase: AES processes the first block and prepares the first counter block.
• Header phase: AES processes associated data (A), with tag computation only.
• Payload phase: IP processes plaintext (P), with tag computation, counter block
encryption, and data XOR-ing. It works in a similar way for ciphertext (C).
• Final phase: AES generates the message authentication code (MAC).
CCM Init phase
In this phase, the first block B0 of the CCM message is written into the AES_IVRx register.
The AES_DOUTR register does not contain any output data. The recommended sequence
is:
1. Ensure that the AES peripheral is disabled (the EN bit of the AES_CR must be 0).
2. Select CCM chaining mode, by setting to 100 the CHMOD[2:0] bitfield of the AES_CR
register, and optionally, set the DATATYPE[1:0] bitfield.
3. Indicate the Init phase, by setting to 00 the GCMPH[1:0] bitfield of the AES_CR
register.
4. Set the MODE[1:0] bitfield of the AES_CR register to 00 or 10. Although the bitfield is
only used in payload phase, it is recommended to set it in the Init phase and keep it
unchanged in all subsequent phases.
5. Initialize the AES_KEYRx registers with a key, and initialize AES_IVRx registers with
B0 data as described in Table 220.
6. Start the calculation of the counter, by setting to 1 the EN bit of the AES_CR register
(EN is automatically reset when the calculation finishes).
7. Wait until the end of computation, indicated by the CCF flag of the AES_SR transiting
to 1. Alternatively, use the corresponding interrupt.
8. Clear the CCF flag in the AES_SR register, by setting to 1 the CCFC bit of the AES_CR
register.
CCM header phase
This phase coming after the GCM Init phase must be completed before the payload phase.
During this phase, the AES_DOUTR register does not contain any output data.
The sequence to execute, identical for encryption and decryption, is:
1. Indicate the header phase, by setting to 01 the GCMPH[1:0] bitfield of the AES_CR
register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. Enable the AES peripheral by setting the EN bit of the AES_CR register.
3. If it is the last block and the AAD size in the block is inferior to 128 bits, pad the
remainder of the block with zeros. Then append the data block into AES in one of ways
described in Section 29.4.4: AES procedure to perform a cipher operation. No data is
read during this phase.
4. Repeat the step 3 until the last additional authenticated data block is processed.
Note: The header phase can be skipped if there is no associated data, that is, Len(A) = 0.
The first block of the associated data (B1) must be formatted by software, with the
associated data length.

984/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

CCM payload phase (encryption or decryption)

This phase, identical for encryption and decryption, is executed after the CCM header
phase. During this phase, the encrypted/decrypted payload is stored in the AES_DOUTR
register. The sequence to execute is:
1. Indicate the payload phase, by setting to 10 the GCMPH[1:0] bitfield of the AES_CR
register. Do not modify the MODE[1:0] bitfield as set in the Init phase.
2. If the header phase was skipped, enable the AES peripheral by setting the EN bit of the
AES_CR register.
3. If it is the last data block to encrypt and the plaintext size in the block is inferior to 128
bits, pad the remainder of the block with zeros.
4. Append the data block into AES in one of ways described in Section 29.4.4: AES
procedure to perform a cipher operation on page 963, and read the result.
5. Repeat the previous step till the second-last plaintext block is encrypted or till the last
block of ciphertext is decrypted. For the last block of plaintext (encryption only), apply
the two previous steps. For the last block, discard the data that is not part of the
payload when the last block size is less than 16 bytes.
Note: The payload phase can be skipped if there is no payload data, that is, Len(P) = 0 or
Len(C) = Len(T).
Remove LSBLen(T)(C) encrypted tag information when decrypting ciphertext C.
CCM final phase
In this last phase, the AES peripheral generates the GCM authentication tag and stores it in
the AES_DOUTR register. The sequence to execute is:
1. Indicate the final phase, by setting to 11 the GCMPH[1:0] bitfield of the AES_CR
register.
2. Wait until the end-of-computation flag CCF of the AES_SR register is set.
3. Read four times the AES_DOUTR register: the output corresponds to the CCM
authentication tag.
4. Clear the CCF flag of the AES_SR register by setting the CCFC bit of the AES_CR
register.
5. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.
6. For authenticated decryption, compare the generated encrypted tag with the encrypted
tag padded in the ciphertext.

Note: In this final phase, swapping is applied to tag data read from AES_DOUTR register.
When transiting from the header phase to the final phase, the AES peripheral must not be
disabled, otherwise the result is wrong.
Application must mask the authentication tag output with tag length to obtain a valid tag.

RM0438 Rev 7 985/2194

1004
AES hardware accelerator (AES) RM0438

Suspend/resume operations in CCM mode

To suspend the processing of a message in header or payload phase, proceed as
follows:
1. If DMA is used, stop the AES DMA transfers to the IN FIFO by clearing the DMAINEN
bit of the AES_CR register. If DMA is not used, make sure that the current computation
is completed, which is indicated by the CCF flag of the AES_SR register set to 1.
2. In the payload phase, if DMA is not used, read four times the AES_DOUTR register to
save the last-processed block. If DMA is used, wait until the CCF flag is set in the
AES_SR register then stop the DMA transfers from the OUT FIFO by clearing the
DMAOUTEN bit of the AES_CR register.
3. Clear the CCF flag of the AES_SR register, by setting to 1 the CCFC bit of the AES_CR
register.
4. Save the AES_SUSPxR registers (where x is from 0 to 7) in the memory.
5. Save the AES_IVRx registers as, during the data processing, they changed from their
initial values.
6. Disable the AES peripheral, by clearing the EN bit of the AES_CR register.
7. Save the current AES configuration in the memory, excluding the initialization vector
registers AES_IVRx. Key registers do not need to be saved as the original key value is
known by the application.
8. If DMA is used, save the DMA controller status (pointers for IN data transfers, number
of remaining bytes, and so on). In the payload phase, pointers for OUT data transfers
must also be saved.
To resume the processing of a message, proceed as follows:
1. If DMA is used, configure the DMA controller in order to complete the rest of the FIFO
IN transfers. In the payload phase, the rest of the FIFO OUT transfers must also be
configured in the DMA controller.
2. Ensure that the AES peripheral is disabled (the EN bit of the AES_CR register must be
0).
3. Write the suspend register values, previously saved in the memory, back into their
corresponding AES_SUSPxR registers (where x is from 0 to 7).
4. Write the initialization vector register values, previously saved in the memory, back into
their corresponding AES_IVRx registers.
5. Restore the initial setting values in the AES_CR and AES_KEYRx registers.
6. Enable the AES peripheral by setting the EN bit of the AES_CR register.
7. If DMA is used, enable AES DMA requests by setting to 1 the DMAINEN bit (and
DMAOUTEN bit if in payload phase) of the AES_CR register.

986/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.4.13 AES data registers and data swapping

Data input and output
A 128-bit data block is entered into the AES peripheral with four successive 32-bit word
writes into the AES_DINR register (bitfield DIN[31:0]), the most significant word (bits
[127:96]) first, the least significant word (bits [31:0]) last.
A 128-bit data block is retrieved from the AES peripheral with four successive 32-bit word
reads from the AES_DOUTR register (bitfield DOUT[31:0]), the most significant word (bits
[127:96]) first, the least significant word (bits [31:0]) last.
The 32-bit data word for AES_DINR register or from AES_DOUTR register is organized in
big endian order, that is:
• the most significant byte of a word to write into AES_DINR must be put on the lowest
address out of the four adjacent memory locations keeping the word to write, or
• the most significant byte of a word read from AES_DOUTR goes to the lowest address
out of the four adjacent memory locations receiving the word
For using DMA for input data block write into AES, the four words of the input block must be
stored in the memory consecutively and in big-endian order, that is, the most significant
word on the lowest address. See Section 29.4.16: AES DMA interface.

Data swapping
The AES peripheral can be configured to perform a bit-, a byte-, a half-word-, or no
swapping on the input data word in the AES_DINR register, before loading it to the AES
processing core, and on the data output from the AES processing core, before sending it to
the AES_DOUTR register. The choice depends on the type of data. For example, a byte
swapping is used for an ASCII text stream.
The data swap type is selected through the DATATYPE[1:0] bitfield of the AES_CR register.
The selection applies both to the input and the output of the AES core.
For different data swap types, Figure 217 shows the construction of AES processing core
input buffer data P127..0, from the input data entered through the AES_DINR register, or the
construction of the output data available through the AES_DOUTR register, from the AES
processing core output buffer data P127..0.

RM0438 Rev 7 987/2194

1004
AES hardware accelerator (AES) RM0438

Figure 217. 128-bit block construction with respect to data swap

increasing memory address
byte 3 byte 2 byte 1 byte 0
D63 D56 D55 D48 D47 D40 D39 D32
DATATYPE[1:0] = 00: no swapping
MSB LSB
Word 3 Word 2 Word 1 Word 0
D127 D96 D95 D64 D63 D32 D31 D0

1 2 3 4
D127 D96 D95
P95 D64 D63 D32 D31 D0
MSB LSB

DATATYPE[1:0] = 01: 16-bit (half-word) swapping

MSB LSB
Word 3 Word 2 Word 1 Word 0
D127 D112 D111 D96 D95 D80 D79 D64 D63 D48 D47 D32 D31 D16 D15 D0

1 2 3 4

D111 D96 D127 D112 D79 D64 D95 D80 D47 D32 D63 D48 D15 D0 D31 D16
MSB LSB

DATATYPE[1:0] = 10: 8-bit (byte) swapping

MSB LSB
Word 3 Word 2 Word 1 Word 0
D127..120 D119..112 D111.104 D103..96 D95..88 D87..80 D79..72 D71...64 D63...56 D55...48 D47...40 D39...32 D31...24 D23...16 D15...8 D7...0

1 2 3 4

D103..96 D111.104 D119..112 D127..120 D71...64 D79..72 D87..80 D95..88 D39...32 D47...40 D55...48 D63...56 D7...0 D15...8 D23...16 D31...24
MSB LSB

DATATYPE[1:0] = 11: bit swapping

MSB LSB
Word 3 Word 2 Word 1 Word 0
D127 D126 D125 D98 D97 D96 D95 D94 D93 D66 D65 D64 D63 D62 D61 D34 D33 D32 D31 D30 D29 D2 D1 D0

1 2 3 4

D96 D97 D98 D125 D126 D127 D64 D65 D66 D93 D94 D95 D32 D33 D34 D61 D62 D63 D0 D1 D2 D29 D30 D31
MSB LSB

Legend: AES input/output data block in memory MSB most significant bit (127) of memory data block / AEC core buffer
AES core input/output buffer data LSB least significant bit (0) of memory data block / AEC core buffer
Zero padding (example) 1 4 Order of write to AES_DINR / read from AES_DOUTR
Data swap Dx input/output data bit ‘x’ MSv42153V2

Note: The data in AES key registers (AES_KEYRx) and initialization registers (AES_IVRx) are not
sensitive to the swap mode selection.

Data padding
Figure 217 also gives an example of memory data block padding with zeros such that the
zeroed bits after the data swap form a contiguous zone at the MSB end of the AES core
input buffer. The example shows the padding of an input data block containing:
• 48 message bits, with DATATYPE[1:0] = 01
• 56 message bits, with DATATYPE[1:0] = 10
• 34 message bits, with DATATYPE[1:0] = 11

988/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.4.14 AES key registers

The AES_KEYRx write-only registers store the encryption or decryption key bitfield
KEY[127:0] or KEY[255:0]. The data to write to each register is organized in the memory in
little-endian order, that is, with most significant byte on the highest address (reads are not
allowed for security reason).
The key is spread over eight registers as shown in Table 221.

Table 221. Key endianness in AES_KEYRx registers (128- or 256-bit key length)
AES_KEYR7 AES_KEYR6 AES_KEYR5 AES_KEYR4 AES_KEYR3 AES_KEYR2 AES_KEYR1 AES_KEYR0
[31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0] [31:0]
- - - - KEY[127:96] KEY[95:64] KEY[63:32] KEY[31:0]

KEY[255:224] KEY[223:192] KEY[191:160] KEY[159:128] KEY[127:96] KEY[95:64] KEY[63:32] KEY[31:0]

The key for encryption or decryption may be written into these registers when the AES
peripheral is disabled, by clearing the EN bit of the AES_CR register.
The key registers are not affected by the data swapping controlled by DATATYPE[1:0]
bitfield of the AES_CR register.

29.4.15 AES initialization vector registers

The four AES_IVRx registers keep the initialization vector input bitfield IVI[127:0]. The data
to write to or to read from each register is organized in the memory in little-endian order, that
is, with most significant byte on the highest address. The registers are also ordered from
lowest address (AES_IVR0) to highest address (AES_IVR3).
The signification of data in the bitfield depends on the chaining mode selected. When used,
the bitfield is updated upon each computation cycle of the AES core.
Write operations to the AES_IVRx registers when the AES peripheral is enabled have no
effect to the register contents. For modifying the contents of the AES_IVRx registers, the EN
bit of the AES_CR register must first be cleared.
Reading the AES_IVRx registers returns the latest counter value (useful for managing
suspend mode).
The AES_IVRx registers are not affected by the data swapping feature controlled by the
DATATYPE[1:0] bitfield of the AES_CR register.

29.4.16 AES DMA interface

The AES peripheral provides an interface to connect to the DMA (direct memory access)
controller. The DMA operation is controlled through the AES_CR register.

Data input using DMA

Setting the DMAINEN bit of the AES_CR register enables DMA writing into AES. The AES
peripheral then initiates a DMA request during the input phase each time it requires to write
a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 218.
Note: According to the algorithm and the mode selected, special padding / ciphertext stealing
might be required. For example, in case of AES GCM encryption or AES CCM decryption, a

RM0438 Rev 7 989/2194

1004
AES hardware accelerator (AES) RM0438

DMA transfer must not include the last block. For details, refer to Section 29.4.4: AES
procedure to perform a cipher operation.

Figure 218. DMA transfer of a 128-bit data block during input phase
Chronological order
Increasing address
Memory accessed through DMA
Word3 Word2 Word1 Word0

System
D127 DIN[127:96] D96 D95 DIN[95:64] D64 D63 DIN[63:32] D32 D31 DIN[31:0] D0
MSB LSB

DMA DMA DMA DMA

DMA req N single write DMA req N+1 single write DMA req N+2 single write DMA req N+3 single write

1 2 3 4
AES_DINR

peripheral
(No swapping) 1 2 3 4

AES
AES core input buffer
I127 I96 I95 I64 I63 I32 I31 I0
MSB LSB

1 4 Order of write to AES_DINR MSv42160V1

Data output using DMA

Setting the DMAOUTEN bit of the AES_CR register enables DMA reading from AES. The
AES peripheral then initiates a DMA request during the Output phase each time it requires
to read a 128-bit block (quadruple word) to the AES_DINR register, as shown in Figure 219.
Note: According to the message size, extra bytes might need to be discarded by application in the
last block.

Figure 219. DMA transfer of a 128-bit data block during output phase
Chronological order
Increasing address
Memory accessed through DMA
Word3 Word2 Word1 Word0

System
D127 DOUT[127:96] D96 D95 DOUT[95:64] D64 D63 DOUT[63:32] D32 D31 DOUT[31:0] D0
MSB LSB

DMA DMA DMA DMA

DMA req N single read DMA req N+1 single read DMA req N+2 single read DMA req N+3 single read

1 2 3 4
AES_DOUTR
peripheral

(No swapping) 1 2 3 4
AES

AES core output buffer

O127 O96 O95 O64 O63 O32 O31 O0
MSB LSB

1 4 Order of read from AES_DOUTR MSv42161V1

DMA operation in different operating modes

DMA operations are usable when Mode 1 (encryption) or Mode 3 (decryption) are selected
via the MODE[1:0] bitfield of the register AES_CR. As in Mode 2 (key derivation) the
AES_KEYRx registers must be written by software, enabling the DMA transfer through the
DMAINEN and DMAOUTEN bits of the AES_CR register have no effect in that mode.
DMA single requests are generated by AES until it is disabled. So, after the data output
phase at the end of processing of a 128-bit data block, AES switches automatically to a new
data input phase for the next data block, if any.

990/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

When the data transferring between AES and memory is managed by DMA, the CCF flag is
not relevant and can be ignored (left set) by software. It must only be cleared when
transiting back to data transferring managed by software. See Suspend/resume operations
in ECB/CBC modes in Section 29.4.8: AES basic chaining modes (ECB, CBC) as example.

29.4.17 AES error management

AES configuration can be changed at any moment by clearing the EN bit of the AES_CR
register.

Read error flag (RDERR)

Unexpected read attempt of the AES_DOUTR register sets the RDERR flag of the AES_SR
register, and returns zero.
RDERR is triggered during the computation phase or during the input phase.
Note: AES is not disabled upon a RDERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 29.5: AES interrupts.
The RDERR flag is cleared by setting the ERRIE bit of the AES_CR register.

Write error flag (WDERR)

Unexpected write attempt of the AES_DINR register sets the WRERR flag of the AES_SR
register, and has no effect on the AES_DINR register. The WRERR is triggered during the
computation phase or during the output phase.
Note: AES is not disabled after a WRERR error detection and continues processing.
An interrupt is generated if the ERRIE bit of the AES_CR register is set. For more details,
refer to Section 29.5: AES interrupts.
The WRERR flag is cleared by setting the ERRC bit of the AES_CR register.

29.5 AES interrupts

Individual maskable interrupt sources generated by the AES peripheral signal the following
events:
• computation completed
• read error
• write error
The individual sources are combined into the common interrupt signal aes_it that connects
to NVIC (nested vectored interrupt controller). Each can individually be enabled/disabled, by
setting/clearing the corresponding enable bit of the AES_CR register, and cleared by setting
the corresponding bit of the AES_CR register.
The status of each can be read from the AES_SR register.
Table 222 gives a summary of the interrupt sources, their event flags and enable bits.

RM0438 Rev 7 991/2194

1004
AES hardware accelerator (AES) RM0438

Table 222. AES interrupt requests

Interrupt Interrupt clear
AES interrupt event Event flag Enable bit
acronym method

computation completed flag CCF CCFIE set CCFC(1)

AES read error flag RDERR
ERRIE set ERRC(1)
write error flag WRERR

1. Bit of the AES_CR register.

29.6 AES processing latency

The tables below summarize the latency to process a 128-bit block for each mode of
operation.

Table 223. Processing latency for ECB, CBC and CTR

Clock
Key size Mode of operation Algorithm
cycles

Mode 1: Encryption ECB, CBC, CTR 51

128-bit Mode 2: Key derivation - 59
Mode 3: Decryption ECB, CBC, CTR 51
Mode 1: Encryption ECB, CBC, CTR 75
256-bit Mode 2: Key derivation - 82
Mode 3: Decryption ECB, CBC, CTR 75

Table 224. Processing latency for GCM and CCM (in clock cycles)
Header Payload
Key size Mode of operation Algorithm Init Phase Tag phase(1)
phase(1) phase(1)

Mode 1: Encryption/ GCM 64 35 51 59

128-bit
Mode 3: Decryption CCM 63 55 114 58

Mode 1: Encryption/ GCM 88 35 75 75

256-bit
Mode 3: Decryption CCM 87 79 162 82
1. Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles, typical 1 cycle).

992/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.7 AES registers

29.7.1 AES control register (AES_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CHMOD[2]
KEYSIZE
Res. Res. Res. Res. Res. Res. Res. Res. NPBLB[3:0] Res. Res.

rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAOUTEN

DMAINEN

Res. GCMPH[1:0] ERRIE CCFIE ERRC CCFC CHMOD[1:0] MODE[1:0] DATATYPE[1:0] EN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept at reset value.

Bits 23:20 NPBLB[3:0]: Number of padding bytes in last block
The bitfield sets the number of padding bytes in last block of payload:
0000: All bytes are valid (no padding)
0001: Padding for one least-significant byte of last block
...
1111: Padding for 15 least-significant bytes of last block
Bit 19 Reserved, must be kept at reset value.
Bit 18 KEYSIZE: Key size selection
This bitfield defines the length of the key used in the AES cryptographic core, in bits:
0: 128
1: 256
Attempts to write the bit are ignored when the EN bit of the AES_CR register is set before the write
access and it is not cleared by that write access.
Bit 17 Reserved, must be kept at reset value.
Bit 15 Reserved, must be kept at reset value.
Bits 14:13 GCMPH[1:0]: GCM or CCM phase selection
This bitfield selects the phase of GCM, GMAC or CCM algorithm:
00: Init phase
01: Header phase
10: Payload phase
11: Final phase
The bitfield has no effect if other than GCM, GMAC or CCM algorithms are selected (through the
ALGOMODE bitfield).

RM0438 Rev 7 993/2194

1004
AES hardware accelerator (AES) RM0438

Bit 12 DMAOUTEN: DMA output enable

This bit enables/disables data transferring with DMA, in the output phase:
0: Disable
1: Enable
When the bit is set, DMA requests are automatically generated by AES during the output data
phase. This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0]
bitfield. It is not effective for Mode 2 (key derivation).
Bit 11 DMAINEN: DMA input enable
This bit enables/disables data transferring with DMA, in the input phase:
0: Disable
1: Enable
When the bit is set, DMA requests are automatically generated by AES during the input data phase.
This feature is only effective when Mode 1 or Mode 3 is selected through the MODE[1:0] bitfield. It is
not effective for Mode 2 (key derivation).
Bit 10 ERRIE: Error interrupt enable
This bit enables or disables (masks) the AES interrupt generation when RDERR and/or WRERR is
set:
0: Disable (mask)
1: Enable
Bit 9 CCFIE: CCF interrupt enable
This bit enables or disables (masks) the AES interrupt generation when CCF (computation complete
flag) is set:
0: Disable (mask)
1: Enable
Bit 8 ERRC: Error flag clear
Upon written to 1, this bit clears the RDERR and WRERR error flags in the AES_SR register:
0: No effect
1: Clear RDERR and WRERR flags
Reading the flag always returns zero.
Bit 7 CCFC: Computation complete flag clear
Upon written to 1, this bit clears the computation complete flag (CCF) in the AES_SR register:
0: No effect
1: Clear CCF
Reading the flag always returns zero.
Bits 16, 6:5 CHMOD[2:0]: Chaining mode selection
This bitfield selects the AES chaining mode:
000: Electronic codebook (ECB)
001: Cipher-block chaining (CBC)
010: Counter mode (CTR)
011: Galois counter mode (GCM) and Galois message authentication code (GMAC)
100: Counter with CBC-MAC (CCM)
others: Reserved
Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the
write access and it is not cleared by that write access.

994/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Bits 4:3 MODE[1:0]: AES operating mode

This bitfield selects the AES operating mode:
00: Mode 1: encryption
01: Mode 2: key derivation (or key preparation for ECB/CBC decryption)
10: Mode 3: decryption
11: reserved
Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the
write access and it is not cleared by that write access.
Bits 2:1 DATATYPE[1:0]: Data type selection
This bitfield defines the format of data written in the AES_DINR register or read from the
AES_DOUTR register, through selecting the mode of data swapping:
00: None
01: Half-word (16-bit)
10: Byte (8-bit)
11: Bit
For more details, refer to Section 29.4.13: AES data registers and data swapping.
Attempts to write the bitfield are ignored when the EN bit of the AES_CR register is set before the
write access and it is not cleared by that write access.
Bit 0 EN: AES enable
This bit enables/disables the AES peripheral:
0: Disable
1: Enable
At any moment, clearing then setting the bit re-initializes the AES peripheral.
This bit is automatically cleared by hardware upon the completion of the key preparation (Mode 2)
and upon the completion of GCM/GMAC/CCM initial phase.

29.7.2 AES status register (AES_SR)

Address offset: 0x04
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY WRERR RDERR CCF
r r r r

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 BUSY: Busy
This flag indicates whether AES is idle or busy during GCM payload encryption phase:
0: Idle
1: Busy
When the flag indicates “idle”, the current GCM encryption processing may be suspended to
process a higher-priority message. In other chaining modes, or in GCM phases other than payload
encryption, the flag must be ignored for the suspend process.

RM0438 Rev 7 995/2194

1004
AES hardware accelerator (AES) RM0438

Bit 2 WRERR: Write error

This flag indicates the detection of an unexpected write operation to the AES_DINR register (during
computation or data output phase):
0: Not detected
1: Detected
The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR
register.
Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR
register.
The flag setting has no impact on the AES operation. Unexpected write is ignored.
Bit 1 RDERR: Read error flag
This flag indicates the detection of an unexpected read operation from the AES_DOUTR register
(during computation or data input phase):
0: Not detected
1: Detected
The flag is set by hardware. It is cleared by software upon setting the ERRC bit of the AES_CR
register.
Upon the flag setting, an interrupt is generated if enabled through the ERRIE bit of the AES_CR
register.
The flag setting has no impact on the AES operation. Unexpected read returns zero.
Bit 0 CCF: Computation completed flag
This flag indicates whether the computation is completed:
0: Not completed
1: Completed
The flag is set by hardware upon the completion of the computation. It is cleared by software, upon
setting the CCFC bit of the AES_CR register.
Upon the flag setting, an interrupt is generated if enabled through the CCFIE bit of the AES_CR
register.
The flag is significant only when the DMAOUTEN bit is 0. It may stay high when DMA_EN is 1.

29.7.3 AES data input register (AES_DINR)

Address offset: 0x08
Reset value: 0x0000 0000
Only 32-bit access type is supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DIN[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

996/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Bits 31:0 DIN[31:0]: Input data word

A four-fold sequential write to this bitfield during the input phase results in writing a complete 128-bit
block of input data to the AES peripheral. From the first to the fourth write, the corresponding data
weights are [127:96], [95:64], [63:32], and [31:0]. Upon each write, the data from the 32-bit input
buffer are handled by the data swap block according to the DATATYPE[1:0] bitfield, then written into
the AES core 128-bit input buffer.
The data signification of the input data block depends on the AES operating mode:
- Mode 1 (encryption): plaintext
- Mode 2 (key derivation): the bitfield is not used (AES_KEYRx registers used for input)
- Mode 3 (decryption): ciphertext
The data swap operation is described in Section 29.4.13: AES data registers and data swapping on
page 987.

29.7.4 AES data output register (AES_DOUTR)

Address offset: 0x0C
Reset value: 0x0000 0000
Only 32-bit read access type is supported.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DOUT[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DOUT[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 DOUT[31:0]: Output data word

This read-only bitfield fetches a 32-bit output buffer. A four-fold sequential read of this bitfield, upon
the computation completion (CCF set), virtually reads a complete 128-bit block of output data from
the AES peripheral. Before reaching the output buffer, the data produced by the AES core are
handled by the data swap block according to the DATATYPE[1:0] bitfield.
Data weights from the first to the fourth read operation are: [127:96], [95:64], [63:32], and [31:0].
The data signification of the output data block depends on the AES operating mode:
- Mode 1 (encryption): ciphertext
- Mode 2 (key derivation): the bitfield is not used
- Mode 3 (decryption): plaintext
The data swap operation is described in Section 29.4.13: AES data registers and data swapping on
page 987.

RM0438 Rev 7 997/2194

1004
AES hardware accelerator (AES) RM0438

29.7.5 AES key register 0 (AES_KEYR0)

Address offset: 0x10
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[31:16]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[15:0]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[31:0]: Cryptographic key, bits [31:0]

This write-only bitfield contains the bits [31:0] of the AES encryption or decryption key, depending on
the operating mode:
- In Mode 1 (encryption), Mode 2 (key derivation): the value to write into the bitfield is the encryption
key.
- In Mode 3 (decryption): the value to write into the bitfield is the encryption key to be derived before
being used for decryption.
The AES_KEYRx registers may be written only when KEYSIZE value is correct and when the AES
peripheral is disabled (EN bit of the AES_CR register cleared). Note that, if, the key is directly
loaded to AES_KEYRx registers (hence writes to key register is ignored and KEIF is set).
Refer to Section 29.4.14: AES key registers on page 989 for more details.

29.7.6 AES key register 1 (AES_KEYR1)

Address offset: 0x14
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[63:48]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[47:32]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[63:32]: Cryptographic key, bits [63:32]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

998/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.7.7 AES key register 2 (AES_KEYR2)

Address offset: 0x18
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[95:80]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[79:64]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[95:64]: Cryptographic key, bits [95:64]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

29.7.8 AES key register 3 (AES_KEYR3)

Address offset: 0x1C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[127:112]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[111:96]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[127:96]: Cryptographic key, bits [127:96]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

29.7.9 AES initialization vector register 0 (AES_IVR0)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RM0438 Rev 7 999/2194

1004
AES hardware accelerator (AES) RM0438

Bits 31:0 IVI[31:0]: Initialization vector input, bits [31:0]

Refer to Section 29.4.15: AES initialization vector registers on page 989 for description of the
IVI[127:0] bitfield.
The initialization vector is only used in chaining modes other than ECB.
The AES_IVRx registers may be written only when the AES peripheral is disabled

29.7.10 AES initialization vector register 1 (AES_IVR1)

Address offset: 0x24
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[63:48]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[47:32]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[63:32]: Initialization vector input, bits [63:32]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

29.7.11 AES initialization vector register 2 (AES_IVR2)

Address offset: 0x28
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[95:80]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[79:64]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 IVI[95:64]: Initialization vector input, bits [95:64]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

29.7.12 AES initialization vector register 3 (AES_IVR3)

Address offset: 0x2C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IVI[127:112]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IVI[111:96]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

1000/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

Bits 31:0 IVI[127:96]: Initialization vector input, bits [127:96]

Refer to the AES_IVR0 register for description of the IVI[128:0] bitfield.

29.7.13 AES key register 4 (AES_KEYR4)

Address offset: 0x30
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[159:144]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[143:128]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[159:128]: Cryptographic key, bits [159:128]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

29.7.14 AES key register 5 (AES_KEYR5)

Address offset: 0x34
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[191:176]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[175:160]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[191:160]: Cryptographic key, bits [191:160]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

29.7.15 AES key register 6 (AES_KEYR6)

Address offset: 0x38
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[223:208]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[207:192]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[223:192]: Cryptographic key, bits [223:192]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

RM0438 Rev 7 1001/2194

1004
AES hardware accelerator (AES) RM0438

29.7.16 AES key register 7 (AES_KEYR7)

Address offset: 0x3C
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
KEY[255:240]
w w w w w w w w w w w w w w w w
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY[239:224]
w w w w w w w w w w w w w w w w

Bits 31:0 KEY[255:224]: Cryptographic key, bits [255:224]

Refer to the AES_KEYR0 register for description of the KEY[255:0] bitfield.

Note: The key registers from 4 to 7 are used only when the key length of 256 bits is selected. They
have no effect when the key length of 128 bits is selected (only key registers 0 to 3 are used
in that case).

29.7.17 AES suspend registers (AES_SUSPxR)

Address offset: 0x040 + x * 0x4, (x = 0 to 7)
Reset value: 0x0000 0000
These registers contain the complete internal register states of the AES processor when the
AES processing of the current task is suspended to process a higher-priority task.
Upon suspend, the software reads and saves the AES_SUSPxR register contents (where x
is from 0 to 7) into memory, before using the AES processor for the higher-priority task.
Upon completion, the software restores the saved contents back into the corresponding
suspend registers, before resuming the original task.
Note: These registers are used only when GCM, GMAC, or CCM chaining mode is selected.
These registers can be read only when AES is enabled. Reading these registers while AES
is disabled returns 0x0000 0000.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SUSP[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SUSP[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 SUSP[31:0]: AES suspend

Upon suspend operation, this bitfield of the corresponding AES_SUSPxR register takes the value of
one of internal AES registers.

1002/2194 RM0438 Rev 7

RM0438 AES hardware accelerator (AES)

29.7.18 AES register map

Table 225. AES register map and reset values

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
DATATYPE[1:0]
CHMOD[1:0]
DMAOUTEN
GCMPH[1:0]
NPBLB[3:0]

MODE[1:0]
CHMOD[2]

DMAINEN
KEYSIZE

ERRIE
CCFIE
ERRC
CCFC
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.

Res.

EN
AES_CR
0x000

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WRERR
RDERR
BUSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

CCF
AES_SR
0x004

Reset value 0 0 0 0

AES_DINR DIN[31:0]
0x008
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_DOUTR DOUT[31:0]
0x00C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR0 KEY[31:0]
0x010
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR1 KEY[63:32]
0x014
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR2 KEY[95:64]
0x018
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR3 KEY[127:96]
0x01C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR0 IVI[31:0]
0x020
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR1 IVI[63:32]
0x024
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR2 IVI[95:64]
0x028
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_IVR3 IVI[127:96]
0x02C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR4 KEY[159:128]
0x030
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR5 KEY[191:160]
0x034
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_KEYR6 KEY[223:192]
0x038
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RM0438 Rev 7 1003/2194

1004
AES hardware accelerator (AES) RM0438

Table 225. AES register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
AES_KEYR7 KEY[255:224]
0x03C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP0R SUSP[31:0]
0x040
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP1R SUSP[31:0]
0x044
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP2R SUSP[31:0]
0x048
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP3R SUSP[31:0]
0x04C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP4R SUSP[31:0]
0x050
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP5R SUSP[31:0]
0x054
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP6R SUSP[31:0]
0x058
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AES_SUSP7R SUSP[31:0]
0x05C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x060-
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reserved
0x3FF

Refer to Section 2.3 on page 87 for the register boundary addresses.

1004/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

30 Hash processor (HASH)

30.1 Introduction
The hash processor is a fully compliant implementation of the secure hash algorithm
(SHA-1, SHA-224, SHA-256), the MD5 (message-digest algorithm 5) hash algorithm and
the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for
applications requiring message authentication.
The hash processor computes FIPS (Federal Information Processing Standards) approved
digests of length of 160, 224, 256 bits, for messages of up to (264 – 1) bits. It also computes
128-bit digests for the MD5 algorithm.

30.2 HASH main features

• Suitable for data authentication applications, compliant with:
– Federal Information Processing Standards Publication FIPS PUB 180-4, Secure
Hash Standard (SHA-1 and SHA-2 family)
– Federal Information Processing Standards Publication FIPS PUB 186-4, Digital
Signature Standard (DSS)
– Internet Engineering Task Force (IETF) Request For Comments RFC 1321, MD5
Message-Digest Algorithm
– Internet Engineering Task Force (IETF) Request For Comments RFC 2104,
HMAC: Keyed-Hashing for Message Authentication and Federal Information
Processing Standards Publication FIPS PUB 198-1, The Keyed-Hash Message
Authentication Code (HMAC)
• Fast computation of SHA-1, SHA-224, SHA-256, and MD5
– 82 (respectively 66) clock cycles for processing one 512-bit block of data using
SHA-1 (respectively SHA-256) algorithm
– 66 clock cycles for processing one 512-bit block of data using MD5 algorithm
• Corresponding 32-bit words of the digest from consecutive message blocks are added
to each other to form the digest of the whole message
– Automatic 32-bit words swapping to comply with the internal little-endian
representation of the input bit-string
– Word swapping supported: bits, bytes, half-words and 32-bit words
• Automatic padding to complete the input bit string to fit digest minimum block size of
512 bits (16 × 32 bits)
• Single 32-bit input register associated to an internal input FIFO, corresponding to one
block size
• AHB slave peripheral, accessible through 32-bit word accesses only (else an AHB
error is generated)
• 8 × 32-bit words (H0 to H7) for output message digest
• Automatic data flow control with support of direct memory access (DMA) using one
channel.
• Only single DMA transfers are supported

RM0438 Rev 7 1005/2194

1027
Hash processor (HASH) RM0438

• Interruptible message digest computation, on a per-block basis

– Re-loadable digest registers
– Hashing computation suspend/resume mechanism, including DMA

30.3 HASH implementation

The devices have a single instance of HASH peripheral.

30.4 HASH functional description

30.4.1 HASH block diagram

Figure 220 shows the block diagram of the hash processor.

Figure 220. HASH block diagram

Banked Registers

swapping
16x32-bit
IN FIFO
Data, key HASH_DIN HASH
Core
32-bit AHB2 bus

(SHA-1,
HASH_HRx Secure digest SHA-224,
SHA-256,
Status HASH_SR MD5)
Control HASH_CR
AHB +
interface Start HASH_STR
HMAC
logic
HASH_CSRx Suspend/Resume

hash_hclk

DMA
hash_dma Control Logic
interface
IRQ
hash_it
interface

MSv62405V3

1006/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

30.4.2 HASH internal signals

Table 226 describes a list of useful to know internal signals available at HASH level, not at
product level (on pads).

Table 226. HASH internal input/output signals

Signal name Signal type Description

hash_hclk digital input AHB bus clock

hash_it digital output Hash processor global interrupt request
hash_dma digital input/output DMA transfer request/ acknowledge

30.4.3 About secure hash algorithms

The hash processor is a fully compliant implementation of the secure hash algorithm
defined by FIPS PUB 180-4 standard and the IETF RFC1321 publication (MD5).
With each algorithm, the HASH computes a condensed representation of a message or
data file. More specifically, when a message of any length below 264 bits is provided on
input, the HASH processing core produces respectively a fixed-length output string called a
message digest, defined as follows:
• For MD5 digest size is 128-bit
• For SHA-1 digest size is 160-bit
• For SHA-224 and SHA-256, the digest size is 224 bits and 256 bits, respectively
The message digest can then be processed with a digital signature algorithm in order to
generate or verify the signature for the message.
Signing the message digest rather than the message often improves the efficiency of the
process because the message digest is usually much smaller in size than the message. The
verifier of a digital signature has to use the same hash algorithm as the one used by the
creator of the digital signature.
The SHA-2 functions supported by the hash processor are qualified as “secure” by NIST
because it is computationally infeasible to find a message that corresponds to a given
message digest, or to find two different messages that produce the same message digest
(SHA-1 does not qualify as secure since February 2017). Any change to a message in
transit, with very high probability, results in a different message digest, and the signature
fails to verify.

30.4.4 Message data feeding

The message (or data file) to be processed by the HASH should be considered as a bit
string. Per FIPS PUB 180-4 standard this message bit string grows from left to right, with
hexadecimal words expressed in “big-endian” convention, so that within each word, the
most significant bit is stored in the left-most bit position. For example message string “abc”
with a bit string representation of “01100001 01100010 01100011” is represented by a
32-bit word 0x00636261, and 8-bit words 0x61626300.
Data are entered into the HASH one 32-bit word at a time, by writing them into the
HASH_DIN register. The current contents of the HASH_DIN register are transferred to the
16 words input FIFO each time the register is written with new data. Hence HASH_DIN and
the FIFO form a seventeen 32-bit words length FIFO (named the IN buffer).

RM0438 Rev 7 1007/2194

1027
Hash processor (HASH) RM0438

In accordance to the kind of data to be processed (e.g. byte swapping when data are ASCII
text stream) there must be a bit, byte, half-word or no swapping operation to be performed
on data from the input FIFO before entering the little-endian hash processing core.
Figure 221 shows how the hash processing core 32-bit data block M0...31 is constructed
from one 32-bit words popped into input FIFO by the driver, according to the DATATYPE
bitfield in the HASH control register (HASH_CR).
HASH_DIN data endianness when bit swapping is disabled (DATATYPE = 00) can be
described as following: the least significant bit of the message has to be at MSB position in
the first word entered into the hash processor, the 32nd bit of the bit string has to be at MSB
position in the second word entered into the hash processor and so on.

Figure 221. Message data swapping feature

DATATYPE “00”: no swapping

LSB written first! System interface MSB
Word0 Word1 Word2 Word3
bit31 bit0 bit31 bit0 bit31 bit0 bit31 bit0

M0 M31 M32 M63 M64 M95 M96 M127

LSB HASH core interface MSB

DATATYPE “01”: 16-bit or half-word swapping

LSB written first! System interface MSB
Word0 Word1 Word2 Word3
bit31 bit16 bit15 bit0 bit31 bit16 bit15 bit0 bit31 bit16 bit15 bit0 bit31 bit16 bit15 bit0

M0 M15 M16 M31 M32 M47 M48 M63 M96 M111 M112 M127
LSB HASH core interface MSB

DATATYPE “10”: 8-bit or byte swapping

LSB written first! System interface MSB
Word0 Word1 Word2 Word3
bit31..24 bit23..16 bit15..8 bit7..0 bit31..24 bit23..16 bit15..8 bit7..0 bit31..24 bit23..16 bit15..8 bit7..0 bit31..24 bit23..16 bit15..8 bit7..0

M0..7 M8..15 M16..23 M24..31 M96..103 M112..119 M120..127

LSB HASH core interface MSB

DATATYPE “11”: bit swapping

LSB written first! System interface MSB
Word0 Word1 Word2 Word3
bit31 bit30bit29 bit2 bit1 bit0 bit31 bit30 bit29 bit2 bit1 bit0 bit31bit30 bit29 bit2 bit1 bit0

M0 M1 M2 M29 M30 M31 M32 M33 M34 M61 M62 M63 M96 M97 M98 M125M126M127
LSB HASH core interface MSB

MSv41984V4

1008/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

30.4.5 Message digest computing

The hash processor sequentially processes several blocks when computing the message
digest. For MD5, SHA1 and SHA2, the block size is 512 bits.
Each time the DMA or the CPU writes a block to the hash processor, the HASH
automatically starts computing the message digest. This operation is known as partial digest
computation.
As described in Section 30.4.4: Message data feeding, the message to be processed is
entered into the HASH 32-bit word at a time, writing to the HASH_DIN register to fill the
input FIFO.
In order to perform the hash computation on this data below sequence must be used by the
application:
1. Initialize the hash processor using the HASH_CR register:
a) Select the right algorithm using the ALGO bitfield. If needed program the correct
swapping operation on the message input words using DATATYPE bitfield in
HASH_CR.
b) When the HMAC mode is required, set the MODE bit, as well as the LKEY bit if the
HMAC key size is greater than the known block size of the algorithm (else keep
LKEY cleared). Refer to Section 30.4.7: HMAC operation for details.
c) Set MODE = 1 and select the key length using LKEY if HMAC mode has been
selected.
d) Update NBLW[4:0] to define the number of valid bits in last word of the message if
it is different from 32 bits. NBLW[4:0] information are used to correctly perform the
automatic message padding before the final message digest computation.
2. Complete the initialization by setting to 1 the INIT bit in HASH_CR. Also set the bit
DMAE to 1 if data are transferred via DMA.
Caution: When programming step 2, it is important to set up before or at the same time the correct
configuration values (ALGO, DATATYPE, HMAC mode, key length, NBLW[4:0]).
3. Start filling data by writing to HASH_DIN register, unless data are automatically:
transferred via DMA. Note that the processing of a block can start only once the last
value of the block has entered the input FIFO. The way the partial or final digest
computation is managed depends on the way data are fed into the processor:
a) When data are filled by software:
– Partial digest computation are triggered each time the application writes the first
word of the next block. Once the processor is ready again (DINIS = 1 in
HASH_SR), the software can write new data to HASH_DIN. This mechanism
avoids the introduction of wait states by the HASH.
– The final digest computation is triggered when the last block is entered and the
software writes the DCAL bit to 1. If the message length is not an exact multiple of
the block size, the NBLW[4:0] bitfield in HASH_STR register must be written prior
to writing DCAL bit (see Section 30.4.6 for details).
b) When data are filled by DMA as a single DMA transfer (MDMAT bit = 0):
– Partial digest computations are triggered automatically each time the FIFO is full.
The final digest computation is triggered automatically when the last block has
been transferred to the HASH_DIN register (DCAL bit is set to 1 by hardware). If
the message length is not an exact multiple of the block size, the NBLW[4:0] field

RM0438 Rev 7 1009/2194

1027
Hash processor (HASH) RM0438

in HASH_STR register must be written prior to enabling the DMA (see

Section 30.4.6 for details).
c) When data are filled using multiple DMA transfers (MDMAT bit = 1):
– Partial digest computations are triggered as for single DMA transfers. However the
final digest computation is not triggered automatically when the last block has
been transferred to the HASH_DIN register (DCAL bit is not set to 1 by hardware).
It allows the hash processor to receive a new DMA transfer as part of this digest
computation. To launch the final digest computation, the software must set
MDMAT bit to 0 before the last DMA transfer in order to trigger the final digest
computation as it is done for single DMA transfers (see description before).
4. Once the digest computation is complete (DCIS = 1), the resulting digest can be read
from the output registers as described in Table 227.

Table 227. Hash processor outputs

Algorithm Valid output registers Most significant bit Digest size (in bits)

MD5 HASH_H0 to HASH_H3 HASH_H0[31] 128

SHA-1 HASH_H0 to HASH_H4 HASH_H0[31] 160
SHA-224 HASH_H0 to HASH_H6 224
HASH_H0[31]
SHA-256 HASH_H0 to HASH_H7 256

For more information about HMAC detailed instructions, refer to Section 30.4.7: HMAC
operation.

30.4.6 Message padding

Overview
When computing a condensed representation of a message, the process of feeding data
into the hash processor (with automatic partial digest computation every block transfer)
loops until the last bits of the original message are written to the HASH_DIN register.
As the length (number of bits) of a message can be any integer value, the last word written
to the hash processor may have a valid number of bits between 1 and 32. This number of
valid bits in the last word, NBLW[4:0], has to be written to the HASH_STR register, so that
message padding is correctly performed before the final message digest computation.

Padding processing
Detailed padding sequences with DMA enabled or disabled are described in Section 30.4.5:
Message digest computing.

Padding example
As specified by Federal Information Processing Standards PUB 180-4, the message
padding consists in appending a “1” followed by k “0”s, itself followed by a 64-bit integer that
is equal to the length L in bits of the message. These three padding operations generate a
padded message of length L + 1 + k + 64, which by construction is a multiple of 512 bits.
For the hash processor, the “1” is added to the last word written to the HASH_DIN register at
the bit position defined by the NBLW[4:0] bitfield, and the remaining upper bits are cleared
(“0”s).

1010/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Example from FIPS PUB180-4

Let us assume that the original message is the ASCII binary-coded form of “abc”, of length
L = 24:
byte 0 byte 1 byte 2 byte 3
01100001 01100010 01100011 UUUUUUUU
<-- 1st word written to HASH_DIN -->
NBLW[4:0] has to be loaded with the value 24: a “1” is appended at bit location 24 in the bit
string (starting counting from left to right in the above bit string), which corresponds to bit 31
in the HASH_DIN register (little-endian convention):
01100001 01100010 01100011 1UUUUUUU
Since L = 24, the number of bits in the above bit string is 25, and 423 “0” bits are appended,
making now 448 bits.
This gives in hexadecimal (byte words in big-endian format):
61626380 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000018
The message length value, L, in two-word format (that is 00000000 00000018) is appended.
Hence the final padded message in hexadecimal (byte words in big-endian format):
61626380 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000018
If the hash processor is programmed to swap byte within HASH_DIN input register
(DATATYPE = 10 in HASH_CR), the above message has to be entered by following the
below sequence:
1. 0xUU636261 is written to the HASH_DIN register (where ‘U’ means don’t care).
2. 0x18 is written to the HASH_STR register (the number of valid bits in the last word
written to the HASH_DIN register is 24, as the original message length is 24 bits).
3. 0x10 is written to the HASH_STR register to start the message padding (described
above) and then perform the digest computation.
4. The hash computing is complete with the message digest available in the HASH_HRx
registers (x = 0...4) for the SHA-1 algorithm. For this FIPS example, the expected value
is as follows:
HASH_HR0 = 0xA9993E36
HASH_HR1 = 0x4706816A
HASH_HR2 = 0xBA3E2571
HASH_HR3 = 0x7850C26C
HASH_HR4 = 0x9CD0D89D

RM0438 Rev 7 1011/2194

1027
Hash processor (HASH) RM0438

30.4.7 HMAC operation

Overview
As specified by Internet Engineering Task Force RFC2104 and NIST FIPS PUB 198-1, the
HMAC algorithm is used for message authentication by irreversibly binding the message
being processed to a key chosen by the user. The algorithm consists of two nested hash
operations:
HMAC(message)= Hash((Key | pad) XOR opad |
Hash((Key | pad) XOR ipad | message))
where:
• opad = [0x5C]n (outer pad) and ipad = [0x36]n (inner pad)
• [X]n represents a repetition of X n times, where n equal to the size of the underlying
hash function data block (n = 64 for 512-bit blocks).
• pad is a sequence of zeroes needed to extend the key to the length n defined above. If
the key length is greater than n, the application must first hash the key using Hash()
function and then use the resultant byte string as the actual key to HMAC.
• | represents the concatenation operator.

HMAC processing
Four different steps are required to compute the HMAC:
1. The software writes the INIT bit to 1 with the MODE bit at 1 and the ALGO bits set to
the value corresponding to the desired algorithm. The LKEY bit must also be set to 1 if
the key being used is longer than 64 bytes. In this case, as required by HMAC
specifications, the hash processor uses the hash of the key instead of the real key.
2. The software provides the key to be used for the inner hash function, using the same
mechanism as the message string loading, that is writing the key data into HASH_DIN
register then completing the transfer by writing DCAL bit to 1 and the correct
NBLW[4:0] to HASH_STR register.
Note: Endianness details can be found in Section 30.4.4: Message data feeding.
3. Once the processor is ready again (DINIS = 1 in HASH_SR), the software can write the
message string to HASH_DIN. When the last word of the last block is entered and the
software writes DCAL bit to 1 in HASH_STR register, the NBLW[4:0] bitfield must be
written at the same time to a value different from zero if the message length is not an
exact multiple of the block size. Note that the DMA can also be used to feed the
message string, as described in Section 30.4.4: Message data feeding.
4. Once the processor is ready again (DINIS = 1 in HASH_SR), the software provides the
key to be used for the outer hash function, writing the key data into HASH_DIN register
then completing the transfer by writing DCAL bit to 1 and the correct NBLW[4:0] to
HASH_STR register. The HMAC result can be found in the valid output registers
(HASH_HR7) as soon as DCIS bit is set to 1.
Note: The computation latency of the HMAC primitive depends on the lengths of the keys and
message, as described in Section 30.6: HASH processing time.
HMAC example
Below is an example of HMAC SHA-1 algorithm (ALGO = 00 and MODE = 1 in HASH_CR)
as specified by NIST.

1012/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Let us assume that the original message is the ASCII binary-coded form of “Sample
message for keylen = blocklen”, of length L = 34 bytes. If the HASH is programmed
in no swapping mode (DATATYPE = 00 in HASH_CR), the following data must be loaded
sequentially into HASH_DIN register:
1. Inner hash key input (length = 64, that is no padding), specified by NIST. As key
length = 64, LKEY bit is set to 0 in HASH_CR register
00010203 04050607 08090A0B 0C0D0E0F 10111213 14151617
18191A1B 1C1D1E1F 20212223 24252627 28292A2B 2C2D2E2F
30313233 34353637 38393A3B 3C3D3E3F
2. Message input (length = 34, that is padding required). HASH_STR must be set to
0x20 to start message padding and inner hash computation (see ‘U’ as don’t care)
53616D70 6C65206D 65737361 67652066 6F72206B 65796C65
6E3D626C 6F636B6C 656EUUUU
3. Outer hash key input (length = 64, that is no padding). A key identical to the inner
hash key is entered here.
4. Final outer hash computing is then performed by the HASH. The HMAC-SHA1 digest
result is available in the HASH_HRx registers (x = 0 to 4), as shown below:
HASH_HR0 = 0x5FD596EE
HASH_HR1 = 0x78D5553C
HASH_HR2 = 0x8FF4E72D
HASH_HR3 = 0x266DFD19
HASH_HR4 = 0x2366DA29

RM0438 Rev 7 1013/2194

1027
Hash processor (HASH) RM0438

30.4.8 HASH suspend/resume operations

Overview
It is possible to interrupt a hash/HMAC operation to perform another processing with a
higher priority. The interrupted process completes later when the higher-priority task has
been processed, as shown in Figure 222.

Figure 222. HASH suspend/resume mechanism

Message 1 Message 2
Block 1

Block 2

New higher HASH suspend

priority message sequence
2 to be processed Block 3
Block 1

Block 2
(last block)
Block 4

HASH resume
sequence
Block 5

Block 6

... MSv41985V2

To do so, the context of the interrupted task must be saved from the HASH registers to
memory, and then be restored from memory to the HASH registers.
The procedures where the data flow is controlled by software or by DMA are described
below.

1014/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Data loaded by software

When the DMA is not used to load the message into the hash processor, the context can be
saved only when no block processing is ongoing.
To suspend the processing of a message, proceed as follows after writing 16 words 32-
bit (plus one if it is the first block):
1. In Polling mode, wait for BUSY = 0, then poll if the DINIS status bit is set to 1.
In Interrupt mode, implement the next step in DINIS interrupt handler (recommended).
2. Store the contents of the following registers into memory:
– HASH_IMR
– HASH_STR
– HASH_CR
– HASH_CSR0 to HASH_CSR37. HASH_CSR38 to HASH_CSR53 registers must
also be saved if an HMAC operation was ongoing.
To resume the processing of a message, proceed as follows:
1. Write the following registers with the values saved in memory: HASH_IMR,
HASH_STR and HASH_CR.
2. Initialize the hash processor by setting the INIT bit in the HASH_CR register.
3. Write the HASH_CSRx registers with the values saved in memory.
4. Restart the processing from the point where it has been interrupted.
Note: To optimize the resume process when NBW[3:0] = 0x0, HASH_CSR22 to HASH_CSR37
registers do not need to be saved then restored as the FIFO is empty.

Data loaded by DMA

When the DMA is used to load the message into the hash processor, it is recommended to
suspend and then restore a secure digest computing is described below.
To suspend the processing of a message using DMA, proceed as follows:
1. In Polling mode, wait for BUSY = 0. If DCIS is set in HASH_SR, the hash result is
available and the context swapping is useless. Else go to step 2.
2. In Polling mode, wait for BUSY = 1.
3. Disable the DMA channel. Then clear DMAE bit in HASH_CR register.
4. In Polling mode, wait for BUSY = 0. If DCIS is set in HASH_SR, the hash result is
available and the context swapping is useless. Else go to step 5.
5. Save HASH_IMR, HASH_STR, HASH_CR, and HASH_CSR0 to HASH_CSR37
registers. HASH_CSR38 to HASH_CSR53 registers must also be saved if an HMAC
operation was ongoing.

RM0438 Rev 7 1015/2194

1027
Hash processor (HASH) RM0438

To resume the processing of a message using DMA, proceed as follows:

1. Reconfigure the DMA controller so that it proceeds with the transfer of the message up
to the end if it is not interrupted again. Do not forget to take into account the words that
have been already pushed into the FIFO if NBW[3:0] is higher than 0x0.
2. Program the values saved in memory to HASH_IMR, HASH_STR and HASH_CR
registers.
3. Initialize the hash processor by setting the INIT bit in the HASH_CR register.
4. Program the values saved in memory to the HASH_CSRx registers.
5. Restart the processing from the point where it was interrupted by setting the DMAE bit.
Note: To optimize the resume process when NBW[3:0] = 0x0, HASH_CSR22 to HASH_CSR37
registers do not need to be saved then restored as the FIFO is empty.

30.4.9 HASH DMA interface

The HASH only supports single DMA transfers.
The hash processor provides an interface to connect to the DMA controller. This DMA can
be used to write data to the HASH by setting the DMAE bit in the HASH_CR register. When
this bit is set, the HASH initiates a DMA request each time a block has to be written to the
HASH_DIN register.
Once four 32-bit words have been received, the HASH automatically triggers a new request
to the DMA. For more information refer to Section 30.4.5: Message digest computing.
Before starting the DMA transfer, the software must program the number of valid bits in the
last word that is copied into HASH_DIN register. This is done by writing in HASH_STR
register the following value:
NBLW[4:0] = Len(Message)% 32 where “x%32” gives the remainder of x divided
by 32.
The DMAS bit of the HASH_SR register provides information on the DMA interface activity.
This bit is set with DMAE and cleared when DMAE is cleared and no DMA transfer is
ongoing.
Note: No interrupt is associated to DMAS bit.
When MDMAT is set, the size of the transfer must be a multiple of four words.

30.4.10 HASH error management

No error flags are generated by the hash processor.

30.5 HASH interrupts

Two individual maskable interrupt sources are generated by the hash processor to signal
the following events:
• Digest calculation completion (DCIS)
• Data input buffer ready (DINIS)
Both interrupt sources are connected to the same global interrupt request signal (hash_it),
which is in turn connected to the NVIC (nested vectored interrupt controller). Each interrupt
source can individually be enabled or disabled by changing the mask bits in the HASH_IMR
register. Setting the appropriate mask bit to 1 enables the interrupt.

1016/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

The status of each maskable interrupt source can be read from the HASH_SR register.
Table 228 gives a summary of the available features.

Table 228. HASH interrupt requests

Enable
Interrupt acronym Interrupt event Event flag Interrupt clear method
control bit

Digest computation completed DCIS DCIE Clear DCIS or set INIT

HASH Data input buffer ready to get a Clear DINIS or write to
DINIS DINIE
new block HASH_DIN

30.6 HASH processing time

Table 229 summarizes the time required to process an intermediate block for each mode of
operation.

Table 229. Processing time (in clock cycle)

Mode of operation FIFO load(1) Computation phase Total

MD5 16 50 66
SHA-1 16 66 82
SHA-224
16 50 66
SHA-256
1. Add the time required to load the block into the processor.

The time required to process the last block of a message (or of a key in HMAC) can be
longer. This time depends on the length of the last block and the size of the key (in HMAC
mode).
Compared to the processing of an intermediate block, it can be increased by the factor
below:
• 1 to 2.5 for a hash message
• ~2.5 for an HMAC input-key
• 1 to 2.5 for an HMAC message
• ~2.5 for an HMAC output key in case of a short key
• 3.5 to 5 for an HMAC output key in case of a long key

RM0438 Rev 7 1017/2194

1027
Hash processor (HASH) RM0438

30.7 HASH registers

The HASH core is associated with several control and status registers and several message
digest registers. All these registers are accessible through 32-bit word accesses only, else
an AHB error is generated.

30.7.1 HASH control register (HASH_CR)

Address offset: 0x00
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ALGO1 Res. LKEY
rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. MDMAT DINNE NBW[3:0] ALGO0 MODE DATATYPE[1:0] DMAE INIT Res. Res.
rw r r r r r rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value.

Bit 17 Reserved, must be kept at reset value.
Bit 16 LKEY: Long key selection
This bit selects between short key (≤ 64 bytes) or long key (> 64 bytes) in HMAC
mode.
0: the HMAC key is shorter or equal to 64 bytes. The actual key value written to
HASH_DIN is used during the HMAC computation.
1: the HMAC key is longer than 64 bytes. The hash of the key is used instead of
the real key during the HMAC computation.
This selection is only taken into account when the INIT bit is set and MODE = 1.
Changing this bit during a computation has no effect.
Bit 15 Reserved, must be kept at reset value.
Bit 14 Reserved, must be kept at reset value.
Bit 13 MDMAT: Multiple DMA transfers
This bit is set when hashing large files when multiple DMA transfers are needed.
0: DCAL is automatically set at the end of a DMA transfer.
1: DCAL is not automatically set at the end of a DMA transfer.
Bit 12 DINNE: DIN not empty
This bit is set when the HASH_DIN register holds valid data (that is after being
written at least once). It is cleared when either the INIT bit (initialization) or the
DCAL bit (completion of the previous message processing) is written to 1.
0: No data are present in the data input buffer
1: The input buffer contains at least one word of data
This bit is read-only.

1018/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Bits 11:8 NBW[3:0]: Number of words already pushed

This bitfield reflects the number of words in the message that have already been
pushed into the IN FIFO. NBW is incremented by one when a write access to the
HASH_DIN register is performed (except if DINNE = 0 and the DMA is not used,
see below description). NBW goes to zero when the INIT bit is written to 1.
This bitfield is read-only.
If the DMA is not used
0000: if DINNE = 0, no word has been pushed into the DIN buffer (both
HASH_DIN register and IN FIFO are empty), otherwise one word has been
pushed into the DIN buffer (HASH_DIN register contains one word and IN FIFO
is empty)
0001: two words have been pushed into the DIN buffer (that is HASH_DIN
register and the IN FIFO contain one word each)
...
1111: 16 words have been pushed into the DIN buffer.

If the DMA is used

NBW contains the exact number of words that have been pushed into the IN
FIFO by the DMA.
Bits 18, 7 ALGO[1:0]: Algorithm selection
These bits select the hash algorithm.
00: SHA-1
01: MD5
10: SHA-224
11: SHA-256
This selection is only taken into account when the INIT bit is set. Changing this
bitfield during a computation has no effect.
Bit 6 MODE: Mode selection
This bit selects the HASH or HMAC mode for the selected algorithm:
0: Hash mode selected
1: HMAC mode selected. LKEY must be set if the key being used is longer than
64 bytes.
This selection is only taken into account when the INIT bit is set. Changing this
bit during a computation has no effect.
Bits 5:4 DATATYPE[1:0]: Data type selection
Defines the format of the data entered into the HASH_DIN register:
00: 32-bit data. The data written into HASH_DIN are directly used by the HASH
processing, without reordering.
01: 16-bit data, or half-word. The data written into HASH_DIN are considered as
two half-words, and are swapped before being used by the HASH processing.
10: 8-bit data, or bytes. The data written into HASH_DIN are considered as four
bytes, and are swapped before being used by the HASH processing.
11: bit data, or bit-string. The data written into HASH_DIN are considered as 32
bits (1st bit of the string at position 0), and are swapped before being used by
the HASH processing (1st bit of the string at position 31).

RM0438 Rev 7 1019/2194

1027
Hash processor (HASH) RM0438

Bit 3 DMAE: DMA enable

0: DMA transfers disabled
1: DMA transfers enabled. A DMA request is sent as soon as the HASH core is
ready to receive data.
After this bit is set it is cleared by hardware while the last data of the message is
written into the hash processor.
Setting this bit to 0 while a DMA transfer is on-going is not aborting this current
transfer. Instead, the DMA interface of the IP remains internally enabled until the
transfer is completed or INIT is written to 1.
Setting INIT bit to 1 does not clear DMAE bit.
Bit 2 INIT: Initialize message digest calculation
Writing this bit to 1 resets the hash processor core, so that the HASH is ready to
compute the message digest of a new message.
Writing this bit to 0 has no effect. Reading this bit always return 0.
Bits 1:0 Reserved, must be kept at reset value.

30.7.2 HASH data input register (HASH_DIN)

Address offset: 0x04
Reset value: 0x0000 0000
HASH_DIN is the data input register. It is 32-bit wide. This register is used to enter the
message by blocks. When the HASH_DIN register is programmed, the value presented on
the AHB databus is ‘pushed’ into the hash core and the register takes the new value
presented on the AHB databus. To get a correct message format, the DATATYPE bits must
have been previously configured in the HASH_CR register.
When a complete block has been written to the HASH_DIN register, an intermediate digest
calculation is launched:
• by writing new data into the HASH_DIN register (the first word of the next block) if the
DMA is not used (intermediate digest calculation),
• automatically if the DMA is used.
When the last block has been written to the HASH_DIN register, the final digest calculation
(including padding) is launched by writing the DCAL bit to 1 in the HASH_STR register (final
digest calculation). This operation is automatic if the DMA is used and MDMAT bit is set to 0.
Reading the HASH_DIN register returns the last word written to this location (zero after
reset).
Note: When the HASH is busy, a write access to the HASH_DIN register might stall the AHB bus if
the digest calculation (intermediate or final) is not complete.
.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATAIN[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATAIN[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

1020/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Bits 31:0 DATAIN[31:0]: Data input

Writing this register pushes the current register content into the IN FIFO, and the
register takes the new value presented on the AHB databus.
Reading this register returns the current register content.

30.7.3 HASH start register (HASH_STR)

Address offset: 0x08
Reset value: 0x0000 0000
The HASH_STR register has two functions:
• It is used to define the number of valid bits in the last word of the message entered in
the hash processor (that is the number of valid least significant bits in the last data
written to the HASH_DIN register)
• It is used to start the processing of the last block in the message by writing the DCAL
bit to 1

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. DCAL Res. Res. Res. NBLW[4:0]
rw rw rw rw rw rw

Bits 31:9 Reserved, must be kept at reset value.

Bit 8 DCAL: Digest calculation
Writing this bit to 1 starts the message padding, using the previously written
value of NBLW[4:0], and starts the calculation of the final message digest with all
data words written to the input FIFO since the INIT bit was last written to 1.
Reading this bit returns 0.
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 NBLW[4:0]: Number of valid bits in the last word
When the last word of the message bit string is written in HASH_DIN register, the
hash processor takes only the valid bits specified as below, after internal data
swapping:
0x00: All 32 bits of the last data written are valid message bits that is M[31:0]
0x01: Only one bit of the last data written (after swapping) is valid that is M[0]
0x02: Only two bits of the last data written (after swapping) are valid that is
M[1:0]
0x03: Only three bits of the last data written (after swapping) are valid that is
M[2:0]
...
0x1F: Only 31 bits of the last data written (after swapping) are valid that is
M[30:0]
The above mechanism is valid only if DCAL = 0. If NBLW[4:0] bitfield is written
while DCAL is set to 1, the NBLW[4:0] bitfield remains unchanged. In other words
it is not possible to configure NBLW[4:0] and set DCAL at the same time.
Reading NBLW[4:0] bitfield returns the last value written to NBLW[4:0].

RM0438 Rev 7 1021/2194

1027
Hash processor (HASH) RM0438

30.7.4 HASH digest registers

These registers contain the message digest result named as follows:
• HASH_HR0, HASH_HR1, HASH_HR2, HASH_HR3 and HASH_HR4 registers return
the SHA-1 digest result
• HASH_HR0, HASH_HR1, HASH_HR2 and HASH_HR3 registers return A, B, C and D
(respectively), as defined by MD5.
• HASH_HR0 to HASH_HR6 registers return the SHA-224 digest result.
• HASH_HR0 to HASH_HR7 registers return the SHA-256 digest result.
In all cases, the digest most significant bit is stored in HASH_H0[31] and unused
HASH_HRx registers are read as zeros.
If a read access to one of these registers is performed while the hash core is calculating an
intermediate digest or a final message digest (DCIS bit equals 0), then the read operation is
stalled until the hash calculation has completed.
Note: When starting a digest computation for a new message (by writing the INIT bit to 1),
HASH_HRx registers are forced to their reset values.
HASH_HR0 to HASH_HR4 registers can be accessed through two different addresses.

HASH aliased digest register x (HASH_HRAx)

Address offset: 0x0C + 0x04 * x, (x = 0 to 4)
Reset value: 0x0000 0000
The content of the HASH_HRAx registers is identical to the one of the HASH_HRx registers
located at address offset 0x310.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Hx[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Hx[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 Hx[31:0]: Hash data x

Refer to Section 30.7.4: HASH digest registers introduction.

HASH digest register x (HASH_HRx)

Address offset: 0x310 + 0x04 * x, (x = 0 to 4)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Hx[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Hx[15:0]
r r r r r r r r r r r r r r r r

1022/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Bits 31:0 Hx[31:0]: Hash data x

Refer to Section 30.7.4: HASH digest registers introduction.

HASH supplementary digest register x (HASH_HRx)

Address offset: 0x310 + 0x04 * x, (x = 5 to 7)
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Hx[31:16]
r r r r r r r r r r r r r r r r
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Hx[15:0]
r r r r r r r r r r r r r r r r

Bits 31:0 Hx[31:0]: Hash data x

Refer to Section 30.7.4: HASH digest registers introduction.

30.7.5 HASH interrupt enable register (HASH_IMR)

Address offset: 0x20
Reset value: 0x0000 0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DCIE DINIE
rw rw

Bits 31:2 Reserved, must be kept at reset value.

Bit 1 DCIE: Digest calculation completion interrupt enable
0: Digest calculation completion interrupt disabled
1: Digest calculation completion interrupt enabled.
Bit 0 DINIE: Data input interrupt enable
0: Data input interrupt disabled
1: Data input interrupt enabled

RM0438 Rev 7 1023/2194

1027
Hash processor (HASH) RM0438

30.7.6 HASH status register (HASH_SR)

Address offset: 0x24
Reset value: 0x0000 0001

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BUSY DMAS DCIS DINIS
r r rc_w0 rc_w0

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 BUSY: Busy bit
0: No block is currently being processed
1: The hash core is processing a block of data
Bit 2 DMAS: DMA Status
This bit provides information on the DMA interface activity. It is set with DMAE
and cleared when DMAE = 0 and no DMA transfer is ongoing. No interrupt is
associated with this bit.
0: DMA interface is disabled (DMAE = 0) and no transfer is ongoing
1: DMA interface is enabled (DMAE = 1) or a transfer is ongoing
Bit 1 DCIS: Digest calculation completion interrupt status
This bit is set by hardware when a digest becomes ready (the whole message
has been processed). It is cleared by writing it to 0 or by writing the INIT bit to 1
in the HASH_CR register.
0: No digest available in the HASH_HRx registers (zeros are returned)
1: Digest calculation complete, a digest is available in the HASH_HRx registers.
An interrupt is generated if the DCIE bit is set in the HASH_IMR register.
Bit 0 DINIS: Data input interrupt status
This bit is set by hardware when the FIFO is ready to get a new block (16
locations are free). It is cleared by writing it to 0 or by writing the HASH_DIN
register.
0: Less than 16 locations are free in the input buffer
1: A new block can be entered into the input buffer. An interrupt is generated if
the DINIE bit is set in the HASH_IMR register.
When DINIS=0, HASH_CSRx registers reads as zero.

30.7.7 HASH context swap registers

These registers contain the complete internal register states of the hash processor. They
are useful when a suspend/resume operation has to be performed because a high-priority
task needs to use the hash processor while it is already used by another task.
When such an event occurs, the HASH_CSRx registers have to be read and the read
values have to be saved in the system memory space. Then the hash processor can be
used by the preemptive task, and when the hash computation is complete, the saved
context can be read from memory and written back into the HASH_CSRx registers.
HASH_CSRx registers can be read only when DINIS equals to 1, otherwise zeros are
returned.

1024/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

HASH context swap register x (HASH_CSRx)

Address offset: 0x0F8 + x * 0x4, (x = 0 to 53)
Reset value: 0x0000 0002 (HASH_CSR0)
Reset value: 0x0000 0000 (HASH_CSR1 to 53)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CSx[31:16]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CSx[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:0 CSx[31:0]: Context swap x

Refer to Section 30.7.7: HASH context swap registers introduction.

RM0438 Rev 7 1025/2194

1027
Hash processor (HASH) RM0438

30.7.8 HASH register map

Table 230 gives the summary HASH register map and reset values.

Table 230. HASH register map and reset values

Offset Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name

DATATYPE
NBW[3:0]
ALGO[1]

ALGO[0]
.MDMAT
DINNE

MODE

DMAE
LKEY
HASH_CR

INIT
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.

Res.
Res.

Res.
Res.
0x00

Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_DIN DATAIN[31:16]
0x04
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NBLW[4:0]
DCAL
HASH_STR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

Res.
Res.
Res.
0x08

Reset value 0 0 0 0 0 0
HASH_HRA0 H0[31:0]
0x0C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HRA1 H1[31:0]
0x10
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HRA2 H2[31:0]
0x14
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HRA3 H3[31:0]
0x18
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HRA4 H4[31:0]
0x1C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DINIE
DCIE
HASH_IMR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x20
Reset value 0 0
DMAS
BUSY

DINIS
DCIS

HASH_SR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.

0x24
Reset value 0 0 0 1
0x28 to
Reserved Res.
0xF4
HASH_CSR0 CS0[31:0]
0x0F8
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

1026/2194 RM0438 Rev 7

RM0438 Hash processor (HASH)

Table 230. HASH register map and reset values (continued)

Offset Register

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12

10
11

9
8
7
6
5
4
3
2
1
0
name
0x0F8 + HASH_CSRx CSx[31:0]
0x4 * x,
(x = 1 to
53)
Last Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
address:
0x1CC
...
0x1D0
Reserved Res.
to 0x30C
HASH_HR0 H0[31:0]
0x310
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR1 H1[31:0]
0x314
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR2 H2[31:0]
0x318
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR3 H3[31:0]
0x31C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR4 H4[31:0]
0x320
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR5 H5[31:0]
0x324
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR6 H6[31:0]
0x328
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HASH_HR7 H7[31:0]
0x32C
Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Section 2.3 on page 87 for the register boundary addresses.

RM0438 Rev 7 1027/2194

1027
On-the-fly decryption engine (OTFDEC) RM0438

31 On-the-fly decryption engine (OTFDEC)

31.1 Introduction
OTFDEC allows on-the-fly decryption of the AHB traffic based on the read request address
information. Four independent and non-overlapping encrypted regions can be defined in
OTFDEC.
OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency. As a
consequence, each time the content of one encrypted region is changed, the entire region
must be re-encrypted with a different cryptographic context (key or initialization vector). This
constraint makes OTFDEC suitable to decrypt read-only data or code, stored in external
NOR Flash.
Note: When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to access the Flash
memory using the Memory-mapped mode of the Flash memory controller.
When security is enabled in the product, OTFDEC can be programmed only by a secure
host.

31.2 OTFDEC main features

• On-the-fly 128-bit decryption during the OCTOSPI Memory-mapped read operations
(single or multiple).
– Use of AES in counter (CTR) mode, with two 128-bit keystream buffers
– Support for any read size
– Physical address of the reads used for the encryption/decryption
• Up to four independent encrypted regions
– Granularity of the region definition: 4096 bytes
– Region configuration write-locking mechanism
– Each region has its own 128-bit key, two bytes firmware version, and eight bytes
application-defined nonce. At least one of those must be changed each time an
encryption is performed by the application.
• Encryption keys confidentiality and integrity protection
– Write-only registers, with software locking mechanism
– Availability of 8-bit CRC as public key information
• Support for OCTOSPI pre-fetching mechanism
• Possibility to select an enhanced encryption mode to add a proprietary layer of
protection on top of AES stream cipher (execute only)
• AMBA AHB slave peripheral, accessible through 32-bit word single accesses only
(otherwise an AHB bus error is generated, and write accesses are ignored)
• Secure only programming if TrustZone security is enabled in the product
• Encryption mode

1028/2194 RM0438 Rev 7

RM0438 On-the-fly decryption engine (OTFDEC)

31.3 OTFDEC functional description

31.3.1 OTFDEC block diagram

Figure 223. OTFDEC block diagram

OTFDEC
IRQ
otfdec_it interface
Banked registers
(x=1 to 4)

RxCFGR Control
AHB lite
RxADDR Logic
32-bit AHB bus

slave
interface RxKEYR

Key

IVs
RxNONCE
...
AES-CTR
otfdec_hclk

To/From Keystream[0]
control logic Keystream[1]
otfdec_tzen AHB clock domain

OCTOSPI (Slave)
hreadyout_o Proprietary hreadyout_i

AHB memory
XOR
32-bit AHB bus

hrdata_o[31:0] hrdata_in[31:0]

interface
XOR

haddr[31:0] AHB memory haddr[31:0]

Other AHB signals interface Other AHB signals

MS48972V2

31.3.2 OTFDEC internal signals

Table 231 describes a list of useful to know internal signals available at OTFDEC level, not
at the product level (on pads).

Table 231. OTFDEC internal input/output signals

Signal name Signal type Description

otfdec_hclk Digital input AHB bus clock

otfdec_it Digital output OTFDEC global interrupt request
OTFDEC TrustZone enable, controlling TrustZone features of the
otfdec_tzen Digital input
peripheral (TZEN)

RM0438 Rev 7 1029/2194

1049
On-the-fly decryption engine (OTFDEC) RM0438

The TZEN option bit in FLASH is used to activate TrustZone in the device.
• TZEN = 1: TrustZone security is enabled in the product.
• TZEN = 0: TrustZone security is disabled in the product.

31.3.3 OTFDEC on-the-fly decryption

Introduction
Typical usage for OTFDEC is shown on Figure 224.

Figure 224. Typical OTFDEC use in a SoC

Instruction data/system
cache cache

OTFDEC
OCTOSPI

SPI bus
SoC boundary

SPI NOR
Flash
MS48973V1

Original purpose of OTFDEC is to protect the confidentiality of read-only firmware libraries

stored in external SPI NOR Flash devices.
A special locking scheme is available in OTFDEC in order to protect the integrity of the
decryption keys and also to protect the other configurations against software denial of
services attacks. OTFDEC is only writeable by TrustZone CPU, when TrustZone security is
activated.
When OTFDEC is used in conjunction with OCTOSPI, it is mandatory to read the Flash
memory using the Memory-mapped mode of the Flash controller.
On top of decrypting on-the-fly, OTFDEC can also encrypt 32-bit word at a time (see
Section 31.5.3: Encrypting for OTFDEC for more details).

OTFDEC architecture
OTFDEC analyzes all AHB read transfers on the associated AHB bus. If the read request is
within one of the four regions programmed in OTFDEC, the control logic triggers a
keystream computation based on AES algorithm in counter mode. This keystream is then
used to decrypt on-the-fly the data present in the read transfer from the OCTOSPI AHB
master, tying low the HREADYOUT signal of this master while the keystream information is
being computed (this takes up to 11 cycles). Any accesses outside the enabled OTFDEC
regions belong to a non-encrypted region.
Each OTFDEC region is programmed through OTFDEC_RxCFGR,
OTFDEC_RxSTARTADDR, OTFDEC_RxENDADDR, OTFDEC_RxNONCER and

1030/2194 RM0438 Rev 7

RM0438 On-the-fly decryption engine (OTFDEC)

OTFDEC_RxKEYR registers, where x = 1 to 4. In OTFDEC_RxCFGR, the MODE bits

define the OTFDEC operating mode (standard or enhanced encryption).
Granularity for the region determination is 4096 bytes.
Note: Although OTFDEC does not prevent region overlapping, it is not a valid programming and it
must be avoided by application software.
OTFDEC can decrypt incremental or wrap bursts only if they do not cross the 4096-byte
aligned address boundaries.

31.3.4 AES in counter mode decryption

Figure 225 shows how OTFDEC uses industry standard Advanced Encryption Standard
(AES) algorithm in counter chaining mode. This mode is specified by NIST in Special
Publication 800-38A, Recommendation for Block Cipher Modes of Operation.

Figure 225. AES CTR decryption flow

AES_IV AES_IV
Nonce Version Id Address_0 Nonce Version Id Address_1

128-bit

AES_KEY AES_KEY
AES Block cipher AES Block cipher
encryption encryption
128-bit 128-bit

Keystream_0 Keystream_1

128-bit
AES_DIN (cipher text 0) AES_DIN (cipher text 1)

128-bit 128-bit

AES_DOUT (plain text 0) AES_DOUT (plain text 1)

MS48969V1

Every 128-bit data block, a special keystream information is computed using AES block
cipher, as defined below:
• initialization vector AES_IV[127:0] = RxNONCER1[31:0] || RxNONCER0[31:0] ||
0b0000 0000 0000 0000 || RxCFGR[31:16] || 0b00 || (x-1) || ReadAddress[31:4]
• key material AES_KEY[127:0] = RxKEYR3[31:0] || RxKEYR2[31:0] || RxKEYR1[31:0] ||
RxKEYR0[31:0]
Note: Above x is the RegionID of the selected encrypted region (x=1 to 4).
ReadAddress is the AHB address of the encrypted data block, modulo 128-bit.
Resulting 128-bit keystream is XORed with 128-bit cipher text data to produce the 128-bit
clear text data.
• AES_DIN and AES_DOUT data blocks are constructed following the rule below (“|”
represents a binary concatenation):
AES_Dx[127:0]= AHB_word(@ | 0xC)[31:0] | AHB_word(@ | 0x8)[31:0] | AHB_word(@
| 0x4)[31:0] || AHB_word(@ | 0x0)[31:0], where @ is the hexadecimal address used to
compute the keystream (ReadAddress[31:4] above).

RM0438 Rev 7 1031/2194

1049
On-the-fly decryption engine (OTFDEC) RM0438

When the read request is not within an encrypted region, or the decryption is not enabled in
this region, the AHB data is not changed.
Note: When the application sets the MODE bitfield to 11 in OTFDEC_RxCFGR, an additional layer
of protection is added on top of the AES stream cipher. This enhanced encryption mode can
only be used with instructions (execute-only region).

31.3.5 Flow control management

Figure 226 shows how OTFDEC manages one INCR4 AHB burst that corresponds to one
128-bit AES data block.

Figure 226. OTFDEC flow control overview (dual burst read request)

AHB Clock
120MHz

HADDR Add(A) Add(B) Add(C)

HREADY
HRDATA 1 Data(A) Data(B) Data(C) Data(D)
2
Keystream[0] Keystream[1]
OTFDEC (AES)
OTFDEC (XOR) XOR(A) XOR(B) XOR(C) XOR(D)

>12 cycles MS48974V1

with the following notes:

1. OTFDEC enforces HREADY signal from the AHB master low as it is not ready to
decrypt data (keystream computation).
2. Thanks to the keystream buffer, OTFDEC can be ready to process a new batch of data
within 12 cycles in this configuration (120 MHz AHB clock, 104 MHz SPI bus delivering
2 bytes per SPI clock).

31.3.6 OTFDEC error management

OTFDEC automatically manages errors defined as below:
• Illegal read to OTFDEC_RxKEYR registers
• Illegal write to OTFDEC_RxKEYR registers while CONFIGLOCK or KEYLOCK = 1 in
OTFDEC_RxCFGR, while the access is secure. If the security is disabled in the
product, the same error occurs when the access is non-secure.
• Illegal write to OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR,
OTFDEC_RxENDADDR or OTFDEC_RxNONCER registers while CONFIGLOCK = 1
in OTFDEC_RxCFGR (x = 1 to 4), while the access is secure. If the security is disabled
in the product the same error occurs when the access is non-secure.
• Illegal read to an execute-only region (MODE[1:0] = 11). Such illegal request returns
0x0, without bus error.
• Execution request to a region while encryption is enabled (ENC = 1). The request
returns 0x0, without bus error.
• Key error: read request to an encrypted region while its key registers are null or not
properly initialized (KEYCRC=0x0). Source of the error can be an incorrect key loading
sequence (see KEYCRC in OTFDEC_RxCFGR) or it can be an abort event (tamper

1032/2194 RM0438 Rev 7

RM0438 On-the-fly decryption engine (OTFDEC)

detection, unauthorized debug connection, untrusted boot, RDP level regression).

Such read request returns 0x0, without bus error.
• Write to any registers while the access is non-secure, if TrustZone security is enabled
in the product.
This last error is managed and cleared through TrustZone interrupt controller, as
described in the GTZC section of the product reference manual.
For these errors (except the last one), an interrupt can be generated if the SEIE, XONEIE or
KEIE bit is set in OTFDEC_IER register (see Section 31.4).
Note: After a key error, OTFDEC keys must be properly initialized again, and a reset of OTFDEC
may be needed if registers are locked.

31.4 OTFDEC interrupts

There are three independent maskable interrupt sources generated by the OTFDEC,
signaling following security events:
• Illegal read or write access to keys (SEIF flag), see Section 31.3.6
• Illegal write to a region configuration while CONFIGLOCK = 1 (SEIF flag), see
Section 31.3.6
• Read access to an execute-only region (MODE[1:0] = 11), triggering the XONEIF flag
• Executing while encryption is enabled (XONEIF flag)
• Key error (encrypted regions read as zero) triggering the KEIF flag, see Section 31.3.6.
Interrupt sources are connected to the same global interrupt request signal.
OTFDEC interrupt sources can be enabled/disabled by setting the corresponding SEIE,
XONEIE or KEIE bit in OTFDEC_IER, as described in Table 232. Status of the interrupt
event is found in OTFDEC_ISR, and this event can be cleared using OTFDEC_ICR.
Table 232. OTFDEC interrupt requests
Interrupt Enable
Interrupt event Event flag(1) Interrupt clear method
acronym control bit

Security error SEIF SEIE Set SEIF in OTFDEC_ICR

Execute-only
OTFDEC Execute while XONEIF XONEIE Set XONEIF in OTFDEC_ICR
encryption
Key error KEIF KEIE Set KEIF in OTFDEC_ICR
1. The event flags are found in the OTFDEC_ISR register.

31.5 OTFDEC application information

31.5.1 OTFDEC initialization process

Introduction
One key aspect of OTFDEC is the trusted initialization of its registers, as it involves secret
keys. Two trusted initialization schemes are recommended here below.

RM0438 Rev 7 1033/2194

1049
On-the-fly decryption engine (OTFDEC) RM0438

Note: Those sequences are for production code, as during firmware development, it is not always
recommended to lock the key or the region configuration.
Writes to configuration registers are effective when the configuration locks allow it, even if
the region is enabled.

Initialization scheme 1: one key for all regions

In this scheme, one entity owns the secret key used to decrypt the four protected regions.
The recommended OTFDEC configuration sequence is described below:
1. For x = 1 to 4, write the correct MODE[1:0] value in OTFDEC_RxCFGR.
2. For x = 1 to 4, program OTFDEC_RxKEYR registers using the sequence described in
KEYCRC (to have a valid CRC). Warning as key registers are write only.
3. For x = 1 to 4, check the key CRC. If OK, set KEYLOCK bit in OTFDEC_RxCFGR. This
bit cannot be cleared (key registers in this region x are no more writable).
4. To do to decrypt a region x (task that does not necessarily have to be performed by the
entity that owns the decryption keys):
a) Verify if the key CRC corresponds to the encrypted binary stored in the region.
b) Fill the detailed information corresponding to this binary (nonce, start address, end
address, version number).
c) Enable decryption of this region using REG_EN.
d) Set CONFIGLOCK bit in OTFDEC_RxCFGR. This bit cannot be cleared (the
region configuration is no more writable).
Caution: For a given region, when MODE bits are changed, the key registers and associated CRC
are cleared by hardware. As a consequence, step 1 above must be done before step 2, and
MODE bits must not be modified after step 2.

Initialization scheme 2: one key per region

In this scheme, one entity can own the secret used to decrypt one (or more) protected
region. The recommended OTFDEC configuration sequence is described below:
1. To do to decrypt a region x (this task must be performed by the entity that owns the
corresponding key):
a) Write the correct MODE[1:0] value in OTFDEC_RxCFGR.
b) Program OTFDEC_RxKEYR registers using the sequence described in KEYCRC
(to have a valid CRC). Warning as key registers are write only.
c) Check the key CRC. If OK, set KEYLOCK bit in OTFDEC_RxCFGR. This bit
cannot be cleared (key registers are no more writable).
d) Fill the detailed information corresponding to the protected firmware (nonce, start
address, end address, version number).
e) Enable decryption of this region using REG_EN.
f) Set CONFIGLOCK bit in OTFDEC_RxCFGR. This bit cannot be cleared (the
region configuration is no more writable).
Caution: For a given region, when MODE bits are changed, the key registers and associated CRC
are cleared by hardware. As a consequence step a) above must be done before step b),
and MODE bits must not be modified after step b).

1034/2194 RM0438 Rev 7

RM0438 On-the-fly decryption engine (OTFDEC)

31.5.2 OTFDEC and power management

Each time OTFDEC is reset, the correct key loading sequence described in Section 31.5.1
must be performed (in this case KEYCRC = 0 in OTFDEC_RxCFGR).
It is recommended for application software to verify this point each time OTFDEC is reset by
hardware.

31.5.3 Encrypting for OTFDEC

Code and data standard encryption
OTFDEC uses standard AES in counter mode when processing a binary stored in a
protected region with MODE[1:0] = 10. When this mode is selected, any AES compatible
hardware accelerator or library can be used to encrypt those protected libraries. OTFDEC
can be used as well, as described in enhanced encryption section below (with
MODE[1:0] = 10).
Definition and endianness of the AES inputs and outputs are defined in Section 31.3.4: AES
in counter mode decryption.

Enhanced encryption with OTFDEC

OTFDEC uses a proprietary layer of protection on top of the standard AES in counter mode
when processing a code stored in a protected region with MODE[1:0] = 11.
Enhanced encryption mode can be used to increase the robustness against tampering.
Recommended sequence to encrypt using OTFDEC is described below:
1. The application in charge of the encryption sets the ENC bit in OTFDEC_CR. This
application must run in TrustZone secure mode when TrustZone security is enabled in
the product. If PRIV bit is set in OTFDEC_PRIVCFGR, this application must be
privileged.
2. Encryption application initializes OTFDEC as described in Section 31.5.1: OTFDEC
initialization process. OCTOSPI must also be properly clocked, so that OTFDEC is fully
functional in encryption mode. This step can also be done before step 1.
3. Encryption application writes 32-bit of clear-text data at the expected protected
address, then reads it back encrypted at the same address to store it in RAM. Note that
this data stays inside the device, as it is intercepted by OTFDEC in encryption mode.
4. Encryption application goes back to previous step (changing the address) until the
whole binary is processed.
5. Encryption application clears the ENC bit in OTFDEC_CR. Another application can
then take the encrypted binary and flash it to the correct address in external Flash.
There are few important notes about this procedure:
• Encryption granularity is 32-bit (single 32-bit access is mandatory).
• While ENC bit is set, reads to non-encrypted regions return normal data (such as no
encryption nor decryption). While in encryption mode, no access to OCTOSPI
(including registers) must be done. This is because the OTFDEC cuts the
communication with OCTOPSI while ENC bit is set.
• OTFDEC does not support execution while ENC = 1 (only encrypted data reads). Upon
illegal execution detection a XONEIF flag is raised and zero is returned.

RM0438 Rev 7 1035/2194

1049
On-the-fly decryption engine (OTFDEC) RM0438

31.5.4 OTFDEC key CRC source code

Below is the CRC source code that can be used to compare with the result of the
computation provided by OTFDEC in KEYCRC bitfield after loading the keys in
OTFDEC_RxKEYR registers.

uint8_t getCRC(uint32_t * keyin)

{
const uint8_t CRC7_POLY = 0x7;
const uint32_t key_strobe[4] = {0xAA55AA55, 0x3, 0x18, 0xC0};
uint8_t i, j, k, crc = 0x0;
uint32_t keyval;

for (j = 0; j < 4; j++)

{
keyval = *(keyin+j);
if (j == 0)
{
keyval ^= key_strobe[0];
}
else
{
keyval ^= (key_strobe[j] << 24) | (crc << 16) | (key_strobe[j] << 8)
| crc;
}

for (i = 0, crc = 0; i < 32; i++)

{
k = (((crc >> 7) ^ (keyval >> (31-i))&0xF)) & 1;
crc <<= 1;
if (k)
{
crc ^= CRC7_POLY;
}
}
crc^=0x55;
}
return crc;
}

1036/2194 RM0438 Rev 7

RM0438 On-the-fly decryption engine (OTFDEC)

31.6 OTFDEC registers

31.6.1 OTFDEC control register (OTFDEC_CR)

Address offset: 0x0
Reset value: 0x0000 0000
Non-TrustZone AHB write access (HNONSEC = 1) is discarded if the TrustZone security is
enabled in the product.
Unprivileged reads return zero and unprivileged writes are ignored if PRIV bit is set in
OTFDEC_PRIVCFGR.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ENC

rw

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 ENC: Encryption mode bit
When this bit is set, OTFDEC is used in encryption mode, during which application can write
clear text data then read back encrypted data. When this bit is cleared (default), OTFDEC is
used in decryption mode, during which application only read back decrypted data. For both
modes, cryptographic context (keys, nonces, firmware versions) must be properly initialized.
When this bit is set, only data accesses are allowed (zeros are returned otherwise, and
XONEIF is set). When MODE = 11, enhanced encryption mode is automatically selected.
0: OTFDEC working in decryption mode
1: OTFDEC working in encryption mode
Note: When ENC bit is set, no access to OCTOSPI must be done (registers and
Memory-mapped region).

31.6.2 OTFDEC privileged access control configuration register

(OTFDEC_PRIVCFGR)
Address offset: 0x10
Reset value: 0x0000 0000
Non-TrustZone AHB write access (HNONSEC = 1) is discarded if the TrustZone security is
enabled in the product.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PRIV

rw

RM0438 Rev 7 1037/2194

1049
On-the-fly decryption engine (OTFDEC) RM0438

Bits 31:1 Reserved, must be kept at reset value.

Bit 0 PRIV: Privileged access protection.
0: No additional protection is added on OTFDEC register accesses.
1: An additional protection is added when accessing all registers except
OTFDEC_PRIVCFGR:
– Unprivileged read accesses to registers return zeros
– Unprivileged write accesses to registers are ignored.
Note: This bit can only be written in privileged mode. There is no limitations on reads.

31.6.3 OTFDEC region x configuration register (OTFDEC_RxCFGR)

Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4)
Reset value: 0x0000 0000
Non-TrustZone AHB write access (HNONSEC = 1) is discarded if the TrustZone security is
enabled in the product.
Unprivileged reads return zero and unprivileged writes are ignored if PRIV bit is set in
OTFDEC_PRIVCFGR.
Writes are ignored if CONFIGLOCK bit is set to 1.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REGx_VERSION[15:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONFI REG_
KEYCRC[7:0] Res. Res. MODE[1:0] Res. KEYLOCK
GLOCK EN
r r r r r r r r rw rw rs rs rw

Bits 31:16 REGx_VERSION[15:0]: region firmware version

This 16-bit bitfield must be correctly initialized before the region corresponding REG_EN bit
is set in OTFDEC_RxCFGR.
Bits 15:8 KEYCRC[7:0]: region key 8-bit CRC
When KEYLOCK = 0, KEYCRC bitfield is automatically computed by hardware while loading
the key of this region in this exact sequence: KEYR0 then KEYR1 then KEYR2 then finally
KEYR3 (all written once). A new computation starts as soon as a new valid sequence is
initiated, and KEYCRC is read as zero until a valid sequence is completed.
When KEYLOCK = 1, KEYCRC remains unchanged until the next reset.
CRC computation is an 8-bit checksum using the standard CRC-8-CCITT algorithm
X8 + X2 + X + 1 (according the convention). Source code is available in Section 31.5.4.
This field is read only.
Note: CRC information is updated only after the last bit of the key has been written.
Bits 7:6 Reserved, must be kept at reset value.

1038/2194 RM0438 Rev 7

RM0438 On-the-fly decryption engine (OTFDEC)

Bits 5:4 MODE[1:0]: operating mode

This bitfield selects the OTFDEC operating mode for this region:
10: All read accesses are decrypted (instruction or data).
11: Enhanced encryption mode is activated, and only instruction accesses are decrypted
Others: Reserved
When MODE ≠ 11, the standard AES encryption mode is activated.
When either of the MODE bits are changed, the region key and associated CRC are zeroed.
Bit 3 Reserved, must be kept at reset value.
Bit 2 KEYLOCK: region key lock
0: Writes to this region KEYRx registers are allowed.
1: Writes to this region KEYRx registers are ignored until next OTFDEC reset. KEYCRC
bitfield is locked.
Note: This bit is set once: if this bit is set, it can only be reset to 0 if the OTFDEC is reset.
Bit 1 CONFIGLOCK: region config lock
0: Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR,
OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are allowed.
1: Writes to this region OTFDEC_RxCFGR, OTFDEC_RxSTARTADDR,
OTFDEC_RxENDADDR and OTFDEC_RxNONCERy registers are ignored until next
OTFDEC reset.
No