25/01/2020

XJEL3285/ELEC3285
Integrated Circuit Design
Dr Paul Steenson
Rm 464, Email d.p.steenson@leeds...

Recommended Books :-

Introduction to VLSI circuits and Systems, by J. P. Uyemura – which gives an excellent coverage of my material
or vice versa - the main book that I will use to take examples from and support the course
6 copies in Library and £15-60 on Amazon – paperback

There is a wealth of material on the Interweb so no excuses please!

Chip Design for Submicron VLSI CMOS Layout and simulation, by J.P. Uyemura – another good book and accompaniment
to Microwind
Introduction to VLSI Systems: A Logic, Circuit and System Perspective, by Ming-Bo Lin – A more comprehensive book
covering largely the same topics but to a greater depth than Uyemura’s book
N.Weste & K.Eshraghian, Principles of CMOS VLSI Design:- Old book but foundations haven’t changed all that much
Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin, CRC Press, 2011.
K. Martin, Digital Integrated Circuit Design :- More physical approach with good links to SPICE
J.F. Wakerley, Digital Design, principles and practices :- Typical digital design perspective
R.C.Jaeger, Microelectronic Circuit Design :- More microelectronics centred

Module Objectives

Goal is to link the layout and physical properties of transistors and logic gates to their
performance via switching behaviour, circuit timing, power, noise etc – so you can
understand the importance and implications (trade-offs) on performance of size reduction
power dissipation strategies and the underlying structure and constraints for your CPU’s,
GPU’s, FPGAs, CPDs etc.

We will be studying the transistor transient behaviour (from a quasi analogue point of
view to understand the limits when used as binary switches) then moving to a simpler
switch based picture (in order to cope with the complexity of 100B transistors), to see the
relationship between switching speed, layout and construction, device physics and circuit
models.

Primarily, it is the channel and access resistance, and associated capacitances that are
the key determinants of overall switching behaviour, i.e. speed and power and these are
largely determined by size (length and width) of the transistor channel, materials and
construction.

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Changes made after student feedback from Last year

• 20 lectures and 210 slides - now 16 lectures and ~160 slides

• Rearranged material in a more logical sequence with more
notes pages added (still recommend following in textbook)
– Transistors as switches (Physical & Electrical)>Logic Gates (Simple to more advanced) >System Level
(Architectures, Memory, Synchronisation and Data flow)
• No Examples Classes – now 4 examples classes covering 4
topics/e
• No suggested self study discussion topics – now 1 / class
• Rewritten CAD Lab support materials – aim is to be clearer
• Assessment of CAD lab changed to include several clearer
mini project based tasks requiring some out of class
problem solving in your own time then some individual VLE
based data input for evaluation – this part equates to 3
credits i.e. ~10-20hours of own study time.

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Scope / Coverage
I intend to skim through the first 5 chapters of Uyemura over the next 2-4
lectures I would implore you to take some time to do this yourself, as it will
greatly help you to understand and engage with this module - The material
in the latter parts of Ch3 and Ch4 will not be covered this year – I would
encourage anyone who is keen to read this as well, but the IC fabrication
detail is not essential for this module. later we will use Microwind to
explore some of the switching behaviour and operating principles and
relationships with transistor and logic gate construction.

I will then cover some key topics which I think are important from the
remainder of the book (chapters 6-8, 1st part of Ch9, & 13 and 15) this
seems a lot but involves only a few basic concepts upon which everything
is built.

- so for a deep level of understanding and to maximise your chances to

achieve excellent marks then you should read the book by JP Uyemura
to fill in any gaps in your understanding of those topics that I have selected.

Coverage in Ming-Bo Lin

• Chapter 1 all (except 1.2.4 and 1.2.5 – not so important)
• Chapter 2.3 onwards – although for completeness 2.1 and 2.2 offer a recap of the important
aspects of your first year semiconductor physics (Physical Electronics -1&2, XJEL1900 & XJEL1901).
Key sections are 2.3.1 through to 2.3.4
• I’ll not be discussing any of Ch3 other than to comment where the choice of a material or size might
significantly effect the electrical characteristics, so you might skim through this just to understand
the basic principles of how we make the IC’s – this could be and indeed is a course in itself
• In chapter 4 I’m only going to focus on 4.1.1 but the remainder of the chapter is good background
for the CAD and Microwind work later on for those that are deeply interested.
• In chapter 5 I’m going to cover 5.1 through to 5.2.1* and 5.2.5 then 5.3 through to 5.3.3.1 inclusive.
• Chapter 6 All relevant, but I’ll only have time to skim through a lot of this and mainly focussing on
6.1 and 6.2 then 6.3.1 and the same can be said of the later chapters – that I’ll be skimming through
large parts and focussing here and there to give you an important overview
• In ch7 sections 7.1, 7.157.2.2, 7.2.3.1 are key
• In ch8 then sections 8.1 through to 8.2.2 then 8.2.4 and 8.3.1 and 8.5.1.1 are particularly valuable
• In ch9 sections 9.1, 9.2.1.1, 9.2.2.19.3, and 9.4 are important
• In Ch11 I’m only going to focus on the key basics of DRAM, SRAM, Non-volatile RAM (Flash RAM
and EEPROM) and even though its important I’m going to ignore all but 13.2 of ch13 and finish on
14.2

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This Lecture: Introduction

Setting the scene
• Background
– I would strongly encourage you to read the first introductory chapters of
Uyemura and Ming-Bo Lin and listen to my pre-recorded lectures 1-3
from last year as an introduction
• Analogue versus Digital
– I remind you of the philosophy or why you would use digital and why and
when analogue realisations
• Why CMOS
– Why did CMOS lead to what many call “The Second Industrial Revolution”
• Levels of integration > present day
• Design issues & associated costs
– This is covered in my 3rd lecture and in Ming-Bo Lin Ch1
• Structured design & representational levels
• PLD’s
– IC’s versus programmable devices – What’s the difference?
Learning objectives

Appreciation of some of the key background & issues

Familiarity with some of the terminology & design strategies as an aid to building future
deeper understanding

Why CMOS ?
• Extremely low static power consumption
• Similar gate transition times (predictability)
– Symmetric switching (high>low, low>high)
• Fully restored logic (clear 1’s and 0’s)
• Straightforward memory and latch elements
– Low off-state leakage currents (DRAM hold times and dissipation)
• Switching voltages are a fraction of supply voltages
– Threshold voltages < supply voltages (VT~1/3VDD)
• Large noise margins (~25-40% of voltage swing)
– Immunity to processing and environmental changes
• Regular layout & smaller device sizes
– Design and implementation is easily automated
• But, bipolar(npn) circuits can exhibit
– Faster switching than CMOS & higher current driving capability :- hence
BiCMOS

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Floating fire ant colony: what you can do in large “coordinated” numbers !

The VLSI design funnel

The sum of this work has been refined by

about 100 billion hours of combined and
Continuous human effort over the last
60 or so years, but like any exponential growth
the progress and variety has exploded
in the last 20-30 years

Silicon Ingots

A wafer of devices being functionally

Tested before dicing and packaging

Slightly light-hearted or whimsical figure from Uyemura

Figure 1.1

Structured Design Strategy:

How to manage this great complexity

• Complex digital designs are broken down into

increasingly simple interconnected modules In the trade these modules are
referred to as Instances
– Hierarchical implementation Eg. Memory units, registers, flip-flops
buffers, ALU’s, simple and more complex
• Standard modules & rules for interconnection Logic gates or blocks of combinational
Logic – anything that’s useful and
– Regular placement & routing of transistors / gates Repeted

• Concepts of Hierarchy, Modularity and Regularity are

all part of a structured design strategy
• Top-down design
– Complex systems are decomposed into ever simpler subsystems
down to transistor level
• Bottom-up design
– Transistors grouped into gates, gates to sub-cells then these into
modules, sub-systems and interconnected sub-systems

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Study & Discussion Topic

How do the radius of a silicon atom and an electron compare and approximately
how many silicon atoms are there in a distance of 10nm ?

How does this relate to future silicon integrated circuit designs ?

Design flow for a microprocessor

HDL

RTL

Logic

Interconnected layout

Figure 1.3 (p. 5)

Vast number of interconnected transistor switches

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Overview of Design Hierarchy

Abstract / top level – i.e. overall architecture

Register Transfer Level (RTL)

How the data is moved
and operated on unit by unit

Fig 11.10 from Uyemura

Top down hierarchy

Silicon Compiler !
Envisaged by
D. Johannson & C Mead
In 1979 to go straight
from HDL to transistor
and interconnect layout
} Register Transfer Level (RTL)

Possible now using standard

I With tool such as Synopsis®
cell library elements and through n
FPGA’s and CPLD’s 1
9
Greatly aided by standard and
7 specialist cell libraries – gate
9 primitives & leaf cells and other
repeated structures

We are going to spend most of

our time around here but S
Freear will be covering more
abstract upper levels in his
FPGA course and John
Cunningham will cover
microfabrication next year.

This is covered in some depth in Ch10 of Uyemura for those that are interested

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Recap: System Representation

• Behavioural Level
– Problem broken down into sequence of actions / events then
logic arising from behavioural requirement is formulated and
verified, then structural design is synthesised
• Structural Level
– Interconnection of gates
– Functional testing of logic to verify meets behavioural
requirement
• Physical Level
– Decomposed into “leaf “ cells or gate-primitives then transistors and
interconnects to realise gates etc.
– Optimised for speed, power consumption and area (Full-Custom) or
for standard cell (Semi-Custom )
– Checked against functional requirement (timing etc) & optimised

Transistor Size Reduction V’s Time

Plan view of single transistor In the 70’s Gate length was 7.5μm and 1 transistor
Occupied 6000 μm2 with < 10k transistors on a single
IC operating at <0.1MIPS – Intel 4004 CPU by Federico Faggin
(an Italian Physicist)
Note: the 4 processor Cray 2 supercomputer of the mid 80’s
(based on 1um transistors) were about as powerful as a
single processor in an iPad 2 !
By 1995 for the Pentium Gate length had shrunk to
<0.5 μm and associated transistor area was <1% of
that in the 70’s with 10M transistors on a chip and
Operating at 500MIPS
2λ
Now the gate length is <20nm with >5B transistors, multiple cores
Pentium 4, Itanium, Xeon (server apps) with 2-4GHz
clock speeds & I/O transfer rates from 10’s GBit/S and
system bus speeds of 400-800MHz
2λ
with the chips now dissipating ~150W this is setting a thermal
limit at present ie Numbers of transistors for a given clock
speed – multiple cores, variable clocks and supply rail voltages
to cope with heat generation.
2λ
Note: the 2x6 core 2.9GHz Intel Xeon in Mac Pro performs as well as a
Supercomputer from the mid 90’s with a performance of 3.5TFLOP !
2λ
By comparison 1 layer of atoms ~ 0.25nm thick and a 10nm2 area
Gate Lengths Except now ~ a cluster of 160 atoms !
Now ~10nm Tri-Gates / or finfets

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How far we have come since Jack Kilby

Patented the IC in 1959
• https://youtu.be/Fxv3JoS1uY8
• Intel 8-Core Gaming Processor an 8 core, 16 thread gaming processor Intel® Core™ i7-5960X

Considerable processing power combined

with ubiquitous high bandwidth (5G)
communications is transforming our world
Today eg real time traffic data via network of
phones and GPS on each showing real time
traffic data which can be harvested and
mapped

Intel’s 15nm process

Edge-on view of interconnects and transistors (very bottom layer)

Intel’s 15nm process using

broadwall (or FINFET)
design approach

i.e. folded surface to give more

surface area on the otherwise flat
surface

Surface of the Silicon:

where all the action happens!

http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-usb-finfet-2014Q3.aspx

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Programmable Devices
PIC’s, FPGA’s and CPD’s
• Programmable integrated circuits (PICs), programmable microcontrollers
and then on to complex programmable logic devices (CPLDs) and field
programmable devices (FPGAs) are similar in many ways to non-
programmable IC’s but differ in their general purpose and more flexible
nature – this usually comes at the cost of performance (power, speed,
chip-area, cost). However the extreme parallel nature of FPGA’s can give
performance boosts for certain tasks and the IP or intellectual property
(soft) cores can be changed and optimised at will or even remotely.

Cost Breakdown
More often than not determines choices of
technology
• Non Recurrent Engineering (NRE) costs are highest for Custom Application Specific IC’s
(ASIC’s)
– + £10,000-£500,000, compared to discrete implementation
• 1 off design cost of 100,000 gate ASIC could be £50k-£200k !
– So per-unit saving must be anticipated :- large sales volume
• Individual transistor or gate level optimisation could cost 10 times above figure ! ( + high
risk !!)
– Typically use library of standard (pre-optimised and validated) cells used
– Eg. Decoders, Registers, Counters etc.
• For ASIC’s one option is for groups to collaborate to buy wafer “real estate” by the square
mm !
• Gate arrays have lower NRE costs £10k-£100k
– Faster design to product
– But, chips are larger and slower - ie micro-cells and layout not as well optimised as
standard cell approach
• Complex Programmable, FPGA and PICs are new electronic lego building blocks except
where specialist functionality required – more often than you might think!

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Now Lets Look at the Components that

make all this possible
: - Recap of Logic before looking closely at the
CMOS transistors

• Behaviour of assert-high (NMOS) and assert-low switches(PMOS)

NMOS Switch

PMOS Switch

The Basics: Transistors as Switches

A positive voltage on gate of a nFET A negative (relative*) voltage on gate of a pFET

closes the switch – or creates a low closes the switch – or creates a low
resistance channel between the source resistance channel between the source
and the drain and the drain

Relative* - because what’s important is the relative voltage between the source and the gate. i.e. Although positive and negative
rail voltages would be nice, in practice we usually only have positive voltages available – helps simply things from an
implementation point of view (PoV)!

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Logic Realisation basic

or/and topology
OR gate based on
NMOS or nFETs

0 0 0
0 1 1
1 0 1
1 1 1

NAND gate based on

PMOS or pFETs

0 0 1
0 1 0
1 0 0
1 1 0

Switch based NOT gate

Above circuit is representational but as we will see later this can be rearranged to
form an actual inverter – where the 1 input here is VDD and 0 is VSS or 0v or Gnd

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Single rail power supply & Logic Levels

Strong Logic 1

Weak Logic 1

Weak Logic 0

Strong Logic 0

* We try to avoid voltages in the undefined region – or making decisions or switching inputs or outputs when the voltages
could be in the undefined region

Fig 2.11 Uyemura

Very quick overview of MOS fab

process

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