ELEC 3285

Integrated Circuit Design

Dr Paul Steenson
Rm 267, Email d.p.steenson@leeds...
Recommended Books :-

Introduction to VLSI circuits and Systems, by J. P. Uyemura – which gives an excellent coverage of my material
or vice versa - the main book that I will use to take examples from and support the course
6 copies in Library and £15-60 on Amazon – paperback

There is a wealth of material on the Interweb so no excuses please!

Chip Design for Submicron VLSI CMOS Layout and simulation, by J.P. Uyemura – another good book and accompaniment
to Microwind
N.Weste & K.Eshraghian, Principles of CMOS VLSI Design:- Old book but foundations haven’t changed all that much
Introduction to VLSI Systems: A Logic, Circuit and System Perspective – Ming-BO Lin, CRC Press, 2011.
K. Martin, Digital Integrated Circuit Design :- More physical approach with good links to SPICE
J.F. Wakerley, Digital Design, principles and practices :- Typical digital design perspective
R.C.Jaeger, Microelectronic Circuit Design :- More microelectronics centred
 You knew this was important!
How did we get here? > 10-100Bn Hrs* of effort and understanding !

Homo sapiens ~0.2M yr ~1.7Bn Hrs!!

~$500Bn

UK GDP 2017 $2,600Bn (2017)

The year-on-year growth in 2018 is expected to see growth rates of 12.4 percent. The largest semiconductor chip maker
is Samsung Electronics, which generated 59.88 billion U.S. dollars in revenue in 2017

Because of the slowdown in the Chinese economy and drop in demand Apple’s stock has dipped by $450Bn between Oct18 and Jan19
• 50yr, 8h/d, 100,000 scientists / workers
• Jack Kilby 1957/58 Patented 1959 “a body of semiconducting material” Nobel Prize in 2000 for the Invention of the IC!
 Teaching & Assessment

Teaching ~ 18 1h lectures (Mondays 10-11am, Wednesdays 9:00-10am )

+ example classes

There will be one in-class CAD Lab assessment worth 30%, based on
culmination of 4x2h sessions
– CAD Labs start on the Thurs 28th Feb 3-5pm
- In-class assessment Thursday 28th March 3-5pm
- Term ends on 29th March

2hr unseen exam 70%, date: TBA

 Module Objectives

Aim is to link the layout and physical properties of transistors and logic gates to their
switching behaviour, and circuit timing, power, noise etc – so you can understand the
importance and implications (trade-offs) on performance of size reduction and the
underlying structure and constraints for your CPU’s, GPU’s, FPGAs, CPDs etc.

We will be studying the transistor transient behaviour (from a quasi analogue point of
view) then moving to a simpler switch based picture (to cope with the complexity), to see
the relationship between switching speed and construction, device physics and circuit
models.

Primarily, it is the channel resistance, and capacitance that are the key determinants of
overall switching behaviour, i.e. speed and power and these are largely determined by size
(length and width) of the transistor channel, materials and construction.
 Scope / Coverage
I intend to skim through the first 5 chapters of Uyemura over the next 2-4
lectures I would implore you to take some time out to do this yourself as it
will greatly encourage you to engage with this module - The material in the
latter parts of Ch3 and Ch4 will not be covered this year – I would
encourage anyone that’s keen to read this as well, but the IC fabrication
detail is not essential for this module. later we will use Microwind to
explore some of the switching behaviour and operating principles and
relationships with transistor and logic gate construction.

I will then cover some key topics which I think are important from the
remainder of the book (chapters 6-8, 1st part of Ch9, & 13 and 15) this
seems a lot but involves only a few basic concepts upon which everything
is built.

- so for a deep level of understanding and to maximise your chances to

achieve excellent marks then you should read the book by JP Uyemura
and understand those topics that I have selected.
 This Lecture: Introduction
Setting the scene
• Background
• Analogue versus Digital
• Why CMOS
• Levels of integration > present day
• Design issues & associated costs
• PLD’s
• Structured design & representational levels

Learning objectives

Appreciation of some of the key background & issues

Familiarity with some of the terminology & design strategies as an aid to
building future deeper understanding
 Where does this all Fit
(with what you know already)
• Behavioural Level
– More abstract problem broken down into sequence of actions / events – non
unique generalised description – Finite State Machines
• HDL (Verilog, VHDL, C etc)
– Synchronous circuit consisting of combinational logic and registers (DFFs)
allows synthesis of RTL description
• Register Transfer Level (RTL)
– Lower level code describing registers, gates, data paths, operations and clock
cycles - that can be synthesised to form combinational logic blocks, latches etc
• Structural Level (Gates)
– Interconnection of gates
– Functional testing of logic to verify meets behavioural requirement
• Physical Level
– Decomposed into “leaf “ Cells then transistors and interconnects to realise
gates etc.
– Optimised for speed, power consumption and area (Full-Custom) or for
standard cell (Semi-Custom )
– Checked against functional requirement (timing etc) & optimised
 Concepts of Structured Design
• Complex digital designs are broken down into increasingly simple
interconnected modules
– Hierarchical implementation
• Standard modules & rules for interconnection
– Regular placement & routing of transistors / gates / terminals
• Concepts of Hierarchy, Modularity and Regularity are all part of a
Structured design strategy
• Top-down design (HDL)
– Complex systems are decomposed into ever simpler subsystems
down to transistor level
• Bottom-up design
– Transistors grouped into gates, gates to sub-cells then these
into modules, sub-systems and interconnected sub-systems
 How

• Introduction
• CMOS from a device oriented perspective
• Background for VLSI/ULSI: appreciation of device level and higher order issues
leading to an appreciation of bottom-up and top-down design methods
• Recap of MOSFET, then study of simplest CMOS circuit or building-block,
• ie the Inverter (eg for factors effecting speed, power, leakage and noise etc
• Introduction to CAD simulation (SPICE, via Microwind and Dsch)
– Via various design exercises (Custom ASIC leaf-cell evaluation)
• Combinational & Sequential logic & some examples
• Introduction to some more common circuit primitives / leaf-cells
• Introduction to some important aspects of system design and architectures
• Introduction to memory
 In more detail

• Review of CMOS – Enhancement mode MOS & Bi-CMOS

• Ids versus Vds, Zpu/Zpd, Vth, Gm, ω0, SPICE Models, IL, PDiss,
Latch-up, I/O Design
• Layout and Design Rules
• λ based design rules, half-pitch, proximity effects
• Leaf cells, instances and macros
• Combinational Logic Networks and related issues
• Layout, Switching delays and modelling, power, interconnects
• Static Vs Dynamic Vs Pseudo NMOS and Switch based logic
• Sequential Logic
• RAM, ROM, Static, Dynamic, EEPROM, Latches, FFs,
Switching and settling delays, Pipelining, Clocking
 Transistor Size Reduction V’s Time
Plan view of single transistor In the 70’s Gate length was 7.5μm and 1 transistor
Occupied 6000 μm2 with < 10k transistors on a single
IC operating at <0.1MIPS – Intel 4004 CPU by Federico Faggin
(an Italian Physicist)

Note: the 4 processor Cray 2 supercomputer of the mid 80’s

(based on 1um transistors) were about as powerful as a
single processor in an iPad 2 !
By 1995 for the Pentium Gate length had shrunk to
<0.5 μm and associated transistor area was <1% of
that in the 70’s with 10M transistors on a chip and
Operating at 500MIPS

Now the gate length is <20nm with >5B transistors, multiple cores
Pentium 4, Itanium, Xeon (server apps) with 2-4GHz
clock speeds & I/O transfer rates from 10’s GBit/S and
system bus speeds of 400-800MHz

with the chips now dissipating ~150W this is setting a thermal

limit at present ie Numbers of transistors for a given clock
speed – multiple cores, variable clocks and supply rail voltages
to cope with heat generation.

Note: the 2x6 core 2.9GHz Intel Xeon in Mac Pro performs as well as a
Supercomputer from the mid 90’s with a performance of 3.5TFLOP !

Gate Lengths Except now By comparison 1 layer of atoms ~ 0.25nm thick and a 10nm2 area
Now ~10nm Tri-Gates / or finfets
~ a cluster of 160 atoms !
 Intel’s 15nm process
Edge-on view of interconnects and transistors (very bottom layer)

Intel’s 15nm process using

broadwall (or FINFET)
design approach

i.e. folded surface to give more

surface area on the otherwise flat
surface

http://www.synopsys.com/Company/Publications/DWTB/Pages/dwtb-usb-finfet-2014Q3.aspx
 Brief background
• Presently ~ 800M (0.8B) transistors / core and multiple cores / chip
– (Sizes ~ 25mm x 25mm  30-45cm Dia. wafers ! )
• Moores Law (1963 !) ?
– Speed, Complexity & Numbers of transistors / unit area doubles every 1-2
yrs
• Although advances are rapid (RTL, TTL, ECL, NMOS, CMOS, BICMOS,
LDMOS, GaAsFET, FINFET, FD-SOI, Sub-Threshold etc) the underlying
principles remain valid
• Design methodology remains broadly similar
– Logic circuits similar :- Inverter, NOR, NOT etc.
– Functional blocks similar :- Combinational & Sequential etc.
– Structured design :- managed complexity through ever higher
levels of abstraction
• Will study transistors & simple logic circuits to illustrate issues
– eg. Timing, Noise Margins / Immunity, Scaling and Fan-in/out
 Why Digital ?
• Predictable outcome for known inputs
– Reproducibility of results in light of environmental changes
• Tolerence to temperature, rail-voltage variation, component ageing,
etc
• Systematic design approach
– Simple building blocks arranged in ever more complex ways :-
TransistorsGatesBlocksIC’s via systematic approach
– Most important for IC is that its operation is functionally correct then can
try to improve speed and power consumption
• Analogue problem reduced to digital representation
– Well established methods for encoding & manipulation ie ADC, DSP,
Encryption, Error Correction, etc
– Once in digital domain then can take advantages of advances in
technology without reformulation & can embed as part of a much larger
complex system (eg Engine management, ABS, intelligent cruse control &
parking, CAN bus etc)
– Advancing towards AI i.e. chips and programs that can seemingly learn
 Analogue Versus Digital
• Analogue :- Devices and systems use continuous range and variation of
inputs and outputs
– (limited these days mainly to transducers and specialist hardware i.e.
comms front ends and sensors)
• In the real world, so to do digital circuits !
– Analogue input and time broken down into discrete steps (quantised)
– Each step being represented by an N-bit number (integer)
– Number of bits determines accuracy
– Each bit represented by ‘1’ or ‘0’with a “guard-band” between levels leads
to high degree of noise immunity
– Logic Gates and Boolean Algebra allow these bits to be treated in a
systematic way
• In analogue world accuracy & stability of physical quantities &
components difficult to obtain / maintain
– eg manufacturing tolerances, temperature, feedback etc
• If used analogue approach
– Each new problem requires new (possibly unique) implementation which
is hard to design, maintain and validate i.e. not systematic
 Analogue Versus Digital
• Digital Approach
– Harnesses similar building blocks & solutions to previous problems
– ie high levels of repeated identical underlying hardware (devices) only
interconnections, functional blocks etc changed
• At a more philosophical level a mixture of Analogue and Digital
techniques are used to “Model” more complex (even Chaotic) Systems
– At the extreme (very large number of sensitive variables even chaos) then
scale model’s such a wind tunnels and wave tanks still used
– Ever larger data recording and manipulation, leading to simplified but
ever more complex computational model (Digital simulation)
– But important to understand approximations used and constraints which
result from such simplifications
– Analytical Modelling - (small number of complex equations probably with
many variables) versus Finite Difference or Finite Element Modelling
(FEM) – (extremely large number of relatively simple equations)
 Why CMOS ?
• Extremely low static power consumption
• Similar gate transition times (predictability)
– Symmetric switching (high>low, low>high)
• Fully restored logic (clear 1’s and 0’s)
• Straightforward memory and latch elements
– Low off-state leakage currents (DRAM hold times and dissipation)
• Switching voltages are a fraction of supply voltages
– Threshold voltages < supply voltages
• Large noise margins
– Immunity to processing and environmental changes
• Regular layout & smaller device sizes
– Design and implementation is easily automated
• But, bipolar circuits can exhibit
– Faster switching than CMOS & higher current driving capability :- hence
BiCMOS
 Some Important Definitions
• Combinational circuits (no memory!)
– Output depends only on current state of the inputs
– Eg. Simple circuits, such as; Inverter, NOR, NOT etc.

• Sequential circuits (includes memory!)

– Output depends both on the current state of the inputs and the previous
state of the circuit
– ie. The circuit has memory (in the form of delayed feedback)
– Eg. Latches & Flip-flops

• State machines (combinational & sequential ccts)

– Moore: Instantaneous outputs depend ONLY on present state (i.e.
logic and previous inputs delayed by one clock cycle) Safer because
change of state only on clock edge
– Mealy: Instantaneous outputs depend on previous state, as in the
Moore machine, AND by the present inputs (may have fewer states and
consequently faster but can suffer from race problems)
 Design Requirement
• Definitions
– SSI (Small Scale Integration) ~1-20 Gates / Circuit
– MSI (Medium..) ~ 20-200 Gates
– LSI (Large…) ~ 200-200,000 Gates
– VLSI (Very Large..) ~ > 1M Transistors
– Present ULSI, SoC and beyond >1B Transistors / IC
• Increasing density leads to increased speed, functionality and power !
• Complexity (sheer number of gates) forces designer to work at higher
levels of abstraction (hierarchy) using structured approach and dedicated
CAD tools for checking speed and reliability
– Managed systematic data entry & design rule checking (DRC)
– Hardware Description Language (HDL)
• Originally from circuit modelling. Now used to decompose higher
level design into functional modules & associated software (s/w)
– Simulators for logic functionality and timing (s/w & h/w)
• Hardware (h/w) simulators / Real-time :- PLA’s & FPGA’s
 PLA’s & PLD’s
• Programmable Logic Arrays (PLA’s) & Programmable Logic
Devices (Developed in the 1980’s)
– 2 level structure of AND and OR gates
– Logic implemented in form of Sum of Products [(A.B)+(A.C)]
• Issues of scaling for large numbers of gates (fan-in of OR Gate)
• Complex Programmable Logic Devices (CPLD)
– Collection of multiple PE’s (Sea-of-Gates, SoG’s) +
programmable interconnect structure – larger number of
product terms and inputs to fewer more complex logic elements
and registers – tend to be EEPROM based (can be v low power,
instant on)
• Field Programmable Gate Arrays (FPGA’s)
– Similar to CPLD’s but much larger number (100’s k) of
smaller individual blocks (based on LUTs with fewer inputs) +
large distributed interconnect structure – flexible & fast, high
performance - tend to be RAM based (usually needs booting).
 CPLD’s & FPGA’s

• Time to market
– Hardware design to production V. rapid
– Achieved using Systematic, Hierarchical design methods and CAD
tools to automatically compile these designs
– Download to FPGA in minutes
• Time to program each device is a factor for V. large production
runs ie £££ !
– If 30s to programme one ~ 3000 / day! therefore final metal PLA’s
rather than CPLD / FPGA’s
• If circuit optimisation or very high volume is required, then full
custom may be preferred
 Costs
• Non Recurrent Engineering (NRE) costs are highest for Full
Custom Application Specific IC’s (ASIC’s)
– Scales with logic gate number, £100,000-£M’s
– So per-unit saving must be anticipated :- large sales volume (to
amortize cost)
• Individual transistor or gate level optimisation could cost 10 times
above figure ! ( + high risk !!)
– Typically library of standard (optimised) cells used
– Eg. Decoders, Registers, Counters etc.
• For ASIC’s one option is for groups to collaborate to buy wafer
“real estate” by the square mm (~$5k/mm2 for 50nm process)!
• Gate (Semi-custom)arrays and PLD’s have lower NRE costs £5k-
£100k
– Faster design to product
– But, chips can be larger and slower - ie micro cells and layout
not as well optimised as standard cell approach
 Price & Cost Breakdown
• Selling price = Ctotal /1-m
– Ctotal = Cprocess + Cpackage +Ctest
• m = profit margin
• NRE costs
– Design & prototype production costs
• Gate array 9 weeks (1000 gates)-29 weeks (10K gates)
– With modern Logic Synthesis and DRC (CAD) tools this time has
dropped significantly
• Mask costs (£1000+ / plate / reticle), test fixtures £2k-£10k,
package tooling (favours standard packages)
• Recurring costs
– Cprocess = (Wafer + Processing) / NYWYPYFT
• Fixed costs
– Application notes, Failure Analysis, Sales etc
These Design issues and the MOSFET details are well covered in “Principles of CMOS VLSI Design”
by N.H.E. Weste and K. Eshraghian, Pub. Addison-Wesley
 Result

• Disadvantage of Each Approach

– Lack of systematic procedures for optimal decomposition and
implementation (top-down) or grouping and interconnection
(bottom-up)
• Result ?
– Relies on experience
– Both approaches used in-part
• System decomposed into sub-systems which consists of pre-
qualified and optimised primitive modules or leaf cells