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Types of Memory
— ROM: read-only memory
o Non-volatile –mask programmed
— RWM: read-write memory (RAM, random access memory)
o SRAM: static memory
— Data is stored as the state of a bistable circuit
MEMORIES — State is retained without refresh as long as power is supplied
o DRAM: dynamic memory
— Data is stored as a charge on a capacitor
— State leaks away, refresh is required

— NVRWM: non-volatile read-write memory (also called NVRAM,

non-volatile random access memory)
o Flash (EEPROM): ROM at low voltages, writable at high voltages
(Electrically Erasable Programmable Read-Only Memory)
o EPROM: ROM, but erasable with UV light (falling out of common
usage)
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Memory Usage in Computers Memory Hierarchy

— DRAM Memory
o Main memory storage. Used for data and programs

— SRAM Memory
o Faster than DRAM, however, uses more transistors
— Used to be used for external cache
— Variant used in internal cache (on chip cache)

— FLASH Memory and ROM

o Used for BIOS data storage in PCs
o Also used to store pictures, MP3 files for digital cameras and MP3
players –eventually for hard disk

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Memory Circuit Operation

— Memory cells arranged in a — Wordlines(WL):- control row (word) access
rectangular array o Usually control gates of pass transistors
— Rows correspond to data words — Bitlines(BL):- route column data (individual bits)
o Accessed through a row decoder o Bitlines usually precharged high (like dynamic logic)
o Memory cells discharge bitline depending on stored data (bitline left
— Columns to individual bits high if cell stores 1, bitline discharged if cell stores 0)
o Selected through a column mux
o Bitline swings usually small (10s –100s of mV) and must be
amplified by sense amplifiers
— Bit voltage amplified by sense
amplifier — Memory cells store data value
— o Static vs. dynamic, single or multiple bits, etc.

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DRAM DRAM Issues

— Smaller cell size (1 transistor or 1T — Must be periodically refreshed
cell)
o Reads are destructive (modify voltage stored on capacitor)
o Reason for inexpensive memory in o Every read followed by a refresh of the bit (write back of read value)
computers
o Tradeoff of area (memory density) vs. — No static power dissipation
speed and complexity (refreshing)
o Write: CS is charged (or discharged) — Output voltage is charge sharing result of storage capacitor and
by asserting WL and asserting (or bitline capacitance
lowering) BL
o More complex sense amplifiers
o Read: Charge redistribution takes
places between bit line and storage o Higher noise susceptibility
capacitance
𝐶' — Requires different CMOS process than high performance logic
Δ𝑉 = 𝑉!"# − 𝑉$%&
𝐶' + 𝐶!(

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SRAM Cell Full CMOS SRAM Cell

— Cross-coupled inverters: bistable element

— Density is important in memories
o Single NMOS pass transistor used for reading/writing
o Transistor sizes should take up minimum area
— Faster than DRAM since typically fewer cells
— No refresh required (nondestructive reads)
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SRAM Design: Read “0”

— Transistors M3 and M4 are turned on by WL line select
circuitry

— Cc = Vdd to start…capacitance discharges through M1.

— Need to make sure the ratio between M1 and M3 does not allow Q
to go above VTN so that M2 remains off in the read operation
o Otherwise node Q is accidentally discharged
o Conservative since there will also be charge sharing at that node as
well between small internal node capacitance and large bitline
capacitance
— Prior to read operation, voltage at node VQ = 0V and VQ = Vdd,
bit lines are precharged to Vdd — Sense amplifier detects that node Q was a stored 0 due to the
minor drop of voltage on the bitline
o M2 and M5 are off and M1 and M6 are in Linear region

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SRAM Design: Read “0” SRAM Design: Write “0”

— Assume VBL initially remains at VDD: M3 in saturation, M1 in linear
V1,max <= VT,2

— To avoid altering the state of the cell when reading, then

conductance of M1 must be about 3 times that of M3 so that the
drain voltage of M1 does not rise about VTN

kn,3 k
— Assume VQ = VDD and VQ = 0V
2

2
(VDD − VQ − VTN ) = 2n,1 "#2 (VDD − VTN )VQ − VQ2 $%
o M1 and M6 are off and M2 and M5 are in linear
To guarantee VQ < VTN , substitute VQ = VTN in the above equation
— Data must be forced into the cell
( )
W — VQ must fall below the threshold of the NMOS (turns M2 off).
kn,3 L 3 < 2 (VDD −1.5VTN ) VTN
= 2 — This allows VQ to go high enough to go above the VTN of M1
kn,1 ( )
W
L1 (VDD − 2VTN )
o This discharges node Q and stores a 0

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— Write "1" operation: The voltage level of column C’ is forced to logic-

low by the data-write circuitry. The driver transistor MI turns off. The
voltage V1, attains a logic-high level, while V2 goes low.
— The cell must be designed such that the conductance of M3 is
several times larger than that of M5 so that the drain of M1 (VQ) — Read "1" operation: The voltage of column C retains its precharge level
and gate of M2 may be brought below VTN while the voltage of column C’ is pulled down by M2 and M4. The data-
read circuitry detects the small voltage difference (V > Vc’) and amplifies
— At VQ = VTN, M3 – linear M5 - saturation it as a logic "1" data output.

k p,5 2 k — Write "0" operation: The voltage level of column C is forced to logic-
(0 − VDD − VTP ) = n,3 "#2 (VDD − VTN ) VQ − VQ2 $% low by the data-write circuitry. The driver transistor M2 turns off. The
2 2 voltage V2 attains a logic-high level, while V1 goes low.
Re arranging the above equation results in,
— Read "0" operation: The voltage of column C’ retains its precharge level
(W L) 5
<
µ n 2 (VDD −1.5VTN ) VTN while the voltage of column C is pulled down by MI and M3. The data-
2
read circuitry detects the small voltage difference (Vc < Vc’) and
(W L) 3
µp (VDD + VTP ) amplifies it as a logic "0" data output.

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The Ripple-Carry Adder

Adders, Multipliers

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Array Multiplier
— Carry Look Ahead Adder
— Carry-Select Adder
— Carry Save Adder

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— Wallace Tree Multiplier

— Booth Multiplier

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