Assignment 1F VLSI (1)
Uploaded by
Babar AzamAssignment 1F VLSI (1)
Uploaded by
Babar AzamAmerican International University - Bangladesh (AIUB)
Faculty of Engineering
Department of Electrical and Electronic Engineering (EEE)
Course Name: VLSI Circuit Design Course Code: EEE 4217
Semester: Spring 2022-23 Term: Final
Total Marks: 10 Submission Date: 17-04-2023
Faculty Name: Prof. Dr. Engr. Muhibul Haque Bhuyan Assignment #: 01
Course Outcome Mapping with Questions
Obtained
Item COs POIs K P A Marks
Marks
CO4: Apply concepts of different logic families to design a
P1, P3,
Q1 complete complex system within the given specifications P.c.2.C6 K5 20
P7
considering reliability issues.
Total: 20
Student Information:
Student Name: MIM Umma Aysha Section: C
Student ID #: 19-40777-2 Submitted on Department: EEE
Marking Rubrics (to be filled by Faculty):
No
Excellent Proficient Good Acceptable Unacceptable Secured
COs-POIs Response
[10] [8-9] [6-7] [4-5] [1-3] Marks
[0]
All the problems are Most of the problems
All the problems are All the problems are All the problems are
solved correctly. The are not solved
solved correctly. The solved correctly. The not solved correctly.
computing processes correctly. The
computing processes computing processes The computing
are clearly described, computing processes
are clearly described, are not clearly processes are not well
and results are are not well
and results are described, and all described, and all No
CO4 generated by correct described, and most
generated by correct results are not results are not responses
P.c.2.C6 procedures. Most of of the results are not
procedures. All generated by correct generated by correct at all
the necessary generated by correct
necessary procedures. Some procedures. Some
computations are procedures. Most of
computations are necessary necessary
shown with formulas the necessary
shown with computations are not computations are not
but a few are computations are not
formulas. shown with formulas shown with formulas
missing. shown with formulas
Comments Total Marks (10)
Page 1 of 2
1. Assuming that a silicon oxide layer of thickness x is grown by thermal oxidation,
show that the thickness of silicon being consumed is 0.44x. The molecular weight
of Si is 28.9 g/mol, and the density of Si is 2.33 gm/cm3. The corresponding values
for SiO2 are 60.08 g/mol and 2.21 g/cm3.
2. A silicon sample is oxidized in dry O2 at 12000C for one hour.
(a) What is the thickness of the oxide grown?
(b) How much additional time is required to grow 0.1 µm more oxide in wet O2 at
12000C?
3. Find the parameter γ for the photoresists shown in Figure 2.13.
4. Calculate the Al average etch rate and etch rate uniformity on a 200-mm-diameter
silicon wafer, assuming that the etch rates at the center, left, right, top, and bottom
of the wafer are 750, 812, 765, 743, and 798 nm/min, respectively.
5. The electron densities in RIE and HDP systems range between 10 9 –1010 and 1011 –
1012 cm−3, respectively. Assuming that the RIE chamber pressure is 200 mTorr and
HDP chamber pressure is 5 mTorr, calculate the ionization efficiency in RIE
reactors and HDP reactors at room temperature. The ionization efficiency is the
ratio of the electron density to the density of molecules.
6. For a boron diffusion in silicon at 1000 0C, the surface concentration is maintained
at 1019 cm−3 and the diffusion time is 1 h. If the diffusion coefficient of boron at
10000C is 2×1014 cm2/s, find Q(t) and the gradient at x = 0 and at a location where
the dopant concentration reaches 1015 cm−3.
7. Arsenic was pre-deposited by arsine gas, and the resulting total amount of dopant
per unit area was 1×10 14 atoms/cm2. How long would it take to drive the arsenic
into a junction depth of 1 µm? Assume a background doping of CB = 1×1015
atoms/cm3 and a drive-in temperature of 1200◦C. For As diffusion, D0 = 24 cm2/s,
and Ea = 4.08 eV.
8. Assume 100 keV boron implants on a 200 mm silicon wafer at a dose of 5×10 14
ions/cm2. The projected range and projected straggle (p) are 0.31 and 0.07 µm,
respectively. Calculate the peak concentration and the required ion-beam current
for 1 min of implantation.
9. If a 125 mm diameter wafer is exposed for 1 minute to an air stream under a
laminar-flow condition at 30 m/min, how many dust particles will land on the
wafer in a class-10 clean room? For a class-10 clean room, there are 350 particles
(0.5 m or larger) per cubic meter.
10. The killing defect density is responsible for yield loss and depends on the design
rule or size of the device on a chip. This is because when the design rule becomes
smaller, a smaller particle can contribute to yield loss. For a 16M DRAM chip, the
design rule is 0.5 µm, the chip size is 1.4 cm 2, and the killing defect size is 0.18
µm. Due to contamination that occurs in a cleanroom, the wafer defect density
relationship 𝑌 = 𝑒−𝐷𝐴 where D is the defect density and A is the chip area,
measured at size 0.3 µm increases fivefold from 0.2 D/cm2 to 1.0 D/cm2. Using the
calculate the yield loss of a 16M DRAM wafer due to the increase in the defect
density assuming that the defect density is roughly inversely proportional to the
defect size to the second power.
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