2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

VENICE: A Compact Vector Processor for FPGA Applications

Aaron Severance, Guy Lemieux

Department of ECE, UBC
Vancouver, Canada
[email protected], [email protected]

Abstract—VENICE is a new soft vector processor (SVP) for Nios

I$
FPGA applications that is designed for maximum through-

DDR2
Altera Avalon
Fabric
II/f
D$ CPU
put with a small number (1 to 4) of ALUs. By increasing Custom Instruction Port

clockspeed and eliminating bottlenecks in ALU utilization, VENICE Vector Engine

Instruction Queue
VENICE achieves over 2x better performance-per-logic block DMA Address Logic

than VEGAS, the previous best SVP. VENICE is also simpler

to program, as its instructions use standard C pointers into a Align 1
MUL
SHIFT
(2nd
pipe
scratchpad memory rather than vector registers. Scratchpad
Memory
ROTATE stage)
Accum.

2kB - 2MB

Keywords-vector; SIMD; soft processors; scratchpad mem- Align 3 2x clk

Align 2
ALU
EXTEND ABS
ory; FPGA; CMOV

Instead of application-specific accelerators to harness the

parallelism of FPGAs, this work builds a soft vector proces-
sor (SVP), named VENICE, which can be used to accelerate
a wide range of tasks that fit the SIMD programming model. Figure 1. VENICE Architecture (vertical gray bars are pipeline stages)
VENICE is smaller and faster than all previously published


SVPs. Overall, it achieves roughly 2× better performance

! 


 

  

 "

per logic block (speedup per ALM) than the previous best 




SVP, VEGAS [1], and 5.2× better than Altera’s fastest scalar 


processor, the Nios II/f. As a result, less area is needed to 




achieve a fixed level of performance, reducing device cost  




or allowing more room to be left for other application logic. 

Programming VENICE requires little specialized knowl- 







edge, utilizing the C programming langauge with simple ex-







tensions. Changes to algorithms require a simple recompile




!

taking a few seconds rather than several minutes or hours  
! 


 

"

for FPGA synthesis. In particular, the removal of separate
vector address registers from scalar registers, streamlining Figure 2. Speedup (geomean of 9 Benchmarks) vs Area Scaling
of instructions, and support for full speed unaligned oper-
ations make VENICE easier to program than VEGAS. In
addition, a compiler from Microsoft’s Accelerator language formance while using less area than VEGAS. Figure 2
to VENICE C code has been developed [2]. demonstrates this with a speedup versus area plot. The
A block diagram of the VENICE (Vector Extensions to speedup and area axes are normalized to the Nios II/f
NIOS Implemented Compactly and Elegantly) architecture is performance and ALM count. VENICE dominates VEGAS
shown in Figure 1. The VENICE vector engine implements in both area and speed, achieving a maximum speedup of
a wide, double-clocked scratchpad memory which holds all 20.6× Nios II/f at an area overhead of 4.0×.
vector data. Operating concurrently with the vector ALUs R EFERENCES
and the Nios core (to hide latency), a DMA engine transfers
[1] C. H. Chou, A. Severance, A. D. Brant, Z. Liu, S. Sant, and
data between the scratchpad and main memory. There are G. Lemieux. VEGAS: Soft vector processor with scratchpad
a configurable number of vector lanes (32-bit vector ALUs) memory. In FPGA, pages 15–24, 2011.
that provide scalable parallelism. Each 32-bit ALU supports
subword SIMD operations on halfwords or bytes, thus [2] Z. Liu, A. Severance, S. Singh, and G. G. Lemieux. Accelerator
compiler for the venice vector processor. In Proceedings of the
doubling or quadrupling the parallelism available with these ACM/SIGDA international symposium on Field Programmable
smaller data types, respectively. Gate Arrays, FPGA ’12, pages 229–232, New York, NY, USA,
The VENICE processor is designed to offer higher per- 2012. ACM.

978-0-7695-4699-5/12 $26.00 © 2012 Crown Copyright 245

DOI 10.1109/FCCM.2012.55
Authorized licensed use limited to: AMITY University. Downloaded on September 09,2023 at 04:54:10 UTC from IEEE Xplore. Restrictions apply.