Reg. No.

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Question Paper Code : 21172

B.E. / B.TECH. DEGREE EXAMINATIONS, MAY / JUNE 2024
Second Semester
Artificial Intelligence and Data Science
23AD201 – DIGITAL LOGIC DESIGN
(Regulations: Mepco – R2023)
Duration: 3 Hours Max. : 100 Marks
Answer ALL Questions
PART A – (10  2 = 20 Marks)
BTL, CO

A,CO1 1. The Simplified SOP form of the given Boolean expression.

(P  Q  R).(P  Q  R).(P  Q  R) is __________. Justify your answer.

A) (P.Q  R) .  R)
B) (P  Q.R) C) (P.Q  R) D) (PQ
A,CO1 2. Realize AB using NAND gate.
R,CO2 3. In half adder, the total number of inputs and outputs are __________. Justify your
answer.
A) 1,2 B) 2,1 C) 3,2 D) 2,2
U,CO2 4. Determine the minterms for the given logic shown below which indicates the
implementation of a Boolean logic using 4 x 1 MUX.

A) Σm(1,3,5,6) B) Σm(0,2,4,7) C) Σm(0,2,3,4,5) D) Σm(0,1,2,5,6)

R,CO3 5. Classify the memories.
R,CO3 6. List the different types of programmable logic devices.
A,CO4 7. The minimum number of JK FFs required to construct a synchronous counter with
count sequence is (0,0,1,1,2,2,3,3,0,0…) is ___________. Justify your answer.

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A,CO4 8. The initial content of the 4-bit serial in parallel out (SIPO) shift register shown in
figure is 1000. The content of the shift register after 3 clock pulses is ____________.
Justify your answer.

A,CO5 9. Realize the switching function f(A,B,C) = ∑m(2,4,5,6) by a hazard free logic gate
network.
U,CO5 10. Compare critical and non-critical races in asynchronous circuits.

PART B – (4  15 = 60 Marks)
A,CO1 11. a) i. Simplify the Boolean function using K-Map and implement the
minimal expression using universal logical gates.
f = ∑m(0,2,4,6,7,8,10,12,13,15) (10 Marks)
A,CO1 11. a) ii. Draw a NOR logic diagram that implements the complement of the
following function:
F(A, B, C, D) =  (0, 1, 2 , 3, 6, 10, 11, 14) (5 Marks)
OR
A,CO1 11. b) i. Using the tabular reduction method, minimize the given combinational
function f(w,x,y,z) = ∑m(1,3,4,5,9,10,11)+ ∑d(6,8). (10 Marks)
A,CO1 11. b) ii. Realize the following Boolean expression using NAND gates:
Y = (A+C) (A+D’) (A+B+C’) (5 Marks)

A,CO2 12. a) i. Realize the following logic expression using a 4:1 MUX:
F(A,B,C,D) = ∑m(1,3,4,11,12,13,15) (8 Marks)
A,CO2 12 a) ii. Write HDL code for an full adder circuit. (7 Marks)
OR
A,CO2 12. b) i. Design an octal to binary encoder circuit using logic gates. (8 Marks)
A,CO2 12. b) ii. Design a full subtractor using logic gates. (7 Marks)

A,CO3 13. a) Implement the following Boolean expressions using a suitable PLA:
A (x,y,z) = ∑ m (1,2,3,4)
B (x,y,z) = ∑ m (0,1,5,7)
C (x,y,z) = ∑ m (2,6)
D (x,y,z) = ∑ m (1,2,3,5,7) (15 Marks)
OR
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A,CO3 13. b) Implement the following Boolean functions using a suitable PAL:
w(A, B, C, D) = ∑(2, 11, 13)
x(A, B, C, D) = ∑(8, 9, 10, 11, 12, 13, 14, 15)
y(A, B, C, D) = ∑(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 12,15)
z(A, B, C, D) = ∑(1, 2, 8, 12, 13) (15 Marks)

A,CO4 14. a) Design a 3-bit synchronous Up-Down counter and implement the
circuit using JK Flip-flops. (15 Marks)
OR
A,CO4 14. b) A clocked sequential circuit is provided with a single input x and
single output z. Whenever the input produces a string of pulses 111 or
000, the circuit should produce an output z = 1. (Overlapping is
allowed)
A) Obtain the state diagram
B) Obtain the state table
C) Design the sequence detector using D Flip Flop. (15 Marks)

PART C – (1  20 = 20 Marks)
A,CO5 15. a) i. An asynchronous sequential circuit is described by the following
excitation and output function:
Y = x1x2 + (x1+x2)y
Z=y
A) Draw the logic diagram of the circuit.
B) Derive the transition table and output map.
C) Describe the behavior of the circuit. (12 Marks)
U,CO5 15. a) ii. Analyze the hazards in asynchronous sequential circuits and suggest
steps to avoid the hazards. (8 Marks)
OR
A,CO5 15. b) i. Design an asynchronous sequential circuit with two inputs x1 and x2
and one output Z. Initially both the inputs are equal to zero. When x1
or x2 becomes 1, the output Z becomes 1. When the second input also
becomes 1 the output changes to 0. The output stays at 0 until the
circuit goes back to initial state. (12 Marks)
U,CO5 15. b) ii. Analyze the effect of races in asynchronous sequential circuit design. (8 Marks)

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