SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

Multiplier Design Incorporating Logarithmic

Number System for Residue Number System
in Binary Logic
Shalini R. V#1, Dr. P. Sampath*2
#
Research Scholar & ECE & Bannari Amman Institute of Technology, Sathyamangalam
Tamil Nadu, India
*Professor & ECE & Bannari Amman Institute of Technology, Sathyamangalam
Tamil Nadu, India

Abstract
Residue Number System (RNS) incorporates DSP applications generally deal with consecutive
several significant features that are indispensible in multiplication and addition operations, therefore
Digital Signal Processing (DSP) applications. It designing with reduced computational complexity is
includes higher operational speed, secured processing essential. Introducing LNS into RNS proves to
of data, carry free operations that reduces produce more compressed architectures compared to
propagation of error among modules and so on. those designs including RNS features alone [11-13].
Multiplication process is the vital part of several DSP The combination of these unusual number systems is
functions and hence design of such process using RNS proposed by Arnold [14] represented as Residue
system is gaining potential. For further improving the Logarithmic Number System (RLNS). As addition
processing speed and security level of RNS, and subtraction in LNS are difficult compared to
Multilevel-Residue Number System (MRNS) is multiplication and division operation, more research
introduced. This paper deals about the works are published for the efficient design of the
implementation of Logarithmic Number System (LNS) former [15].
in RNS to propose the multiplication design based on The literature survey depicts the use of RLNS
Residue Logarithmic Number System (RLNS). technique with the operands of format bq [16, 17],
Multilevel-Residue Number System (M-RNS) is where b and q are integers >1. But for the operands
incorporated in this research work introducing which are not in exact power of logarithmic base (b),
Multilevel-Residue Logarithmic Number System (M- the multiplier design becomes complex and produces
RLNS) based multiplier design. Use of logarithmic inaccurate results. It is due to logarithmic and
numbers are restricted on accuracy constraints, hence antilogarithmic approximations made during the
improvement in accuracy is realized by employing corresponding conversion process [18]. LNS is
error correction circuits. Area, Total Power avoided due to this accuracy constraint, though it can
Dissipation (TPD), delay and Power Delay Product provide promising results in terms of hardware
(PDP) of the multiplication design proposed are utilization and power dissipation values [11]. In this
tabulated for number of bits, N=8, 16 and 32 and the paper the multiplication process with Residue
same is compared with the existing design. Logarithmic Number System (RLNS) technique is
implemented for all numbers with no consideration
Keywords - Residue Number System (RNS), about the number format mentioned above.
Logarithmic Number System (LNS), Multilevel-
Residue Number System (M-RNS), Multilevel-Residue II. MATHEMATICAL OPERATION OF RNS
Logarithmic Number System (M-RLNS), Error AND LNS
correction circuits.
The three major processes involved in RNS are
I. INTRODUCTION forward conversion, residue arithmetic unit and
reverse conversion. In forward conversion process the
RNS involves in reducing the longer length input input operand is converted into its corresponding
operands to shorter length modulo values. This helps residues. The integer number representation based on
in producing high speed processing aspect in the RNS is defined by a set of „Q‟ relatively prime
system where it is involved. Thus the scope of RNS is integers or moduli set given by
widened for filter design [1-4], cryptography [5-7] and
 m , m    , m  . The suffix variable „L‟
1L 2L QL
several Digital Image Processing applications [8-10].
RNS involves in converting the binary weighted value denotes the type of logic used in the RNS processing
into its residues and vice versa with the predefined which is represented as „b‟ or „t‟ for binary or ternary
moduli set. Therefore the intermediate residue values logic based circuits. Relatively prime integers taken as
obtained cannot be processed further without knowing moduli set values is given by, gcd (miL, mjL) = 1 for i ≠
the exact moduli set values. j. The weighted input operand is denoted as,

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

X L
 x 1L
, x2 L , , xQL  where the value of xiL is In this work, analysis of only positive
input operands is considered and the value of „s‟ is
calculated by the expression, always „0‟. The multiplication and division operations
x iL  X m o d m iL  X 0  x iL  m iL using LNS on the operands say A and B is given by
L m iL (1)
the following logarithmic rules,
The residue computation is limited for
any integer XL, given the range  0 , M  , where M is lo g L A B   lo g L A  lo g L B
L L
(5)
the dynamic range given
as M  m 1 L  m 2 L   ..  m Q L . The arithmetic lo g L A / B   lo g L A – lo g L B
L
(6)
operations such as addition, subtraction,
multiplication, division, exponentiation and squaring III. THE PROPOSED MULTIPLIER DESIGN
values can be computed by RNS in parallel channels FOR RLNS BASED SYSTEM
[1]. The carry free propagation across the channels The algorithm of RLNS based
accounts for high speed computation in RNS. Let multiplication is as follows. Let the weighted input
T L denotes the required computation to be carried operands be represented as A and B . The b b

out, then T  X  Y , where ◦ may be any of the

L L L
multiplication proposed for RLNS based design using
operations mentioned above. Thus the corresponding binary logic for input operands with number of bits,
residues of the final result can be represented as N = 8, 16 and 32 produces the output with number of
b

bits, 16, 32 and 64 respectively. The block diagram of

the proposed Nb bit multiplication process for RLNS
t 1L
, t 2 L ,  ., t Q L  
based is shown in Fig. 1.
x 1L
 y1 L
m1 L
, x2L  y2L
m2 L
, x3L  y3L
m3 L
, ..., x Q L  y Q L
mQ L  Ab Bb

(2) N b bits N b bits

logarithmic logarithmic
conversion conversion
process process
The value t iL is calculated from x iL and
Acb .Amn b Bcb .Bmn b
y iL in a modulo channel with the corresponding
Acb Amn b Bcb Bmn b
modulus value given by m , i = 1,2,…..,Q. The iL Bcb mod m ib
Acb mod m ib B-LEC B-LEC
residue values of a specific operation has to be
converted back to its corresponding weighted number. Ac1b , Ac2b Acmn b Bc1b , Bc2b Bcmn b

This process is done by the reverse conversion

method. The algorithm for the reverse conversion
process is primarily based on the Chinese Remainder Ac1b .Acmn b Ac2b .Acmn b Bc1b .Bcmn b Bc2b .Bcmn b

Theorem (CRT) [19-21], Mixed Radix Conversion

(MRC) [21] and New Chinese Remainder Theorem
(New CRT) [22]. In this research work smaller moduli cmn b
t1b .cmn b t2b .cmn b
set values are chosen, hence CRT is more suitable 10 bits

compared with other reverse conversion processes. t1b and t2b

B-ALEC
LSBs '0'
mn b
CRT

The logarithmic value of an integer „a‟ is 2N b bit logarithmic

Tb shifter
given as,
Final

a     s , lo g L a 
LNS
multiplication
(3) result ( Z b )

Fig 1: Binary logic based multiplication process for

Where „s‟ denotes the sign of „a‟ and „L‟ represents RLNS based system
the logarithmic base value that can be „2‟ (binary
logic) or „3‟(ternary logic) based on the logic used. A. First step of RLNS
The first step of the proposed technique
involves in the logarithmic conversion of the input
operands A and B producing the corresponding
b b

characteristics ( A cb and B cb ) and mantissa values

(4) ( A m n and B m n ) respectively. Logarithmic
b b

conversion process is accomplished by the Leading

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

One Detector circuit (LOD), N b  lo g 2 N b bit MOS ±1, ±2…….; k = 0, ±1, ±2… and k ≥ j. B can be
represented as,
ROM structure and N bit logarithmic shifter [23]. k


b

i
B 2 z ib
The logarithmic conversion of the input operand is i 1
(7)
shown in Fig. 2.

Ab or Bb zib is either „0‟ or „1‟ as the design is based on binary

N b bit input logic. Let zkb denote the Most Significant Bit (MSB)
and is assumed as zkb = 1. If 2k is factored out as per
N b bit LOD circuit
Mitchells approximation, the value of B becomes,
N b bits
k 1
k  

i k
N b -word * log 2 N b bit MOS B  2 1  2 z ib 
ROM  i 1 
(8)

k
log 2 N b bits

i k
N b bit Logarithmic shifter Let the term B  2 z ib is < 1 be the mantissa part
i 1
control
word Amn b or
Bmn b represented as „m‟, then the equation (8) becomes,
B-LEC

B  2 (1  m ) (9)
k
Acmn b or
Acb or Bcb
Bcmn b

Characteristic
mantissa part
part
log 2 N b bits (10 bits)
The actual value of binary logarithm is given as,

lo g 2 B  k  lo g 2  1  m  (10)
Fig 2 : Logarithmic conversion process

The mantissa value is obtained from the Mitchell approximation for the logarithmic value of B
Nb bit logarithmic shifter. The mantissa values can be is represented as  lo g 
2
B and is given by,
approximated using several error correction
techniques. The existing research works for reducing
the error value can be summarized as LUT based 
approach [24, 25], improving the accuracy of  lo g 2
B  k  m (11)
Mitchell‟s approach using correction term based [18],
Linear Approximation [26-29] etc. LUT based error The error value (E) in the approximation
correction method involves in storage of data which procedure followed by Mitchell is calculated from the
expands with the increase in number of bits of input equation given below,
operands [30-32]. As linear approximation provides
reduced hardware implementation compared with

LUT based approach, this method is used in this E  lo g 2 B   lo g 2 B  (12)
research work to reduce error value. Dividing the
mantissa interval, m (0 ≤ m < 1) to 2, 4 or more
improves the accuracy of the logarithmic value [26,  lo g 2 (1  m ) -  m  (13)
29]. In this research work, the mantissa region is
divided into eight equal intervals where each interval
is estimated by a straight-line equation y=ajx + bj, The proposed error correction procedure
where „j‟= 1 to 8, a and b are constant values chosen following linear approximation technique is explained
randomly based on several trial and error method. as follows.

The procedure explaining the The equations of the resulting piecewise

logarithmic error correction for the mantissa values linear approximations for lo g  1  m  are given 2

( A m n and B m n ) is explained as follows.

b b
below, where „cm‟ denotes the corrected value and „m‟
represents the actual mantissa input.
1. Binary – logarithmic error correction (B-LEC)
circuit 13 1
The procedure of logarithmic conversion is initially cm  m  m , fo r 0  m  (14)
32 8
proposed by Mitchell Jr 1962. Let B be the binary
k 1 j
number in the interval 2  B  2 , where j = 0,

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

23 1 1 The input mantissa bit is taken as

cm  m  m , fo r  m  (15)
64 8 4 mj with the corresponding output value as c m ,  j

where the value of „j‟ ranges from 1 to 10 representing

73 1 3
the 10 bits of result of the correction circuit (B-LEC).
cm  m  , fo r  m  (16) The corrected logarithmic value obtained is used for
1024 4 8
the proposed multiplication.

43 3 1
cm  m  , fo r  m  (17)
512 8 2

1 3 1 5
cm  m  m  , fo r  m 
7 M SB
8 128 2 8

(18)

1 15 5 6
cm  m  m  , fo r  m 
7 M SB
8 512 8 8

(19)

17 6 7
cm  m  m
5 M SB
, fo r  m  (20) Fig 3: Binary-Logarithmic Error Correction (B-LEC)
64 8 8 circuit

s1 s2
5 7
cm  m  m , fo r  m 1 (21) a 0 m -1m -2
5 M SB 0
32 8 b 1 c 1
m -3
m -1
m -2

The expansion of the coefficient values are given 0

output
1
below,
d 0
e 1
13 -2 -3 -5 23 2 4 5 6
 2  2  2 ;  2  2  2  2 ;
32 64
Fig 4 : Block A
73 4 7 10 43 4 6 8 9
 2 2 2 ;  2  2  2  2 ;
1024 512 m -1m -2
3 6 8 15 6 7 8 9
 2  2  2  2  2  2 ;
128 512 a 0
b m -1 m -2
1
17 2 6 5 3 5
 2  2 ;  2  2 ;
64 32 0
output
c 1

paragraphs The value of m 7 M S B and m 5 M S B denote

Fig 5 : Block B
the inversion of first 7 and 5 Most Significant Bits
(MSBs) of the mantissa part respectively. The error s2
correction circuit proposed uses 10 MSBs of the s1 m -1m -2
0
mantissa part and produces 10 bit result. The proposed a 1
Binary- Logarithmic Error Correction (B-LEC) is
shown in Fig. (3 – 6). Sequence of Full Adder (FA)
m -3
m -1
m -2

0
output
and Half Adder (HA) circuits are used in the error 1

correction circuit. The carry value generated at each b 0

adder is propagated to the consecutive adder from the c 1
LSB of the mantissa value (m-10). The carry value
from the most significant mantissa bit value (m-1) is
neglected, as it is always „0‟. Fig 6 : Block C

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

The corrected mantissa values evaluated from the The added operands are represented as
proposed B-LEC circuit (cm) are denoted as t 1 b .c m n b and in equations (24) and (25), where
t 2 b .cm n b
A c m n and B c m n respectively in Fig. 1.
b b t is the characteristic part and
ib
cm nb the added
mantissa value.
After the logarithmic conversion, the
steps of typical RNS processing are followed. Based C. THIRD STEP OF RLNS
on the application of the multiplier design for a RLNS The third step includes the reverse
based system the moduli set values are selected. The conversion and antilogarithmic conversion. The result
dynamic range provided by the moduli set values of reverse conversion is given as the control input to
chosen must cover the possible output values of the the antilogarithmic conversion.
multiplication operation. The moduli set values chosen The entire process of RLNS is carried
for the proposed binary logic based RLNS design is out using small range of logarithmic values and hence
{ 2 b - 1, 2 b  1} . Substituting N = 3 the values of the
N N
b the reverse conversion operation is done by Chinese
moduli set is given by, {m1b, m2b} = {7, 9}. The Remainder Theorem (CRT). CRT method of reverse
dynamic range value provided by these values is given conversion process is explained using the following
by [0, 2  1 ], where M  7  9  6 3 . This moduli set
Mb
b
equations.
values cover the multiplication result for input
operands with bit length, Nb = 8, 16 and 32. Q

Tb   t i b  N ib M ib
(26)
i 1 m ib
M
b

In forward conversion process, the

characteristic values A c and B c are converted into
b b
M

b
its corresponding residues with respect to the moduli M ib
(27)
m ib
set {7, 9} by direct conversion method [33, 34] and is
given by,
N ib  M
-1
ib
m
(28)
ib
A c ib  A c b m o d m ib (22)

Tb is the reverse conversion result

B c ib  B c b m o d m ib (23) calculated from the residue values t1b and t2b obtained
from equations (18) and (19). Nib is the multiplicative
Two moduli values are taken for the process therefore inverse of Mib modulus mib. The dynamic range Mb is
„i‟ takes the value of 1 and 2 respectively. calculated from the equation given below,

B. Second step of RLNS M b

  m ib (29)
i  1
As multiplication operation is the idea of
research, the residues are calculated based on the
logarithmic rule in equation (5). The residue Where i = 1,2,...,Q denotes the number of moduli set
arithmetic unit is the second step of RLNS processing. values chosen. From the moduli set values chosen, the
The addition operation on the residues along with the constant values M , N , N , M and M areb 1b 2b 1b 2b
corrected mantissa part is performed by ripple carry calculated as per the equations (20) – (23) and are
addition, where „+‟ in Fig. 1 denotes the addition 6310, 410, 410, 910 and 710 respectively.
operation. As area and power efficient design is the
main aim of this research work, ripple carry addition
method is used. The modulo operation on the added Antilogarithmic conversion includes the
result is given by the equations (24) and (25). antilogarithmic error correction circuit and the
t .c m n  A c . A c m n  B c . B c m n (24) logarithmic shifter. Several works are reported in
1b b 1b b 1b b m
1b literature to design antilogarithmic converters with or
without using ROM, LUT etc., [34 and 35]. Limiting
t 2 b .c m n b  A c2b .A cm nb  B c .B c m n b (25) the deviations of the result from the actual
2b m
2b antilogarithmic curve by linear approximations, the
proposed method using 12 MSBs of the mantissa part
shows considerable increase in the accuracy of the
The bracket represents the modulo operation final antilogarithmic value when compared with the
performed with the corresponding modulo value existing work [34]. In the proposed error correction
method, improvement is made in the piecewise linear
approximation procedure by designing 8-region
correction circuit using 10 MSBs of the mantissa part.

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

The added mantissa value (cmnb) is corrected by the  29 4 5

2   m   2  2  2  m  (39)
m -7 -8 -1 0
, fo r
error correction procedures proposed and is denoted as 32 8 8
mnb in Fig. 1.

 29 5 6
2   m   2  2  2  m  (40)
m -6 -9 -1 0
1.Binary-antilogarithmic error correction (B-ALEC) , fo r
32 8 8
circuit
Let the characteristic part of the
logarithmic value be „k‟ and the mantissa part be „m‟.  15 6 7
2   m   2  2  m  (41)
m -8 -1 0
The improvement of antilogarithmic approximation is , fo r
16 8 8
as follows [18],
Let A   lo g B   k  m (30)

2
15 7
2   m   2  2  2  2  2  m 1
m -6 -7 -8 -9 -1 0
, fo r
16 8
The antilogarithm of A is given as, (42)

a n ti lo g 2 A  2 The expansion of the coefficient values used are given

A

(31)
as,
7 1 2 3 15 -1 -2 -3 4
A k m k m  2  2  2 ;  2  2  2  2 ;
2  2  2 .2 8 16
(32)
29 1 2 3 5
 2  2  2  2 ;
The antilogarithmic approximation is given as, 32
51 -4 -5 -8 9 7 -8 -9 -1 0
 2  2  2  2 ;  2  2  2
512 1024
( a n ti lo g 2 A ) '  2 1  m 
k
(33)

The block diagram of B-ALEC proposed

The error value (E) due to the above approximation is, is shown in Fig. 7, 8. 10 MSBs denoted by m , are i

input to B-ALEC where i ranges from 1 to 10. B-LEC

E  2 2 - 1  m   (34)
k m

  
produces 11 bit approximated mantissa value  2  as
m

output denoted by „cm-j‟, where „j‟ ranges from 0 to

The proposed 8-region antilogarithmic 10. 11 bit output is thus obtained by keeping the MSB
approximation equations with the approximated value of the output as „1‟ as shown in Fig. 7 and the circuit

denoted as  2  are given below, diagram of block D used in B-ALEC circuit is shown
m

in Fig. 8.


2  
m

7 51 1
m  ( c1  c 2  c 3 )  ( c 1)  (c 2) (35)
8 512 128
1 7 1
 (c3)  ( c 4 ) , fo r 0  m 
64 1024 8

 15
2   m   2  2  2  2
m -6 -8 -9 -1 0
,
16
(36)
1 1
fo r  m 
8 4

 29 1 3
2   m   2  2 , fo r  m  (37)
m -6 -7

32 4 8

 29 3 4
2   m   2  2 , fo r  m  (38)
m -7 -9
Fig 7 : Binary-Antilogarithmic Error Correction (B-
32 8 8
ALEC) circuit

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

m -1 m -2
Thus the corrected mantissa part
m -3
obtained from the proposed
a 0
B-ALEC circuit, denoted as mnb in Fig. 1 is given as
0 input to the 2Nb bit logarithmic shifter [34] of the
b 1 output
0
antilogarithmic conversion. The antilogarithmic
1
conversion process is shown in Fig. 10.

Fig 8 : Block D of B-ALEC circuit

Final sum mantissa value
(cmn b )

10 MSBs

Additional condition variables c1, c2, c3, c4 and c5 are

B-ALEC
used for the error correction given by equation (29),
for the mantissa part in the interval 0 ≤ m <0.125. At mn b 11 bits remaining
LSBs '0'

this region of mantissa part, the value of 1‟s that occur

in the positions from m to m are taken for the error
4 10 T(0-5) b
2N b -bit logarithmic shifter

correction process as shown in equation (29). For the control

linear approximation in the region 0 ≤ m <0.125, the input

value of „1‟ present from the positions m  4 to m  1 0 are

2N b -bit

result

detected using LOD circuit. Based on the leading

position the corresponding output a m , where ‘j‟  j Fig 10 : Antilogarithmic conversion process
ranges from 4 to 10 are obtained as shown in Fig. 9.
The logarithmic shifter provides the shifted result
m -4 c5

based on the value of the control word, „ T „

m -5 c5 m -6 c5 m -10 c5

calculated by the equation (20). As the reverse

conversion result is the output modulo 63, the
Vdd
................
maximum bit length is 6 as shown in Fig. 10. The
0 0 ................ 0
control input decides the number of shifts required to
1 1 1
get the final multiplication result denoted as „ Z „, in b
MUX MUX MUX

Fig. 1.

................ IV. PROPOSED BINARY LOGIC

MULTIPLICATION PROCESS USING MRNS
CONCEPT IN RLNS DESIGN
am -4 am -5 am -6 am -10

To improve the data encryption feature of the

Fig 9 : Altered mantissa value (am-j) proposed RLNS based multiplication structure, MRNS
concept is incorporated proposing a new idea of
Based on several trial and error method Multi-level Residue Logarithmic Number System
for the input operands in this interval, the conditional (MRLNS). The feature of MRNS include choosing
variables c1, c2, c3 and c4 are realized using equations moduli set values at different levels of RNS until the
(37) - (41). These equations are used to add the residue values becomes simple. The condition in
corresponding constant coefficients with the MRNS technique is to check the dynamic range of the
approximated mantissa value given in equation (36) to moduli set values. The dynamic range in 1st level
get corrected output in this region. should be greater or equal to that of the next level
[36,37], and the process is continued further until
lower values of moduli set is achieved. Reducing the
c1   am  4
  am  5
  am  6
  am  7
(43) moduli values further reduces the complexity of the
conversion circuits and its operations [36, 38].
In MRLNS based multiplier design, two
c2   am 
5
  am  7
(44) level RNS is considered. As the characteristic values
of smaller range are involved in RLNS, simple values
of residues are obtained in the second level of
c3   am 
6
  am 7
(45)
MRLNS technique. In the proposed design of
MRLNS, the moduli set chosen for the first level is
c4   am    am    am  (46) given as  m , m  = {7, 9}, substituting N = 3 in
1 Ab 2 Ab b
8 9 10

the set  2 Nb
 1, 2
Nb
 1 . This moduli set provides the
63
c 5  m 1  m 2  m 3 (47) dynamic range, [0, 2 -1], enabling the comparison of

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

MRLNS design with the proposed single level RLNS to the moduli set {7, 9}. This residue values obtained
scheme in terms of dynamic range. The second level are denoted as a and b in Fig. 11, where „i‟ takes
ib ib

of the moduli set chosen is  m , m  1Bb 2 Bb the value of 1 and 2, as the number of moduli chosen
= 2
Nb
, 2
Nb
 1 , given Nb = 2 the values are {4, 5}, is 2. The variables c , d , e and f represent the
ib ib ib ib

which is lesser than the previous moduli set values. second four set of residue values obtained for the
The reverse conversion is carried out in the reversed moduli set {4, 5} from a and b respectively. As ib ib

order of moduli set values chosen i.e., first and the the number of second set moduli values are also 2, „i‟
second level reverse conversion process use second takes the value of 1 and 2 in the second level also. As
and the first level moduli set values respectively. the required arithmetic process is multiplication, the
Therefore the first level moduli set values decides the logarithmic values are added using the equations
dynamic range of the multiplier design. The below, to give final two set of residues.
multiplication process using MRLNS is shown in Fig.
11.
u ib  c ib  e ib  C b (48)
m iB b

The binary input operands X b

and
v ib  d ib  f ib  C b (49)
Yb with N number of bits are initially converted into
b
m iB b

its logarithmic format with its characteristic part

X c and Y c and its mantissa m n 1 and m n 2
b b b b Cb is the carry value obtained from the addition of the
respectively. The error value of the mantissa m n1 b and mantissa values c m n 1 b and cm n 2 b respectively. The
mn2b is corrected by the error correction circuit (B- set of residue values u and v are given as input to
ib ib

LEC), that gives the results the first level of reverse conversion. The reverse
c m n 1 and c m n 2 respectively. The corrected mantissa
b b conversion process is done using CRT method, to
values are added to give c m n which along with the differentiate for each level it is taken as CRT B in first
b
level and CRT A for the second level, as shown in Fig.
residue values are taken for the antilogarithmic
6. The corresponding dynamic range, moduli values
conversion process.
and the variables N1, N2, M1 and M2 that are required
according to the CRT method are calculated. At each
Xb Yb
level of reverse conversion the corresponding
logarithmic conversion
variables calculated are represented with suffix B and
logarithmic conversion
A respectively based on the moduli set values utilized
Xcb , Xmn b Ycb , Ymn b at each level. The use of lower case suffix „b‟ denotes
Ymn b

B-LEC
Xmn b Xcb Ycb
B-LEC
the binary logic. The operation to calculate the values
<Xcb >7,9 <Ycb >7,9

Xcmn b Ycmn b w 1 b and w 2 b denoted as CRT B blocks in Fig. 11 is

a 1b a 2b b 1b b 2b
given below,
<a 1b >4,5 <a 2b >4,5 <b 1b >4,5 <b 2b >4,5

( u 1b  N 1 B b  M ) 
c1b c2b d 1b d2b e1b e 2b f1b f2b
m 1Bb 1Bb

w1b  (50)
Cb ( u 2b  N 2 Bb  M )
Cb Xcmn b Ycmn b m 2 Bb 2 Bb

M Bb
cmn b
u 1b u2b v1b v2b

B-ALEC ( v1b  N 1 B b  M ) 
CRT B CRT B m 1Bb 1Bb

<w1b >7 <w2b >9 mn b

w 2b  (51)
( v 2b  N 2 Bb  M
t1b t2b
)
m 2 Bb 2 Bb

CRT A
LSBs '0' M Bb

2N b bit logarithmic
Tb shifter
M value used in the equations (51 and 52) denote
Bb

Final
multiplication the dynamic range provided by the second level
result ( Zb )
moduli set, {4, 5}. The value of M , is calculated Bb

from the product of 4 and 5, M = 20. The values

Fig 11 :Multiplication process using Multi-level Residue Bb

Logarithmic Number System (MRLNS) technique and M

N iB b are calculated from {4, 5} using
iB b

During the first level of equations (12 -14) and the calculated values are
MRLNS the characteristic part of the operands are N1Bb
1 , N  4 , M
2 Bb
 5 and M  4 . From
1Bb 2 Bb

converted into its corresponding residues with respect the values of w ib , the second set of residues, t ib is

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

calculated from the modulo operation done by the logarithmic shifter.‟ T „ controls the shifting
b

values { m , m 1 Ab
} = {7, 9} using the equations
2 Ab operation of the given mantissa input in the shifter
(52) and (53). providing 2 N bit final multiplication result
b

represented as „ Z „.
b

t1 b  w1b (52)
m1 Ab
V. SIMULATION RESULTS OBTAINED FOR
t2b  w2b (53) THE PROPOSED DESIGN AND ITS
m 2 Ab COMPARISON WITH THE EXISTING
TECHNIQUES
The calculated values of t1b and t2b are
given as input to the second level of reverse Simulation of the circuits are made using
conversion (CRT A). The reverse conversion result, Cadence tool, Virtuoso 6.1.5 with 45nm TSMC
T is taken as output modulo of M = 63 in this level CMOS technology and supply voltage of 0.5 V. For
b Ab
logic states of „1‟ and „0‟, 0.5 V and 0 V are used
(CRT A block) as shown in Fig. 11. The
respectively. The design of the proposed and existing
corresponding reverse conversion operation is as
research works are made for Nb = 8, 16 and 32 and the
follows,
simulation results are compared. The area occupied,
Total Power Dissipation (TDP) value, delay and PDP
( t1 b  N 1 A b  M )  values of the proposed multiplication structure (RLNS
m 1 Ab 1 Ab

Tb  (54) and MRLNS) are compared with the existing work

( t2 b  N 2 Ab  M ) [40] in Table 1. To prove the efficiency of the
m 2 Ab 2 Ab

M Ab
proposed design for a RLNS based system, the
existing work of modulo multiplier design using
Radix-8 booth encoding technique for a RNS based
This „ Tb „ value along with the added system is designed with the same TSMC 45nm
mantissa part „ c m n „ is input for the antilogarithmic
b
technology file using Cadence tool.
conversion process. The mantissa part „ c m n „ is b

corrected by the proposed Binary- Antilogarithmic The simulation results including area,
Error Correction Circuits (B-ALEC) and is denoted as TPD, delay and PDP of the existing work are given in
Table 1.
„ m n „ in Fig. 11. „mnb‟ is given as input to the 2 N bit
b b

Table 1 Comparison of Area, Power and Delay values

Multiplication structure Area (µm2) Total Power Delay Power Delay

Dissipation (ns) Product
Technique used Number of (TPD) (µW) (PDP)
bits, N (Joules)
8 41094 2.918 78 227.6
RLNS 16 49545 4.033 142 572.68
32 60364 5.169 281 1452.48
8 47702 3.228 89 287.2
MRLNS 16 52121 4.271 194 828.57
32 66597 5.817 310 1803.27
Radix-8 booth 8 117676 15.97 130 2076.1
encoding technique 16 164997 32.15
[40] 340 10931
32 215781 53.25 567 30192.75

It is inferred from the values, the multiplication structure using MRLNS technique is
proposed multiplication design provide efficient 15% more compared to that of RLNS technique due to
results in terms of area, TPD, delay and PDP values. the additional forward and reverse conversion
The area occupied, TPD and delay values of operations carried out in two levels. The percentage of

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

parameter values saved by the proposed techniques it is 0.77. The Error Percentage (EP) calculated for the
compared to the existing work is given in Table 2. input operands includes both positive and negative
From the percentage values it is inferred that 67.3% of error value. The value of EP is as obtained without
area and 45% delay are saved whereas TPD and PDP considering the positive and negative range of the
are 86% and 92% less compared to that of existing error value produced.
work.
Table 3 Comparison of Average Error Percent (AEP)
Table 2 Percentage of TPD, area, delay and PDP (%) obtained for the proposed multiplication design with
saved by the proposed techniques over existing method existing error correction circuits

Percentage of parameter Average Error Percentage (AEP) of the

Multiplication Number values saved over existing results obtained with the proposed designs
structure of bits, technique (%) (RLNS and MRLNS)
using Nb
TPD Area Delay PDP With
8 82 65 40 89.03 Number proposed With existing error
RLNS of bits B-LEC correction circuits
16 87.4 70 58.2 95 (Nb) and B- [29, 34]
32 90.2 72 50.4 95 ALEC
8 80 59 31.5 86 8 0.39 0.54
MRLNS 16 87 68 43 92 16 0.40 0.69
32 89.07 69 45.3 94
32 0.30 1.08

The advantage of using LNS eliminates

the partial product generation and its accumulation From the multiplication results it is
process of the existing modulo multiplier designs, observed that the proposed error correction circuits
thereby reducing the TPD, area and delay values. As (B-LEC and B-ALEC) reduces the AEP to 48% when
LNS involves only the addition of input operands the compared with the existing work [29, 34] for the
error reduction of logarithmic and antilogarithmic proposed multiplier design for RLNS based system.
values, is done by the proposed B-LEC and B-ALEC The AEP values obtained for each N category is
b

circuits. The EP values are calculated for the random same for the proposed RLNS and MRLNS based
selection 250 set of input values for each Nb category multiplication designs as the correction is done in the
chosen. The formula for calculating the EP includes mantissa part in the logarithmic and antilogarithmic
the True Value (TV) of the multiplication result and conversion process. The difference in the RLNS and
the Experimental Value (EV) obtained from the MRLNS structures is in processing the corresponding
proposed technique as given below, characteristic values to get two stages of residues. The
residues transmitted with two levels of encryption
prevents the misuse of data, as the two levels of
TV  EV
EP   100% moduli set values are known only to(49) user [37, 39].
TV Thus MRLNS based design may be considered for
secured applications.
The Average Error Percent (AEP) of the final
VI. CONCLUSION
multiplication values obtained with the existing works
[29, 34] and proposed (B-LEC and B-ALEC) error
The multiplier design for RLNS based system is
correction circuits respectively for Nb = 8, 16 and 32
proposed in this research reducing the area, TPD and
are given in Table 3. The AEP value is calculated
delay values when compared with the existing
using the formula given below,
research. Using LNS in the design of multipliers
simplifies the operation by avoiding the partial
N
product reduction and accumulation as only addition
 EP
of the input operands is performed. In order to reduce
n 1
AEP  (50)
N the error produced due to the approximation process
using LNS, error correction circuits are proposed in
this research to produce the final multiplication result
N denotes the number of input set of operands with AEP = 0.36. MRLNS technique is proposed to
considered and its value is 250. The AEP value include the secured features of MRNS that includes
obtained with the proposed B-LEC and B-ALEC multilevel forward and reverse conversion processes.
circuits is 0.36 and for existing error correction circuit,

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 SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) – Volume 5 Issue 3 – Sep to Dec 2018

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