Verilog

Interview Questions
 1. What do you understand from Verilog?
Answer: Verilog is a hardware description language (HDL) used for modeling and
simulation of digital circuits. It is primarily utilized in designing and verifying digital
systems, including applications in integrated circuits (ICs) and FPGA designs. Verilog
enables engineers to describe hardware behavior at different levels of abstraction—
behavioral, dataflow, and structural modeling.

2. Are Verilog and VHDL the same or different?

Answer: Verilog and VHDL are both hardware description languages used for
designing digital circuits, but they differ in syntax, style, and capabilities.
o Verilog is similar to the C programming language, making it more concise and
easier to learn.
o VHDL is derived from Ada and is more verbose, offering stronger type
checking and a richer set of data types.
o Verilog is widely used in ASIC and FPGA design, whereas VHDL is commonly
used for FPGA designs in industries like aerospace and defense.

3. How are Verilog and VHDL different from each other?

Answer:

Parameters Verilog VHDL

Data Types Limited types (wire, reg) Rich set of types (scalar, composite)
Modeling Uses always @ constructs Uses process(clk, rst) syntax
Hierarchy Uses module and instance Uses entity and architecture
Signal Assignment Supports = and <= for assignments Uses <= for signals
Usage Preferred for ASIC designs Widely used in FPGA designs

4. What are HDL Simulators?

Answer: HDL simulators are software tools used to verify and analyze the behavior
of hardware description languages (HDLs) such as Verilog and VHDL. These
simulators allow engineers to test digital circuit designs before actual fabrication,
ensuring correctness and functionality.
 5. What is the difference between == and === in Verilog?
Answer:
o == compares values bit by bit but ignores X and Z values.
o === performs a strict comparison, considering X and Z values.
o == is used in synthesis, while === is mainly used in simulation.

6. What are the five basic differences between Verilog’s task and function?
Answer:

Feature Task Function

Definition A procedural block An expression evaluated to a value
Return Type Does not return values Returns a single value
Usage in Expressions Cannot be used directly Can be used in expressions
Blocking Statements Allows blocking statements (#10;) Only non-blocking statements
Execution Executes sequentially Executes concurrently

7. What is Continuous Assignment in Verilog?

Answer: Continuous Assignment allows assigning values to a wire in Verilog using the
assign keyword. It is typically used for combinational logic where outputs are directly
dependent on inputs.

8. How does the Verilog repeat loop work?

Answer: The repeat loop executes a block of code a specified number of times.

9. Define $monitor, $display, and $strobe in Verilog.

Answer:
o $monitor: Continuously watches variables and displays them when they
change.
o $display: Prints values immediately at simulation time.
o $strobe: Prints values at the end of the simulation time step.

10. How are Blocking and Non-Blocking Assignments executed in Verilog?

Answer:
o Blocking (=): Executes statements sequentially.
o Non-blocking (<=): Executes statements in parallel without waiting.
11. What are the features of VHDL?
Answer: VHDL features include:
o Strong typing for design clarity.
o Hierarchical design support.
o Rich libraries and packages.
o Concurrent and sequential modeling.

12. What is a Programming Language Interface (PLI) in Verilog?

Answer: PLI allows Verilog to interact with external programming languages like
C/C++. It enhances simulation capabilities and integrates Verilog with external tools.

13. What do you understand from the Sensitivity List?

Answer: A Sensitivity List in Verilog specifies the signals or variables that trigger the
execution of a process or always block when their values change.

14. Explain the steps for writing the FSM code.

Answer:
o Define states and state register.
o Describe state transitions using always or case constructs.
o Implement combinational logic for the next state and output.
o Use non-blocking assignments (<=) for state updates.

15. What are Deposit and Force Commands?

Answer:
o Deposit (deposit command): Directly assigns values to variables without
triggering continuous assignments.
o Force (force command): Assigns values while also evaluating continuous
assignments, making changes observable during simulation.

16. Which will update first between Variable and Signal?

Answer: Variables update immediately, whereas signals update at the end of the
simulation time step.
17. What is the difference between Virtual and Pure Virtual Functions in Verilog?
Answer:
o Virtual Function: Can be overridden in a derived class.
o Pure Virtual Function: Must be overridden in a derived class and cannot have
a default implementation.

18. What are Semaphores?

Answer: Semaphores are synchronization constructs used to control access to a
shared resource in a multi-process or multi-threaded environment.

19. Explain the uses of Clocking Blocks.

Answer: Clocking blocks in Verilog are used to model clock and reset events for
improved simulation accuracy and synthesis optimizations.

20. Why do we need an Alias in Verilog?

Answer: An Alias in Verilog is a way to reference a variable or signal using another
name. It provides flexibility in design and improves readability.

21. In Verilog, what do the casex and casez statements mean?

Answer:
o casex: Treats ‘x’ as a don’t care but considers ‘z’ as a high impedance.
o casez: Treats both ‘x’ and ‘z’ as don’t care values, making comparisons more
flexible.

22. When can Race Conditions occur in Verilog?

Answer: Race conditions occur when the output of a logic circuit depends on the
timing or sequence of events, leading to unpredictable behavior.

23. What does Verilog code Timeframe 1 Ns/ 1 Ps mean?

Answer: This defines the time resolution in simulation: 1 nanosecond for behavioral
models and 1 picosecond for gate-level models.
24. Is it required to list every input in the Sensitivity Disc for a Pure Combinational
Circuit? If so, why then?

Answer: In pure combinational circuits, it’s essential to list all input signals in the
sensitivity list because the output directly depends on the inputs. Any change in
inputs must trigger the evaluation of the output.

25. Explain three types of coding in Verilog?

Behavioral coding and Register Transfer Level (RTL) focus on data transfer between
registers, whereas Gate-level coding describes circuits using logic gates.

In Verilog, there are three primary coding styles:

Behavioral Coding: This style focuses on describing the system’s behavior without
detailing its structure. It primarily uses constructs like always blocks and procedural
assignments to model functionality, making it easier to conceptualize complex
operations without diving into the specific hardware implementation details.

Register Transfer Level (RTL): RTL coding represents the system’s behavior by
emphasizing the transfer of data between registers. It concentrates on describing
how data moves between registers through combinational logic, capturing the
essence of digital hardware design.

Gate-level Coding: This style describes the system using basic logic gates like AND,
OR, NOT, etc. It is highly detailed, defining the hardware structure explicitly and
using primitive gates or modules to represent the actual physical components of the
circuit.

26. Which software is used for Verilog?

Tools like Xilinx Vivado, Altera Quartus, Synopsys Design Compiler, and Mentor
Graphics ModelSim are popular for Verilog-based design, simulation, and synthesis.
27. Can you tell me about the datatypes in Verilog?

Verilog consists of a range of data types essential for design representation. These
types serve distinct functions, which are as follows:

Wire: Connects hardware components, modeling interconnections between modules.

Register (reg): Acts as a storage element, similar to hardware flip-flops, allowing

data storage and manipulation within procedural blocks.

Integer: Represents signed 32-bit integer values, utilized for arithmetic operations in
Verilog.

Real: Represents floating-point numbers, enabling floating-point calculations.

Time: Handles time values and delays during simulations.

28. What is RTL in Verilog?

RTL, short for Register Transfer Level, is an important modeling abstraction within Verilog.
It describes digital circuit behavior by emphasizing the flow of data between registers using
combinational logic. This level of abstraction captures the essence of hardware design without
delving into the physical implementation details, enabling designers to specify circuit
functionality at a level closely aligned with actual hardware operations.

29. What are Verilog full case statements and Verilog parallel case statements?
Verilog’s full case statements cover all potential input conditions, ensuring explicit definition
and execution of associated statements for each match within the case structure. On the other
hand, Verilog’s parallel case statements execute only the first encountered match within the
case structure, optimizing simulation efficiency by stopping further evaluations after finding a
match, although it may not explicitly cover all potential conditions.

30. What is the difference between $monitor and $display?

In Verilog, $monitor keeps a constant watch on variables, displaying their updated values as
they change during simulation. On the other side, $display outputs specific values or strings
at set simulation times, serving for debugging or data analysis purposes without automatically
tracking variable changes.
31. What is #0 in Verilog and its usage?
Zero delay control is used to control execution order when multiple procedural blocks try to
update values of the same variable. Both always and initial blocks execution order is non-
deterministic as they start evaluation at the same simulation time. The statement having zero
control delay executes last, thus it avoids race conditions.

32. What is Synthesis?

The process of converting hardware description language like Verilog code into the equivalent
netlist design that has flip-flops, logic gates, and required digital circuit components.

33. Write an RTL code to generate 100MHz clock?

To generate clock frequency, time period needs to be calculated.
Time Period = 1/frequency = 1/100MHz = 10ns
With a 50% duty cycle, clock has to flip a bit after every 5ns.

Example:

module clk_gen;

reg clk;
always #5 clk = ~clk;
endmodule

34. Difference between `define and `include?

`define is a compiler directive that substitutes itself in the code with a defined context. In
simple words, wherever macro is used, it is replaced with macro context and gives compilation
error in case of misuse.
The `include is also a compiler directive is used to include another filename. The double quote
“<file_name>” is used in the `include directive. It is widely used to include library files, and
common code instead of pasting the same code repeatedly

35. What is FIFO? What are underflow and overflow conditions in FIFO? Write Verilog code for
the design?
FIFO stands for first in first out which means that the first element enters into the buffer and
comes out first.
Underflow: When an attempt is made to read data from an empty FIFO, it is called an
underflow. The design should have an ‘empty’ flag to avoid getting invalid values
Overflow: When an attempt is made to write data into the already full FIFO, it is called an
overflow. The design should have a ‘full’ flag to avoid losing the data sent from the previous
module.
36. What is infer latch means? How can you avoid it?
Infer latch means creating a feedback loop from the output back to the input due to missing
if-else condition or missing ‘default’ in a ‘case’ statement.
Infer latch indicates that the design might not be implemented as intended and can result in
race conditions and timing issues.
How to avoid it?
Always use all branches in the ‘if’ and ‘case’ statements.
Use default in the ‘case’ statement.
Have a proper code review.
Use lint tools, and logical-equivalence-check tools

37. Difference b/w inter delay and intra delay?

Inter statement delay refers to the delay between two statements. It represents the time
difference between the completion of one statement and the start of another statement.

Intra statement delay refers to the delay within a single statement. It represents the time
difference between the start of a statement and the execution of a specific operation within
that statement.

38. What is detla simulation time?

Delta delay is a special type of delay in Verilog, which is used to model the execution of
hardware events that take zero simulation time. It is also known as zero delay.
In Verilog, the delta delay is the smallest delay that can be specified. It represents the smallest
unit of simulation time in Verilog. A delta delay can occur when an event is triggered
immediately after the completion of the current statement. In this case, the simulation engine
does not advance the simulation time, as there is no actual delay between the two events.
Instead, the simulation time stays the same, and the event is executed in a single simulation
time step.

39. What does a wire refers?

In Verilog, a wire is a type of net data type that represents a physical connection between two
or more logic gates. It is called a "wire" because it behaves like a real-world electrical wire,
allowing signals to flow from one point to another.

Wires are used to connect signals between modules, and can only be driven by a module's
output. They are also used internally to connect different logic gates within a module. Wires
are meant to represent continuous values, such as analog signals, rather than discrete values
like bits.

40. What is a reg in Verilog?

In Verilog, reg is a data type used to store and manipulate binary and integer values.
Despite its name, a reg does not always represent a physical register or flip-flop. It is a variable
that can store a value determined by combinational logic or sequential logic. It's value can be
set or reset using an always block or an initial block. Once set, the value can be updated or
accessed anytime within the module.
41. Give me the major difference b/w function and task?
Tasks and functions are the subroutines used in Verilog. The primary difference is that a task
can contain statements that consume simulation time like delays, whereas a function cannot.

42. What are HDL Simulation?

HDL (Hardware Description Language) simulators are software tools used in the design and
testing of digital hardware. They simulate the behavior of digital circuits written in hardware
description languages such as Verilog and VHDL. HDL simulators allow designers to test the
functionality, timing, and performance of their designs before they are implemented in
physical hardware. They are essential tools in the design and verification of complex digital
systems such as microprocessors, FPGAs, and ASICs. HDL simulators come in different forms,
including standalone software tools, integrated development environments (IDEs), and cloud-
based platforms.

43. What is the difference $setup and $hold?

$setup and $hold are timing checks used in Verilog to ensure that the input signals are stable
at the input of the flip-flop during the setup and hold time windows of the flip-flop.
$setup is a timing check used to ensure that the input signal to a flip-flop changes sufficiently
ahead of the clock rising edge so that the signal can settle stable by the time the clock edge
arrives. $setup specifies the minimum time required for the input signal to reach a stable value
before the active edge of the clock. Violation of the setup time can cause a race condition,
metastability, and unpredictable behavior of the flip-flop.

44. What is duty cycle?

Duty cycle is a percentage ratio of the time that a signal is ON compared to the total period of
the signal. The duty cycle of a periodic waveform is defined as:
Duty cycle = (time the signal is ON / total period of the signal) * 100
A signal with 50% duty cycle means that the signal is ON for half of the total period and OFF
for half of the total period.
The concept of duty cycle is used in many electronic devices and circuits, such as pulse width
modulation (PWM), signals from oscillators, and digital communication systems. In PWM, the
duty cycle of a square wave signal determines the amount of energy that is being delivered to
a load, such as a motor or an LED. In digital communication systems, the duty cycle of a signal
affects its power consumption and the signal quality

45. What is $random?

In Verilog, the random system task generates a random value. It is used to simulate
unpredictable values in a Verilog testbench. You can use the $random task to generate a
random value for a signal every time the module is executed, thereby ensuring that the design
is tested with different scenarios.
The $random system task returns a 32-bit signed integer. The range of values that the
$random task can generate is dependent on the simulator and the seed value used. The seed
value is an initial value that is used by the random number generator to produce the sequence
of random numbers.
46. What is Synthesis?
Synthesis is the process of converting a high-level hardware description language (HDL) code,
such as Verilog or VHDL, into a gate-level netlist that can be used for physical implementation
of a digital circuit on an integrated circuit (IC) or field-programmable gate array (FPGA).
The synthesis process involves analyzing the HDL code to determine the intended functionality
of the circuit, optimizing the design for the desired performance and resource utilization, and
generating a gate-level netlist that describes the circuit in terms of logic gates and flip-flops.

47. How does the presence of latches affect the testability ?

One of the main issues with latches is that they can cause the propagation of glitches, which
are short-lived pulses that can be difficult to observe during testing. These glitches can be
especially problematic if they propagate to other parts of the design, potentially causing
unintended behavior or creating false positives during testing.
Output of a latch is not controllable directly from a primary input since, the enable to a latch
is not the regular clock going to rest of the flops in the design. The enable pin to the latch
needs to be OR'd with a test mode enable signal.

48. Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?
No, you cannot use a Verilog function to define the width of a multi-bit port, wire, or reg type.
The width of a Verilog port, wire, or reg declaration must be a constant or a parameter value,
both of which are determined at compile-time.
Functions, on the other hand, are executed at run-time and their return values cannot be used
to dynamically set the widths of Verilog objects. Attempting to use a function to define the
width of a port, wire, or reg will result in a compile-time error. However, you can use function
parameters to define the width of Verilog objects. For example, you can declare a parameter
and use it.

49. Summarize the main differences between $strobe and $monitor?

$strobe displays values of selected signals at the end of the current simulation time when all
simulation events have occurred and just before time advances whereas $monitor displays
the value of selected signals whenever its value changes.

50. What are the differences between synchronous and asynchronous state machines?

Synchronous state machines have a clock input that triggers state transitions at specific times.
When the clock signal rises, the state machine updates its output values and transitions to the
next state based on its current state and input values.

Asynchronous state machines do not require a clock signal as they are triggered by input signals
that are not synchronized in time. Each input signal can trigger a state transition at any time,
independent of any clock signal. Asynchronous state machines can be more complex to design
and test due to the possibility of race conditions and glitches, but they can be more efficient and
consume less power compared to synchronous state machines