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Digital Logic Families

The document discusses digital logic families, detailing integration levels from SSI to GSI and highlighting Moore's law regarding transistor growth. It compares saturated and unsaturated logic families, particularly focusing on the advantages of CMOS logic gates, such as low power dissipation and high noise immunity. Additionally, it covers key voltage levels and noise margins relevant to logic gate performance.

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souryasirsha.mukherjee
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11 views16 pages

Digital Logic Families

The document discusses digital logic families, detailing integration levels from SSI to GSI and highlighting Moore's law regarding transistor growth. It compares saturated and unsaturated logic families, particularly focusing on the advantages of CMOS logic gates, such as low power dissipation and high noise immunity. Additionally, it covers key voltage levels and noise margins relevant to logic gate performance.

Uploaded by

souryasirsha.mukherjee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Logic Families

Dept. of ECE
UEM Kolkata
Integration Levels
• Gate/transistor ratio is roughly 1/10
– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip
Moore’s law
• A prediction made by Moore (a co-founder
co of Intel) in
1965: “… a number of transistors to double every 2
years.”
saturated logic, the transistor is switched between the off and saturation regions, while in non-satura
non
ic, the transistor is switched between the off and active regions.
urated logic families like TTL are based on bipolar transistors and offer faster switching speeds but
her power consumption, while unsaturated logic families like CMOS use MOSFETs, providing lower
wer consumption and the ability to operate at lower voltages
Diode-Transistor
Transistor Logic (DTL) – NAND Gate

• essentially diode logic with transistor amplification


• reduced power consumption
• faster than RTL

AND gate Saturating inverter


Logic families: V levels
VOH(min) – The minimum voltage level at an
output in the logical “1” state under defined
load conditions
VOL(max) – The maximum voltage level at an
output in the logical “0” state under defined
load conditions
VIH(min) – The minimum voltage required at
an input to be recognized as “1” logical state
VIL(max) – The maximum voltage required at
an input that still will be recognized as “0”
logical state
Propagation delay
Noise Margin
HI state noise margin:
VNH = VOH(min) – VIH(min)

LO state noise margin:


VNL = VIL(max) – VOL(max)

VNH
Noise margin:
VN = min(VNH,VNL)
VNL
TTL NAND Gate
CMOS NAND Gate
antages of CMOS Logic Gates

Extremely large fan-out capability (>50).


Lowest power dissipation of all gates (a few nW).
Very high noise-immunity and noise-margin
margin (typically, VDD/2)
Lower propagation delay than NMOS.
Higher speed than NMOS. Currently, computer chips operating at (or more than) 4 GHz are
able in the open market.
Large logic swing (=VDD).
Only a single power supply (+ VDD) is required.
Directly compatible with TTL gates.
Temperature stability is excellent.
Low-voltage (1.5 V) chips are now available.

MOS chips must be protected from acquiring static charges by keeping the leads
ted. Static charges acquired in leads will destroy the chip. At present this problem has
rectified by using built-in
in protective devices or circuits.

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