180 nm CMOS Fabrication Process Flow
Big picture of fabrication process flow 2
1. Si substrate preparation
2. Shallow Trench Isolation (STI) Formation
Wire
3. Well Formation
Contact
Gate Side wall
4. Gate Formation N-type P-type
Source/Drain Source/Drain
5. Lightly Doped Drain (LDD) Formation Shallow trench
isolation (STI)
6. Side wall formation Si substrate
P-type Well N-type Well
N-type
Light Doped Drain
P-type
7. Source/Drain Formation Light Doped Drain Si Poly-Si High N-Dopant
(≃1020 cm-3)
SiO2 Silicide
High P-Dopant
8. Silicide Formation Si3N4 TiN/Ti (≃1020 cm-3)
Tungsten Low-k Low P-Dopant
(≃1016 cm-3)
9. Contact Formation Cu
Low N-Dopant
(≃1016 cm-3)
10. Wire Formation
Si Substrate Preparation – Quality Check 3
Explanation
Check the quality of the substrates received from the supplier.
Why important ?
If the substrate preparation is flawed, the entire downstream
process may be wasted. Therefore, it is essential to carefully verify
What, Why, How do we do in this process?
What Why How
Dopant concentration Affect built-in potential ・Sheet Resistance
check of PN junction, leading ・SIMS
Si to fluctuate Vth
Crystallographic Affect carrier mobility ・XRD
Orientation defect check ・Photoluminescence
Bow and Wrap Focus misalignment ・Stylus profiler
during exposure, leading
CD variation
Si Substrate Preparation - Cleaning 4
Explanation
Native, oxide, organic contaminants, and metal impurities are
removed prior to starting the fabrication process
Why important ?
If there is contamination on the silicon substrate, it may become
trapped beneath the gate, leading to defects. It can also alter
etching and deposition characteristics, ultimately affecting yield.
Si
Shallow Trench Isolation – Thermal Oxidation 5
Purpose : Sacrificial layer for ion implantation
protecting product area against CMP
Method : Thermal Oxidation
Deposited material : Silicon Dioxide
Thickness : 10 nm
Si
SiO2 Metrology : Spectroscopy Ellipsometry
Shallow Trench Isolation – Stopping layer deposition 6
Purpose : Stopping layer against CMP
Method : Low Pressure CVD
Deposited material : Silicon Nitride
Thickness : 20~50 nm?
Si Metrology : Spectroscopy Ellipsometry
SiO2
Si3N4
Shallow Trench Isolation – STI Patterning 7
Purpose : Form pattern on wafer
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : 300~800 nm
Si Metrology : Spectroscopy Interferometry
SiO2
Si3N4
Resist
Shallow Trench Isolation – RIE Etching 8
Purpose : Form Shallow Trench
Method : RIE
Etched material : SiN/SiO2/Si
Thickness : 700 nm~2 µm
Si Metrology : Stylus Profiler
SiO2
Si3N4
Resist
Shallow Trench Isolation – Resist Stripping 9
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Metrology : Surface Particle Inspection System
SiO2
Si3N4
Resist
Shallow Trench Isolation – SiO2 Deposition 10
Purpose : Overfill Trench
Method : TEOS CVD (TEOS is good coverage)
Deposited material : Silicon Dioxide
Thickness : 1.5 ~ 2.5 µm
Si Metrology : Spectroscopic Interferometry
SiO2
Si3N4
Resist
Shallow Trench Isolation – Planarization 11
Purpose : Planarize surface for embedding Silicon
dioxide into STI
Method : Chemical Mechanical Polishing(CMP)
(Colloidal silica, Alumina slurry)
Polished material : Silicon Dioxide
Si Thickness : 500 ~ 700 nm
SiO2
Si3N4
Metrology : In-situ end point detection
Resist
(Reflectivity, Torque)
Shallow Trench Isolation – Remove Stopping layer 12
Purpose : To remove Stopping layer
Method : Wet Etching (Hot Phosphorous acid)
Etched material : Silicon Nitride
Thickness : 20 ~ 50 nm
Si Metrology : Surface analysis (FT-IR, XPS)
SiO2
Si3N4
Resist
Well Channel Formation – N-MOS Well Patterning 13
Purpose : Being able to protect from Ion
implantation
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : 300 ~ 800 nm
Si
SiO2 Metrology : Spectroscopy Interferometry
Si3N4
Resist
Well Channel Formation – N-MOS Well Ion Implantation 14
Purpose : Implant Dopant for forming N-MOS Well
Method : Ion Implantation
Implanted material : Boron
Concentration : 1016 ~ 1017 cm-3
Thickness : Few hundred nm ~ µm
Si
SiO2
Metrology : Secondary Ion Mass Spectroscopy
Si3N4
Resist
(SIMS)
P-Dopant
Well Channel Formation – N-MOS Well Pattern Stripping 15
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Metrology : Surface Particle Inspection System
SiO2
Si3N4
Resist
P-Dopant
Well Channel Formation – P-MOS Well Patterning 16
Purpose : Being able to protect from Ion
implantation
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : 300 ~ 800 nm
Si
SiO2 Metrology : Spectroscopy Interferometry
Si3N4
Resist
P-Dopant
Well Channel Formation – P-MOS Well Ion Implantation 17
Purpose : Implant Dopant for forming P-MOS Well
Method : Ion Implantation
Implanted material : Phosphorous
Concentration : 1016 ~ 1017 cm-3
Thickness : Few hundred nm ~ µm
Si
SiO2
Metrology : Secondary Ion Mass Spectroscopy
Si3N4
Resist
(SIMS)
P-Dopant
N-Dopant
Well Channel Formation – P-MOS Well Resist Stripping 18
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Metrology : Surface Particle Inspection System
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Well Channel Formation – Remove Sacrificial layer 19
Purpose : To Remove the sacrificial layer
(Because damaged by ion implantation)
Method : Wet Etching (BHF)
Etched material : Silicon dioxide
Thickness : 10 nm
Si
SiO2 Metrology : Surface analysis (FT-IR, XPS)
Si3N4
Resist
P-Dopant
N-Dopant
Gate Formation – Gate oxidation 20
Purpose : To form Gate oxidation
Method : Thermal oxidation
Deposited material : Silicon dioxide
Thickness : few nm
Si Metrology : Spectroscopic Ellipsometry(On line)
SiO2 X-ray Refractometry (Off line)
Si3N4
Resist
P-Dopant
N-Dopant
Gate Formation – Gate deposition 21
Purpose : To form poly silicon
Method : LP-CVD
Deposited material : Poly-Si, a-Si
Thickness : 5 ~ 30 nm
Si Poly-Si Metrology : Spectroscopic Ellipsometry
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Gate Formation – Gate patterning 22
Purpose : Gate patterning
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : Few hundred nm
Si Poly-Si Metrology : Spectroscopy Interferometry
SiO2 (Thickness)
Si3N4
CD-SEM (Dimension)
Resist
P-Dopant
N-Dopant
Gate Formation – Gate Etching 23
Purpose : Gate Etching (Isotropic etching )
Method : RIE (Cl base gas)
Etched material : Poly-Si, a-Si
Thickness : Few hundred nm
Si Poly-Si Metrology : Spectroscopy Interferometry
SiO2 (Thickness)
Si3N4
CD-SEM (Dimension)
Resist
P-Dopant
N-Dopant
Gate Formation – Stripping resist 24
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si Metrology : Surface Particle Inspection System
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Gate Formation – Re-oxidation 25
Purpose : To reform the sacrificial layer for LDD
implantation.
Because Gate oxide(SiO2) is physically
etched due to isotropic RIE.
Method : Thermal oxidation
Deposited material : Silicon dioxide
Si Poly-Si Thickness : 10 nm
SiO2
Si3N4
Metrology : Spectroscopy Ellipsometry
Resist
P-Dopant
N-Dopant
Lightly Doped Drain (LDD) Formation – NMOS Patterning 26
Purpose : Being able to protect from Ion
implantation
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si
SiO2 Metrology : Spectroscopy Interferometry
Si3N4
Resist
P-Dopant
N-Dopant
Lightly Doped Drain (LDD) Formation – LDD implantation 27
Purpose : To form LDD for preventing from hot
carrier effect.
Method : Ion implantation
Implanted material : Phosphorous, Boron
Concentration : 1016 ~ 1017 cm-3
Si Poly-Si
SiO2 Metrology : Secondary Ion Mass Spectroscopy
Si3N4
(SIMS)
Resist
P-Dopant
N-Dopant
※P-MOS LDD is omitted
Lightly Doped Drain (LDD) Formation – Resist strip 28
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si Metrology : Surface Particle Inspection System
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Lightly Doped Drain (LDD) Formation – Remove sacrificial layer 29
Purpose : To Remove the sacrificial layer
(Because damaged by ion implantation)
Method : Wet Etching (BHF)
Etched material : Silicon dioxide
Thickness : 10 nm
Si Poly-Si
SiO2 Metrology : Surface analysis (FT-IR, XPS)
Si3N4
Resist
P-Dopant
N-Dopant
Lightly Doped Drain (LDD) Formation –Form sacrificial layer 30
Purpose : To reform the sacrificial layer for LDD
implantation.
Because Gate oxide(SiO2) is physically
etched due to isotropic RIE.
Method : Thermal oxidation
Deposited material : Silicon dioxide
Si Poly-Si Thickness : 10 nm
SiO2
Si3N4
Metrology : Spectroscopy Ellipsometry
Resist
P-Dopant
N-Dopant
Side wall formation– SiN Deposition 31
Purpose : To form sidewall film for determining
the channel length
Method : TEOS CVD ( is better )
Deposited material : Silicon Nitride
Thickness : Few hundred nm
Si Poly-Si Metrology : Spectroscopy interferometry
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Side wall formation– Anisotropic etching
Purpose : To form sidewall film for determining
the channel length
Method : RIE ( as anisotropic as possible)
Etched material : Silicon Nitride
Thickness : Few hundred nm
Si Poly-Si Metrology : Spectroscopy interferometry
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Source/ Drain Formation– Patterning 33
Purpose : Being able to protect from Ion
implantation
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si
SiO2 Metrology : Spectroscopy Interferometry
Si3N4
Resist
P-Dopant
N-Dopant
Source/ Drain Formation– Ion implantation 34
Purpose : To form LDD for preventing from hot
carrier effect.
Method : Ion implantation
Implanted material : Arsenic, Boron difluoride
Concentration : 1020 cm-3
Si Poly-Si
SiO2 Metrology : Secondary Ion Mass Spectroscopy
Si3N4
(SIMS)
Resist
P-Dopant
N-Dopant
※P-MOS LDD is omitted
Source/ Drain Formation– Resist Strip 35
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si Metrology : Surface Particle Inspection System
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Source/ Drain Formation– Annealing 36
Purpose : To recover damage caused by
implantation
To combine dopant and substrate
Method : Furnace annealing
(Vertical furnace annealing)
Temperature : Over 1000℃
Si Poly-Si
SiO2
Si3N4
Resist
P-Dopant
N-Dopant
Source/ Drain Formation– Remove sacrificial layer 37
Purpose : Removal of the sacrificial layer is
required to facilitate the formation of silicide on
the surface
Method : Wet Etching (BHF)
Etched material : Silicon dioxide
Si Poly-Si Thickness : 10 nm
SiO2
Si3N4
Metrology : Surface analysis (FT-IR, XPS)
Resist
P-Dopant
N-Dopant
Silicide Formation – Deposit Silicide Material 38
Purpose : Silicide materials are deposited by
sputtering to react with silicon and form low-
resistance metal silicide contacts during
annealing.
Method : Sputtering
Deposited material : Ti, Co or Ni etc.
Si Poly-Si Thickness : 30 ~ 80 nm
SiO2
Si3N4
Resist
Metrology : Ellipsometry, XRR, XRF
P-Dopant
N-Dopant
Silicide (Before annealing)
Silicide Formation – 1st Annealing 39
Purpose : Initiate the reaction between the
deposited metal and the underlying silicon to form
a preliminary silicide phase
(C49 phase which is high resistivity).
Method : Furnace annealing
Deposited material : Si + Silicide material
(Ti, Co, Ni)
Si Poly-Si
SiO2
Temperature : 600 ~ 700℃
Si3N4
Resist
P-Dopant
N-Dopant
Silicide (Before annealing)
Silicide Formation – Wet Etching 40
Purpose : To eliminate only the non-silicide area
Method : Wet etching (HF + H2O2)
Etched material : Silicide material
Si Poly-Si
SiO2 Silicide
Si3N4
Resist
P-Dopant
N-Dopant
Silicide Formation – 2nd Annealing 41
Purpose : To convert the high-resistance C49
phase into the low-resistance C54 phase.
Method : Furnace annealing
Deposited material : Silicide material
Temperature : 700 ~ 900℃
Si Poly-Si Note: Why this flow?
SiO2 Silicide (1st anneal → Wet etching → 2nd anneal)
Si3N4
Resist
This sequence helps prevent unintended silicide
P-Dopant
formation and reduces the risk of electrical failure.
N-Dopant
Contact Formation – Deposit Inter level dielectric 42
Purpose : Stopping layer for the Contact etching.
Because Source/Drain is different height.
Method :LPCVD, SOG
Deposited material : Silicon Nitride / Silicon Dioxide
Thickness : Few hundred nm
Si Poly-Si
SiO2 Silicide
Si3N4
Resist
P-Dopant
N-Dopant
Contact Formation – Planarization 43
Purpose : Before contact patterning, the surface
must be flat to avoid fluctuations in focus during
lithography.
Method : CMP
Polished material : Silicon Dioxide
Thickness : Few hundred nm
Si Poly-Si
SiO2 Silicide Metrology : Spectroscopy Interferometry
Si3N4
Resist
P-Dopant
N-Dopant
Contact Formation – Adjust the thickness of ILD 44
Purpose : Due to the possibility that the CMP
endpoint detection may not function effectively with
this film configuration, an additional film thickness
will be deposited at this point.
Method : LP CVD
Polished material : Silicon Dioxide
Si Poly-Si Thickness : Few hundred nm
SiO2 Silicide (Depending on the measured data)
Si3N4
Resist
P-Dopant
Metrology : Spectroscopy Interferometry
N-Dopant
Contact Formation – Contact Patterning 45
Purpose : Being able to protect from Ion
implantation
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : Few µm
Si Poly-Si
SiO2 Silicide Metrology : Spectroscopy Interferometry
Si3N4
Resist
P-Dopant
N-Dopant
Contact Formation – Contact Etching 1 46
Purpose : Since there is a step between the
source/drain and the gate, contact etching is
performed down to the SiN stop layer.
Method : RIE (CHF3 Gas)
Etched material : Silicon dioxide
Thickness : Few hundred nm
Si Poly-Si
SiO2 Silicide
Si3N4
Metrology : Stylus profiler
Resist
P-Dopant
N-Dopant
Contact Formation – Contact Etching 2 47
Purpose : Etching until reaching the silicide layer
to complete contact etching
Method : RIE
Etched material : Silicon nitride
Thickness : Few hundred nm
Si Poly-Si
Metrology : Stylus profiler
SiO2 Silicide
Si3N4
Resist
P-Dopant
N-Dopant
Contact Formation – Photoresist Stripping 48
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si Metrology : Surface Particle Inspection System
SiO2 Silicide
Si3N4
Resist
P-Dopant
N-Dopant
Wire Formation – Barrier layer deposition 49
Purpose : Prevent Tungsten from diffuse with
Silicon. Deposit Barrier layer
Method : CVD ( is better because good coverage)
Deposited material : TiN/Ti
Thickness : Few ten nm
Si Poly-Si
SiO2 Silicide Metrology :
Si3N4 TiN/Ti
Thickness → Spectroscopy Ellipsometry, XRR,XRF
Resist
P-Dopant
Coverage → FIB, SEM, TEM
N-Dopant
Wire Formation – Tungsten layer Deposition 50
Purpose : Deposit Wiring layer
Method : CVD ( is better because good coverage)
Deposited material : Tungsten
Thickness : Few hundred nm ~ few µm
Metrology :
Si Poly-Si Thickness → Spectroscopy Ellipsometry, XRR,XRF
SiO2 Silicide Coverage → FIB, SEM, TEM
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant
N-Dopant
Wire Formation – Planarization 51
Purpose : To embed tungsten into contact hole
Method : CMP (Al2O3, H2O2 slurry)
Planarized material : Tungsten
Thickness : Few hundred nm ~ few µm
Metrology :
Si Poly-Si Thickness → Spectroscopy Ellipsometry, XRR,XRF
SiO2 Silicide Coverage → FIB, SEM, TEM
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant
N-Dopant
Wire Formation – ILD deposition 52
Purpose : To provide insulation between metal
layers
Method : PE-CVD
Planarized material : FSG, SIOC, p-SIOC
Thickness : Few hundred nm ~ few µm
Si Poly-Si Metrology :
SiO2 Silicide Thickness → Spectroscopy Ellipsometry, XRR,XRF
Si3N4 TiN/Ti Density → Spectroscopy Ellipsometry
Resist Tungsten
P-Dopant Low-k
N-Dopant
Wire Formation – ILD patterning 53
Purpose : Being able to protect from Ion
implantation
Method : Coating, Exposure, Development
Deposited material : Photoresist
Thickness : Few µm
Si Poly-Si
SiO2 Silicide Metrology : Spectroscopy Interferometry
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant Low-k
N-Dopant
Wire Formation – Electrode Formation Etching 54
Purpose : To ensure that the semiconductor
operates properly by allowing electrical signals
and power to flow between components.
Method : RIE
Deposited material : FSG, SIOC, p-SIOC
Thickness : Few hundred nm ~ few µm
Si Poly-Si
SiO2 Silicide Metrology : Sylus profiler
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant Low-k
N-Dopant
Wire Formation – Stripping 55
Purpose : Strip resist
Method : O2 ashing
Etched material : Photoresist
Thickness : 300 ~ 800 nm
Si Poly-Si Metrology : Surface Particle Inspection System
SiO2 Silicide
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant Low-k
N-Dopant
Wire Formation – Deposit barrier layer for Via 56
Purpose : Prevent copper from diffuse, erosion.
Method : Sputtering
Deposited material : TiN/Ti/Cu
TiN→ Barrier metal
Ti →Adhesion layer
Cu→ Copper underlayer
Thickness : Few ten nm
Si Poly-Si
SiO2 Silicide Metrology :
Si3N4 TiN/Ti
Resist Tungsten
Coverage → FIB, SEM, TEM
P-Dopant Low-k
N-Dopant Cu
Wire Formation – Copper Electroplating 57
Purpose : Filling copper to form wire
Method : Electroplating (Copper sulfate plating)
Deposited material : Cu
Thickness : Few µm
Metrology :
Si Poly-Si
Thickness → XRF
SiO2 Silicide
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant Low-k
N-Dopant Cu
Wire Formation – Copper Planarization 58
Purpose : To embed copper into contact wire
Method : CMP (Colloidal Silica, H2O2 slurry)
Planarized material : Copper
Thickness : Few µm
Metrology :
Si Poly-Si Thickness → XRF
SiO2 Silicide Coverage → FIB, SEM, TEM
Si3N4 TiN/Ti
Resist Tungsten
P-Dopant Low-k
N-Dopant Cu
