Microprocessors and

Microcontrollers (EC3L007)

Instruction set of 8085 – Part 1

Summary of Last Class
• Pin diagram and function of these pins
• Architecture (brief)
• Common microprocessor operations
• Programming model
• Registers, Accumulator, Flags
• Program Counter
• Stack Pointer
• Format of Instructions
• Addressing Modes

2
Learning Objectives
• Machine Cycles
• Instruction set classification
• Data Transfer Instructions

• Arithmetic Instructions

• Logical Instructions

• Branching Instructions

• Control Instructions

3
Introduction

• An instruction is a binary pattern designed inside a

microprocessor to perform a specific function.

• All instructions that a microprocessor supports is called

Instruction Set.

• A microcomputer performs a task by reading and

executing the set of instructions written in its memory.
This set of instructions, written in a sequence, is called a
program.

4
Introduction
• Each instruction in the program is a command, in binary,
to perform an operation.

• 8085 has 246 instructions.

• Each instruction is represented by an 8-bit binary value.

• These 8-bits of binary value is called Op-Code or

Instruction Byte.

5
Format of 8085 Instructions
• The size of 8085 can be one byte, two byte or three
byte.

6
Addressing Modes

7
Addressing Modes
• In each instruction, programmer has to specify 3 things:
1. Operation to be performed.
2. Address of source data.
3. Address of destination of result.

• The method by which the address of source data or the

address of destination of result is given in the instruction
is called Addressing Modes.

• The term addressing mode refers to the way in which

the operand of the instruction is specified.

8
Addressing Modes
The 8085 supports the following Five addressing modes.

1. Immediate Addressing

2. Direct Addressing

3. Register Addressing

4. Register Indirect Addressing

5. Implied/Implicit Addressing

9
Immediate Addressing
• The data is specified in the instruction itself. The data
will be part of the program instruction.

MVI A, 05 H Move 05 H in accumulator

• MVI is the operation.

• 05h is the immediate data (source).
• A is the destination.

10
Direct Addressing Mode
• The address of the operand is given in the instruction
itself.

LDA 2500 H Load the contents of memory location

2500 H in accumulator.

• LDA is the operation.

• 2500 H is the address of source.
• Accumulator is the destination.

11
Register Addressing Mode
• The operand is in general purpose register.

MOV A, B Move the contents of register B to A

• MOV is the operation.

• B is the source of data.
• A is the destination.

12
Register Indirect Addressing Mode
• In this mode, the address of operand is specified by a
register pair.

MOV A, M Move data from memory location specified

By H-L pair to accumulator.

• MOV is the operation.

• M is the memory location specified by H-L register pair.
• A is the destination.

13
Implicit Addressing Mode
• If address of source of data as well as address of
destination of result is fixed, then there is no need to
give any operand along with the instruction.

CMA Complement accumulator

• CMA is the operation.

• A is the source.
• A is the destination.

14
Machine (Processor) Cycles

15
Machine Cycles
• The time required to complete the execution of an
instruction is called an “Instruction Cycle”.

• Each instruction cycle of a processor may consist of a

number of machine cycles.

• To execute an instruction, the processor executes one or

more machine cycles in a particular sequence.

16
Machine cycles of 8085
• The 8085 processor has seven basic machine cycles:

1. Opcode fetch cycle (4T or 6T)

2. Memory read cycle (3T)
3. Memory write cycle (3T)
4. IO read cycle (3T)
5. IO write cycle (3T)
6. Interrupt acknowledge cycle (6T or 12T)
7. Bus idle cycle (2T or 3T)

17
T-state
• The time taken by the processor to execute a machine
cycle is expressed in T-states.

• One T-state is equal to the time period of the internal

clock signal of the processor.

• The T-state start at the falling edge of the clock.

Clock Signal
18
Timing Diagram

• The timing diagram provides information about the

various conditions ( high state or low state or high
impedance state) of the signals while a machine cycle
is executed.

• The timing diagrams are supplied by the manufacturer of

the microprocessor.

• The timing diagrams or essential for a system designer--

- to form a system with microprocessor as CPU.

19
Opcode Fetch Machine Cycle

20
Opcode Fetch Machine Cycle
• The Opcode fetch cycle, fetches the instructions from
memory and delivers it to the instruction register of the
microprocessor.

T1 State
• The high order 8 address bits are placed on the address
lines A8 – A15 and the low order bits are placed on
AD7–AD0.
• The ALE signal goes high to indicate that AD0 – AD7 are
carrying an address.
ഥ signal goes low to
• At exactly the same time, the IO/M
indicate a memory access operation.

21
Opcode Fetch Machine Cycle
T2 State

• At the beginning of the T2 cycle, the low order 8 address

bits are removed from AD7– AD0 and the controller
sends the Read (RD) signal to the memory.

• The RD signal remains low (active) for two clock periods

to allow for slow devices.

• During T2, memory places the data from the memory

location on the lines AD7– AD0.

22
Opcode Fetch Machine Cycle
T3 State
• During T3 the RD signal is Disabled (goes high). This
turns off the output Tristate buffers in the memory.
• That makes the AD7– AD0 lines go to high impedance
mode.
• In this state of the cycle, the opcode of the AD bus is
transferred to the instruction register of the
microprocessor.

T4 State
• In this state the opcode which was fetched from the
memory is decoded.

23
Memory Read Machine Cycle

24
Memory Read Machine Cycle
T1 state

• At the falling edge of T1, the microprocessor outputs the

low byte address on AD0-AD7 lines and high byte on A8-
A15 lines.

• ALE is asserted high to enable the external address

latch.

• The microprocessor identifies the memory read machine

cycle from the status signals IO/M’=0, S1=1, S0=0. This
condition indicates the memory read cycle.

25
Memory Read Machine Cycle
T2 state
• RD’ goes LOW
• Selected memory location is placed on the AD0-AD7.
The time allowed for memory to output the data is the
time during which RD’ remains low.

T3 State
• At the end of T3, the read signal is asserted high. On
the rising edge of read signal, the data is latched into the
microprocessor.

26
Memory write cycle

27
Memory Write Machine Cycle
T1 state

• At the falling edge of T1, the microprocessor outputs the

low byte address on AD0-AD7 lines and high byte on A8-
A15 lines.

• ALE is asserted high to enable the external address

latch.

• The other control signals are asserted as follows:

IO/M’=0, S1=0, S0=1

28
Memory Write Machine Cycle
T2 state
• At the falling edge of T2, the processor outputs the data
on AD0-AD7 lines, request memory for write operation
by asserting the write control signal WR’ to low.

T3 State
• At the end of T3, the write signal is asserted high. This
enables the memory to latch the data into it. The
memory should prepare itself to accept data within the
time duration in which the write control signal remains
low.

29
Instruction Set Classification
• The 8085 instructions can be classified into the following
five functional groups:

• Data Transfer Instructions

• Arithmetic Instructions

• Logical Instructions

• Branching Instructions

• Control Instructions

30
Data Transfer Instructions

31
Data Transfer (Copy) Instructions
• These instructions move data between registers, or
between memory and registers.

• One of the primary functions of the microprocessor is

copying data, from a register (or I/O or memory) called the
source, to another register (or I/O or memory) called the
destination.

• While copying, the contents of source are not modified.

• The previous contents of the destination are replaced by

the contents of the source.

• In 8085, data transfer instructions do not affect the flags

32
Data Transfer Instructions
Opcode Operand Description
MOV Rd, Rs Copy data from source register to
destination register.
1 byte instruction
M, Rs Copy data from source register to
Rd, M memory location or vice versa.
1 byte instruction

• If one of the operands is a memory location, its location

is specified by the contents of the HL registers.
• Example: MOV B, C
MOV B, M
33
Example:

34
Example:

35
Example:

36
Data Transfer Instructions

Opcode Operand Description

MVI Rd, Data Loads the 8 bits of the second
M, Data byte into the register specified.
This is a 2-byte instruction.

• The 8-bit data is stored in the destination register or

memory.

• If the operand is a memory location, its location is

specified by the contents of the H-L registers.

• Example: MVI B, 57H or MVI M, 57H

37
Example:

38
Example:

39
Data Transfer Instructions

Opcode Operand Description

LDA 16-bit address Load Accumulator

• The contents of a memory location, specified by a 16-bit

address in the operand, are copied to the accumulator.

• The contents of the source are not altered.

• Example: LDA 2034H

40
Example:

41
Data Transfer Instructions

Opcode Operand Description

LDAX B/D Register Pair Load accumulator indirect

• The contents of the designated register pair point to a

memory location.

• This instruction copies the contents of that memory

location into the accumulator.

• The contents of either the register pair or the memory

location are not altered.

• Example: LDAX B
42
Example:

43
Data Transfer Instructions

Opcode Operand Description

LXI Reg. pair, Load register pair immediate
16-bit data

• This instruction loads 16-bit data in the register pair.

• Example: LXI H, 2034 H

44
Example:

45
Data Transfer Instructions

Opcode Operand Description

LHLD 16-bit Load H-L registers direct
address

• This instruction copies the contents of memory location

pointed out by 16-bit address into register L.

• It copies the contents of next memory location into

register H.

• Example: LHLD 2040 H

46
Example:

47
Data Transfer Instructions

Opcode Operand Description

STA 16-bit address Store accumulator direct

• The contents of accumulator are copied into the memory

location specified by the operand.

• Example: STA 2500 H

48
Example:

49
Data Transfer Instructions

Opcode Operand Description

STAX Reg. pair Store accumulator indirect

• The contents of accumulator are copied into the memory

location specified by the contents of the register pair.

• Example: STAX B

50
Example:

51
Data Transfer Instructions

Opcode Operand Description

SHLD 16-bit Store H-L registers direct
address

• The contents of register L are stored into memory

location specified by the 16-bit address.

• The contents of register H are stored into the next

memory location.

• Example: SHLD 2550 H

52
Example:

53
Data Transfer Instructions

Opcode Operand Description

XCHG None Exchange H-L with D-E

• The contents of register H are exchanged with the

contents of register D.

• The contents of register L are exchanged with the

contents of register E.

• Example: XCHG

54
Example:

55
Data Transfer Instructions

Opcode Operand Description

SPHL None Copy H-L pair to the Stack
Pointer (SP)

• This instruction loads the contents of H-L pair into SP.

• Example: SPHL

56
Example:

57
Data Transfer Instructions

Opcode Operand Description

XTHL None Exchange H–L with top of stack

• The contents of L register are exchanged with the

location pointed out by the contents of the SP.

• The contents of H register are exchanged with the next

location (SP + 1).

• Example: XTHL

58
Example:

59
Data Transfer Instructions

Opcode Operand Description

PCHL None Load program counter with H-L
contents

• The contents of registers H and L are copied into the

program counter (PC).

• The contents of H are placed as the high-order byte and

the contents of L as the low-order byte.

• Example: PCHL

60
Data Transfer Instructions

Opcode Operand Description

PUSH Reg. pair Push register pair onto stack

• The contents of register pair are copied onto stack.

• SP is decremented and the contents of high-order

registers (B, D, H, A) are copied into stack.

• SP is again decremented and the contents of low-order

registers (C, E, L, Flags) are copied into stack.

• Example: PUSH B

61
Example:

62
Example:

63
Data Transfer Instructions

Opcode Operand Description

POP Reg. pair Pop stack to register pair

• The contents of top of stack are copied into register pair.

• The contents of location pointed out by SP are copied to

the low-order register (C, E, L, Flags).

• SP is incremented and the contents of location are

copied to the high-order register (B, D, H, A).

• Example: POP H
64
Example:

65
Example:

66
Data Transfer Instructions

Opcode Operand Description

IN 8-bit port Copy data to accumulator from a
address port with 8-bit address

• The contents of I/O port are copied into accumulator.

• Example: IN 8C H

67
IN

68
Data Transfer Instructions

Opcode Operand Description

OUT 8-bit port Copy data from accumulator to a
address port with 8-bit address

• The contents of accumulator are copied into the I/O port.

• Example: OUT 78 H

69
OUT

70
References
• Ramesh Gaonkar, “Microprocessor, Architecture,
Programming, & Applications with the 8085 6/e”

• Various online resources.

• Reading:
Chapter 6 & 7, Ramesh Gaonkar

71