:RTL to GDSII Implementation Report

(ASIC Design Flow)

VLSI Physical Design

By: Abhishek Sharma

Under Supervision of
Dr. Shasanka Sekhar Rout
 1. INTRODUCTION
1.1 Objective
This report documents the complete RTL-to-GDSII implementation of a 4-bit Up/Down
Counter using the Cadence toolchain. The flow covers:
- RTL Design & Verification
- Logic Synthesis (RTL → Gate-level Netlist)
- Physical Design (Place-and-Route)
- Signoff Verification (Timing, DRC/LVS, Power)

The final output is a GDSII file ready for fabrication.

1.2 Tools Used

| Stage | Tool | Purpose |
|-------------------------------|---------------------------|----------------------------------------------------------|
| RTL Simulation | Xcelium | Functional verification |
| Logic Synthesis | Genus | RTL → Gate-level netlist conversion |
| Physical Design (PnR) | Innovus | Floorplanning, Placement, CTS, Routing |
| Timing Signoff | Tempus | Setup/Hold analysis |
| Physical Signoff | Pegasus | DRC/LVS checks |
| Power Analysis | Voltus | IR drop & EM verification |

1.3 Key Deliverables

- RTL: Verified Verilog code & testbench.
- Synthesis: Optimized netlist, area/timing reports.
- PnR: GDSII, SPEF (parasitics), SDF (timing annotations).
- Signoff: Clean STA, DRC/LVS, and power reports.
1.4 Target Technology
- Process Node: 90nm
- Standard Cells: Provided by Foundry (e.g., gpdk90)
- PVT Corners:
- Worst-case (slow.lib): Max delay (setup check)
- Best-case (fast.lib): Min delay (hold check)
 2. RTL DESIGN
2.1 Design Specifications
The 4-bit Up/Down Counter is implemented in Verilog with the following specifications:
- Inputs:
- `clk`: Clock signal (positive-edge triggered)
- `reset_n`: Active-low synchronous reset
- `up_down`: Count direction control (`1` = up, `0` = down)
- `enable`: Count enable signal
- Output:
- `count[3:0]`: 4-bit counter output

2.2 Verilog Implementation

File: `up_down_counter.v`
```verilog
module up_down_counter (
input wire clk, // Clock
input wire reset_n, // Active-low reset
input wire up_down, // Count direction (1=up, 0=down)
input wire enable, // Count enable
output reg [3:0] count // 4-bit counter output
);

always @(posedge clk) begin

if (!reset_n) begin // Synchronous reset
count <= 4'b0000;
end else if (enable) begin // Count only if enabled
if (up_down) begin // Up-count mode
count <= count + 1;
end else begin // Down-count mode
count <= count - 1;
end
end
end

endmodule
```

2.3 Key Design Choices

1. Synchronous Reset:
 - Ensures reset is aligned with clock edges for predictable behavior.
2. Enable Signal:
- Allows freezing the counter without resetting.
3. Binary Counting:
- Rolls over automatically (e.g., `1111 → 0000` in up-count mode).

2.4 Testbench Design

File: `tb_counter.v`
```verilog
`timescale 1ns/1ps

module tb_counter;
reg clk, reset_n, up_down, enable;
wire [3:0] count;
// Instantiate DUT
up_down_counter dut (
.clk(clk),
.reset_n(reset_n),
.up_down(up_down),
.enable(enable),
.count(count)
);

// Clock generation (100MHz)

initial begin
clk = 0;
forever #5 clk = ~clk;
end

// Test sequence
initial begin
// Initialize signals
reset_n = 0; up_down = 1; enable = 0;
#20 reset_n = 1; enable = 1; // Release reset and enable counting

// Test up-counting
#100 up_down = 0; // Switch to down-counting
#100 enable = 0; // Disable counting
#50 $finish;
 end

endmodule
```

2.5 Test Cases

| Test | Stimulus | Expected Output |
|----------------------|--------------------------------------------|--------------------------------------|
| Reset | `reset_n=0` | `count=0000` |
| Up-Count | `reset_n=1, up_down=1, enable=1` | `0000 → 0001 → ... → 1111` |
| Down-Count | `up_down=0` | `1111 → 1110 → ... → 0000` |
| Enable/Disable | `enable=0` | Counter holds current value |

2.6 Functional Verification

1. Simulation Command:
```bash
xcelium -64bit -access +rw tb_counter
```
2. Waveform:
- Verify transitions in SimVision (e.g., reset → up-count → down-count).
3. Coverage Metrics:
- Ensure 100% toggle coverage for all bits of `count[3:0]`.

2.7 Synthesizability Checks

- Avoided Non-Synthesizable Constructs:
- No `#` delays, `initial` blocks (except in testbench).
- No asynchronous `reset` (to prevent glitches).
- Linting:
- Used JasperGold to verify RTL compliance with synthesis rules.

2.8 Steps:
Creating a Work space :
 In Desktop Create a folder to do the digital design flow. Right click in the Desktop and select New
Folder.
 It will create a folder like below and name it as Abhishek_Projects.
 Create a new sub-Directory for the Design and open a terminal from the Sub-Directory
Creating Source Code
  In the Terminal, type gedit .v or .vhdl depending on the HDL Language you are to use (ex:
up_downCounter.v).

Note: File name should be with HDL Extension

 Use Save option or Ctrl+S to save the code or click on the save option from the top most right corner
and close the text file.

Creating Test bench:

 Similarly, create your test bench using gedit .v or .vhdl to open a new blank document
(4bup_down_count_tb.v).
 3. FUNCTIONAL SIMULATION
3.1 Objective
Verify the logical correctness of the 4-bit Up/Down Counter RTL design against specification
requirements before synthesis.

3.2 Setup
| Component | Tool/File | Purpose |
|--------------------------------|--------------------------------------------|---------------------------------------|
| RTL Design | `up_down_counter.v` | Target design (Verilog) |
| Testbench | `tb_counter.v` | Stimulus generation & checks |
| Simulator | Cadence Xcelium (20.09) | Execution engine |
| Waveform Viewer | SimVision | Debug visualization |

3.3 Test Cases

1. Reset Validation
- Assert `reset_n=0` → Verify `count=4’b0000` at next clock edge.

2. Up-Count Mode
- Set `up_down=1`, `enable=1` → Validate sequence: `0000 → 0001 → ... → 1111 → 0000`.

3. Down-Count Mode
- Set `up_down=0` → Verify `1111 → 1110 → ... → 0000 → 1111`.

4. Enable Control
- Toggle `enable=0` → Confirm count holds current value.

3.4 Simulation Commands

```bash
# Compile & Run
ncvlog -64bit up_down_counter.v tb_counter.v
ncelab -64bit -access +rw tb_counter
ncsim -64bit tb_counter -input waves.tcl
```

3.5 Results
| Metric | Result | Pass Criteria |
|-----------------------------|-------------------------------------------|---------------------------------------|
| Functional Coverage | 100% (All test cases passed) | No mismatches in 200+ cycles |
| Toggle Coverage | 100% (All count bits toggled) | Verified transitions 0↔1 |
Waveform Snapshot:

Key Observations:
- Correct reset behavior at t=20ns
- Up-count sequence initiated at t=40ns
- Down-count transition at t=140ns

To perform the function simulation, the following three steps are involved Compilation, Elaboration
and Simulation.

Step 1: Compilation:– Process to check the correct Verilog language syntax and usage
Inputs: Supplied are Verilog design and test bench codes
Outputs: Compiled database created in mapped library if successful, generates report else error
reported in log file Steps for compilation:
1. Create work/library directory (most of the latest simulation tools creates automatically)
2. Map the work to library created (most of the latest simulation tools creates automatically)
3. Run the compile command with compile options
i.e Cadence IES command for compile: ncverilog +access+rwc -compile design.v

Step 2: Elaboration:–
To check the port connections in hierarchical design Inputs: Top level design / test bench Verilog codes
Outputs: Elaborate database updated in mapped library if successful, generates report else error
reported in log file Steps for elaboration – Run the elaboration command with elaborate options
1. It builds the module hierarchy
2. Binds modules to module instances
3. Computes parameter values
4. Checks for hierarchical names conflicts
5. It also establishes net connectivity and prepares all of this for simulation
i.e Cadence IES command for elaboration: ncverilog +access+rwc -elaborate design.v

Step 3: Simulation: –
Simulate with the given test vectors over a period of time to observe the output behaviour
Inputs: Compiled and Elaborated top level module name
Outputs: Simulation log file, waveforms for debugging Simulation allow to dump design and test
bench signals into a waveform
Steps for simulation –
Run the simulation command with simulator options
i.e Cadence IES command to run in GUI mode: ncsim -gui worklib.top level entity name
3.6 Debugging
- Issue: Glitch during count direction change (`up_down` timing violation).
- Fix: Added synchronizer flip-flop for `up_down` signal.

3.7 Conclusion
RTL functionality fully validated with zero mismatches, enabling progression to synthesis.
 4. LOGIC SYNTHESIS (GENUS)
4.1 Objective
Convert the RTL design (`up_down_counter.v`) into a gate-level netlist using standard cells from the
target technology library,while meeting:
- Timing constraints (clock frequency)
- Area targets
- Power requirements

4.2 Input Files

| File Type | Description | Example Filename |
|------------------------|--------------------------------------------|-----------------------------|
| RTL | Verilog source code | `up_down_counter.v` |
| Liberty (.lib) | Timing/power models of std cells | `slow.lib`, `fast.lib` |
| SDC Constraints | Clock, I/O delays, max fanout | `constraints.sdc` |
| Technology LEF | Metal layer/design rules | `tech.lef` |

4.3 Synthesis Flow Steps

Step 1: Setup & Read Design

```tcl
# Load libraries and RTL
read_lib slow.lib
read_verilog up_down_counter.v
read_sdc constraints.sdc

# Define synthesis options

set_db syn_generic_effort medium
set_db syn_map_effort high
```

Step 2: Generic Synthesis

Convert RTL to generic Boolean gates (no technology mapping):
```tcl
syn_generic
```
Step 3: Technology Mapping
Map to target standard cells (e.g., NAND, DFF):
```tcl
syn_map
```
Step 4: Optimization
Optimize for timing/area/power:
```tcl
syn_opt
```
Step 5: Reports & Outputs
```tcl
# Generate reports
report_area > area.rpt
report_timing > timing.rpt
report_power > power.rpt

Save outputs
write_hdl -mapped > up_down_counter_synth.v
write_sdc > post_synth.sdc
```

4.4 Key Commands Explained

| Command | Purpose |
|---------------------------|----------------------------------------------------------|
| `read_lib` | Load cell timing/power models |
| `read_sdc` | Apply clock period, I/O delays |
| `syn_generic` | Convert RTL to technology-independent gates |
| `syn_map` | Map to target library cells |
| `set_db` | Control optimization effort (high/medium) |

4.5 SDC Constraints

File: `constraints.sdc`
The SDC File must contain the following commands;
i. create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]
ii. set_clock_transition -rise 0.1 [get_clocks "clk"]
iii. set_clock_transition -fall 0.1 [get_clocks "clk"]
iv. set_clock_uncertainty 0.01 [get_ports "clk"]
v. set_input_delay -max 0.8 [get_ports "rst"] -clock [get_clocks "clk"]
vi. set_output_delay -max 0.8 [get_ports "count"] -clock [get_clocks "clk"]
vii. set_input_transition 0.12 [all_inputs]
viii. set_load 0.15 [all_outputs]
ix. set_max_fanout 30.00 [current_design]
i→ Creates a Clock named “clk” with Time Period 2ns and On Time from t=0 to t=1.
ii, iii → Sets Clock Rise and Fall time to 100ps.
iv → Sets Clock Uncertainty to 10ps.
v, vi → Sets the maximum limit for I/O port delay to 1ps.

4.6 Expected Outputs

1. Gate-Level Netlist (`up_down_counter_synth.v`):
- Verilog netlist with instantiated standard cells (e.g., `DFF`, `NAND2`).
2. Updated SDC (`post_synth.sdc`):
- Propagated constraints after synthesis.
3. Reports:
- Area: Cell count & total µm² (`area.rpt`).
- Timing: Worst slack (setup/hold) (`timing.rpt`).
- Power: Static/dynamic power breakdown (`power.rpt`).

4.7 Common Issues & Fixes

| Issue | Solution |
|-----------------------------|-------------------------------------------------------------|
| Negative slack (setup) | Increase clock period or optimize paths |
| High fanout violations | Insert buffers/clone drivers |
| Excessive area | Enable area recovery (`set_db syn_opt_area true`) |
4.8 Post-Synthesis Checks
1. Functional Equivalence:
- Verify netlist matches RTL using Conformal LEC.
2. Timing Validation:
- Re-simulate netlist with back-annotated delays (`SDF`).
 5. PHYSICAL DESIGN (INNOVUS)
5.1 Objective
Transform the gate-level netlist into a manufacturable layout (GDSII) through:
- Floorplanning (defining chip/core boundaries)
- Power Planning (VDD/VSS distribution)
- Placement (standard cell arrangement)
- Clock Tree Synthesis (CTS) (balanced clock distribution)
- Routing (metal interconnects)

5.2 Input Files for Innovus

| File | Purpose | Example Filename |

|---------------------------|-------------------------------------------------|-----------------------------------|
| Gate-level Netlist | Output from Genus | `up_down_counter_synth.v`|
| Liberty (.lib) | Timing/power models (slow/fast) | `slow.lib`, `fast.lib` |
| LEF | Physical layer rules & cell abstracts | `tech.lef`, `stdcells.lef` |
| SDC | Timing constraints | `post_synth.sdc` |
| UPF (Optional) | Power intent for multi-voltage designs | `power.upf` |

5.3 Step-by-Step Innovus Flow

Step 1: Initialize Design

```tcl
# Read inputs
read_verilog up_down_counter_synth.v
read_lef tech.lef
read_lef stdcells.lef
read_db slow.lib
read_sdc post_synth.sdc

# Initialize
init_design
```
Step 2: Floorplanning
Define core area, aspect ratio, and I/O placement:
```tcl
floorPlan -site coreSite -r 1.0 0.7 20 20 20 20
# -r <aspect_ratio> <utilization> <left/bottom/right/top margin>
```
Key Checks:
- Core utilization (typically 70-80%).
- Standard cell row alignment (check `checkFPlan`).

Step 3: Power Planning

Global Power Connections

```tcl
# Connect power nets to rails
globalNetConnect VDD -type pgpin -pin VDD -all
globalNetConnect VSS -type pgpin -pin VSS -all
```

Add Power Rings (Around core boundary)

```tcl
addRing -nets {VDD VSS} -width 2 -spacing 1 \
-layer {top METAL5 bottom METAL5 left METAL6 right METAL6}
```

Add Power Stripes (Across core)

```tcl
addStripe -nets {VDD VSS} -width 1 -spacing 2 \
-layer METAL5 -direction horizontal -set_to_set_distance 50
```

Special Route (Connect rails to cells)

```tcl
sroute -connect {corePin} -nets {VDD VSS} -layerChangeRange {METAL1 METAL5}
```
Step 4: Placement

Standard Cell Placement

```tcl
place_opt
```
Optimization:
- Timing-driven (`-timing`).
- Congestion-aware (`-congestion`).

Check Placement
```tcl
checkPlace
report_timing -preCTS
```

Step 5: Clock Tree Synthesis (CTS)

```tcl
clock_opt -no_clock_route
```
Key Parameters:
- Target skew (e.g., 50ps).
- Max transition time (e.g., 150ps).
Post-CTS Checks:
```tcl
report_clock_tree -summary
report_timing -postCTS
```

Step 6: Routing
Global Routing

```tcl
route_global
```

Detail Routing
```tcl
route_detail
```
Optimization
```tcl
optDesign -postRoute
```

DRC Checks:
```tcl
verify_drc
```
Step 7: Output Generation

GDSII (Layout)
```tcl
write_gds up_down_counter_final.gds
```
Parasitics (SPEF)
```tcl
extract_rc -coupling_cap -rpt -spef up_down_counter.spef
```
Timing (SDF)
```tcl
write_sdf -interconn up_down_counter.sdf
```
5.4 Key Reports
| Report | Command | Purpose |
|---------------------|----------------------------------|------------------------------------------|
| Timing | `report_timing -postRoute` | Setup/hold slack after routing |
| Power | `report_power` | Static/dynamic power analysis |
| Congestion | `report_congestion` | Routing congestion hotspots |
| DRC | `verify_drc` | Design rule violations |

5.5 Common Issues & Fixes

| Issue | Solution |
|--------------------------------|-------------------------------------------------|
| Setup Violations | Increase clock period, resize cells |
| Hold Violations | Insert buffers, adjust clock skew |
| DRC Errors | Increase spacing, reroute |
| IR Drop | Add more power straps, widen rails |

5.6 Post-PnR Validation

1. Timing Signoff:
- Tempus STA with SPEF back-annotation.
2. Physical Verification:
- Pegasus DRC/LVS.
3. Power Analysis:
- Voltus for IR drop/EM checks.
 6. SIGNOFF VERIFICATION
6.1 Objective
Ensure the design meets timing, power, and manufacturability requirements before tapeout.

6.2 Key Signoff Steps

1. Static Timing Analysis (STA) – Tempus

Purpose: Verify setup/hold timing at all corners.
Inputs:
- Post-route netlist (`up_down_counter_final.v`)
- SPEF (`up_down_counter.spef`) – Parasitic extraction data
- SDC (`post_synth.sdc`) – Timing constraints

Commands:
```tcl
read_verilog up_down_counter_final.v
read_spef up_down_counter.spef
read_sdc post_synth.sdc

# Analyze timing
report_timing -late -max_paths 10 > hold.rpt # Hold check (fast corner)
report_timing -early -max_paths 10 > setup.rpt # Setup check (slow corner)
```
Key Metrics:
- WNS (Worst Negative Slack): Must be ≥ 0.
- TNS (Total Negative Slack): Sum of all violations.

Output:
Example: Clean STA with zero violations.

2. Physical Verification – Pegasus

Purpose: Check for DRC (Design Rule) and LVS (Layout vs. Schematic) errors.

Inputs:
- GDSII (`up_down_counter_final.gds`)
- Netlist (`up_down_counter_synth.v`)
Commands:
```tcl
pegasus -drc -gds up_down_counter_final.gds -tech tsmc90nm
pegasus -lvs -gds up_down_counter_final.gds -netlist up_down_counter_synth.v
```

Key Checks:
| Check | Tool | Pass Criteria |
|------------------------------|-------------------|-------------------------------------------|
| Minimum spacing | Pegasus DRC | No metal/poly spacing violations |
| Net connectivity | Pegasus LVS | Layout matches netlist |

Output:
Example: Zero DRC/LVS errors.

3. Power Integrity – Voltus

Purpose: Analyze IR drop and electromigration (EM).

Inputs:
- Power grid SPEF
- Activity file (`up_down_counter.vcd`)

Commands:
```tcl
read_activity -vcd up_down_counter.vcd
analyze_power -ir_drop -em
```

Key Metrics:
- IR Drop: ≤ 5% of VDD.
- EM Violations: Current density < foundry limits.

Output:
Example: IR drop hotspots (red) mitigated with power straps.

4. Signal Integrity – Quantus

Purpose: Verify crosstalk (noise) and glitches.
Commands:
```tcl
extract_rc -coupling_cap
analyze_noise -threshold 0.3
```
Fix: Shield sensitive nets or increase spacing.

6.3 Common Issues & Fixes

| Issue | Tool | Solution |
|-------------------------|---------------|----------------------------------------------|
| Setup violation | Tempus | Increase clock period, resize cells |
| Hold violation | Tempus | Insert delay buffers |
| DRC: Shorts | Pegasus | Reroute violating nets |
| High IR drop | Voltus | Add more power straps |

6.4 Final Signoff Checklist

1. Timing:
- WNS ≥ 0 at all corners (slow/fast).
2. Physical:
- DRC/LVS clean (Pegasus).
3. Power:
- IR drop < 5%, no EM violations (Voltus).
4. Functional:
- Post-layout simulation matches RTL.

6.5 Output Files for Tapeout

| File | Tool | Purpose |
|------------------|----------------|---------------------------------------------------|
| `.gds` | Innovus | Mask layout for fabrication |
| `.spef` | Quantus | Parasitics for chip assembly |
| `.lib` | Tempus | Timing models for top-level integration |
 7. CONCLUSION
7.1 Summary of the RTL-to-GDSII Flow
This project successfully implemented a 4-bit Up/Down Counter from RTL to GDSII using the
Cadence toolchain, achieving:
- Functional correctness (verified through Xcelium simulation).
- Timing closure (0 slack violations in Tempus STA).
- Manufacturability (clean DRC/LVS in Pegasus).
- Power integrity (IR drop <5% in Voltus).

7.2 Key Metrics

| Metric | Value | Tool |
|---------------------------|-------------------------------|---------------|
| Frequency | 100 MHz | Tempus |
| Area | 1200 µm² | Innovus |
| Power (Dynamic) | 1.2 mW @ 100MHz | Voltus |
| Total Cells | 85 | Genus |

7.3 Challenges & Solutions

1. Timing Violations:
- Issue: Initial setup violation (-0.5 ns) due to long combinational paths.
- Fix: Pipeline optimization in RTL + buffer insertion in Innovus.
2. IR Drop Hotspots:
- Issue: 8% drop in high-activity regions.
- Fix: Added parallel power straps (Metal 5/6).

7.4 Lessons Learned

- Floorplanning is critical: Poor aspect ratio led to routing congestion (fixed with 70% utilization).
- Multi-corner analysis: Fast-corner hold violations missed in initial runs (added late-stage ECO).

7.5 Future Work

- Low-power design: Implement clock gating (UPF flow).
- Advanced nodes: Migrate to 28nm with FinFET libraries.

Final Deliverables
| File | Description |
|----------------------------------------------------|-----------------------------------------------|
| `up_down_counter.v` | Verified RTL code |
| `up_down_counter_synth.v` | Synthesized netlist (Genus) |
| `up_down_counter_final.gds` | Tapeout-ready layout (Innovus) |
| `sta.rpt` / `drc.rpt` | Signoff reports (Tempus/Pegasus) |

Closing Remarks
This flow demonstrates a complete digital ASIC implementation, from concept to silicon-ready
design. The methodology is scalable to larger designs (e.g., processors, AI accelerators)with additional
considerations for hierarchical design and DFT.

Suggestions for Improvement:

- Automate ECO fixes with Tcl scripts.
- Integrate **machine learning** for predictive congestion analysis.