Electronics system design using FPGA

Spartan-7
FPGA

By Praveen Sah copyright Copyright: Praveen Sah 1

 Programmable Logic Device

Unprogrammed Programmed

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 FPGA Introduction Traditional Logic device

➢ FPGA stands for Field Programmable Gate Array. It belongs to the

family of logic devices. It is also referred programmable hardware.

➢ An FPGA is made up of a grid of configurable logic, known as adaptive

logic modules (ALMs), and specialized blocks, such as digital signal
processing (DSP) blocks and random-access memory (RAM) blocks.
These programmable blocks are combined via configurable routing
interconnects to implement complete digital circuits.

➢ The functionality inside the device can be changed by changing what FPGA device
electrical inputs and outputs are being received, what logical gates
and flipflops are implemented, and how those gates are being
connected.

➢ Essentially, an FPGA doesn’t do anything itself, but it can be

configured to be just about any digital circuit you want. The magic
here is that nothing physically changes. You simply load a
configuration into the FPGA, and it starts behaving like the circuit you
wanted. No soldering, no jumper wires, no fuss.

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 Configurable Logic Block (CLB)
➢ Each CLB is connected to a switch matrix for accessing common
wiring resources. A CLB contains a pair of slices. A Slice contains
lookup tables, flip-flops, multiplexers, and arithmetic carry logic.

➢ Look-up--table, or LUT for short is essentially a RAM. Currently, 4-input

LUTs are mostly used, so each LUT can be regarded as a RAM with a 4-bit
address line. After the user describes a logic circuit through the schematic
diagram or HDL, the FPGA development software will automatically
calculate all possible results of the logic circuit and write the truth table
into RAM.
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Programmable Switch Matrix (PSM)

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Configurable IO Block (IOB)

IOB (Input Output Block) is a programmable input and output unit, which is the interface points between the FPGA and external devices or other
components on the board. IOBs are configurable to support various signaling standards and protocols, enabling the FPGA to communicate with a
wide range of peripherals

➢ The I/O in the FPGA is classified, and each group can independently
support different I/O standards. Through the flexible configuration of
the software, it can adapt to different electrical standards and I/O
physical characteristics, can adjust the size of the drive current, and
can change the up and down resistance
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What’s behind a FPGA?

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FPGA design flow
Requirements Specification

Architecture

Design Entry
No

VHDL/Verilog /
Behavioral Simulation OK?
Schematics
Yes
Synthesis
No
Vendor Netlist Functional Simulation OK?
Libraries
Yes
Translate, Map, Place & Route
No
Static Timing Analysis OK?
Netlist, Timing, Back
annotation Timing Simulation Yes

Bitstream Generation
Synthesis tools verify the design for syntax errors and do block-level floor
planning. Always follow vendor-specific coding guidelines and library modules
Bitstream for better optimization of the design.
Translate process combines all the input netlists and constraints to a logic
Configure FPGA design file. Constraints assign the signal with its corresponding FPGA pin
number, I/O voltage levels, current-driving strength, clock frequency of the
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FPGA strength
Parallel Task Performance
1) FPGAs Work in Parallel – . CPUs/GPUs work sequentially, processing
one piece at a time, but with a well-configured FPGA you’ll be able
Reconfigurable to simultaneously intake and process the next batch of information before
the first batch is done, giving a low latency.

2) FPGAs are Reconfigurable – The configurability of your average FPGA

Better Performance leaves ASICs in the dust., the real value lies in being able to
reconfigure (and reconfigure again) after installation – something
that ASICs just can’t do.

Low Latency 4) FPGAs Have Optimal Performance per Watt – When compared with
a CPU or GPU, you will be getting higher performance per watt (though it
is closer when using floating point arithmetic) with an FPGA. This low
power consumption can be nearly 3 to 4 times less than that of a GPU.

Faster Time to Market

3) FPGAS Perform Time-Critical Processing – With
the low latency, engineers and developers are able to use FPGAs for
applications that require very time-critical calculations; like software-
Simpler Design Cycles defined radio, medical devices, and mil-aero systems.

5) No OS Overhead – If the latency and computational power of a

CPU/GPU would be comparable to an FPGA, the inside track is lost by the
necessity of running an operating system. The OS brings down
Adaptability the processing cost efficiency, as resources need to be dedicated to it,
increasing the power used and decreasing the compute power.

No OS Overhead copyright By Praveen9Sah

How to choose FPGA for your design? ➢ I/O count ➢ Temperature

FPGA Trade Study

➢ Look at all requirements for Project
➢ Find Solutions that satisfy requirements
➢ Weigh requirements by importance
➢ Down select ➢ Cost

➢ Hard IP blocks
➢ Resources

➢ Miscellaneous ➢ Power ➢ Operating Frequency

• Boot Times
• Instant On flash based or SRAM
based
• Radiation
• Size
• Ball Pitch
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Design Considerations
➢ Power Sequence ➢ Configuration ➢ Reset ➢ Mode

➢ Clock ➢ IO’s bank ➢ JTAG

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FPGA Vs Microcontroller

FPGA MCU
Customizability. high degree of customizability. Execute a program and carry out general tasks
because the ISA and their circuitry are fixed. A
programmer must abide by the restrictions while
developing code of Microcontroller
Reprogramming Fully reprogrammable at the hardware level Varies: relies on embedded operating system,
dynamic
Parallelization Can be configured during programming Limited by hardware architecture

Programming time Longer: requires recoding and recompiling Shorter: aided by manufacturer SDKs and libraries
everything to machine code
Ease of programming Seen as having a steeper learning curve Easy: anyone familiar with common languages can
code
Power consumption Higher Lower

Fixed vs. floating point Configured for fixed point, but floating point can Both are accessible
be implemented during programming
Languages Hardware description language (HDL) C/Assembly language, others if supported by RTOS
(e.g. Python)

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How to choose the right one for your Project?
Example #2
How to choose?
Russell is tasked with taking ultrasound sensor
data and determining distance to objects.
➢ Know your requirements
➢ What’s #1, #2, #3 most important?
Req #1 - Proof of concept needed in 2 months
➢ Weigh solutions and pick best
Req #2 - Cost
Req #3 - Low Power
Example #1 Req #4 – Basic math, can be slow
Jack is tasked with taking HD image data from a computer,
filtering it, and sending it to an OLED screen to display.

Req #1 - Need custom interfaces Winner – Microcontroller

Req #2 - Lots of Math Amazon “Scout ” autonomous delivery
Req #3 - Low Power
Req #4 - Cost

Winner – FPGA
Oculus Rift VR Headset

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 Static Timing Analysis

• Positive Slack- good

• Negative Slack- bad

RTL simulation is a simulation of the code directly,

without timing information, and does not require
code compilation. It is supported only in VHDL and
Verilog. Gate level simulation, on the other hand, is a
simulation of the compiled netlist, and considers the
delay of the gates during verification. The delays will
change according to the library used for synthesis.

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 ◦ By Praveen Sah

“Creativity is thinking up new things. Innovation is doing new things.” ~ Theodore Levitt

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