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Day 6 Adders

The document provides an overview of various types of adders used in digital circuits, including Half Adders, Full Adders, Ripple Carry Adders, and Carry Look Ahead Adders. It explains their functionalities, truth tables, logic diagrams, and applications, highlighting the differences in speed and complexity. Additionally, it discusses the advantages and disadvantages of Ripple Carry Adders and the high-speed capabilities of Carry Look Ahead Adders.

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9 views10 pages

Day 6 Adders

The document provides an overview of various types of adders used in digital circuits, including Half Adders, Full Adders, Ripple Carry Adders, and Carry Look Ahead Adders. It explains their functionalities, truth tables, logic diagrams, and applications, highlighting the differences in speed and complexity. Additionally, it discusses the advantages and disadvantages of Ripple Carry Adders and the high-speed capabilities of Carry Look Ahead Adders.

Uploaded by

kollasunnykumar123
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Date:- 06/04/2025

Day - 6
ADDERS

SRI VENKATA KASYAP CHALLAPALLI


CONTENT TABLE
S. No Topic

1. Half Adders

2. Full Adder

3. Full Adder using Half Adders

4. Full Adder using Universal gates

5. Ripple Carry Adder

6. Carry Look Ahead Adder


1. Half Adder
A half adder is a basic combinational circuit that adds two 1-bit binary numbers
and produces a sum (S) and a carry (C).

Step 1: Identify the both Input and Output variables.


Inputs: A, B
Outputs: Sum (S), Carry (C)
Step 2: Draw the truth table

A B Sum (S) Carry (C)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
1. Half Adder
Step 3: Draw the K - maps for the above truth table and determine the Boolean
function for the truth table.
Step 4: Draw the logic diagram

K-Map for a Half Adder

Logic Diagram of an Half Adder


Applications
Used as a building block in full adders.
Simple arithmetic circuits where carry propagation isn’t needed.
2. Full Adder
A full adder is a combinational circuit that adds three 1-bit binary numbers (A,
B, and Carry-in, Cin) and produces a Sum (S) and Carry-out (Cout). Unlike a
half adder, it accounts for carry propagation, making it essential for multi-bit
addition (e.g., in CPUs).

Step 1: Identify the both Input and Output variables.


Inputs: A, B, Cin
Outputs: Sum (S), Carry (Cout)
Step 2: Draw the truth table

A B Cin Sum (S) Carry (Cout)

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
2. Full Adder
Step 3: Draw the K - maps for the above truth table and determine the Boolean
function for the truth table.
Step 4: Draw the logic diagram

K-Map for a Full Adder

Logic Diagram of an Full Adder


3. Full Adder using Half Adders
A full adder can be constructed using two half adders (HA) and one OR gate.

4. Full Adder using Universal Gates

Full Adder using NAND Gate

Full Adder using NOR Gate


5. Ripple Carry Adder
A Ripple Carry Adder (RCA) is a digital circuit that adds two n-bit binary
numbers by cascading n full adders (FAs) in series, where the carry-out (Cout)
of each stage propagates to the next stage’s carry-in (Cin).

4 Bit Parallel Adder or 4 Bit Ripple Carry Adder

Delay Calculation:
Critical Path Delay = n × T_FA (where T_FA = delay of one full adder).
Slow for large n (e.g., 32-bit RCA is 32× slower than 1-bit FA).

Advantages & Disadvantages:


Pros:
1. Simple design (minimal hardware)
2. Low power
3. Easy to implement
Cons:
1. Slow O(n) due to carry delay.
2. Not scalable for high speed apps.
3. Poor for Large bits widths.

Applications:
1. Low-speed arithmetic units (e.g., calculators).
2. Educational purposes (teaching adder fundamentals).
3. Embedded systems where area > speed.
6. Carry Look Ahead Adder
The Carry Look-Ahead Adder (CLA) is a high-speed parallel adder that reduces
carry propagation delay by computing carry signals in advance using generate
(G) and propagate (P) logic. Unlike the Ripple Carry Adder (RCA), which has
O(n) delay, the CLA achieves O(log n) delay, making it ideal for high-
performance systems.

4 Bit Parallel Adder or 4 Bit Ripple Carry Adder


Key Concepts:
1. Generate (G) and Propagate (P) Signals
Generate (Gᵢ): Indicates if bit i produces a carry-out (Gᵢ = Aᵢ · Bᵢ).
Propagate (Pᵢ): Indicates if bit i passes a carry-in (Pᵢ = Aᵢ ⊕ Bᵢ).
2. Carry Computation
The carry for bit i+1 is:
Ci+1=Gi+(Pi⋅ Ci)Ci+1​=Gi​+(Pi​⋅Ci​)
Expands recursively (e.g., for 4-bit CLA):
C1=G0+(P0⋅C0)C2=G1+(P1⋅G0)+(P1⋅P0⋅C0)C3=G2+(P2⋅G1)+
(P2⋅P1⋅G0)+(P2⋅P1⋅P0⋅C0)C1​C2​C3​​=G0​+(P0​⋅C0​)=G1​+(P1​⋅G0​)+(P1​⋅P0​
⋅C0​)=G2​+(P2​⋅G1​)+(P2​⋅P1​⋅G0​)+(P2​⋅P1​⋅P0​⋅C0​)​
No ripple delay—carries are computed simultaneously.
3. Sum Calculation
Sum at bit i:
Si=Pi⊕CiSi​=Pi​⊕Ci​
6. Carry Look Ahead Adder
Applications
1. High-speed ALUs (in CPUs/GPUs).
2. Cryptography accelerators (where fast addition is critical).
3. DSP chips (e.g., FFT processors).

Limitations
1. Complexity: Requires additional gates for G/P logic.
2. Power Consumption: Higher than RCA due to parallel computation.
3. Fan-Out Issues: Large n (e.g., 64-bit) requires multi-level CLA.

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