SISO

RCA-STR

FA+ TB

UDP- theory

MELAY FSM

FF verilog + RAM

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1.SISO 4 bit code

module siso_214(si,rst,clk,so);

input si,rst,clk;

output so;

reg so;

reg [3:0]q;

always@(si,rst,clk)

begin

if(rst == 1)

begin

so = 1'bZ;

q = 4'b0000;

end

else

begin

q[3] = si;

q[2] = q[3];

q[1] = q[2];

q[0] = q[1];

so = q[0];

end

end

endmodule
1.SISO 8-BIT CODE (optional for reference only)

module siso(si, clk, rst, so);

input si,clk,rst;

output so;

reg so;

reg [7:0]q;

always @ (si, rst, clk)

begin

if (rst==1)

begin

so =1'bz;

q = 8'b00000000;

end

else

begin

q[7] = si;

q[6] = q[7];

q[5] = q[5];

q[4] = q[5];

q[3] = q[4];

q[2] = q[3];

q[1] = q[2];

q[0] = q[1];

so = q[0];

end

end

endmodule
2.4- bit Ripple Carry Adder

module RCA_214(a,b,c0,s,c4);

input[3:0]a,b;

input c0;

output[3:0]s;

output c4;

wire c1,c2,c3;

FA adder1(a[0],b[0],c0,s[0],c1),

FA adder2(a[1],b[1],c1,s[1],c2),

FA adder3(a[2],b[2],c2,s[2],c3),

FA adder4(a[3],b[3],c3,s[3],c4);

endmodule

module FA(x,y,z,sum,carry);

input x, y, z;

output sum,carry;

assign sum=x^y^z;

assign carry= (x&y)|(y&z)|(z&x);

endmodule
Q: Explain User Defined Primitives (UDP) in Verilog with examples.

Answer:

In Verilog, User Defined Primitives (UDP) allow designers to create custom logic functions
beyond the predefined primitive gates. These are mainly used to define small combinational
or sequential logic blocks.

1. Features of UDPs:

 UDPs are declared using the primitive and endprimitive keywords.

 They reduce memory usage in simulation.
 Only scalar inputs and outputs are allowed (no vectors or inouts).
 Two types:
o Combinational
o Sequential (level-sensitive or edge-sensitive)
 UDPs are instantiated just like primitive gates.

2. UDP Table Symbols:

Symbol Meaning
0 Logic 0
1 Logic 1
x Unknown
? Any of 0, 1, or x (don’t care)
b 0 or 1
- No change
(vw) Change from v to w
* Any value change
r Rising edge (01)
f Falling edge (10)
p Positive edge (01, 0x, x1)
n Negative edge (10, 1x, x0)

3. Example – Combinational UDP (2x1 MUX):

primitive mux2X1(o,a,b,s);
output o;
input a,b,s;
table
// a b s : o
0 ? 1 : 0;
1 ? 1 : 1;
? 0 0 : 0;
? 1 0 : 1;
0 0 x : 0;
1 1 x : 1;
endtable
endprimitive

 Output port must come first.

 Each row represents a unique input combination and corresponding output.
 Unspecified input combinations default to 'x' (unknown).

4. Using UDPs in Larger Designs – 4x1 MUX:

module mux4X1 (Z, A, B, C, D, sel);

input A, B, C, D;
input [2:1] sel;
output Z;

mux2X1 (TL, A, B, sel[1]),

(TP, C, D, sel[1]),
(Z, TL, TP, sel[2]);

endmodule

5. Level-Sensitive Sequential UDP:

primitive latch(q, clock, data);

output q;
reg q;
input clock, data;
table
// clock data : state_output : next_state
1 1 : ? : 1;
1 0 : ? : 0;
0 ? : ? : -;
endtable
endprimitive

 ?= don't care, - = no change

 Output depends on input level.

6. Edge-Triggered Sequential UDP (D Flip-Flop):

primitive d_edge_ff(q, clock, data);
output q;
reg q;
input clock, data;
table
(01) 0 : ? : 0;
(01) 1 : ? : 1;
(0x) 1 : 1 : 1;
(0x) 0 : 0 : 0;
endtable
endprimitive

 Triggered on rising edge (01).

 Useful for flip-flops and clocked storage.

7. Example – 3-bit Majority Circuit UDP:

verilog
CopyEdit
primitive majority3(Z, A, B, C);
input A, B, C;
output Z;
table
0 0 ? : 0;
0 ? 0 : 0;
? 0 0 : 0;
1 1 ? : 1;
1 ? 1 : 1;
? 1 1 : 1;
endtable
endprimitive

 Output is 1 if two or more inputs are 1.

4. Full Adder Code with test bench

module full_adder ( a, b, cin, sum, cout);

input a, b, cin;

output sum, cout;

assign sum = a ^ b ^ cin;

assign cout = (a & b) | (b & cin) | (a & cin);

endmodule

module tb_full_adder;

reg a, b, cin;

wire sum, cout;

full_adder uut (.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

initial begin

$monitor("a=%b b=%b cin=%b | sum=%b cout=%b", a, b, cin, sum, cout);

a = 0; b = 0; cin = 0; #10;

a = 0; b = 0; cin = 1; #10;

a = 0; b = 1; cin = 0; #10;

a = 0; b = 1; cin = 1; #10;

a = 1; b = 0; cin = 0; #10;

a = 1; b = 0; cin = 1; #10;

a = 1; b = 1; cin = 0; #10;

a = 1; b = 1; cin = 1; #10;

end

endmodule
5.MEALY FSM

module mealyfsm(a, clk, z);

input a;

input clk;

output z;

reg z;

parameter st0 = 0, st1 = 1, st2 = 2, st3 = 3;

reg [0:1] mealy_state;

initial begin

mealy_state = st0;

end

always @(posedge clk) begin

case (mealy_state)

st0: begin

if (a) begin

z = 1;

mealy_state = st3;

end else begin

z = 0;

end

end

st1: begin

if (a) begin

z = 0;

mealy_state = st0;

end else begin

 z = 1;

end

end

st2: begin

if (a) begin

z = 1;

mealy_state = st1;

end else begin

z = 0;

end

end

st3: begin

z = 0;

if (a) begin

mealy_state = st1;

end else begin

mealy_state = st2;

end

end

endcase

end

endmodule
6. 8 – BIT RAM

module ram(clk, wr_en, data_in, addr, data_out);

input clk;

input wr_en;

input [7:0] data_in;

input [3:0] addr;

output [7:0] data_out;

reg [7:0] data_out;

reg [7:0] mem [0:15];

always @(posedge clk or wr_en or data_in or addr) begin

if (clk) begin

if (wr_en)

mem[addr] = data_in;

else

data_out = mem[addr];

end

end

endmodule
6.B FLIPFLOPS

1.SR FLIPFLOP

module srff_214(s, r, clk, q, qbar);

input s, r, clk;
output q, qbar;
reg q, qbar;

always @(posedge clk) begin

q = 1'b0;
qbar = 1'b1;
if (clk == 1) begin
if (s == 0 && r == 0) begin
q = q;
qbar = qbar;
end
else if (s == 0 && r == 1) begin
q = 1'b0;
qbar = 1'b1;
end
else if (s == 1 && r == 0) begin
q = 1'b1;
qbar = 1'b0;
end
else if (s == 1 && r == 1) begin
q = 1'bx;
qbar = 1'bx;
end
end
if (clk == 0) begin
q = q;
qbar = qbar;
end
end
endmodule
2.JK FLIPFLOP

module jkff_214(j, k, clk, q, qbar);

input j, k, clk;
output q, qbar;
reg q, qbar;

always @(posedge clk) begin

q = 1'b0;
qbar = 1'b1;

if (clk == 1) begin
if (j == 0 && k == 0) begin
q = q;
qbar = qbar;
end
else if (j == 0 && k == 1) begin
q = 1'b0;
qbar = 1'b1;
end
else if (j == 1 && k == 0) begin
q = 1'b1;
qbar = 1'b0;
end
else if (j == 1 && k == 1) begin
q = ~q;
qbar = ~qbar;
end
end

if (clk == 0) begin
q = q;
qbar = qbar;
end
end
endmodule
3.D FLIPFLOP

module dff_214(d, clk, q, qbar);

input d, clk;

output q, qbar;

reg q, qbar;

always @(posedge clk) begin

q = 1'b0;

qbar = 1'b1;

if (clk == 1) begin

if (d == 0) begin

q = 1'b0;

qbar = 1'b1;

end

else if (d == 1) begin

q = 1'b1;

qbar = 1'b0;

end

end

if (clk == 0) begin

q = q;

qbar = qbar;

end

end

endmodule
4.T FLIPFLOP

module tff_214(t, clk, q, qbar);

input t, clk;

output q, qbar;

reg q, qbar;

always @(posedge clk) begin

q = 1'b0;

qbar = 1'b1;

if (clk == 1) begin

if (t == 0) begin

q = q;

qbar = qbar;

end

else if (t == 1) begin

q = ~q;

qbar = ~qbar;

end

end

if (clk == 0) begin

q = q;

qbar = qbar;

end

end

endmodule
2 Marks
1. Task and Function
Task:
 A task performs operations that may include timing delays.
 Can have multiple inputs/outputs.
task display_data;
input [3:0] data;
begin
$display("Data = %d", data);
end
endtask

Function:
 A function performs computation and returns a single value.
 Cannot include delays or time-consuming operations.
function [3:0] add;
input [3:0] a, b;
begin
add = a + b;
end
endfunction

2. Delay
Delays in Verilog are used to simulate the time behavior of digital circuits.
module delay_example;
reg a;
initial begin
a = 0;
#10 a = 1; // 10 time unit delay
end
endmodule
3. Procedural Constructs – Behavioral Modeling
Definition:
Procedural constructs in Verilog (initial and always blocks) describe sequential or behavioral logic in
digital design.

1. initial Block:
 Executes once at the start of simulation.
 Used for initialization and testbenches (not synthesizable).

initial begin
a = 0;
b = 1;
#10 a = 1; // Delay of 10 time units
End

2. always Block:
 Executes continuously based on changes in signals.
 Used for combinational or sequential logic (synthesizable).

always @(*) begin

sum = a + b;
end

Note:
 Use always @(*) for combinational logic.
 Use always @(posedge clk) for sequential logic (like flip-flops).