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Part B Interfacing Expts

The document outlines experiments involving interfacing a stepper motor, 7-segment display, and DAC with the 8051 microcontroller. It includes aims, theoretical background, circuit diagrams, and assembly language programs for each experiment. The results confirm successful execution and output verification for all experiments.

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0% found this document useful (0 votes)
20 views12 pages

Part B Interfacing Expts

The document outlines experiments involving interfacing a stepper motor, 7-segment display, and DAC with the 8051 microcontroller. It includes aims, theoretical background, circuit diagrams, and assembly language programs for each experiment. The results confirm successful execution and output verification for all experiments.

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Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT 13

STEPPER MOTOR INTERFACING WITH 8051


AIM:
Write an ALP to interface stepper motor with 8051 microcontroller in
a) Clock wise direction
b) Anti-clock wise direction

THEORY:

A motor in which the rotor is able to assume only discrete stationary angular
position is a stepper motor. The rotary motion occurs in a step-wise manner from one
equilibrium position to the next. Stepper Motors are used very wisely in position control
systems like printers, disk drives, process control machine tools, etc.

The basic two-phase stepper motor consists of two pairs of stator poles. Each of
the four poles has its own winding. The excitation of any one winding generates a North
Pole. A South Pole gets induced at the diametrically opposite side. The rotor magnetic
system has two end faces. It is a permanent magnet with one face as South Pole and the
other as North Pole.

The Stepper Motor windings A1, A2, B1, B2 are cyclically excited with a DC
current to run the motor in clockwise direction. By reversing the phase sequence as A1,
B2, A2, B1, anticlockwise stepping can be obtained.

2-PHASE SWITCHING SCHEME:

In this scheme, any two adjacent stator windings are energized. The switching
scheme is shown in the table given below. This scheme produces more torque.
ANTICLOCKWISE CLOCKWISE
STEP A1 A2 B1 B2 DATA STEP A1 A2 B1 B2 DATA

1 1 0 0 1 09h 1 1 0 1 0 0Ah

2 0 1 0 1 05h 2 0 1 1 0 06h

3 0 1 1 0 06h 3 0 1 0 1 05h

4 1 0 1 0 0Ah 4 1 0 0 1 09h

Look-up table

PROCEDURE:

Enter the above program starting from location 4100.and execute the same. The
stepper motor rotates. Varying the count at R1 and R3 can vary the speed. Entering the
data in the look-up TABLE in the reverse order can vary direction of rotation

CIRCUIT DIAGRAM:
PROGRAM:

ADDRESS OPCODE LABEL MNEMONCS COMMENTS

START MOV DPTR, #4500 Initialize the Data Pointer


(DPTR) to external
memory address 4500H
MOV R0, #04 Load register R0 with 4,
setting up a counter to
process 4 bytes
J0 MOVX A,@DPTR Move external memory
data from the address
pointed by DPTR into the
Accumulator (A)
PUSH DPH Save the high byte of
DPTR on the stack
PUSH DPL Save the low byte of
DPTR on the stack
MOV DPTR, #FFC0 Set DPTR to the external
memory address FFC0H
for writing data
MOV R2, #04 Initialize outermost delay
counter R2 with 4 (for
longer delay)
MOV R1, #FF Initialize middle delay
counter R1 with 255
DLY1 MOV R3,#FF Initialize innermost delay
counter R3 with 255
DLY DJNZ R3,DLY Decrement R3 and repeat
until R3 = 0 (innermost
delay loop)
DJNZ R1,DLY1 Decrement R1 and repeat
inner loop until R1 = 0
DJNZ R2,DLY1 Decrement R2 and repeat
the overall delay process
until R2 = 0
MOVX @DPTR,A Write the delayed data
from Accumulator (A) to
external memory at
address FFC0H
POP DPL Restore the low byte of
the original DPTR from
the stack
POP DPH Restore the high byte of
the original DPTR from
the stack
INC DPTR Increment DPTR to point
to the next data byte
DJNZ R0,J0 Decrement R0 (data
counter) and repeat loop if
more bytes remain
SJMP START Jump back to START,
creating an infinite loop

OBSERVATION:

Clock wise direction Anti-clock direction

Address Data Address Data

RESULT:
Program executed and output verified
EXPERIMENT 14
DISPLAY INTERFACING USING 8051
AIM:
Write an ALP to interface 7 segment display using 8051

THEORY:
The 7-segment display, also written as “seven segment display”, consists of seven LEDs
(hence its name) arranged in a rectangular fashion as shown. Each of the seven LEDs is called a
segment because when illuminated the segment forms part of a numerical digit (both Decimal and
Hex) to be displayed. An additional 8th LED is sometimes used within the same package thus
allowing the indication of a decimal point, (DP) when two or more 7-segment displays are
connected together to display numbers greater than ten.
Each one of the seven LEDs in the display is given a positional segment with one of its
connection pins being brought straight out of the rectangular plastic package. These individually
LED pins are labelled from a through to g representing each individual LED. The other LED pins
are connected together and wired to form a common pin.So by forward biasing the appropriate
pins of the LED segments in a particular order, some segments will be light and others will be dark
allowing the desired character pattern of the number to be generated on the display. This then
allows us to display each of the ten decimal digits 0 through to 9 on the same 7-segment display.
The displays common pin is generally used to identify which type of 7-segment display it
is. As each LED has two connecting pins, one called the “Anode” and the other called the
“Cathode”, there are therefore two types of LED 7-segment display called: Common Cathode (CC)
and Common Anode (CA).
The difference between the two displays, as their name suggests, is that the common
cathode has all the cathodes of the 7-segments connected directly together and the common anode
has all the anodes of the 7-segments connected together and is illuminated as follows.
The Common Cathode (CC) – In the common cathode display, all the cathode connections of the
LED segments are joined together to logic “0” or ground. The individual segments are illuminated
by application of a “HIGH”, or logic “1” signal via a current limiting resistor to forward bias the
individual Anode terminals (a-g).
CIRCUIT DIAGRAM:
PROGRAM:
ADDRESS OPCODE LABEL MNEMONCS COMMENTS

4100 MOV DPTR, #FFC0 Initialize the Data Pointer


to external memory
address 0xFFC0
4103 MOV A, #00 Load 0x00 into the
accumulator (potentially
to clear or initialize the
display)
4105 MOVX @DPTR,A Write the value to the
external memory (7-
segment display)
4106 MOV A, #CC Load 0xCC into the
accumulator

4108 MOVX @DPTR,A Write it to the same


external memory location
4109 MOV A,#90 Load 0x90 into the
accumulator
410B MOVX @DPTR,A Write it to the same
external memory location
410C MOV A,#DATA Load the value labeled
DATA (should be
predefined with a
segment code)
410E MOVX @DPTR,A Write it to the display

410F MOV R0, #05 Load register R0 with 5,


setting up a loop counter
4111 MOV A, #FF Load 0xFF into the
accumulator
4113 MOVX @DPTR,A Write it to the same
external memory location
4114 L1 DJNZ R0,L1 Decrement R0 and jump
to label L1 if R0 is not
zero (for loop execution)
4116 HERE SJMP HERE
Jump to the HERE label

OBSERVATION:
Input data Output Displayed

RESULT:
Program executed and output verified
EXPERIMENT 15
DAC INTERFACING USING 8051

AIM:
Write an assembly language program for interfacing 8051 Micro Controller with
DAC interface

THEORY:

ADC 0809 is a monolithic CMOS device, with an 8 bit analog to digital


converter, 8 channel multiplexer and microprocessor control logic. The main features of
ADC 0809 are

 8 bit resolution
 100µs conversion time
 8 channel multiplexer with latched control logic
 No need for external zero or full scale adjustments
 Low power consumption(15mW)
 Latched tristate output

PROCESS:

6. A particular input channel is selected by using address decoding.


7. The address is latched into the decoder of the chip on low to high transition of
the address latch enable (ALE).
8. The D/A converter successive approximation register is reset on the positive
edge of the start of conversion pulse.
9. The conversion is begun on the falling edge of the SOC pulse.
10. End of conversion will go low between 0 and 8 clock pulses after the rising edge
of start of conversion.
CIRCUIT DIAGRAM:

1. SQUARE WAVE GENERATION


AIM:
Write an ALP to generate a square wave with DAC interfacing and observe on
CRO/DSO

PROGRAM:
To generate the square wave at DAC With (00 H) as input to DAC, the analog output is
+5v. Similarly with FF (H) as input, the output is +5v.Outputting digital data 00 and FF
at regular intervals to DAC result in a square wave of amplitude 15 v
ADDRESS OPCODE LABEL MNEMONCS COMMENTS

4100 MOV DPTR, #FFC8 Sets the DPTR to the


external memory address
0xFFC8, where the output
device
4103 AGAIN MOV A, #00 Loads 0x00 into the
accumulator to represent
the LOW state
4105 MOVX @DPTR,A Writes the LOW state to
the external port
4106 ACALL DELAY Calls the delay routine to
keep the output LOW for
some time
4108 MOV A, #FF Loads 0xFF into the
accumulator to represent
the HIGH state.
410A MOVX @DPTR,A Writes the HIGH state to
the external port.
410B ACALL DELAY Delays to keep the output
HIGH for the same
duration.
410D SJMP AGAIN umps back to continue
generating the square
wave.
410F DELAY MOV R0, #B6 Loads the register R0 with
0xB6 (decimal 182) to set
the delay count.
4111 L0 DJNZ R0,L0 Decrements R0 and loops
back to L0 until R0 reaches
zero.
4113 RET Returns from the
subroutine after the delay.

RESULT:
Program executed and output verified.
2. TRIANGULAR WAVE GENERATION
AIM:
Write an ALP to generate a triangular wave with DAC interfacing
and observe on CRO/DSO

PROGRAM:

ADDRESS OPCODE LABEL MNEMONCS COMMENTS

MOV DPTR, #FFC8

MOV A, #00

LOOP1 MOVX @DPTR,A

INC A

CJNE A, #FF, LOOP1

LOOP2 MOVX @DPTR, A

DEC A

CJNE A, #00, LOOP2

SJMP LOOP1

RESULT:
Program executed and output verified.

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