Magnetic core memory reborn

Ben North, Oliver Nash

May 9, 2011

Abstract
We outline the theory of magnetic core memory, and describe the
design and fabrication of a core memory Arduino shield.

1 Introduction
1.1 What is magnetic core memory?
Magnetic core memory was the most widely used form of digital com- Core memory is an old
puter memory from its birth in the early 1950s until the era of in- memory technology.
tegrated-circuit memory began in the early 1970s. Aside from being
extremely reliable, magnetic core memory is an appealing technology
because it is based on a very simple idea.
A magnetic core is a ring of ferrite material. It can be permanently A core, a ring of magnetic
magnetised either clockwise or anti-clockwise about its axis just as material, stores one bit by
the direction of its
a vertical bar magnet can be magnetised up or down. We can then
magnetisation.
turn a magnetic core into a bit of digital memory by letting these two
magnetisation states correspond to 0 and 1.
The core needs no power to retain its data. In other words, core It provides non-volatile
memory is a form of non-volatile storage like modern hard disk drives, storage.
although in its day it fulfilled the ‘high-speed’ role of modern RAM.
With many such cores, large memory modules were made, such as
this example from a CDC machine of the mid-1960s. The right-hand
image shows a close-up of the cores themselves.

50 mm 2 mm

1
Cores were c.1 mm across, As the technology developed [1], the cores shrank from c.2 mm di-
and ran at c.1 MHz. Core ameter in the early 1950s to c.0·4 mm by the early 1970s. Access speeds
stores had up to 500,000
rose at the same time, from about 200 kHz to over 1 MHz, and core
cores.
memory modules were manufactured with as many as over half a mil-
lion cores. Furthermore, as recently as 2004, a magnetic core memory
system was found still in service in a telephony control system.
It is still an interesting Magnetic core memory continues to capture the imaginations of
technology even today. modern enthusiasts [2, 3], and it is also the origin of the term core
dump, to mean an on-disk image of the main memory of a process.

1.2 What is an Arduino?

The Arduino is a popular, The Arduino, whose Duemilanove version is shown above [5], is an
easy-to-use, open design open-source physical computing device. It has removed many of the
microprocessor board with
hurdles for people wishing to explore embedded microprocessing. An
IO capabilities.
Arduino is a small single-board computer based on an Atmel AVR
microprocessor, with supporting components to handle USB commu-
nications and provide easy access to input/output pins. The developer
programs the on-board microprocessor using an IDE running on a PC.
It has proved very popular, with six-figure sales, and has been used
in projects as diverse as autopilots for radio-controlled aeroplanes, and
CNC sewing machines.
Add-on shields exist, Several expansion modules exist, allowing the Arduino to perform
providing specialist a greater variety of tasks. These secondary modules, or shields, are
interfacing or control
circuit boards that plug into the Arduino’s pin headers, and supply
functions.
additional hardware to, for example, drive motors or servos, interface
with wireless communication modules, or communicate over Ethernet.

1.3 A core-store shield

We set ourselves theWe had developed an interest in the principles and practice of core
challenge of creating a core
memory, and the creation of a modern core memory module struck us
memory Arduino shield.
as an appealing challenge. Eventually a pleasing idea suggested itself:
we decided to build a magnetic core memory Arduino shield.
New-old-stock cores; Our project was made possible thanks to the existence of a sup-
modern components. ply of surplus ferrite cores manufactured in the 1980s for the magnetic
core memory systems of the time. We decided that we would use these
old cores but permit ourselves to use modern components (transistors,
integrated-circuit logic gates, etc.). This made our work enormously

2
easier than that of the original core memory inventors and manufac-
turers. Also, we knew that our end goal was possible.
We succeeded in building an extremely reliable 32-bit core memory It worked.
shield for the Arduino. It can be used as storage for the Arduino, or
alternatively, any modern computing device with a USB port can now
read and write to magnetic core memory.

2 Principles of core memory

2.1 Magnetic hysteresis
A ferrimagnetic substance has two distinct permanently magnetised
states. In our case, these are clockwise and anti-clockwise round the
cores. The key to their use as computer memory is their behaviour
when an external magnetic field is applied — they exhibit hysteresis.

A weak external field has no effect

If we apply a weak external magnetic field around a core, and then
remove it, there is no lasting effect on the core’s magnetisation:
Start off with a core magne- Apply a weak clockwise exter- But when the external field is
tised in the anti-clockwise di- nal field. This reduces the removed, the magnetism in the
rection: strength of the anti-clockwise core ‘springs back’ to its orig-
magnetism in the core: inal state:

A weak anti-clockwise field similarly produces no lasting change.

Strong external fields cause the magnetisation to switch

However, if we apply a sufficiently strong magnetic field in the opposite
direction, the core will switch from one magnetic state to the other:

Start off with a core magne- Apply a strong clockwise ex- When this external field is
tised in the anti-clockwise di- ternal field. This switches the removed, the magnetism in
rection: core’s magnetism, and the core the core reduces slightly in
now has clockwise magnetism: strength, but remains clock-
wise:

A strong field in the same direction as the core’s existing magnetisation

has no lasting effect — the core is saturated and can be magnetised no
further in that direction.

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 2.2 The magnetic field of a current-carrying wire
Current in a wire creates a The next essential physical fact is that a DC current in a wire creates
magnetic field. a magnetic field circulating about the wire, whose strength is propor-
tional to the size of the current. If we reverse the direction of the
current, the magnetic field circulates in the opposite direction:

Small current down; Large current down; Small current up; weak Large current up;
weak clockwise field strong clockwise field anti-c/w field strong anti-c/w field

2.3 Writing to a one-bit core memory system

We can write a bit by We now know enough to write one bit of core memory. Having threaded
driving appropriate a wire through a core, we can cause the core to become magnetised in
currents.
the clockwise direction by passing a strong enough current in one direc-
tion through the wire, and we can cause the core to become magnetised
in the anti-clockwise direction by passing a strong enough current in
the opposite direction. These two operations correspond to writing 0
and 1 to the core. The magnetisation of the core, and so the bit stored,
remains even after the current stops flowing.

The core is magnetised anti- A large current is supplied, When the current is turned
clockwise, and therefore holds generating a strong magnetic off, the core remains magne-
the bit 1. No current flows field. This switches the core’s tised clockwise, therefore now
through the wire. magnetisation to clockwise. holding 0.

2.4 Reading from a one-bit core memory system

But: how do we read the Core memory would probably have been a lot less popular had it been
state of the core?a write-only technology. To see how to read from the core, we need a
further piece of physics: a changing magnetic field induces a voltage.
When a core switches, it Consider a core which is magnetised anti-clockwise. If we apply
induces a voltage. current which tries to increase this anti-clockwise magnetisation, it
does not in fact change the magnetic field in the core much — it is
already saturated. If, however, we apply enough current in the opposite
direction, the core switches to be magnetised clockwise, as shown above.
This process takes a small amount of time, around 1 µs for typical cores.

4
During that time, the magnetic field is undergoing a large change, and
so induces a noticeable voltage.
The setup for reading the state of a core then is to have two wires A second wire senses the
passing through the core. We use one wire, the drive line, for driving induced voltage.
current back and forth and so to set the state of the core, and we have
circuitry connected to the second wire, the sense line, to measure the
induced voltages.
We start the process of reading the core by writing a 0 to it using To read: write a 0; check if
the drive line. If we observe no significant induced voltage on the sense the core switched. If it
did, it was a 1.
line then we learn the core was already in state 0. If, however, we
observe a large induced voltage on the sense line then we learn that
the core contained a 1 (and we then write 1 back to the core). The
memory is said to operate with a destructive read.
At this point it may help to make this more concrete by exhibiting We measured the sense
some real data. Below we present the results of one of our experiments signals from our cores.
in which we measured the induced voltage on the sense line when writ-
ing 0 to a core which contained 1, and when writing 0 to a core which
already contained 0.

If a core switches from one magnetisation However, if the applied field is in the same
direction to the other, the changing mag- direction as the core’s existing magnetisa-
netic field induces a voltage that peaks at tion, no switching takes places, and we ob-
c.35 mV, staying above 20 mV for c.600 ns: serve a negligible voltage:
40 mV
20 mV

2 µs pulse 2 µs pulse

We also see voltage ‘spikes’ caused by the drive line currents switching
on and off. These transformer-action spikes are significant in magni-
tude but are short and temporally separated from the switching signal.
The pulse shown is in fact the base drive of transistors, and the turn-on
and turn-off delays are visible.
We could now build a one-bit read-write core memory system.

2.5 Arrays of cores and half-select currents

However, we want to have more than one bit of memory without need- Imposing only half the
ing one drive line per core. We make use of a feature of the hystere- field leaves the core alone.
sis behaviour of the core. We previously talked in terms of ‘weak’ or
‘strong’ external magnetic fields. Slightly more quantitatively: the core
is not switched by a field which is half as strong as one which is just
strong enough to switch the core. The field is proportional to the cur-
rent in the drive line, so if we pass half the current required to just
switch a core through the drive line, the core will not switch state.
Now suppose we have nm cores and we arrange them in an n × m A 2-D array gives efficient
rectangular array such that each core has one of n horizontal and one control of every core.
of m vertical drive lines passing through it. With this setup we can

5
 selectively set the (i, j)th core and no other by simultaneously driving
the ith vertical drive line and jth horizontal drive line in the appropri-
ate directions, each with half the current required for switching. For
example, in a 4 × 4 array, with the cores viewed edge-on, we switch the
core shown:

Nine cores like this are completely unaffected.

One core receives a full field and switches.
Six cores like this receive a half-field and are unaffected.

√
We only need O( N ) drive lines for an array of N cores.
In total, each core will have three wires threaded through it: two
perpendicular drive lines, and a sense line. A single sense line can be
threaded through all cores in an array, a point we return to below.

2.6 Exploiting anti-coincidence

One more trick doubles The picture we should now have in mind of a core memory module is
the number of cores we a rectangular array of cores, with one vertical and one horizontal drive
can address.
line passing through each core. There is a further drive-line economy,
which cuts in half the number of drive lines in one dimension.
Two states out of four do Consider a core with its two drive lines. There are then four combi-
nothing. nations of current direction. Two combinations produce a reinforcing
field round the core, but in the other two, the fields cancel round the
core:
Reinforce to write 0: Reinforce to write 1: Cancel; no effect: Cancel; no effect:

We say the currents or fields are coincident if they reinforce, and anti-
coincident if they cancel.
We can use those two Now consider two cores arranged as below. We still have two drive
states. lines, but we have turned one of the drive lines through two right angles
so that it passes through both cores but in opposite directions. If we
now consider the four possible simultaneous states of the drive lines,
we find that all possible combinations are put to use:
Write 0 to left core: Write 1 to left core: Write 0 to right core: Write 1 to right core:

6
 To take the concrete example of the small core array we built, we One sense loop snakes
show a 8 × 4 array. We also now illustrate the single sense line which through all cores.
runs through all cores. The alternating alignment of the cores makes
the threading of the sense loop easier, and also reduces the transformer-
action spikes.

Sense loop

Drive lines

The array of cores can be thought of as two halves, with each core in
the left half having an anti-coincident partner in the right half sharing
the same pair of drive lines.

3 Our implementation
To implement these principles, we have to solve a few fairly distinct
problems. We must be able to drive current through the drive lines;
decide which drive lines need to have current driven through them; and
sense when an induced ‘switching signal’ occurs.

3.1 A current-driving circuit

As noted above, we organise the 32-bit module as a rectangular array The drive circuit is two
with 4 rows and 8 columns in which the columns are paired as above copies (X and Y ) of one
problem: driving one of
using anti-coincidence. As a result, we have 4 vertical and 4 horizontal
four lines in either
drive lines to control. Our current-driving problem is thus two instances direction.
of the same problem: we need to be able to select one of four lines, and
to specify a direction in which to drive current along that line.
Our current sources and sinks are transistors, and we could ac- Drive the four lines as ‘two
complish our goal by connecting each end of each drive line to the by two’.
collectors of both a PNP and an NPN transistor (i.e., by using four
H-bridge circuits). This would work, but would be inefficient in terms
of the number of transistors used. By introducing a few diodes, we can
use a design with half as many transistors.
By turning on the correct transistors in the following circuit, we
can send current in either direction through any of the drive lines. The
resistors R1 and R2 control how much current flows. We discuss their
value below.

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 VCC
P
Q10 VCC

P
Q20
X0 0 R2

N
Q20
GND
N X0 1
Q10
GND

VCC
X1 0
P
Q11
VCC

P
Q21
X1 1 R1

N
Q21

N GND
Q11
GND

Calibrating the half-select current

Experiments determine As we have already discussed, it is important that we drive the right
how much current we amount of current. It must be low enough that the magnetic field
should use.
produced by the current in one drive line is not enough to switch a
core, but high enough that the combined field from two coincident
currents does produce switching. We determined the range of possible
values of current for our cores empirically and established that any
value in the range 250–340 mA works. We set the current by choosing
appropriate values for the resistors in the drive circuit above.

3.2 Addressing
Which transistors should In the circuit above, we want to know which transistors to turn on
we turn on? to drive current left or right in one of the four lines. We must be
able to pulse this current, and so we need to be able to stop all drive
currents. Let the enable Boolean variable be E. Let the variable DX
give the direction, with DX = 0 being leftwards. In order to drive the
line XA1 A2 in the direction DX (as long as E is asserted), the base of
transistor QP11 , for example, must be taken high or low according to
QP11 = E ∧ DX ∧ A1 · In words, QP11 must be on (i.e., its base must be
pulled low) exactly when we are enabled (E = 1) and we wish to drive
current rightwards (DX = 1) through either X10 or X11 (those two
lines have A1 = 1). The formulae for all eight transistors are:

QP10 = E ∧ DX ∧ A1 QP20 = E ∧ DX ∧ A2
QN10 = E ∧ DX ∧ A1 QN20 = E ∧ DX ∧ A2
QP11 = E ∧ DX ∧ A1 QP21 = E ∧ DX ∧ A2
QN
11 = E ∧ DX ∧ A1 QN21 = E ∧ DX ∧ A2

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Combining the X and Y drive addressing
Recall that the current-driving circuitry consists of two instances of this Translating from ‘currents
driving circuit, horizontal and vertical. We thus have bits A1 , A2 , and in lines’ to ‘address and
DX for the first instance and A3 , A4 , and DY , say, for the second. We data’.
can generate a switching field in either direction for any of our 32 cores
by choosing values for these six bits, and then controlling transistor
bases accordingly. Furthermore, looking back at section 2.6, we see that
the tuple (A1 , A2 , A3 , A4 ) determines a pair of anti-coincident partner
cores and that it is the value of A0 := DX ⊕ DY that distinguishes
between these two partner cores. Therefore we reparameterise our six
control bits in terms of the five-bit address A4 A3 A2 A1 A0 and the single
data bit D := DX . We then have DY = DX ⊕A0 . The 32 cores are now
numbered, since each core has a unique five-bit address A4 A3 A2 A1 A0 .
The layout of these addresses in the 8 × 4 array may appear a little
haphazard, but this does not matter.

3.3 Sensing
With the current-driving and addressing circuitry in place, it remains How to detect the bulging
only to describe how to detect the presence or absence of a core- switching signal?
switching signal on the sense line. We chose the comparator-based
circuit described in [1] (and apparently of unknown German origin):

SA

SB VCC VCC
3 .3 k

3 .3 k
20

20
1 .6 k

1 .6 k

OUT
GND GND

The sense line, described above, is threaded once through each of the
32 cores, and its ends are connected to the lines marked SA and SB.
The obvious two-fold symmetry of this circuit reflects the possibility Need to detect positive
that a sense pulse from a switching core can bias SA positively or and negative sense bulges.
negatively relative to SB depending on whether a core is switching
from a clockwise to an anti-clockwise magnetisation state relative to
the sense line or vice-versa.
The resistors ensure that, when no voltage is present across SA/SB, With an input of at least
each comparator’s inverting input is 20 mV above its non-inverting, and ±20 mV, one comparator’s
output goes high.
so both outputs are low. If a positive sense pulse occurs, causing SA
to rise more than 20 mV above SB, the left comparator will detect
this and output ‘high’. Conversely for a negative sense pulse, the right

9
 comparator will fire. We or the two to detect pulses of either polarity.
The threshold of 20 mV was chosen by experiment.
Capture sense output at The final detail of the sense circuitry is that we used a timed latch to
the right moment. catch and store the output of the or gate at the appropriate moment.
sense This ensures that we are not affected by any high comparator outputs
threshold
caused by the transformer-action spikes. The timer delay was chosen
t=0 t=2us
by experiment as 650 ns, although any value 500–900 ns worked.
t=650ns:
latch sense output

4 Finished product
4.1 Complete circuit
Combining these pieces, we arrive at the final circuit, which we give
in appendix A. The design splits the shield into a driver board and
a plug-in core board, as shown in this photograph of the two boards
plugged into the Arduino:

4.2 Fabrication
Our design files are We finally achieved our goal of building a core memory shield by having
available. our schematics fabricated as PCBs. Owing to some late design changes,
we then had to patch the boards slightly; the circuits described here in-
clude the changes. Eagle files for these schematics and PCBs as well as
the Gerber files are available in the online version of this document [6].
Also contained in the Eagle files are the part numbers for the various
components (transistors, logic gates, comparators, etc.) that we used.

4.3 API and testing

How to write to and read Once the core board, driver board and Arduino have been appropriately
from the cores from mated, it is easy to use the Arduino to read from and write to the core
Arduino code.
memory array. To send a write pulse to a core, the Arduino writes the
data bit to digital pin 8, writes the address of the core in question to

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digital pins 3–7 and then asserts enable (digital pin 2) for 2 µs. Once
this is done, reading digital pin 9 reveals whether the core changed
state. Cycle time is such that a 32-bit operation takes 0·5 ms, although
preliminary experiments suggest that by being more aggressive on the
timings we could bring this down to 0·3 ms.
These operations are presented as the functions write_bit and A simple API and
read_bit. Loops turn these into write_word and read_word, to act serial-based CLI is
available.
on the whole core board as a single 32-bit unsigned integer. A further
natural operation is a bit exchange. This, in one operation, writes a new
data bit to a core, and returns the old value, which can be deduced as
(latched-sense-output) xor (new-data). The source-code for this API,
with a command-line interface presented on the serial port, is available
for download [6].
We used this interface to extensively test the core memory shield. The core memory shield
After running continuously for over one hundred hours, the shield had performed error-free for
10 bln operations, running
performed over ten billion successful bit-exchange operations without
for 100 hrs.
a single error.

5 Final words
We hope that our work here might encourage others to take an inter-
est in both the theory and the practice of core memory. For further
reading, excellent descriptions are given by Hilpert [1] and by Jones [4].
Building a reliable 32-bit core memory shield for the Arduino proved
to be a natural stopping point for our work, but there is certainly more
that could be done. Some ideas for future work that appealed to us:

• Many core memory arrays from the heyday of core memory still
exist and indeed are easy to find for sale (e.g., on eBay). It might
be a fun challenge to build a driver module to write to and read
from these old arrays. Perhaps with care and luck one could even
recover some 50-year-old data?

• A completely different approach to core memory, with a non-

destructive read cycle, was invented by Eiichi Goto in the mid-
1950s, and was incorporated in the Japanese Parametron Com-
puter 1 (see [7] for a description). It would be very interesting to
re-implement this significantly different core memory technology.

• In practice, a group of core memory modules of the type described

here, known as planes, were combined into a core store. All
planes could be accessed simultaneously by introducing an inhibit
line [4]. Constructing an 8-bit wide store would be a worthwhile
challenge.

11
 S E NS E
A

LA TC H
TI ME R
!Q CLR
CLK !Q CLR
R/ C
D Q C
Q PRE
B
A
Circuits

POR TB

DR D
DWR

A DDR 4
A DDR 3
A DDR 2
A DDR 1

12
A DDR 0
E NA B LE

POR TD
Firstly, the schematic for the driver board:

C OR E B OA R D
Secondly, the core board’s schematic:
S E NS E DR I V E R B OA R D

The terminating resistor across the sense loop provides a path for the
current caused by the induced voltage round the loop.

References
[1] B. Hilpert. Magnetic core memory systems. http://www.cs.ubc.
ca/~hilpert/e/coremem/index.html.

[2] W. Holder. One bit ferrite core memory. http://sites.google.

com/site/wayneholder/one-bit-ferrite-core-memory.

[3] A. Holme. Magnetic core memory. http://www.holmea.demon.

co.uk/Core/Flipper.htm.

[4] J.R. Jones. Coincident current ferrite core memories. Byte, 11:6–16,
July 1976.

[5] D. Mellis. Photograph of Arduino Duemilanove, cc-by-2·0. http:

//www.flickr.com/photos/mellis/4784965878/.

[6] B. North and O. Nash. Magnetic core memory reborn. http:

//www.corememoryshield.com/.

[7] E. Wada. The Parametron Computer PC-1 and its initial input
routine. In P. Rojas and U. Hashagen, editors, The first computers:
History and architecture, pages 435–452. MIT Press, 2000.

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