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Lab 4

The lab assignment involves building a circuit to display numbers 0 to 7 on a seven-segment display using specific input signals for writing and reading operations. Students are required to design a test bench, synthesize the circuit, and answer questions related to the synthesis report and resource usage. A written report must include design partitions, gate-level diagrams, and K-maps for the components used.

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19 views3 pages

Lab 4

The lab assignment involves building a circuit to display numbers 0 to 7 on a seven-segment display using specific input signals for writing and reading operations. Students are required to design a test bench, synthesize the circuit, and answer questions related to the synthesis report and resource usage. A written report must include design partitions, gate-level diagrams, and K-maps for the components used.

Uploaded by

Ahsaan
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab Assignment 4

Sequential Circuits

1 Lab Tasks
a) The customer asks you to build a circuit to display different numbers (0
to 7) on a seven-segment display. The circuit has the following modular
diagram. The user stores the number to display on first seven-segment dis-
4

1
3
num

sel 2

wr
7

Figure 1:

play by choosing sel = 2‘b00, num_in = desired number and turning


the switch wr ON and then OFF. Similarly, the user stores the numbers to
display on other three seven-segment display by following the same method
except choosing a different memory location with the help of sel. By the
end of this writing process, all the seven-segment displays must show the
four different numbers stored in the circuit before, one at a time. In other
words, when the user selects sel = 2‘b00, wr=0, the first seven-segment
display should show the number stored with sel = 2‘b0. Similarly, if the
user selects sel = 2‘b01, wr=0, the second seven-segment display should
show the number stored with sel = 2‘b01.
Table 1 explains the operations in the circuit in more detail. We will first
use the write operation to store the four values corresponding to different
seven-segment displays. After the write operation, we will read the stored
numbers using WR=0 and sel signals.
The lab manual is for the exclusive use of the students of University of Engineering and
Technology, Lahore. c 2019 UET Lahore.

1
Table 1: Input/Output Truth Table
OPERATION TYPE SEL WR DATA D1 D2 D3 D4
00 1 1 1 OFF OFF OFF
01 1 2 OFF 2 OFF OFF
WRITE OPERATION
10 1 3 OFF OFF 3 OFF
11 1 4 OFF OFF OFF 4
00 0 X 1 OFF OFF OFF
01 0 X OFF 2 OFF OFF
READ OPERATION
10 0 X OFF OFF 3 OFF
11 0 X OFF OFF OFF 4

For information on seven-segment display, refer to the data sheet of the


starter kit.
b) Design a test bench for the circuit of part (a). The test bench should be
exhaustive and should include all possible input patterns.
c) Synthesize the circuit for the starter kit available in the lab. Tie inputs to
the switches and outputs to the seven-segment displays available on the
board.

2 Questions
Answer the following questions:
a) Read the synthesis report of your circuit and describe which path has the
maximum combinational delay?
b) Read the Post-Place & Route static timing report and identify the path
with the maximum combinational delay? Is the path same as the one in
part a?
c) Read the synthesis report and identify how many resources in the FPGA
such as lookup tables (LUTs), input/output (IOs), etc., has been utilized.
Is this resource usage equal to the resource usage of the circuit you de-
signed on paper?
d) Are there any static-zero or static-one hazards in any output of the circuit?
If yes, describe how will you remove it.

3 Instructions
a) A written report is required for this lab. The report should include the
following:

2
(a) A hand-sketched design partition of the system. The design parti-
tion should include multiplexers, demultiplexers, encoders, decoders
and flip flops, and should avoid gates as much as possible. You’re
supposed to design the circuit using the combinational components
mentioned before.
(b) For each component you have drawn in part (a), provide a hand-
sketched gate-level diagram. For example, if you have used a multi-
plexer, draw its gate-level diagram. You can use behavioral modeling
using assign statements for only the components you have studied in
the class.
(c) Different K-maps used to generate component circuits.

b) It is recommended that you bring your simulation in your laptop so that


you can quickly get your assignment partially graded. Otherwise, you will
have to share the computer in the lab and may have to wait. However,
you will need to transfer your code to the lab computer using USB anyway
for the synthsis and downloading the code to the FPGA.
c) The collaboration between students is encouraged, but blind code shar-
ing/copying is not allowed. If you are unable to explain anything in your
code, it will be assumed you have copied it. So make sure you know every
thing you have written in your code. I am least concerned about how you
have learnt something as long as you have learnt it well.

The lab manual is for the exclusive use of the students of University of Engineering and
Technology, Lahore. c 2019 UET Lahore.

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