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Microprocessor 8086 Course

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8086 COURSE

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Introduction to Microprocessors and

Microcontrollers
Lecture notes, Examples, Exercises and AL Programs
BSc students of Electrical Engineering

Dr. Monji Mohamed Zaidi

E.E Department - College of Engineering - King Khalid University – KSA
April - 2024

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Preface …

The fundamentals of 8086 Intel microprocessor and 8255 Intel

microcontroller are covered in this course, which is addressed for
engineering students as well as master's students in electrical and/or
electronics engineering. First, we present the In-Out pins as well as the
internal architecture of 8086 IC, then we introduce the addressing modes and
instructions’ sets. This course also presents 8086 interfacing with 8255
microcontroller.

It is recommended that the reader should have necessary skills in logic

circuits theory and the basics of C language programming.

Enjoy the course

Dr. Monji M.Zaidi

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CHAPTER 1: THE INTEL 8086 MICROPROCESSOR

1. History of Intel 8086 microprocessor (3 decades since 1971)

Processor Year Size( ) Transistors Frequency(MHz) Word size Package

4004 1971 10 2.3 k 0.75 4 16-pin DIP

8008 1972 10 3.5 k 0.5-0.8 8 18-pin DIP

8080 1974 6 6k 2 8 40-pin DIP

8086 1978 3 29 k 5-10 16 40-pin DIP

80286 1982 1.5 134 k 6-12 16 68-pin PGA

Intel 386 1985 1.5-1.0 275 k 16-25 32 100-pin PGA

Intel 486 1989 1-0.6 1.2 M 25-100 32 168-pin PGA

Pentium 1993 0.8-0.35 3.2-4.5 M 60-300 32 296-pin PGA

Pentium Pro 1995 0.6-0.35 5.5 M 166-200 32 387-pin MCM PGA

Pentium2 1997 0.35-0.25 7.5 M 233-450 32 242-pin SECC

Pentium3 1999 0.25-0.18 9.5-28 M 450-1000 32 330-pin SECC2

Pentium4 2001 0.18-0.13 42-55 M 1400-3200 32 478-pin PGA

2. Upcoming processors (Last two decades)

2002: Pentium 4 HT processor

To achieve high performance at low dominant frequencies, Banias has been optimized to allow more
instructions to be executed per clock and to reduce the false prediction rate with advanced branch
prediction. Another notable improvement is the increase in the L2 cache to 1 MB (P3-M and P4-
M are only 512 KB), where most of the estimated 77 million transistors are used.

2005: Pentium D processor

The first Intel Pentium D processor with two processing cores is on the market, officially ushering
in the multi-core era of x86 processors.

2006: Core 2 Duo processor

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The Core microarchitecture desktop processor, whose core is codenamed Conroe and will be called
the Core 2 Duo/Extreme family, offers a 40% performance improvement over the previous Intel
Pentium D 960 (3.6 GHz) processor. . The power saving efficiency also reaches 40%, and the Core
2 Duo processor contains 291 million transistors.

2008: i7 processor

The next-generation desktop processor based on the new Nehalem architecture, "Core", named
the "Intel Core i7" series, is a 64-bit quad-core processor released by Intel in 2008. It follows the
x86-64 instructions and is based on the Intel Nehalem microarchitecture. Replaces Intel Core 2
series processors.

2012: Ivy Bridge processor

On April 24, 2012, Intel officially released the Ivy Bridge (IVB) processor. The 22nm Ivy Bridge
will double the number of execution units to a maximum of 24, which will naturally lead to another
leap in performance. Ivy Bridge adds integrated graphics with DX11 support. Additionally, the
new XHCI USB 3.0 controller shares four of these channels, providing up to four USB 3.0 ports
to support native USB 3.0. The processors are built using 3D transistor technology which cuts a
processor's power consumption in half.

3. Architecture of a microprocessor system

Figure 1.1 Microprocessor system

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In a microprocessor system as shown in figure 1.1 (Von Neumann Architecture), we find at least:

 A microprocessor
 A Read Only Memory (ROM) and a Random Access Memory (RAM)
 Inputs/Outputs interface

All these devices are interconnected with 3 buses: Bidirectional data bus, Address bus and Control
bus

3.1.The microprocessor

This is the heart of the system. It is responsible for the following functions:

 Provides synchronization and control signals to all elements of the system

 Supports the instructions and the data in memory
 Transfers the data between memory and I/O devices and vice versa
 Decodes the instructions
 Performs arithmetic and logical operations provided by the instructions
 Reacts to control signals produced by the inputs/outputs such as the RESET and
INTERRUPTIONS signals.
3.2.Memory

The role of memory is to store groups of binary digits (words) which are either instructions forming
a program, or data that the program needs. It is often broken down into:

3.2.1. Read only Memory (ROM)

It is responsible for storing the program.

 ROM: Read Only Memory. Read-only memory, no writing. Its content is programmed
once for all by the manufacturer.
Advantage: low cost.
Disadvantage: requires production in very large quantities.
 PROM: Programmable Read Only Memory. ROM programmable only once by the user.
 EPROM: Erasable PROM, also called UVPROM. ROM electrically programmable with
a programmer and erasable by exposure to ultraviolet radiation.

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 EEPROM: Electrically Erasable PROM. Programmable and electrically erasable ROM.

EEPROMs contain data that can be modified.
3.2.2. Random Access Memory (RAM)
 Responsible for storing intermediate data or calculation results. It is allowed to read or
write data inside, these data are lost when the power is turned off.
 SRAM: Static Random Access Memory. Static random access memory, based on two-
semiconductor flip-flops (RS flip-flops) state.
 DRAM: Dynamic RAM. Based on capacitor charge: capacitor charged = 1, capacitor
discharged = 0

Hard disk, USB disk, CDROMs … etc. are a storage devices and they are considered as secondary
memory.

We can therefore schematize a memory circuit using the figure 1.2.

Figure 1.2 Functional diagram of a memory

The number of address lines depends on the memory capacity (size): n address lines allow
memory locations to be addressed: 8 address bits allow 256 (2 ) bytes to be addressed, 16 address
bits allow 65536 (2 ) to be addressed bytes (= 64 KB)...

= 2 ∗

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Where n is number if address lines

If the size of one memory location is 8 bits (one byte) then

= 2

3.3.Input-Output interfaces

It is an integrated circuit allowing the microprocessor to communicate with the external

environment (peripherals): keyboard, screen, printer, push button, industrial process, actuators,
etc. I/O exchanges correspond to read and write instructions. Most often the interface circuit
includes a register called a “port”.

 Write: The microprocessor sends the write order and the data is stored in the interface
register.
 Read: the circuit simply presents the device information on the data bus.
4. The Intel 8086 microprocessor (External look)
4.1.Physical description of 8086

The Intel 8086 microprocessor is a 16-bit microprocessor, which appeared in 1978. It is the first
microprocessor in the Intel 80x86 family (8086, 80186, 80286, 80386, 80486, Pentium, etc.). It
comes in the form of a 40-pin DIP (Dual In-line Package) as shown in the figure 1.3.

Figure 1.3 8086 Integrated Circuit (IC)

The 40 pin are detailed as depicted in the figure 1.4.

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Figure 1.4 the 8086 pin assignments in min and max mode

4.2.Functional diagram of the 8086

To specify each category of input-output signals, we represent the 8086 differently as shown by
the figure 1.5.

Figure 1.5 Functional diagram of the 8086

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4.3.Description and use of 8086 signals

 CLK

Input of the clock signal which clocks the operation of the microprocessor. This signal comes from
a clock generator: the 8284.

Since it needed numerous extra circuits to generate the clock in an 8086/8088-based system, the
8284A is a crucial auxiliary part of the 8086/8088 microprocessor. Clock generation system is
given by the figure 1.6.

Figure 1.6 Clock generation from 8284A

 RESET

Microprocessor reset input. When this input is set high for at least 4 clock periods, the
microprocessor is reset: it will execute the instruction located at address FFFF0H (bootstrap
address). The RESET signal is provided by the clock generator.

 AD0 to AD15

Lower-order address buses are data multiplexed. The symbol A is used in place of AD when
transmitting memory addresses via AD lines, such as A0-A15.

The symbol D is used in place of AD when data are transmitted throughout AD lines, such as D0-
D7, D8-D15, or D0-D15.

 A16-S3 to A19-S6

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A16-S3, A17-S4, A18-S5, and A19-S6 Bus with high order address. They are are multiplied with
status signals.

 S0 to S2

Status signals indicating the type of operation in progress on the bus.

Status signals
Machine Cycle

0 0 0 Interrupt acknowledge

0 0 1 Read Input-Output Port

0 1 0 Write Input-Output Port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read from memory

1 1 0 Write on the memory

1 1 1 Passive-Inactive

 ALE

(Address Latch Enable): This signal is an active pulse during a time T1, it indicates that the
information circulating in bus A/D is an address.

Read, data reading signal.

Write, data writing signal.

 M/

Memory/Input-Output, indicates whether the CPU addresses memory (M/ = 1)

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Data Enable, indicates that data is circulating on the A/D bus (equivalent to ALE for data)

 DT/

Data Transmit/Receive, indicates the direction of data transfer

 DT/ = 1 , data transmitted by the microprocessor (writing)

 DT/ = 0, data received by the microprocessor (reading)
 READY

Synchronization input with memory. This signal also comes from the clock generator.

Input to put the microprocessor on hold (waiting) for an external event.

 MN/

Microprocessor operating mode choice input:

 Minimum Mode: MN/ = 1 : The 8086 works autonomously, it generates itself the
control bus ( , , ...)
 Maximum Mode: MN/ = 0 : These control signals are produced by a bus controller,
the 8288. This mode makes it possible to create multiprocessor systems
 NMI and INTR

Interrupt request inputs. INTR: normal interrupt, NMI (Non Maskable Interrupt): priority
interrupt.

Interrupt Acknowledge, indicates that the microprocessor accepts the interrupt

 HOLD and HLDA

Direct Memory Access approve (DMA) request signals

Bus High Enable, signal for reading the most significant byte of the data bus

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Transferred bytes
0 both bytes (full word): 15 − 0
0
1 Significant byte (odd address): 15 − 8
0
0 lower byte (even address): 7 − 0
1
1 no bytes
1

4.4.Basic Connections
 GND: connect to 0V.
 VCC: connect to 5V.
 MN / MX: connect to 5V (minimum mode).
 NMI and INTR: connect to 0V (no support for interrupts).
 CLK: connect to the CLK output of the clock generator.
 HOLD: connect to 0V (no direct memory access).
 TEST: connect to 0V (no wait for co-processors).
 READY: connect to 5V (no wait cycles for slow devices).
 RESET: connect to zero of clock generator output.

Note:

A very simple microprocessor system is made up of the following parts:

a. 8284A Clock Generator (15MHz Crystal)

b. 8086 Microprocessor (Minimum Mode)
c. Bus System (Demultiplexed and Buffered)
d. Memory System (ROM and RAM Modules)
e. I/O System (Switches and LEDs)
4.5.Questions-Answers
1. What are the features of Intel 8086?
• Released by Intel in 1978
• Produced from 1978 to 1990s

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• A 16-bit microprocessor chip.

• Max. CPU clock rate: 5 MHz to 10 MHz
• Instruction set: x86-16
• Package: 40 pin DIP
• 16-bit Arithmetic Logic Unit
• 16-bit data bus (8088 has 8-bit data bus)
• 20-bit address bus - 220 = 1,048,576 = 1 MG
• The address refers to a byte in memory.
• In the 8088, these bytes come in on the 8-bit data bus. In the 8086, bytes at even addresses
come in on the low half of the data bus (bits 0-7) and bytes at odd addresses come in on the
upper half of the data bus (bits 8-15).
• The 8086 can read a 16-bit word at an even address in one operation and at an odd address
in two operations. The 8088 needs two operations in either case.
• The least significant byte of a word on an 8086 family microprocessor is at the lower
address.
2. What is cache memory?
A little, fast memory is called cache memory. It serves as a temporary data and information
storage device between the central processing unit (CPU) and main memory. RAM serves
as the cache memory.
3. What is a bus?
A bus is a collection of conducting lines used to send control, address, and data signals.
4. Why data bus is bi-directional?
In order to process data, the microprocessor must first fetch (read) it from memory or an
input device and then store (write) it to memory or an output device. The data bus is hence
bi-directional.
5. Why address bus is unidirectional?
The microprocessor uses the address, which is an identification number, to locate or access
a memory address or I/O device. It is the processor's output signal. The address bus is
hence unidirectional.
6. What is the data and address size in 8086?

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You can use 8-bit or 16-bit data with the 8086. The 8086 accesses memory with a 20-bit
address and 1/0 devices with a 16-bit address.
7. What are the interrupts of 8086?
NMI and INTR are the 8085/6 interrupts. NMI is a non-maskable interrupt, and INTR is
a generic maskable interrupt.
8. What is Software interrupts?
Program instructions are contained in software interrupts. These instructions are added
to a program at the appropriate places. If a software interrupt instruction is encountered
while a program is running, the processor will carry out an interrupt service routine.
9. What is Hardware interrupt?
A processor interrupt is referred to as a hardware interrupt if it is caused by a suitable
signal at the interrupt pin.
10. Why crystal is a preferred clock source?
Due to its great stability, high QF (Quality Factor), and frequency that remains constant.
The majority of the time, crystal is employed as a clock source.
11. How clock signal is generated in 8086? What is the maximum internal clock
frequency of 8086?
There is no on-chip clock generating circuit in the 8086. Therefore, the CLK pin of 8086 is
connected to the clock generator chip, 8284. For internal use, the 8284-supplied clock signal
is split by three. The 8086's highest internal clock frequency is 5MHz.
12. What is the use of HLDA
The acknowledgment signal for HOLD is HLDA. It denotes the presence or absence of the
HOLD signal. The control signals for DMA operations are HOLD and HLDA.
13. What is the main use of ready pin?
The CPU uses READY to determine if a peripheral is prepared to receive or send data. An
analog to digital converter, LCD display, or any other device can be considered a peripheral.
The READY pin is used to link these devices to the microprocessor. The peripheral is
prepared for data transfer if READY is high. In the event that it doesn't, the CPU waits
until READY reaches high.
14. What is the need for timing diagram?

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The timing diagram provides information regarding the status of various signals, when a
machine cycle is executed. The knowledge of timing diagram is essential for system
designer to select matched peripheral devices like memories, latches, ports, etc., to form a
microprocessor system.
15. Define machine cycle.
A machine cycle is the amount of time needed to do one I/O, memory access, or request
acknowledgment from outside the system. There could be three to six T-states in this cycle.
16. Why interfacing is needed for 1/0 devices?
I/O devices are often slowly devices. As a result, the microprocessor's speed and the speed
of I/O devices are not equal. Thus, an interface is offered between I/O devices and the
system bus.
17. What does memory-mapping mean?
The process of connecting memory to a microprocessor and assigning addresses to each
memory location is known as memory mapping.
18. What is DMA?
DMA is the term for the direct data transmission between an I/O device and memory.
19. How DMA is initiated?
The I/O device will notify the DMA controller with a DMA request signal whenever it
needs a DMA transfer. The processor receives a HOLD request from the DMA controller.
At the conclusion of the current instruction execution, the processor will push its tri-stated
pins to a high impedance state in response to a HOLD request. It will then send an
acknowledgement signal to the DMA controller. DMA transfer will now be carried out by
the DMA controller.
20. Which of the following is not an 8086 maximum mode signal?
(A) LOCK
(B) S0
(C)ALE
(D) QS0
Answer: C (Detailed Solution: ALE is a minimum mode signal)

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21. What is the maximum capacity of the memory that can be interfaced to the
microprocessor which contains 20 address lines?
a.) 64 KB
b.) 1 MB
c.) 64 MB
d.) 1 GB
Answer: B
Detailed Solution: = 2 = 1048576 = 1
22. The size of ALU in 8086 is
a.) 8 bit
b.) 16 bit
c.) 24 bit
d.) 32 bit
Answer is B
23. These are two ways in which a microprocessor can come out of Halt state.
(A) When hold line is a logical 1.
(B) When interrupt occurs and the interrupt system has been enabled.
(C) When both (A) and (B) are true.
(D) When either (A) or (B) are true.
Answer is (A)

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CHAPTER 2: INTERNAL DESIGN OF 8086 MICROPROCESSOR

1. Basic architecture of 8086

The diagram of the internal structure (Figure 2.1) shows two units, one which executes the
instructions (EU, Execution Unit) with its arithmetic and logic unit (UAL) and its registers; the
other which ensures the connection with the outside world (BIU, Bus Interface Unit) generates
the addresses using an address generation unit and reads the instructions which it places in a
queue (Queue), of 6 bytes for the 8086 and 4 for the 8088.

Figure 2.1 Internal architecture of 8086 microprocessor

The 8086 is made up of two units operating in parallel:

 The execution unit (EU: Execution Unit);

 The bus interface unit (BIU: Bus Interface Unit).

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1.1.Role of the two units:

 The bus interface unit (BIU) searches for instructions in memory and places them in a
queue.
 The execution unit (EU) executes the instructions already placed in the queue.

Both units operate simultaneously, resulting in an acceleration of the program execution process
(operation according to the pipeline principle).
Four groups of 14 registers make up the 8086 microprocessor:
1.2.General registers: 4 registers of 16 bits.
 =( , ) : The Accumulator it is used (not limited to) for the following purposes:

General use:

Mandatory for multiplication and division.

Cannot be used for addressing.

 =( , ) : The Base Register it is used (not limited to) for the following purposes:
General use,

Addressing, (By default, its offset is relative to the DS segment)

 =( , ) : The Count Register it is used (not limited to) for the following purposes:

General use.

Used by some instructions as a loop counter.

Cannot be used for addressing.

 =( , ) : The Data Register it is used (not limited to) for the following purposes:

General use.

In 16-bits multiplication and division, it serves as an extension to the AX register to hold

32 bits number.

Cannot be used for addressing.

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These register (AX, BX, CX and DX) can also be considered as 8 registers on 8 bits. They are used
to temporarily hold data.

1.3.Pointer registers: 2 registers of 16 bits.

 SP: Stack Pointer (the stack is a data saving area during the execution of a program).

Used for stack access. Points to the head of the battery. By default, its offset is relative to SS

 BP: Base Pointer, used to address data on the stack. Addressing as base register, (By
default, its offset is relative to SS).General purpose
1.4.Index registers: 2 registers of 16 bits.
 SI: Source Index. Addressing as index register, (By default, its offset is relative to DS).
Some data movement instructions use it as an index of the source operand. The destination operand
being indexed by DI. General purpose.
 DI: Destination Index. Addressing as index register, (By default, its offset is relative to
DS). Some data movement instructions use it as an index of the destination operand. The
destination operand being indexed by SI. General purpose.
1.5.Segment registers: 4 registers of 16 bits.

These registers are combined with the offset registers to form the addresses. A memory location is
identified by an address of the form Segment Register : Offset Register. We place the segment
register at the start of a 64Kb memory zone, then we vary the offset register which specifies the
relative address in relation to this position.

 CS: Code Segment

Defines the start of program memory. The addresses of the different program instructions are
relative to CS

 DS: Data Segment

Start of data memory in which all data processed by the program is stored

 SS: Stack Segment

Start of the stack. The stack is a memory area managed in a particular way. It is organized like a
stack of plates. We always place and remove the plates on the top of the stack. A single offset register

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is therefore sufficient to manage it, the stack pointer (SP). It is called a LIFO (Last IN, First Out)
stack.

Stack data: save data on (top) of the stack (push instruction… soon)

Unstack data: remove data (from the top) of the stack (pop instruction… soon)

 ES: Extra Segment

Start of an auxiliary data segment

Figure 2.2 Segment registers and their equivalent offset

1.6.Instruction pointer and flags: 2 registers of 16 bits.

 IP: Instruction pointer: The program counter here called instruction pointer (IP). This
register is updated by the BIU so that it points to the address of the next instruction.

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 Flag register: The 8086 microprocessor has status indicators, which are updated by the
execution unit. The state of these indicators depends on the result of the arithmetic and
logical operation that has just taken place.

Figure 2.3 gives the location of the inductors in the flag register or (Status flag)

Figure 2.3 Flag register configuration

There are two types of flags of flag register in 8086 Microprocessor:

1.6.1. Status Flags

Carry Flag (CF): After performing any operation on an 8086 microprocessor, the carry flag will
only be set if a carry is created from the MSB of the result.

Parity Flag (PF): the number of 1s in the binary data determines parity. Two different kinds of
parity exist:

Even Parity: The state in which all of the binary data's 1s are even.

When the binary data has an odd number of 1s, it is said to have odd parity.

If there is even parity in the data following the execution of the instruction, the PF is set for the
flag. The flag is reset if not.

Auxiliary Carry Flag (AF): In an arithmetic operation, when the carry is generated from bit D3
to D4, the auxiliary carry flag is set to 1. (Starting from bit D0)

Zero Flag (ZF): The zero flags are set to 1 if an appropriate operation (either logical or arithmetic)
on the instructions yields a zero result. If not, it stays reset.

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Sign Flag (SF): The sign flag is set to 1 if the result of any arithmetic or logic operation carried
out in the provided instruction is negative. If not, the sign flag is left reset in the event of a favorable
outcome.

Overflow Flag (OF): After every arithmetic or logic operation, this flag will be set if the register
overflows with data. This occurs when the carry is received in MSB but the carried out bit cannot
be stored in the register.

A. Example 1: Addition 0Fh + 08h

AL=0Fh 0 0 0 0 1 1 1 1

BL=08h 0 0 0 0 1 0 0 0

AL+BL=17h CF = 0 0 0 0 1 0 1 1 1

CF=0, OF=0

Both operands and the result are positive. PF=1, ZF=0, SF=0, AF=1

The integers 0 to 255 (11111111 in binary) can be expressed with 8 bits. Negative integers can be expressed in binary
format using signed magnitude, for example. Rather than showing the number, the most important element, which is
on the left, is utilized to indicate if the number is positive or negative.

We can generate 256 combinations (ranging from 0 to 255) using an 8-bits number system. Positive numbers are
represented by the first 128 combinations (0 to 127) and negative numbers by the next 128 combinations (128 to 255).

Unsigned numb (decimal) Its binary form Its hex form Signed numb (decimal)

0 00000000 00 +0

1 00000001 01 +1

2 00000010 02 +2

… … …

127 01111111 7F +127

128 10000000 80 -128

129 10000001 81 -127

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… … … …

254 11111110 FE -2

255 11111111 FF -1

Figure 2.4 Signed form of 8 bits data

B. Reminder of the second complement

 Range of represented values: −2 2 −1
 If n=8, then the range is -127 to +127
 The second complement of A is the negative of A
 The sum A + (second complement of A) must be zero
 The final carry is ignored
 B-Example
 Consider the 8 bits number A = 00101100
 First, invert all bits which gives 11010011
 Then Add 1 to 11010011 giving 11010100 which is the second complement of A
 11010100 in signed form gives 4+16+64+ (-128) = - 44
 00101100 + (11010100) = 1 0000 0000 (ignore the final carry 2 )
C. Example 2: Addition 0Fh + F8h

AL=0Fh 0 0 0 0 1 1 1 1

BL=F8h 1 1 1 1 1 0 0 0

AL+BL=07h CF = 1 0 0 0 0 0 1 1 1

CF=1, OF=0, Operands have different sign bits.

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PF=0, ZF=0, SF=0, AF=1

As a signed operation, 15 + (-8) = 7 (ok).

(-8) is the signed form of 1111 1000 obtained using the concept of figure 2.4

As an unsigned operation, 15 + 248 = 263 > 255 (out-of-range).

D. Example 3: Addition 4Fh + 40h

AL=4Fh 0 1 0 0 1 1 1 1

BL=40h 0 1 0 0 0 0 0 0

AL+BL=8Fh CF = 0 1 0 0 0 1 1 1 1

CF=0, OF=1, the result and operands have different sign bits.

PF=0, ZF=0, SF=1, AF=0

As a signed operation, 79 + 64 = 143 > 127 (out-of-range).

As an unsigned operation, 143 < 255 (ok).

1.6.2. Control Flags

To guide the microprocessor for certain tasks, the control flags are employed. A control flag can be
of three types:

Trap Flag (TF): This flag is used of we need single-step debugging in our code. If the TF is set,
then the execution will be done step by step. Otherwise, the free-running operation will be done.

Interrupt Flag (IF): This flag is used to enable the Interrupt. The microprocessor is capable of
handling interrupts only if this flag is in the set mode. Otherwise, any interrupt raised while the
execution of the instructions will not be handled by the microprocessor.

Direction Flag (DF): This flag is used for string operations. If this flag is set, the string will be
read from higher-order bits to lower order bits and vice versa

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2. Memory segmentation and physical address

The 8086 has 20 address bits, so it can address 2 bytes or 1 MB. The address of the first memory
location is 0000 0000 0000 0000 0000 (00000h), the last case is 1111 1111 1111 1111 1111 1111
(FFFFFh).

Figure 2.5 One MB memory addressing concept in 8086 microprocessor

The problem that arises is how to represent these addresses within the µP since the registers are
only 16 bits, i.e. 4 maximum digits in hexadecimal. The solution adopted by Intel was as follows:

Since with 16 bits we can address 2 bytes = 65535 bytes = 64 KB, the total addressable memory
of 1 MB is divided into pages of 64 KB called segments. (It seems like pages)
We then use two registers to address a given memory location, A register to address the segment
which is called segment register and a register to address inside the segment by addressing
register or offset.
An address is always in the form Segment : Offset
As an example, let's divide the memory into 16 non-overlapping segments. (It seems like 16 pages
without intersection to cover all the physical memory:64 ∗ 16 = 1 )

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Segment Starting Address Last Address Segment Pointer

00000 0FFFF 00000
Segment 0 (like page 0)
10000 1FFFF 10000
Segment 1 (like page 1)
20000 2FFFF 20000
Segment 2 (like page 2)
….. ….. …..
…..
E0000 EFFFF E0000
Segment 14 (like page 14)
F0000 FFFFF F0000
Segment 15 (like page 15)

Figure 2.6 memory segmentation concept for 8086 microprocessor

Consider the address memory location 20350, called physical address or linear address. This
memory location is located in segment 2, its address relative to this segment is 350, and we can
therefore reference this location by the pair: ∶ = :

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Figure 2.7 Data location inside a segment register

Now there is the problem of representing this address within the CPU because 16-bits registers
can only contain 4 digits. If there is no problem representing 350 in an offset register, we cannot
represent 20000 in a segment register. The solution adopted by Intel is as follows:

 In the segment register, we write the segment address without the least significant digit
 In the addressing (offset) register we write the relative address in the segment
 To calculate the absolute address that will be sent on the 20-bits address bus, the CPU adds
the two registers after shifting the segment register one digit (4 bits) to the left.

Figure 2.8 Physical address determination by 8086 microprocessor

Shifting 1 digit in hexadecimal (4 bits in binary) is equivalent to multiply by 10 in decimal base

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So:

In our example, the address of the memory box considered becomes 2000:350, i.e.:

Segment = 2000

Offset = 350

= ∶ = :

And the physical address is given by the following formula

= ∗ +

3. Addressing in a specific Segment

We are using here the code segment and it relative pointer IP (see figure 2.2). The concept is the
same for other segment register except the relative pointer will change.

To execute a program, the 8086 fetches the instructions from the code segment.

The logical address of an instruction consists in CS (code segment) and IP (the instruction pointer)

The logical address is then

= :

Example 1 (Addressing in Code segment)

If CS=2500h and IP=95F3h

a. What is the logical address in the 64 KB segment?

b. What will be the physical address in the 1MO memory?

Answer

a. Logical address is CS:IP = 2500:95F3

b. The physical address that will be sent to the address bus by the CPU of 8086 microprocessor
is:
Physical Address (20bits) = CS ∗ 10 + IP = 25000 + 95F3 = ⋯ h

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Example 2 (Addressing in Code segment)

If CS = 24F6h and IP = 634Ah, determine.

a. The logical address in the code segment

b. The offset address in the code segment
c. The physical address in the 1 MB memory
d.The lower range in the code segment
e. The upper range in the code segment

Answer

a. The logical address is : 24F6:634A

b. The offset address is 634A
c. The physical address is 24F6*10+634A = 2B2AA (20 bits)
d.The lower range in the code segment is (24F6:0000) = 24F6+0000=24F6
 The lower range in the physical memory is 24F60+0000=24F60 (20 bits)
e. The upper range in the code segment is (24F6: FFFF) = 24F6+FFFF=24F6
 The upper range in the physical memory is 24F60+FFFF=34F5F (20 bits)

Example 3 (Addressing in Data Segment)

If DS = 7FA2h and IP = 438Eh, determine.

a. The logical address in the data segment

b. The offset address in the date segment
c. The physical address in the 1 MB memory
d.The lower range in the date segment
e. The upper range in the date segment

Answer (do the same as in previous example)

4. Stack Segment and push-pop concept

The CPU uses the stack, which is part of RAM, to temporarily store data. Since there are only a
few registers in the CPU, this storage space is critical.

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To access the stack in the memory, SP (stack pointer) and SS (stack segment) must be loaded.

All CPU registers, with the exception of segment registers and SP, can be loaded from and
transferred to the stack.

In a stack segment, the offset address in the SP register and the segment address in the SS register
are used to indicate the logical address.

SS : SP

4.1.1.Pushing operation in Stack

A push is the process of storing the CPU register in the stack.

 Copy the content of the source (16 bits) into the stack
 SP register is decremented by 2

Example 1

After the following instruction is executed, what are the contents of AX, the top of the stack, and
SP given that SP=1456H?

Answer:

Note that in 80x86 the lower byte of the register is stored to the lower address. (Little Endian
Convention)

Figure 2.9 one push instruction impact on the SS and SP

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AX=2174H (stays the same), SP=1454H (decremented by 2)

Example 2

You are given SP=1236H, AX=24B6H, DI=85C2H, and DX=5F93H, show the contents of the
stack and SP as each of the following instructions is executed.

POP AX

POP DI

POP DX

Answer:

Figure 2.10 Three push instructions impact on the SS and SP

After pushing data from registers to the stack, registers AX, DI and DX stay the same. PUSH
seems like a copy from - to (not cut)

4.1.2.Popping operation in Stack

It is the opposite procedure of Push instruction

Loading the contents of the stack into the CPU register is called a pop.

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Copy the top of the stack into destination (16-bit register)

SP register is incremented by 2

Example 1

Assume that SP=134AH and the illustration on the left shows the content of the top of the stack.
What will be the content of AX and SP after the execution of the following instructions?

SUB AX, AX

POP AX

Answer:

Note that in 80x86 the byte in the Low address goes into the low byte. The byte in the high address
goes into the high byte. (Little Endian Convention)

Figure 2.11 Impact of pop instructions on the SS, destination and SP

Note:

 SUB AX, AX makes AX empty before transferring data

 After popping data from SS to the register AX. SS will be empty

Example 2: Assume that the stack is shown below, and SP=18FAH, show the contents of the
stack and registers as each of the following instructions is executed.

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SUB CX, CX

SUB DX, DX

SUB BX, BX

POP CX

POP DX

POP BX

Answer:

Figure 2.12 Impact of three pop instructions on the SS, destination and SP

Note:

When pushing data from SS to destination, this data is erased from SS.

Exercise (Exchanging data between two registers)

If the stack pointer (SP) = 3499, data index (DI) = 1A5E and BX = 2E4C, what are the contents
of SP, DI and BX after the execution of the following instructions. (Assume the processor is 8086).

PUSH DI

PUSH BX
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POP DI

POP BX

Answer:

To do this, proceed like figures 2.10 and 2.12, you will get the following results

Before Instructions After

SP = 3499 PUSH DI SP = 3499

DI = 1A5E PUSH BX DI = BX= 2E4C

BX = 2E4C POP DI BX = DI = 1A5E

POP BX

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CHAPTER 3: 8086 ADDRESSING MODES

1. Definition

Different methods for accessing an address to a specific data are provided to a processor by the
addressing mode. The specified function is carried out on the data when an instruction is executed
by an 8086 processor. The memory location contains operated data. There are many ways for
defining a data address. We refer to these methods as addressing modes.

2. Classification of Addressing Modes

Addressing mode can be classified according to the following diagram given by figure 3.1.

Figure 3.1 Classification of addressing modes

2.1.Data addressing mode

This mode relates to data transfer operations, i.e., data is moved between registers or from memory
to the 8086 processor's internal registers.

Example: MOV AX, DX

2.2.Program Memory addressing Modes

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Program memory addresses are used throughout numerous activities in this mode.

Example: The code execution control of the JMP AX instruction jumps to the current code segment
location, which is addressed by the contents of the AX register.

Modes of stack memory addressing:

2.3.Stack memory addressing mode.

Stack registry procedures are involved in this mode. An example of an instruction that copies the
contents of the AX register to the stack is PUSH AX.

3. Size of exchanges with memory

Memory is organized in bytes.

When we perform an instruction between a register and data located in memory, it is the register
that determines the size of the operation.

If the register is a simple register (8 bits), the operation will be carried out with a single memory
location.

MOV [address], AL; gives

Figure 3.2 Instruction size when moving one byte to memory location

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If the register is 16 bits (2 bytes), the operation will be carried out with two memory locations

MOV [address], AX; gives

Figure 3.3 Instruction size when moving a word to memory locations

Note that it is the lower part of the register which is processed first, and this in both directions

When we perform an operation between a constant and a memory location, there is ambiguity. The
processor does not know whether to consider the constant on 8 bits or on 16 bits. We must use the
BYTE and WORD prefixes to specify the number of bytes to move:

Figure 3.4 Instruction size when moving a constant (byte/word) to memory locations

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Example

MOV BX, 4000h; address

MOV AX, 2233h

MOV [BX], AX

MOV word [BX+2], 4455h

MOV byte [BX+4], 66

MOV byte [BX+5], 77

a. Show the ram in hexadecimal from position 4000H

b. Show the ram in decimal from position 4000H
4. Data addressing mode

Note: We will use MOV instruction to explain all the data addressing modes.

4.1.Register addressing mode

 A copy of a word or byte is transferred from the source register to the destination register
using register addressing.
 The most frequently used and easiest to use type of data addressing is register addressing,
once you know the register names.
 Register addressing for 8-bit names: AH, AL, BH, BL, CH, CL, DH, and DL.
 AX, BX, CX, DX, SP, BP, SI, DI, IP, CS, SS, DS, and ES are the names of the 16-bit
registers.
 It is not permitted in microprocessors to combine an 8-bit register with a 16-bit register.

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 One never uses the code segment register (CS) as a destination.

 MOV instructions from segment to segment are not allowed.

Example

MOV AL, BL ; Copies 8-bit content of BL into AL

MOV AX, CX ; Copies 16-bit content of CX into AX
MOV EX, DS ; Not allowed (segment to segment)
MOV BL, DX ; Not allowed (mixed size)
MOV CS, AX ; Not allowed (Code segment register may not be destination register)

4.2.Immediate addressing

Immediate addressing transfers the source, an immediate byte or word data, into the destination
register. Immediate data means constant data, whereas data transferred from a register or memory
location are variable data.

Example

MOV BL, 44 ; Copies 44 decimal (2CH) into BL

MOV AX, 44H ; Copies 0044H into AX
MOV AL, ‘A’ ; Copies ASCII of A into AL (8 bits)

MOV SI, 0 ; copies a 0000h into SI (16 bits)

MOV AX, ‘AB’ ; copies ASKI of A and B into AX (16 bits)

MOV CL, 11001110 B ; copies 11001110 binary into CL (8 bits)

Figure 3.5 Register addressing mode

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4.3.Direct addressing

In this mode, one operands references a memory location and other operand references a register.

Example 1

MOV AX, [6107 h]

MOV [6107 h], CL

The square brackets around 6107h denotes the content of the memory. Here, data resides in a
memory location in the data segment, whose physical address may be computed using 6107 h as
the offset address and content of DS (see next table) as segment address. The physical address,
here, is:

ℎ = ∗ 10 ℎ + 6107 ℎ.

In MOV AX, [6107 h], the data located at [ ∗ 10 ℎ + 6107] will be moved to AX

MOV [6107 h], CL, the content of CL will be moved to the address [ ∗ 10 ℎ + 6107]

Important: the following table gives each addressing mode with its relative operands
and default segment

Example 2

Find the physical address of the memory location and its content after the execution of the following
instructions, assuming that DS = 1512h

MOV AL, B2h

MOV [6789], AL

Answer:

First AL is loaded with B2h

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Second, it’s clear referring to the next table that the addressing mode here is the direct addressing
mode. So the default segment is DS and the offset is 6789. We are needed to calculate the physical
address at which we will move the content of the register AL.

Physical address = DS ∗ 10 h + 6789 h

Physical address = 15120h + 6789 h = ( )

Hence the memory location having the address 1B8A9 will contain the content of AL which is B2h

Figure 3.6 Direct addressing mode

Addressing mode Operands Default segment

1. Register addressing Registers None

2. Immediate addressing Immediate data and register None

3. Direct addressing [offset] DS

[BX] DS

4. Register indirect addressing [SI] DS

[DI] DS

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[BP] SS

[BX] + displacement DS
5. Based relative addressing
[BP] + displacement SS

[DI] + displacement DS
6. Indexed relative addressing
[SI] + displacement DS

[BX][SI] + displacement DS

[BX][DI]+ displacement DS
7. Based Indexed relative addressing
[BP][SI] + displacement SS

[BP][DI] + displacement SS

4.4.Register indirect addressing (see table)

 Register indirect addressing is the process of moving a word or byte from a register to a
memory address that is pointed to by an index or base register.
 BP, BX, DI, and SI are the base and index registers. The offset address of the memory
location is stored in these registers.
 When using register indirect addressing or any other addressing mode that addresses
memory using BX, DI, or SI, the data segment (DS) is automatically used.
 Stack segment (SS) is used by default if memory is addressed by BP register.
 In assembly language, the [] sign indicates indirect addressing.
 As an illustration, MOV CX, [BX] copies the word contents of the memory location in the
data segment that BX targeted into CX.
 MOV [BP], DL; copies DL to the memory address in the stack segment that BP addresses
 MOV [DI], [BX]; Memory to memory transfers are not allowed except with string
instructions

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Figure 3.7 Register indirect addressing mode

Example

Assume that DS = 1120, SI = 2498, and AX = 17FE. Shown the content of the memory location
after the execution of MOV [SI], AX

Answer:

Make attention here!! We are moving 16 bits (AX) to a certain memory location having the size
of only 8 bits!! We proceed then as follow

From the form of the instruction MOV [SI], AX and referring to the table we understand that we
are using the Register indirect addressing mode. The used offset is SI. So DS is the default segment
used to generate the physical address.

Physical address = DS ∗ 10 h + SI

ℎ = 11200 + 2498 = ( )

The memory location addressed by can store only 8 bits. Don’t forget we have to move
AX=17FE (16 bits = 8bits + 8 bits). We need then, another memory location to save (store) the
second half of AX. In 8086 microprocessor (indirect addressing mode) the solution is:

ℎ ( )+

So 13699 (13698+1) will be used to store the remaining byte of AX.

Finally:

The memory location addressed by 13698 will store AL = FE

The memory location addressed by 13699 will store AH = 17

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Figure 3.8 Register indirect addressing mode moving 16 bits

4.5.Based-Relative addressing
 In the based relative addressing mode, base registers BX and BP as well as displacement
value are used to generate the physical address.
 The default segment used to calculate the physical address are DS when the using BX and
SS when using BP

Example

MOV CX, [BX] +10

It means, moving the data in the logical address:

 DS: [BX] +10 into CL

The content of [Physical address = DS ∗ 10 + BX + 10] into CL

 DS: [BX] +10+1 into CH

The content of [Physical address + 1 = DS ∗ 10 + BX + 10 + 1] into CH

 Alternative coding are:

 MOV CX, [BX+10]

MOV CX, 10[BX]

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 The lower address content will go into CL

 The higher address content will go in CH
 BX+10 is called the effective address used in Intel literature
4.6.Indexed-Relative addressing
 The indexed relative addressing mode works the same as based relative, except the registers
DI and SI hold the offset address.
 The default segment is always DS whatever using SI or DI

Example

 MOV DX, [SI] +5

The content of [Physical address = DS ∗ 10 + SI + 5] into DL

The content of [Physical address + 1 = DS ∗ 10 + SI + 5 + 1] into DH

 MOV CL, [DI]+20

The content of [Physical address = DS ∗ 10 + DI + 20] into CL

Here, No need for going to the physical address +1. The destination (CL) is 8 bit size.

Numerical example

Assume that: DS=4500, SS=2000, BX=2100, SI=1486, DI=8500, BP=7814 and AX=2512

Show the exact physical memory location when AX is stored in each of the following. Data are in
hexadecimal

a. MOV [BX] + 20, AX

b. MOV [SI] + 10, AX
c. MOV [DI] + 4, AX
d. MOV [BP] + 12, AX

Answer:

In each case, the physical address PA=Segment*10+Offset register + Displacement.

a. It is based relative addressing mode using BX as offset. Default segment will be DS

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Logical address DS: BX+20

PA=DS*10+BX+20 and PA+1=DS*10+BX+20+1 So

Location 47120 = (12) and 47121 = (25)

b. It is indexed relative addressing mode using SI as offset .Default segment will be DS

Logical address DS: SI+10

PA=DS*10+SI+10 and PA+1=DS*10+SI+10+1 So

Location 46496 = (12) and 46497 = (25)

c. It is indexed relative addressing mode using SI as offset .Default segment will be DS

Logical address DS: DI+4

PA=DS*10+DI+4 and PA+1=DS*10+DI+4+1 So

Location 4D504 = (12) and 4D505 = (25)

d. It is based relative addressing mode using BP as offset. Default segment will be SS

Logical address SS: BP+20

PA=SS*10+BP+20 and PA+1=SS*10+BP+20+1 So

Location 27826 = (12) and 27827 = (25)

4.7.Based-Indexed relative addressing

By combining based and indexed addressing mode, a new addressing mode is generated called the
based indexed addressing mode.

In this mode, one base register and one index register are used to generate the physical address

Example (refer to the reference table to know the default segment).

 MOV CL, [BX] [DI] +20 ; PA=DS*10+BX+DI+8

 MOV CH, [BX] [SI] +20 ; PA=DS*10+BX+SI+20
 MOV AH, [BP] [DI] +12 ; PA=SS*10+BP+DI+12
 MOV AH, [BP] [SI] +29 ; PA=SS*10+BP+SI+29

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CHAPTER 4: 8086 INSTRUCTIONS SETS

1. Why Learn Assembly Language?

 Learn how a processor works
 Understand basic computer architecture
 Explore the internal representation of data and instructions
 Gain insight into hardware concepts
 Allows creation of small and efficient programs
 Allows programmers to bypass high-level language restrictions
 Might be necessary to accomplish certain operations
2. Data declaration directives
 ASSUME Directive

To tell the assembler to use the logical segment name for a given segment, we use the ASSUME
directive. There are just four physical segments that the 8086 uses for direct operation: a code
segment, a data segment, a stack segment, and an additional extra segment.

Examples

ASUME CS: CODE

This instructs the assembler to treat the logical segment CODE, which contains the program's
instruction instructions, as a code segment.

ASUME DS: DATA

This instructs the assembler to look for data in the logical segment DATA for any instruction that
references data in the data segment.

 EQU Directive (Define a constant)

IS used to define a constant without occupying a memory location

Example

My-constant EQU A7h; My-constant can be used in many places in the program

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 DB Directive (Define a byte)

A byte can be stored in memory or declared as a variable using the DB directive.

Example
PRICE DB 49h, 98h, 29h;Declare an array of 3 bytes, named as PRICE and initialized to the
given value.

NAME DB ’A-C=EF’; declare an array of 6 bytes and initialize with ASCII code for letters and
symbols

DATA1 DB FFh, FFh, FFh, FFh, FFh; Fill 5 bytes with FFh

DATA2 DB 5DUP (FFh); same as DATA1, Fill 5 bytes with FFH (it saves time and typing)

TEMP DB 100 DUP (?); Set 100 bytes of storage in memory and give it the name as TEMP, but
leave the 100 bytes uninitialized (empty). Program instructions will load values into these
locations.

 DW Directive (Define word = 16 bits)

The DW directive is used to define a variable of type word or to reserve storage location of type
word in memory.

Example

Multiplexer DW 1A2Bh; this declares a variable of type word and named it as Multiplexer. This
variable is initialized with the value 1A2B h when it is loaded into memory to run.

Table DW ABCDh, 5678h, FFFFh; this declares an array of 3 words and initialized with specified
values.

Table2 DW 100 DUP (0); Reserve an array of 100 words of memory and initialize all words with

0000. Array is named as Table2.

 DD Directive (Define double words = 32 bits)

The DD directive is used to allocate memory locations that are 4 bytes (two word)

Example:

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DATA1 DD 1023; allocation of 4 bytes to store specified data

DATA2 DD 0111001101010101; allocation of 4 bytes to store specified data

DATA3 DD A2B1FE27h ; allocation of 4 bytes to store specified data

DATA4 DD C1h, B2h, 84h, F1h ; allocation of 16 bytes to store specified data

 DQ Directive (Define four words = 64 bits)

Is used to allocate memory 8 bytes (4 words) in size. This can be used to represent any variable up
to 64 bit wide

DATA1 DQ AF2345h; allocation of 8 bytes to store specified data

DATA2 DQ ‘HELLO’; allocation 5*4word = 20 words = 40 bytes to store specified data

DATA3 DQ ? ; Allocation of 4 empty words.

 END Directive

END directive is placed after the last statement of a program to tell the assembler that this is the
end of the program module

 ENDP Directive

ENDP directive is used along with the name of the procedure to indicate the end of a procedure to
the assembler

Example:

SCD_COM_NUM PROCE; It start the procedure;

Insert some steps here to find the second complement of a number ….

SCD_COM_NUM ENDP; Hear it is the End for the procedure

 ENDS Directive

This ENDS directive is used with name of the segment to indicate the end of that logic segment.

Example:

CODE SEGMENT;

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Hear it start the logic segment containing code. Some instructions statements to perform the
logical and or arithmetic operations ….

CODE ENDS; End of segment named as CODE

 INCLUDE Directive

This INCLUDE directive is used to insert a block of source code from the named file into the
current source module.

 DOS Function Calls

AH 00H: Terminate a Program

AH 01H: Read the Keyboard

AH 02H: Write to a Standard Output Device

AH 08H: Read a Standard Input without Echo

AH 09H: Display a Character String

AH 0AH: Buffered keyboard Input

INT 21H: Call DOS Function

 PTR operator

This PTR operator is used to assign a specific type of a variable or to a label.

Example:

INC [BX]; this instruction will not know whether to increment the byte pointed by BX or a word
pointed by BX.

INC BYTE PTR [BX]; increment the byte pointed to by BX

3. Standard organization of an Assembly Language program (ALP)

Here is the Code written on assembly language for 8086 microprocessor. This code find if the
number is positive or negative.

Through this sample code we will how an ALP is organized

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Figure 4.1 Standard organization of an APL

4. Instructions Sets
4.1. Data transfer instructions
 MOV destination, Source
 MOV Reg1, Reg2; copy Reg2 in Reg1
 MOV Reg, Mem; copy Mem in Reg
 MOV Mem, Reg; copy Reg in Mem
 MOV Size Mem, immediate; copy immediate in a memory location (Size = byte or Word)

MOV Mem,Mem ; Memory to memory is not allowed

Example

 MOV AX, 0B800h ; set AX to hexadecimal value of B800h.

 MOV DS, AX ; copy value of AX to DS.
 MOV CL, 'A' ; set CL to ASCII code of 'A', it is 41h.
 MOV CH, 1101_1111b ; set CH to binary value.

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 MOV BX, 15Eh ; set BX to 15Eh.

 MOV [BX], CX ; copy contents of CX to memory at B800:015E
 RET ; returns to operating system.

 PUSH Reg (Reg should be 16 bits size)

SP decremented by 2

Copy Reg (16 bit) to Stack Segment location pointed by SP

 PUSH Reg(16)
 PUSH Word [Address]
PUSH immediate, not allowed
PUSH Reg (8), not allowed
 POP Reg (Reg should be 16 bit size)

SP incremented by 2

Copy two memory location content from by SP to 16 bits Reg.

Note (PUSH and POP instruction where discussed in chapter 2)

 XCHG Destination, Source

Exchanges the Source operand with the Destination operand. Impossible on segment.

 XCHG destination, Source

 XCHG R1, R2
 XCHG [adr], R
 XCHG R, [adr]

XCHG [adr ] , [ adr] is Not allowed

Example

For the figure 4.2. What is the result of executing the following instruction?

XCHG AX, [0002]

First, we need to determine the physical address, from which the data will be exchanged.

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From the instruction, it is sample right now to determine the addressing mode and the default
segment as described in chapter 3

Indirect addressing mode and DS is the default segment, so

Physical address = DS ∗ 10 + offset

Physical address = 01000 + 0002 = 01002

 The content of 01002 will go to AL and vice versa

 The content of 01002+1 will go to AH and vice versa

Figure 4.2 XCHG example

 LEA Register(16), Source

This instruction determines the offset of the variable or memory location named as the source and
puts this offset in the indicated 16-bit register. LEA does not affect any flag.

 LEA BX, PRICES Load BX with offset of PRICE in DS

 LEA BP, SS: STACK_TOP Load BP with offset of STACK_TOP in SS
 LEA CX, [BX][DI] Load CX with the Effective Address = [BX] + [DI]

Example

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Figure 4.3 8086 LEA instruction

 LDS Register, Memory address of the first word

This instruction loads new values into the specified register and into the DS register from four
successive memory locations. The word from two memory locations is copied into the specified
register and the word from the next two memory locations is copied into the DS registers. LDS
does not affect any flag.

 LDS BX, [4326] Copy content of memory at displacement 4326H in DS to BL, content of
4327H to BH. Copy content at displacement of 4328H and 4329H in DS to DS register.
 LDS SI, SPTR Copy content of memory at displacement SPTR and SPTR + 1
 LES Register, Memory address of the first word

This instruction loads new values into the specified register and into the ES register from four
successive memory locations. The word from the first two memory locations is copied into the
specified register, and the word from the next two memory locations is copied into the ES register.
LES does not affect any flag.

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 LES BX, [789AH] Copy content of memory at displacement 789AH in DS to BL, content
of 789BH to BH, content of memory at displacement 789CH and 789DH in DS is copied
to ES register.
 LES DI, [BX] Copy content of memory at offset [BX] and offset [BX] + 1 in DS to DI
register. Copy content of memory at offset [BX] + 2 and [BX] + 3 to ES register.
 XLAT
 The XLAT (translate) instruction converts of the AL register into a number stored in a
memory table.
 This instruction performs the direct table lookup technique often used to convert one code
to another.
 An XLAT instruction first adds the contents of AL to BX to form a memory address within
the data segment. It then copies the content of this address into AL.
 This is the only instruction that adds an 8-bit number to a 16-bit number.

Figure 4.4 8086 XLAT instruction

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 IN Accumulator, Port
 OUT Port, Accumulator
 To communicate with an external peripheral, the accumulator is AL for the transfer of a
byte.
 To communicate with an external peripheral, the accumulator is AX for the transfer of a
word.
 When the port number is byte (0 to 255 in/out combination), it can be an immediate value
(included in the instruction itself) : Fixed-port addressing
 When the port number is word (0 to 64K in/out combination), it must be loaded in DX
Variable-port addressing

Example:

IN AL, 76H; 8 bits are input to AL from I/O port 76H (fixed port addressing)

IN AL, DX; 8 bits are input to AL from I/O port DX (variable port addressing)

OUT 51H, AX; 16-bits are output to I/O port 51H from AX (fixed port addressing)

OUT DX, AL; 8-bit data are output to I/O port DX from AL (variable port addressing)

Figure 4.5 IN-OUT instruction with 8086 microprocessor

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4.2. Arithmetic instructions

 ADD Destination, Source
 ADC Destination, Source
 ADD AH, 87H; Add immediate number 87H to content of AH. Result in AH
 ADC CH, BH; Add content of BH plus carry status to content of CH. Result in CH
 ADD DX, AX; Add content of AX to content of DX. Result in DX
 ADD BX, [SI]; Add word from memory at offset [SI] in DS to content of BX
 ADC AL, VALUE [BX]; Add byte from effective address VALUE [BX] plus carry status
to content of AL
 ADD AL, 100 [BX] Add content of memory at effective address 100 [BX] to AL

Example 1 (ADD Instruction)

Show how the flag register is affected by

MOV AL, F5h

ADD AL, 0Bh

After the addition, the AL register (destination) will contain 00h and the flags are as follows:

CF = 1 since there is a carry out from D7

SF = 0 the status of D7 of the result

PF = 1 the number of 1’s is zero (zero is an even number)

AF = 1 There is a carry from D3 to D4

ZF = 1 the result of the instruction is zero (for the 8 bit, don’t consider the last carry)

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Example 2 (ADD Instruction)

Write an ALP to calculate the total sum of 5 bytes of data. Each data does not make more than
255 (FFh). The decimal data are as follows:

50, 111, 144, 199 and 233

DATA SEGMENT
COUNT EQU 05; we define a count with = number of bytes to be added
DATA DB 50, 111, 144, 199, 233; define here your data
SUM DW ? ; Variable to store the sum of the 5 bytes
DATA ENDS; close the segment
CODE SEGMENT
ASSUME CS: CODE, DS: DATA; assign name to each segment
MAIN:
MOV AX, DATA; move your data to AX
MOD DS, AX; move AX to DS because we cannot move data directly to DS
MOV CX, COUNT; CX will be used as a counter
MOV SI, OFFSET DATA; point the start of the defined data with SI
MOV AX, 00H; clear AX, it may be loaded with other data
ALGO; optional name to indicate the start of your developed code
ADD AL, [SI]; add the first byte pointed by SI with the content of AL (00). Result in AL
JNC NEXT; if NO carry go to the line NEXT immediately
INC AH; if there is a carry, save it into AL that was initialized to zero
NEXT ; once we are here will do the following
INC SI; increment SI to point the next data in the memory
DEC CX; decrement CX: saying that it remains CX-1 bytes to process
JNZ ALGO; if CX does not reach zero come back to ALGO
MOV SUM, AX; once we process all bytes, their sum will be stored in SUM
MOV AH, 4CH; terminate the code
INT 21H; return to DOS
CODE ENDS; close the Code Segment
END MAIN; close the main
Example 3 (ADD AND ADC Instruction)

Write an ALP to calculate the total sum of 5 words of data. Each data does not make more than
65555 (FFFFh). The decimal data are as follows:

25411, 26244, 29387, 37549 and 42876

DATA SEGMENT
COUNT EQU 05; we define a count with = number of bytes to be added
DATA DW 25411, 26244, 29387, 37549 and 42876; define here your data
SUM DW 2DUP (?); Variable to store the sum of the 5 words

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DATA ENDS; close the segment

CODE SEGMENT
ASSUME CS: CODE, DS: DATA; assign names to each segment
MAIN:
MOV AX, DATA; move your data to AX
MOD DS, AX; move AX to DS because we cannot move data directly to DS
MOV CX, COUNT; CX will be used as a counter
MOV SI, OFFSET DATA; point the start of the defined data with SI
MOV AX, 00H; AX will store the sum
MOV AX, BX; BX will store the carry
ALGO; optional name to indicate the start of your developed code
ADD AX, [SI]; add the first word pointed by SI with the content of AX (0000). Result in AX
JNC NEXT; if no carry go to the line NEXT immediately
ADC BX, 0; if there is carry from the previous ADD, store it in BX
NEXT: ; once we are here will do the following:
INC SI; increment SI twice
INC SI; to point the next word (don’t forget we are processing words = 2 bytes)
DEC CX; decrement CX: saying that it remains CX-1 words to process
JNZ ALGO; if CX does not reach zero come back to ALGO
MOV SUM, AX; once we process all words, their sum will be stored in SUM (2 bytes)
MOV SUM+2, BX; first two bytes for AX and next two byte for BX
MOV AH, 4CH; terminate the code
INT 21H; return to DOS
CODE ENDS; close the Code Segment
END MAIN; close the main
 SUB Destination, Source
 SBB Destination, Source
 SUB AX, CX; AX – CX; Result in AX
 SBB BH, DL; Subtract content of DL and content of CF from content of BH. Result in BH
 SUB DX, F212H; subtract immediate number F212H from DX
 SBB AX, [9876H]; Subtract word at displacement 9876H in DS and content of CF from
AX
 SUB VALUE [BX], A2H; Subtract A2 from byte at effective address VALUE [BX], if
VALUE is declared with DB; Subtract A2 from word at effective address VALUE [BX],
if it is declared with DW.
 SBB CX, TABLE [BX]; Subtract word from effective address TABLE [BX] and status of
CF from CX.

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 SBB TABLE [BX], CX; Subtract CX and status of CF from word in memory at effective
address TABLE [BX].

Assuming that the 8086 is executing a simple subtract instruction, we can summarize the steps
of the hardware CPU in executing the SUB instruction for unsigned numbers as follows:

 Take the second complement of the source operand

 ADD it to the source operand
 Invert the carry

Example 1 (SUB Instruction)

Show the steps involved in the following:

MOV AL, 3FH

MOV BH, 23H

SUB AL, BH

AL = 3FH = 00111111

BH = 23H = 00100011

AH-BH=AH+2’s (BH) = 00111111+2’s (00100011) = 00111111+11011101

00111111+11011101=00011100 AND CF=1

The flags would be set as follows:

CF=0, ZF=0, AF=0, PF=0 AND SF=0

The programmer must look at the carry flag (not the sign flag) to determine if the result is positive
or negative

After the execution of SUB

If CF=0, the result is positive

If CF=1 the result is negative and the destination has the second complement of the result (SUB
result). Normally the result is left in second complement, but the NOT and INC instructions can
be used to change it.

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Example 2 (SUB Instruction)

Analyze the following program:

;From the data segment
X DB 4CH
Y DB 6EH
Z DB ?
;From the code segment
MOV DH, X; save X in DH
SUB DH, Y; SUB Y from X
JNC NEXT; if CF=0 move to the line NEXT
NOT DH; if CF=1 the take the first complement
INC DH; add 1 to get the second complement
NEXT:
MOV Z, DH; save DH in Z

From the SUB instruction shown above, the CF should be 1. (With respect to CPU steps)

The result is then negative, so the result will be: Minus (2’s (1101 1110)) = - 34 = -22H

Example 3 (SUB AND SBB Instruction)

Analyze the following program:

;From the data segment
X DD 062562FAH; 0625 62FA
Y DD 0412963BH; 0412 963B
RESULT DD ?
;From the code segment
MOV AX, WORD PTR X; AX=62FA
SUB AX, WORD PTR Y; SUB 963B from 62FA
MOV WORD PTR RESULT, AX; save the SUB result of lower word
MOV AX, WORD PTR X+2; AX=0625
SBB AX, WORD PTR Y+2; AX=0625-0412-C (C coming from SUB instruction)
MOV WORD PTR RESULT+2, AX; save the result of upper word

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After the SUB instruction AX=62FA-963B=CCBF and carry flag is set (=1). Since CF=1, when
the SBB is executed AX=0625-0412-1-212, therefore the result stored in RESULT is 0212CCBF

 MUL Source
 MUL BH; Multiply AL with BH; result in AX
 MUL CX; Multiply AX with CX; result high word in DX, low word in AX
 MUL BYTE PTR [BX]; Multiply AL with byte in DS pointed to by [BX]
 MUL FACTOR [BX]; Multiply AL with byte at effective address FACTOR [BX], if it is
declared as type byte with DB. Multiply AX with word at effective address FACTOR [BX],
if it is declared as type word with DW.
 MOV AX, MCAND_16; Load 16-bit multiplicand into AX
 MOV CL, MPLIER_8; Load 8-bit multiplier into CL
 MOV CH, 00H; Set upper byte of CX to all 0’s
 MUL CX; AX times CX 32-bit result in DX and AX
 IMUL Source
 IMUL BH; Multiply signed byte in AL with signed byte in BH; result in AX.
 IMUL AX; Multiply AX times AX; result in DX and AX
 CBW

CBW (Convert Byte to Word) performs an extension of AL into AH. We write the content of AL
in AX respecting the sign (MSB of AL)

If AL contains a positive number (MSB=0), we complete with 0s to obtain the 16-bit representation
of AX

If AL contains a negative number (MSB=1), we complete with 1s to obtain the 16-bit

representation of AX.

AL= (+5) = 0000 0101  AX = 0000 0000 0000 0101

AL= (- 5) = 1111 1011  AX = 1111 1111 1111 1011

 MOV CX, MULTIPLIER; Load signed word in CX
 MOV AL, MULTIPLICAND; Load signed byte in AL
 CBW; Extend sign of AL into AH
 IMUL CX; Multiply CX with AX and the result in DX and AX

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 DIV Source
 DIV BL; Divide word in AX by byte in BL; Quotient in AL, remainder in AH
 DIV CX; Divide down word in DX and AX by word in CX; Quotient in AX, and remainder
in DX.
 IDIV Source
 IDIV BL; Signed word in AX/signed byte in BL
 IDIV BP; Signed double word in DX and AX/signed word in BP
 IDIV BYTE PTR [BX]; AX / byte at offset [BX] in DS
 INC Destination
 INC BL; Add 1 to contains of BL register
 INC CX; Add 1 to contains of CX register
 INC BYTE PTR [BX]; Increment byte in data segment at offset contained in BX.
 INC WORD PTR [BX]; Increment the word at offset of [BX] and [BX + 1] in the data
segment.
 DEC Destination
 DEC CL; Subtract 1 from content of CL register
 DEC BP; Subtract 1 from content of BP register
 DEC BYTE PTR [BX]; Subtract 1 from byte at offset [BX] in DS.
 DEC WORD PTR [BP]; Subtract 1 from a word at offset [BP] in SS.
 DEC COUNT; Subtract 1 from byte or word named COUNT in DS. Decrement a byte if
COUNT is declared with a DB; Decrement a word if COUNT is declared with a DW.
 CMP Destination, Source

AF, OF, SF, ZF, PF, and CF are updated by the CMP instruction. For the instruction
CMP destination, source the values of CF, ZF, and SF will be as follows:

First 8086 executes (destination – source) and check for flags:

 If (CF ZF SF) = (010) then destination =source

 If (CF ZF SF) = (000) then destination > source
 If (CF ZF SF) = (101) then destination < source
 CMP AL, 01H; Compare immediate number 01H with byte in AL

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 CMP BH, CL; Compare byte in CL with byte in BH

 CMP CX, TEMP; Compare word in DS at displacement TEMP with word at CX
 TEST Destination, Source

This instruction ANDs the byte / word in the specified source with the byte / word in the
specified destination. Flags are updated, but neither operand is changed. The test instruction is
often used to set flags before a Conditional jump instruction.

 TEST CL, BL; AND CL with BL. No result stored; Update PF, SF, ZF.
 TEST AX, 000AH; AND AX with immediate number 000AH; No result stored; Update
PF, SF, ZF
 TEST BP, [BX] [DI]; AND word are offset [BX] [DI] in DS with word in BP. No result
stored. Update PF, SF, and ZF
4.3. Logic instructions
 NOT Destination

First complement of the destination

 NOT DX; Complement content or DX register

 NOT BYTE PTR [BP]; Complement memory byte at offset [BP] in data segment.
 NEG Destination
 NEG AL; Replace number in AL with its 2’s complement
 NEG BX; Replace number in BX with its 2’s complement
 NEG BYTE PTR [BX]; Replace byte at offset BX in DX with its 2’s complement
 NEG WORD PTR [BP]; Replace word at offset BP in SS with its 2’s complement
 AND Destination, Source
 AND AX, [DI]; AND word in DS at offset [DI] with word in AX register; Result in CX
register
 AND AL, DH; AND byte in AL with byte in DH; Result in AL
 AND BX, 00FFH; 00FFH Masks upper byte, leaves lower byte unchanged.

Force a bit to 0:

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To force a bit to 0 without modifying the other bits, we use the logical operator AND and these
properties:

Bit AND 0 = 0 (0 = absorbing element of AND)

Bit AND 1 = bit itself (1 = neutral element of AND)

 OR Destination, Source
 OR BH, DL; DL ored with BH, result in BH, DL not changed
 OR BP, SI; SI ored with BP, result in BP, SI not changed

Forcer un bit à 1 :

Force a bit to 1: To force a bit to 1 without modifying the other bits, we use the logical operator
OR and these properties:

Bit OR 1 = 1 (1 = absorbing element of OR)

Bit OR 0 = bit itself (0= neutral element of OR)

 XOR Destination, Source

a b a XOR b
0 0 0
0 1 1

1 0 1
1 1 0

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 XOR CL, BH; Byte in BH exclusive-ored with byte in CL. Result in CL. BH not changed.
 XOR BP, DI; Word in DI exclusive-ored with word in BP. Result in BP. DI not changed.

Invert a bit:

To invert the value of a bit without modifying the other bits, we uses the XOR logical operator
and these properties:

Bit XOR 1 =

Bit XOR 0 = Bit itself (0 = neutral element of XOR)

Logical Shifts vs. Arithmetic Shifts

A logical shift fills the newly created bit position with zero. If we do a single logical right shift on
11001111, it becomes 011001111.

An arithmetic shift is filled with a copy of the original number’s sign bit. If we do a single
arithmetic right shift on 11001111, it becomes 11100111.

 SHL Destination, Count

 SHL BX, 1; Shift word in BX 1 bit position left, 0 in LSB

 SHL reg, imm8
 SHL mem, imm8
 SHL reg, CL
 SHL mem, C L

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MOVBL, 8FH; BL = 1000111b

SHL BL, 1; BL = 00011110b, CF = 1
SHL can be used to perform a high-speed multiplication by powers of 2:
MOV DL, 5; DL = 00000101b=5
SHL DL, 1; DL = 00001010b=10
MOV DL, 2; DL = 00101000b, = 40

 SAL Destination, Count (Shift Arithmetic Left) is identical to the SHL instruction.

 SHR Destination, Count

 SHR BP, 1; Shift word in BP one bit position right, 0 in MSB

 SHR reg, imm8
 SHR mem, imm8
 SHR reg, CL
 SHR mem, C L
MOVAL, D0H; AL = 11010000b
SHR AL, 1; AL = 01101000b, CF = 0
SHR can be used to perform a high-speed division by 2 :
MOV DL, 32; DL = 00100000b = 32
SHR DL, 1; DL = 00010000b = 16
MOV AL, 040h; AL = 01000000b = 64
SHR AL, 3; AL = 00001000b = 8
 SAR Destination, Count (Shift Arithmetic Right)

 SAR DX, 1; Shift word in DI one bit position right, new MSB = old MSB
 SAR reg, imm8

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 SAR mem, imm8

 SAR reg, CL
 SAR mem, C L
MOVAL, F0H; AL = 11110000b = -16
SHR AL, 1; AL = 11111000b = -8; CF = 0
SAR can be used to perform a high-speed signed division by 2 :
MOV DL, -128; DL = 10000000b = -128
SHR DL, 3; DL = 11110000b = -16
 ROL Destination, Count

 ROL AX, 1; Rotate the word in AX 1 bit position left, MSB to LSB and CF
 ROL AX, 1; Rotate the word in AX 1 bit position left, MSB to LSB and CF
 MOV CL, 04H; Load number of bits to rotate in CL
 ROL BL, CL; Rotate BL 4 bit positions
 MOV AL, 40H; AL = 01000000b
 ROL AL, 1; AL = 10000000b, CF = 0
 ROL AL, 1; AL = 00000001b, CF = 1
 ROL AL, 1; AL = 00000010b, CF = 0
 ROR Destination, Count

 ROR BL, 1 Rotate all bits in BL right 1 bit position LSB to MSB and to CF
 ROR reg, imm8
 ROR mem, imm8
 ROR reg, CL
 ROR mem, C L

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 MOV AL, 01H; AL = 00000001b

 ROR AL, 1; AL = 10000000b, CF = 1
 ROR AL, 1; AL = 01000000b, CF = 0
 ROR AL, 1; AL = 00100000b, CF = 0
 RCL Destination, Count

 RCL DX, 1; Word in DX 1 bit left, MSB to CF, CF to LSB

 CLC; CF = 0
 MOV BL, 88H; CF = 0 BL = 10001000b
 RCL BL, 1; CF = 1 AL = 00010000b
 RCL BL, 1; CF = 0 AL = 00100001b
 RCR Destination, Count

 RCR BX, 1; Word in BX right 1 bit, CF to MSB, LSB to CF

4.4. Control instructions
 JMP (unconditional jump to specified destination)

 JMP ABC
 This instruction fetches the next instruction from address at label ABC.
 CLC
 (Clear Carry), put CF at 0
 STC
 (Set Carry) , put CF at 1
 CMC
 (Complement) , put CF at its complement
 JAE / JNB / JNC
 (jump if above or equal / jump if not below / jump if no carry)
 JB / JC / JNAE

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 (jump if below / jump if carry / jump if not above or equal)

 JG / JNLE
 (Jump if greater / jump if not less than or equal)
 JGE / JNL
 (Jump if greater than or equal / jump if not less than)
 JL / JNGE
 (Jump if less than / jump if not greater than or equal)
 JLE / JNG
 (Jump if less than or equal / jump if not greater)
 JE / JZ
 (Jump if equal / jump if zero)
 JNE / JNZ
 (Jump not equal / jump if not zero)
 JS
 (Jump if signed / jump if negative)
 JNS
 (Jump if not signed / jump if positive)
 JP / JPE
 (Jump if parity / jump if parity even)
 JNP / JPO
 (Jump if no parity / jump if parity odd)
 JO
 (Jump if overflow)
 JCXZ
 (Jump if the cx register is zero)
 LOOP
 (Jump to specified label if cx ≠ 0 after auto decrement)
 LOOPE / LOOPZ
 (Loop while cx ≠ 0 and zf = 1)

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 LOOPNE / LOOPNZ
 (Loop while cx ≠ 0 and zf = 0)

It’s largely enough at this level……

4.5. String manipulation instructions

……………….

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CHAPTER 5: 8086 PARALLEL INTERFACING BASED ON 8255

1. Introduction

8255A Programmable Peripheral Interface (PPI)

Figure 5.1 Intel 8255 IC

8255A is a general-purpose parallel I/O interface

The 8086 microprocessor operates faster than the peripheral devices. PPI establishes a connection
between peripheral devices and microprocessors.

Figure 5.2 Interfacing 8086 with 8255

8255A has:

Three I/O ports are available (Port A, Port B, and Port C (Upper and Lower))

Three operating modes (will be discussed with more details in next section)

 Mode 0
 Mode 1
 Mode 2

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The block diagram (In/Out pins) of the 8255A is given by the figure 5.3

Figure 5.3 In-Out Pins of 8255

2. Internal Architecture

Figure 5.4 Internal blocs of 8255

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The C port is divided into two high C port and low C port

 : Selection of 8255A by address decoders.

 Port selection is provided by A0 and A1

RD WR CS Read operation

0 0 0 1 0 =

0 1 0 1 0 =

1 0 0 1 0 =

RD WR CS Write operation

0 0 1 0 0 =

0 1 1 0 0 =

1 0 1 0 0 =

1 1 1 0 0 =

RD WR CS 8255 in high impedance

X X X X 1 =ℎ ℎ ( )

X X 1 1 0 =ℎ ℎ ( )

3. 8255A Operation Modes

3.1. Handshaking signals:

Figure 5.5 Handshaking signals 8066-8255

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The process of establishing inter relation between slower peripheral device and microprocessor is
called handshaking.

8255-based devices performs handshaking using some handshaking signals like, Strobe Input
(STB), Acknowledged (ACK), Input Buffer Full (IBF), Output Buffer Full (OBF).

 (Strobe Input): A ‘‘low’’ on this input loads data into the input latch.
 IBF (Input Buffer Full): A ‘‘high’’ on this output indicates that the data has been loaded
into the input latch; in essence, an acknowledgement. IBF is set by input being low
and is reset by the rising edge of the input.
 INTR (Interrupt Request): A ‘‘high’’ on this output can be used to interrupt the
CPU when an input device is requesting service. INTR is set by the is a ‘‘one’’, IBF
is a ‘‘one’’ and INTE is a ‘‘one’’. It is reset by the falling edge of . This procedure allows
an input device to request service from the CPU by simply strobing its data into the port.
INTE A Controlled by bit set/reset of PC4.
INTE B Controlled by bit set/reset of PC2

Figure 5.6 Mode 1 (Strobed Input)

 (Output Buffer Full): The output will go ‘‘low’’ to indicate that the CPU has
written data out to the specified port. The will be set by the rising edge of the
input and reset by Input being low.

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 (Acknowledge Input): A ‘‘low’’ on this input informs the 82C55A that the data from
Port A or Port B has been accepted. In essence, a response from the peripheral device
indicating that it has received the data output by the CPU.
 INTR (Interrupt Request): A ‘‘high’’ on this output can be used to interrupt the CPU
when an output device has accepted data transmitted by the CPU. INTR is set when
is a ‘‘one’’, is a ‘‘one’’ and INTE is a ‘‘one’’. It is reset by the falling edge of .
INTE A Controlled by bit set/reset of PC6.
INTE B Controlled by bit set/reset of PC2.

Figure 5.7 Mode 1 (Strobed Output)

3.2.Input / Output Mode (Configured by Mode definition CR)

3.2.1. Mode 0
 Port A works as simple input or output without handshaking.
 Port B works as simple input or output without handshaking.
 Port C can be used together as an additional 8 bit port or they can be used individually as
two 4-bit ports.
 When used as outputs, the Port C lines can be individually set or reset by sending a
special control word to the control register address.

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Figure 5.8 Mode 0 definition and Bus Interface

3.2.2. Mode 1
 Used for handshake input/output operation.
 Port B is initialized in mode 1 for either input or output, Pins PC0, PC1 and PC2 function
as handshake lines.
 Port A can also be configured as input or output in mode 1. But handshake signal pins are
not same for input and output mode as like Port B.
 If port A is initialized in mode 1 as handshake input port, then pins PC3, PC4 and PC5
function as handshake signals. (PC6 and PC7 are available for using as input lines or
output lines)
 If port A is initialized as handshake output port, then PC3, PC6 and PC7 function as
handshake signals. (PC4 and PC5 are available for using as input or output lines)

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Figure 5.9 Mode 1 definition and Bus Interface

3.2.3. Mode 2
 Only port A can be initialized in mode 2.
 In mode 2, port A can be used for “bi-directional handshake” data transfer i.e. data can be
input or output on the same eight lines.
 Pins PC3, PC4, PC5, PC6, PC7 used as handshake lines for port A.
 Port B is operating in either mode 0 or mode 1.
 If port B is in mode 0, then PC0, PC1 and PC2 used for I/O.
 If port B is in mode 1, then PC0, PC1 and PC2 used as handshake lines.

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Figure 5.10 Mode 2 definition and Bus Interface

4. 8255 programming

The 8255A can be programmed in three modes:

 Mode 0: Basic input/output.

 Mode 1: Strobed input output.
 Mode 2: Bidirectional bus.

The format as well as the choice of modes is made from the following control word:

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Figure 5.11 Control word and mode Definition format

5. Mode 0 Configurations

There are 16 configuration (16 control words) for mode 0 as shown below:

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MOV AL, XXH ; Control word

MOV DX , @control register
OUT DX, AL ; sent control word to control register

6. Mode 0 Ports definition

A B Group A Group B
#
Port A C-upper Port B C-upper

0 0 0 0 OUTPUT OUTPUT 0 OUTPUT OUTPUT

0 0 0 1 OUTPUT OUTPUT 1 OUTPUT INPUT

0 0 1 0 OUTPUT OUTPUT 2 INPUT OUTPUT

0 0 1 1 OUTPUT OUTPUT 3 INPUT INPUT

0 1 0 0 OUTPUT INPUT 4 OUTPUT OUTPUT

0 1 0 1 OUTPUT INPUT 5 OUTPUT INPUT

0 1 1 0 OUTPUT INPUT 6 INPUT OUTPUT

0 1 1 1 OUTPUT INPUT 7 INPUT INPUT

1 0 0 0 INPUT OUTPUT 8 OUTPUT OUTPUT

1 0 0 1 INPUT OUTPUT 9 OUTPUT INPUT

1 0 1 0 INPUT OUTPUT 10 INPUT OUTPUT

1 0 1 1 INPUT OUTPUT 11 INPUT INPUT

1 1 0 0 INPUT INPUT 12 OUTPUT OUTPUT

1 1 0 1 INPUT INPUT 13 OUTPUT INPUT

1 1 1 0 INPUT INPUT 14 INPUT OUTPUT

1 1 1 1 INPUT INPUT 15 INPUT INPUT

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7. Bit SET/RESET Flag

When bit 7 of the control word is equal to 0, port C bits can be set to 1 or 0 individually,. The
command word then becomes:

Figure 5.12 Bit Set-Reset control word

Example:
To set PC3 =1 the control word becomes 00000111
To reset PC3 01 the control word becomes 00000110

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8. Problems
8.1.Problem 1:
Identify the mode 0 control word to configure port A and upper C as output port and port B and
lower c as input port.
Answer:

8.2.Problem2:
Write a control word to configure port A as input port in mode 0 and port B in mode 1 as output
port.
Answer: (same procedure as problem 1)
The control word is 10010100=94H
8.3.Problem 3:
A control word is given CW=CDH. Explain the conditions of ports of 8255A.
Answer:
CW = CDH = 11001101
 D7=1; I/O Mode.
 D6=1 and D5=0; Port A is in Mode 2.
 D4=0; Port A is output port

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 D3=1; Port C (Upper) is input port.

 D2=1; Port B is in Mode 1.
 D1=0; Port B is output Port.
 D0=0; Port C (Lower) is input port.

8.4.Problem 4:
Figure bellow shows an 8255A interfaced with 8086 microprocessor. Perform the following:
a. Identify the Port Address.
b. Identify the Mode 0 control word to configure Port A and Port C (upper) as output ports
and Port B and Port C (lower) as input ports.
c. Write a program to read the Dual In-line Package (DIP) switches and display the reading
from Port B at Port A, and from Port CL at Port CU.

Answer:
a. This is a memory mapped I/O. when is high then the chip select is enabled
to Port Address

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1 0 0 0 8000H : Port A
1 0 0 1 8001H : Port B
1 0 1 0 8002H : Port C
1 0 1 1 8003H : Control Register

b. The control word is as follow:

: I/O = 1

and = 00 (port A in mode 0)

= 0 (Port A = output )

= 0 (Port C upper = output)

= 0 (Port B in mode 0)

= 1 (Port B = input)

= 1 (Port C lower = input)

The control word is 10000011= 83H

c. CODE
CONTROLREG EQU 8003H;
PORTC EQU 8002H;
PORTB EQU 8001H;
PORTA EQU 8000H;
MOV AL, 83H;
OUT CONTROLREG, AL;
IN AL, PORTB;
OUT PORTA, AL;
IN AL, PORTC;
AND AL, OFH;
MOV CL, 04;
ROL AL, CL;
OUT PORTC, AL;
HLT;

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8.5.Problem 5
An 8086-8255 based microcomputer is required to drive an LED connected to bit 2 of Port B based
on two switch inputs connected to bit 6 and 7 of port A. If both switches are either high or low,
LED will turn on; otherwise, it will remain OFF. Assume base address of 60H. Write an 8086
assembly language program to accomplish this.

Answer:
PORTA EQU 60H
PORTB EQU 61H
CNTRL EQU 63H
MOV AL, 10010000B; Configure Port A as input and Port B as output.
OUT CNTRL, AL;
MAIN : IN AL, PORTA;
AND AL, 11000000B;
JPE LEADON; (JPE= Jump if parity even, p=1)
MOV AL, 00H;
OUT PORTB, AL;
JMP MAIN;
LEDON : MOV AL, 00000100B;
OUT PORTB, AL;
JMP MAIN;
8.6.Problem6
Write a BSR control word subroutine to set bit PC7 and PC3 and reset them after 10ms. Use
Figure of problem 4. Also write the delay procedure considering the processor clock at 5MHz.
Answer:
 BSR control word
to Port Address
0 1 1 1 1 To set PC7: 00001111=0FH
0 1 1 1 0 To reset PC7: 00001110=0EH

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0 0 1 1 1 To set PC3: 00000111=07H

0 0 1 1 0 To reset PC3: 00001100=06H

 Port address for control register using figure of problem 4

to Port Address
1 0 1 1 8003H : Control Register

 The duration of 1 clock pulse is 1/ (5 MHz) = 200ns

So for 10 ms we have to count (10ms)/ (200ns) = 50000 pulses
Assuming that PORTC address is 83 H (Already declared)
BSR: MOV AL, 0FH;
OUT PORTC, AL;
MOVAL, 07H;
OUT PORTC, AL;
CALL DELAT;
MOVAL, 06H;
OUT PORTC, AL;
MOVAL, 0EH;
OUT PORTC, AL;
RET
DELAY PROC ABC
MOV CX, 50000
ABC: LOOP ABC
RET
DELAY ENDP

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