form before it can be used as an input by the
converted into tlhe analogue
microprocessor has to be
om a
ctuato.
Binary Numbers:
these possible beino 0V
on just tlhe two symbols or stntes 0 nd 1,
The binarvsvstem is based
ntnber is represented by
this system.tlbe d:.
binary digits or bits. When a
5V signals. These are termed attached to ench digit, the weight
incrensing by n fnctorofo
the weight
nosition in the nun ber indicates
right to left:
as we proceed from
20
22
bit 1 bit O
bit 3 bit 2
20+2*22"2* m1111 in the binary system,
ln a binary
For exanpie, the decinal number 15 is most significant 2bit
the bit 0 termed as least significant bit (LSB) And the higlhest bit the
number Such a
a number is termed as word, Thus 1111is 4-bit word.
(MSB), The combination of bits to represent
The tern byte is used,for a group of 8bits.
word coukt be used to represent the size of signal.
Analogue to digital conversion:
Input: Qutput:
Sample and Analoguc-to
hold digital converter digtal signal
analágue
signai
(u)
sAmlignalogoe
(b) (c)
and
Sunl
beded
"Time
(4) (e)
Figure 2.18 (a) Analogue-to-digital conversion, (b) analogue input, (c)
clock signal, (d) sampled
signal,e) sampled and held signal.
Analogue-to-digitel co11version involves coverting analogue signals into biuary
cleinessts of aualogue-to digital conversion. Tlhe words. The basic
procedure used is thut a clock supplies regular time
16 4
signal pulses to the nnalogue-todigital eonversion and evoy tine it recelves a pulae it samplew the
analogue signals.
(Figure 2.I8 (a)This nnaloguetodigitnl conversionby slhowing
the types of aig1nls iuvolved at ie
stages. The analogue sinal and (igure 2. 18 (e) the clock aignal whicli upplies the time siginals
various 2.18 ()) A
which the &ling occurw. The teault of tho Ntnpling is nrleN of narrow pulsen (Plgure
nt until he neat pulse oecurs, with the
reslt
hokl each NDMpled vlue
sample and hold nit is then used to requires n finite
2. 18 (e).The sample and hold unit is necessnyy becnuse the ADC
shown in Figure analogue signal into a digitnl one.
conversion time, toconvort tlhe
amount of time, termed the
Propornellay line
2uwnriunnn
uvul
0
010
lnput
Analoyrue input voltae es fruQtion n l l u u l o
Input/output for an ADc.
Figure 2.19
illustratedl by
and the output far an ADC ia
held input 8
relationship between
the sAmpled and to 3 bits. With 3 blts there aro 23
restricted
The
digital output which annlogue input can
be only one
figure 2.19, lr a represeut the
the graplh slown ol the ADC to The eioht
Thus, since the outptut the bitjpiut docs not chango.
levels. for whicli between two
passible output iange olinputa analogue voltage
possible levels; there is a lovels and the
lilerence in
interyol is 1V.
of these eight teruned
quantizatlon
given the
quantization
levels are lntervals. Thua
tha ADC proportionnl to
the
DOssibie outpit not always
quaatization
iw
js termed the digitaloutput
relationship, the
errog
odiacent levels the
quaatigatlon
tep-like naturo of being taeruod tlhe
Becauso of tlhe
& orror, this
there will Ies
thus
nnalogLie
input, and
EXAMPLEAELASHARE
Kalkswlspu
leaisur
output tor a DAC,
viguro 2.20 Input/
17.|Pag
in the ladder. Thu# when th# onalogu# voltace is noclied to the ADC, al thse Gnnprat
n h
whieh the analog6 voltnges grenter than the referance yotngn of n 6anjhtater ii to hV
eibing 6utsts are to4 in pArnle!
utpit And thone lor which it s leeA will he low. The
gnte syetem which ranslotea tlieu into n dipitn) word.
PIOITALT9-ANALOQVE CONVERSION
tn B
onverter (DAC) L4 Mbinery wnd, thw
T# input to a diptal t0 uabgis s ,
weiglted wwsof tws m-1obás teysunws y tiie wna,
6nlog signal that represos the uivwn y ws inpt AN
0010 must ive nn auujouse vutyut wisls lu tica thut
kp, n input of or unwigbd bátary Wor.
2.20 illustrats ths lor us iuuput to n DAC witth reolutkosof 1V
Fgue
adelitional bit inoreusos the output voltnyw ly 19, Tis 14
microvsochr gives un
vutput d B-bit wond.
Considor the situation wlwre a GY to
cnstrol valve, The ontrol
vuve reiires
digitnl-0-4salouw cover er to the vave lor a
ed tirog}h an 8-bit will be the outyut to the
open state is indicated Iy 11111111whut
Ls fally opon,1f tho fully
change of Ilit? is
dividod irnto 2 intervals. Aclarge of 1 bát
ull-scale output voltage of 6.9Vwill be
Tle
voltnge of 6.0/ 25 0.023 V,
thua a change ín the aitput
010
101 111
01 O11
Digsol input
Input/output lor a PAC.
Tlgure 2.21
Weighted-Resistor DACI weighted
Section 3.2.3) to forn the
sineky fornof DAC UseNA Bnming nnplifer uee conected to t
A reerence votege is
inpt word (PgIre 4.5) Te
-ero bits in the
efut tte values of ue input resistaree
swituchcs wiicli respond to binary 1. The
eslstorsy smeans of
cleetrorúc sceeasise tit
tie value of the resistor lor
erend os which bit in the word u switch isrespoding to, Suct
sum of Uhe voltage is a wegted um of thedigts in the wogd.
tor the LSB beig halved. 1lence the 18 {Paze
