Priority Encoders

VHDL
Following is the VHDL code for a 3-bit 1-of-9 Priority Encoder.
library ieee; use ieee.std_logic_1164.all; entity priority is port ( sel : in std_logic_vector (7 downto 0); code :out std_logic_vector (2 downto 0)); end priority; architecture archi of priority is begin code <= "000" when sel(0) = '1' else "001" when sel(1) = '1' else "010" when sel(2) = '1' else "011" when sel(3) = '1' else "100" when sel(4) = '1' else "101" when sel(5) = '1' else "110" when sel(6) = '1' else "111" when sel(7) = '1' else "---"; end archi;

VHDL Code
Following is the VHDL code for a 4-to-1 1-bit MUX using an If statement.
library ieee; use ieee.std_logic_1164.all; entity mux is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end mux; architecture archi of mux is begin process (a, b, c, d, s) begin if (s = "00") then o <= a; elsif (s = "01") then o <= b; elsif (s = "10") then o <= c; else o <= d;

end if; end process; end archi;

VHDL Code
Following is the VHDL code for a 4-to-1 1-bit MUX using a Case statement.
library ieee; use ieee.std_logic_1164.all; entity mux is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end mux; architecture archi of mux is begin process (a, b, c, d, s) begin case s is when "00" => o <= a; when "01" => o <= b; when "10" => o <= c; when others => o <= d; end case; end process; end archi;

VHDL Code
Following is the VHDL code for a 4-to-1 1-bit MUX using tristate buffers.
library ieee; use ieee.std_logic_1164.all; entity mux is port (a, b, c, d : in std_logic; s : in std_logic_vector (3 downto 0); o : out std_logic); end mux; architecture archi of mux is begin o o o o <= <= <= <= a b c d when when when when (s(0)='0') (s(1)='0') (s(2)='0') (s(3)='0') else else else else 'Z'; 'Z'; 'Z'; 'Z';

end archi;

VHDL Code
Following is the VHDL code for a 3-to-1 1-bit MUX with a 1-bit latch.
library ieee; use ieee.std_logic_1164.all; entity mux is port (a, b, c, d : in std_logic; s : in std_logic_vector (1 downto 0); o : out std_logic); end mux; architecture archi of mux is begin process (a, b, c, d, s) begin if (s = "00") then o <= a; elsif (s = "01") then o <= b; elsif (s = "10") then o <= c; end if; end process; end archi;

Logical Shifters
VHDL
Following is the VHDL code for a logical shifter.
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity lshift is port(DI : in unsigned(7 downto 0); SEL : in unsigned(1 downto 0); SO : out unsigned(7 downto 0)); end lshift; architecture archi of lshift is begin with SEL select SO <= DI when "00", DI sll 1 when "01", DI sll 2 when "10", DI sll 3 when others; end archi;

VHDL Following is the VHDL code for an unsigned 8-bit Adder.

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(A,B : in std_logic_vector(7 downto 0); SUM : out std_logic_vector(7 downto 0)); end adder; architecture archi of adder is begin SUM <= A + B; end archi;

VHDL Following is the VHDL code for an unsigned 8-bit adder with carry in.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port(A,B : in std_logic_vector(7 downto 0); CI : in std_logic; SUM : out std_logic_vector(7 downto 0)); end adder; architecture archi of adder is begin SUM <= A + B + CI; end archi;

VHDL Following is the VHDL code for a simple signed 8-bit adder.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity adder is port(A,B : in std_logic_vector(7 downto 0); SUM : out std_logic_vector(7 downto 0)); end adder; architecture archi of adder is begin SUM <= A + B; end archi;

VHDL
Following is the VHDL code for an unsigned 8-bit subtractor.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity subtr is port(A,B : in std_logic_vector(7 downto 0); RES : out std_logic_vector(7 downto 0)); end subtr; architecture archi of subtr is begin RES <= A - B; end archi;

VHDL
Following is the VHDL code for an unsigned 8-bit adder/subtractor.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addsub is port(A,B : in std_logic_vector(7 downto 0); OPER: in std_logic; RES : out std_logic_vector(7 downto 0)); end addsub; architecture archi of addsub is begin RES <= A + B when OPER='0' else A - B; end archi; endmodule

VHDL
Following is the VHDL code for an unsigned 8-bit greater or equal comparator.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity compar is port(A,B : in std_logic_vector(7 downto 0); CMP : out std_logic); end compar; architecture archi of compar is begin CMP <= '1' when A >= B else '0';

end archi;

VHDL
Following is the VHDL code for an unsigned 8x4-bit multiplier.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mult is port(A : in std_logic_vector(7 downto 0); B : in std_logic_vector(3 downto 0); RES : out std_logic_vector(11 downto 0)); end mult; architecture archi of mult is begin RES <= A * B; end archi; --

counter

LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_arith.all ; ENTITY counter IS PORT(clk: input: output: ld: inc: clr: ) ; END counter ; IN IN OUT IN IN IN std_logic ; std_logic_vector(11 DOWNTO 0) ; std_logic_vector(11 DOWNTO 0) ; std_logic ; std_logic ; std_logic

ARCHITECTURE behavioral OF counter IS BEGIN generic_counter: PROCESS(clk, input, ld, inc, clr) VARIABLE tmpvar: unsigned(11 DOWNTO 0) ; BEGIN IF (rising_edge(clk)) THEN IF (clr = '1') THEN tmpvar := (OTHERS => '0') ; ELSIF (ld = '1') THEN tmpvar := unsigned(input) ; ELSIF (inc = '1') THEN tmpvar := tmpvar + "000000000001" ; END IF ; output <= std_logic_vector(tmpvar) ; END IF ; END PROCESS ; END behavioral ;

Design a 2-bit count-down counter

LIBRARY USE USE USE USE ieee ; ieee.std_logic_1164.all ; ieee.std_logic_arith.all ; ieee.std_logic_signed.all ; ieee.std_logic_unsigned.all ; IN OUT IN IN std_logic ; std_logic_vector(1 DOWNTO 0) ; std_logic ; std_logic

ENTITY down_counter IS PORT(SIGNAL x: SIGNAL count : SIGNAL reset: SIGNAL clk: ) ; END down_counter ;

ARCHITECTURE arch1 OF down_counter IS BEGIN PROCESS(clk, x, reset) VARIABLE tmp_cnt: unsigned(1 DOWNTO 0) ; BEGIN IF (reset = '1') THEN tmp_cnt := "00" ; ELSIF rising_edge(clk) THEN IF (x = '1') THEN tmp_cnt := tmp_cnt - "01" ; END IF ; END IF ; count <= std_logic_vector(tmp_cnt) ; END PROCESS ; END arch1 ;

-- 8 to 3 priority encoder
LIBRARY USE ieee ; ieee.std_logic_1164.all ; IN OUT std_logic_vector(7 DOWNTO 0) ; std_logic_vector(2 DOWNTO 0)

ENTITY enc8to3 IS PORT(SIGNAL input: SIGNAL output: ) ; END enc8to3 ;

ARCHITECTURE arch1 OF enc8to3 IS BEGIN output <= "111" WHEN (input(7) "110" WHEN (input(6) "101" WHEN (input(5) "100" WHEN (input(4) "011" WHEN (input(3) "010" WHEN (input(2) "001" WHEN (input(1) "000" ;

= = = = = = =

'1') '1') '1') '1') '1') '1') '1')

ELSE ELSE ELSE ELSE ELSE ELSE ELSE

END arch1 ;

FULL ADDER
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fa IS PORT( a, b cin cout sum ) ; END fa ; : : : : in std_logic ; in std_logic ; out std_logic ; out std_logic

ARCHITECTURE arch1 OF fa IS BEGIN sum <= (a XOR b) XOR cin ; cout <= (a AND b) OR ((a OR b) AND cin) ; END arch1 ;

--

REGISTER

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY reg IS PORT(clk: input: output: ld: ) ; END reg ; IN IN OUT IN std_logic ; std_logic_vector(15 DOWNTO 0) ; std_logic_vector(15 DOWNTO 0) ; std_logic

ARCHITECTURE behavioral OF reg IS BEGIN generic_register: PROCESS(clk, input, ld) BEGIN IF (rising_edge(clk)) THEN IF (ld = '1') THEN output <= input ; END IF ; END IF ; END PROCESS ; END behavioral ;

D F/F
library ieee ; use ieee.std_logic_1164.all; use work.all; entity dff is port( data_in: clock: data_out: ); end dff; in std_logic; in std_logic; out std_logic

architecture behv of dff is begin process(data_in, clock) begin -- clock rising edge if (clock='1' and clock'event) then data_out <= data_in; end if; end process; end behv;

JK F/F
library ieee; use ieee.std_logic_1164.all; entity JK_FF is port ( clock: J, K: reset: Q, Qbar: ); end JK_FF; in std_logic; in std_logic; in std_logic; out std_logic

architecture behv of JK_FF is -- define the useful signals here signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin -- combine inputs into vector input <= J & K; p: process(clock, reset) is begin if (reset='1') then state <= '0'; elsif (rising_edge(clock)) then -- compare to the truth table case (input) is when "11" => state <= not state; when "10" => state <= '1'; when "01" => state <= '0'; when others => null; end case; end if; end process; -- concurrent statements Q <= state; Qbar <= not state; end behv;

--

3-bit Shift-Register/Shifter

library ieee ; use ieee.std_logic_1164.all; entity shift_reg is port( I: clock: shift: Q: ); end shift_reg; in std_logic; in std_logic; in std_logic; out std_logic

architecture behv of shift_reg is -- initialize the declared signal signal S: std_logic_vector(2 downto 0):="111"; begin process(I, clock, shift, S) begin -- everything happens upon the clock changing if clock'event and clock='1' then if shift = '1' then S <= I & S(2 downto 1); end if; end if; end process; -- concurrent assignment Q <= S(0); end behv;

COUNTER
library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is generic(n: natural :=2); port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end counter; architecture behv of counter is signal Pre_Q: std_logic_vector(n-1 downto 0); begin -- behavior describe the counter process(clock, count, clear) begin if clear = '1' then Pre_Q <= Pre_Q - Pre_Q; elsif (clock='1' and clock'event) then if count = '1' then Pre_Q <= Pre_Q + 1; end if; end if; end process; -- concurrent assignment statement Q <= Pre_Q; end behv;

VHDL Code for Shift registers

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then for i in 0 to 6 loop tmp(i+1) <= tmp(i); end loop; tmp(0) <= SI; end if; end process; SO <= tmp(7); end archi;

VHDL Code Following is the VHDL code for an 8-bit shift-left register with a negative-edge clock, clock enable, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, CE : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='0') then if (CE='1') then for i in 0 to 6 loop tmp(i+1) <= tmp(i); end loop; tmp(0) <= SI; end if; end if; end process; SO <= tmp(7); end archi;

VHDL Code Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, asynchronous clear, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, CLR : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= (others => '0'); elsif (C'event and C='1') then tmp <= tmp(6 downto 0) & SI; end if; end process; SO <= tmp(7); end archi;

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, synchronous set, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, S : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, S) begin if (C'event and C='1') then if (S='1') then tmp <= (others => '1'); else tmp <= tmp(6 downto 0) & SI; end if; end if; end process; SO <= tmp(7); end archi;

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI : in std_logic; PO : out std_logic_vector(7 downto 0)); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then tmp <= tmp(6 downto 0)& SI; end if; end process; PO <= tmp; end archi;

VHDL Code
Following is VHDL code for an 8-bit shift-left register with a positive-edge clock, asynchronous parallel load, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, ALOAD : in std_logic; D : in std_logic_vector(7 downto 0); SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C, ALOAD, D) begin if (ALOAD='1') then tmp <= D; elsif (C'event and C='1') then tmp <= tmp(6 downto 0) & SI; end if; end process; SO <= tmp(7); end archi;

VHDL Code
Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock, synchronous parallel load, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, SLOAD : in std_logic; D : in std_logic_vector(7 downto 0); SO : out std_logic); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then if (SLOAD='1') then tmp <= D; else tmp <= tmp(6 downto 0) & SI; end if; end if; end process; SO <= tmp(7); end archi;

VHDL Code
Following is the VHDL code for an 8-bit shift-left/shift-right register with a positive-edge clock, serial in, and serial out.
library ieee; use ieee.std_logic_1164.all; entity shift is port(C, SI, LEFT_RIGHT : in std_logic; PO : out std_logic_vector(7 downto 0)); end shift; architecture archi of shift is signal tmp: std_logic_vector(7 downto 0); begin process (C) begin if (C'event and C='1') then if (LEFT_RIGHT='0') then tmp <= tmp(6 downto 0) & SI; else tmp <= SI & tmp(7 downto 1); end if; end if; end process; PO <= tmp; end archi;

VHDL Code
Following is the VHDL code for a 4-bit unsigned down counter with synchronous set. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, S : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C) begin if (C'event and C='1') then if (S='1') then tmp <= "1111"; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;

VHDL Code
Following is the VHDL code for a 4-bit unsigned up counter with asynchronous load from primary input. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, ALOAD : in std_logic;
D : in std_logic_vector(3 downto 0); Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, ALOAD, D) begin if (ALOAD='1') then tmp <= D; elsif (C'event and C='1') then tmp <= tmp + 1; end if; end process; Q <= tmp; end archi;

VHDL CODE
Following is the VHDL code for a 4-bit unsigned up counter with asynchronous clear and clock enable. library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; entity counter is port(C, CLR, CE : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (CE='1') then tmp <= tmp + 1; end if; end if; end process; Q <= tmp; end archi;

VHDL Code
Following is the VHDL code for a 4-bit unsigned up/down counter with asynchronous clear.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(C, CLR, UP_DOWN : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (C, CLR) begin if (CLR='1') then tmp <= "0000"; elsif (C'event and C='1') then if (UP_DOWN='1') then tmp <= tmp + 1; else tmp <= tmp - 1; end if; end if; end process; Q <= tmp; end archi;