Problem: Assume that a large room has three doors and that a switch near each door

controls a light in the room. It has to be possible to turn the light on or off by
changing the state of any one of the switches. Design a logic network that realizes
this scenario.
• Light ON if exactly any 1 switch closed & OFF is a second switch also closed.
• But if a 3rd switch also closed then light is ON.
• Let x1, x2, x3 represents the input variable that denote the state of each switch.
And f(x1, x2, x3) represents the state of the light.

• Then SOP form is

• Then POS form is

Stephen Brown, Zvonko Vranesic, “Fundamentals of

Digital logic with Verilog Design”, Tata McGraw Hill 1
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Stephen Brown, Zvonko Vranesic, “Fundamentals of
Digital logic with Verilog Design”, Tata McGraw Hill 2
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Procedure to get Standard SOP Form (Canonical SOP Form)
• Domain of a Boolean Expression : The set of variables contained in the expression
• Ex) A’B+AB’C : the domain is {A, B, C}
• Procedure to get Standard SOP Form (Canonical SOP Form)
❑For all the missing variables, apply (x+x’)=1 to the AND terms of the expression
❑List all the min-terms in forms of the complete set of variables in ascending order
• Qn. : Convert the following expression into standard SOP form: AB’C+A’B’+ABC’D
Sol) domain={A,B,C,D}, AB’C(D’+D)+A’B’(C’+C)(D’+D)+ABC’D
=AB’CD’+AB’CD+A’B’C’D’+A’B’C’D+A’B’CD’+A’B’CD+ABC’D
Input configurations : 1010+1011+0000+0001+0010+0011+1101
 minterms: m10+m11+m0+m1+m2+m3+m13
 AB’C+A’B’+ABC’D = (m0,m1,m2,m3,m10,m11,m13) = m(0,1,2,3,10,11,13)
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Procedure to obtain Standard POS Form (Canonical POS Form)
❑For all the missing variables, apply (x’x) = 0 to the OR terms of the expression
❑List all the max-terms in forms of the complete set of variables in ascending order

• Ex : Convert the following expression into standard POS form:

(A+B’+C)(B’+C+D’)(A+B’+C’+D)
Sol) domain ={A,B,C,D},
⁼ (A+B’+C)(B’+C+D’)(A+B’+C’+D)
⁼ (A+B’+C+D’D)(A’A+B’+C+D’)(A+B’+C’+D)
⁼ (A+B’+C+D’)(A+B’+C+D)(A’+B’+C+D’)(A+B’+C+D’)(A+B’+C’+D)
⁼ > (0101)(0100) (1101)(0101)(0110) => M5M4M13M5M6
⁼ M(4,5,6,13)

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Problem : If f(x1,x2,x3)=Σm(2,3,4,6,7)=ΠM(0,1,5). i) Express in terms of
canonical SOP and POS form. ii)Simplify to obtain the cost-efficient designs.
Sol: Canonical SOP form is,

This expression can be simplified using the identities as,

Canonical POS form is,

Stephen Brown, Zvonko Vranesic, “Fundamentals of

Digital logic with Verilog Design”, Tata McGraw Hill 5
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Contd..
This expression can be simplified using the identities as,

Another way of deriving this product-of-sums expression is to use the sum-of-

products form

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SOP using NAND gates
• Sum-of-products or product-of-sums form, will have networks that have either an
AND-OR or an OR-AND structure, respectively.
• These networks can be implemented using only NAND gates or only NOR gates.

• AND-OR (SOP) network implemented using only NAND gates.

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Using NOR gates to implement a product-of-sums

• OR-AND (POS) network can be implemented as a NOR-NOR network

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 SOP form of XOR Gate
• The XOR operation is usually denoted with the ⊕ symbol.
• Truth table & symbol are,

It can be realized in the SOP form as,

SOP realization

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 Addition of binary numbers - Half Adder
• Consider the addition of two one-digit binary numbers a and b.
• The sum S = s1s0 will be a two-digit binary number, because when a =
b = 1 then S = 10.

Sum

Carry

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Introduction to Karnaugh Map (K-Map)
• For Boolean simplification, we need a method which allows easy
discovery of groups of minterms for which f = 1 such that they can be
combined easily.
• Karnaugh map (K Map) is such a method. It is also an alternative to
the truth-table form for representing a function.
• K map consists of cells that correspond to the rows of the truth table.
• Minterms in any two cells that are adjacent, either in the same row or
the same column, can be combined.

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Karnaugh Map (K- Map) Steps
1.Sketch a Karnaugh map grid for the given problem in power of 2N Squares
• N is number of variables
2.Fill in the 1’s and 0’s from the truth table of SOP or POS Boolean function
3.For SOP, circle groups of 1’s.
 Circle the largest groups of 2, 4, 8, etc. first.
 Minimize the number of circles but make sure that every 1 is in these circles.
4.Write an equation using these circles.

Y
x

Stephen Brown, Zvonko Vranesic, “Fundamentals of

XY’+XY=X(Y’+Y)=X
Digital logic with Verilog Design”, Tata McGraw Hill 12
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Contd.

• In 2nd row, both of the cells are identified by x2 = 1, but x1 = 0 for the left cell and
x1 = 1 for the right cell.
• Similarly, f = 1 for both cells in the first column. These cells are identified by x1 =
0 leading to the product term 𝑥ഥ1.
• Since this takes care of all instances where f = 1, it follows that the minimum-cost
realization of the function is :
𝑓 = 𝒙𝟐 + 𝒙𝟏
• To find a minimum-cost implementation of a given function, it is necessary to find
the smallest number of product terms that produce a value of 1 for all cases where
f = 1.
• Moreover, the cost of these product terms should be as low as possible.
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 3 variable map
YZ
Gray code X

The map should be visualised as a rectangle folded

into a cylinder where the left and the right edges
are made to touch

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Contd. E.g. F(X,Y,Z)=m(0,2,4,6) = XZ+XZ  =Z(X+X)=Z

Alternate way of writing of K-map

with 4 rows and 2 columns

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E.g.. F(X,Y,Z)=m(2,3,4,5) =XY+XY
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4 variable map
• Truth Table

Stephen Brown, Zvonko Vranesic, “Fundamentals of

Digital logic with Verilog Design”, Tata McGraw Hill Alternate Way of writing K Map
16
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4 variable map

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Strategy for Minimization -
Terminology
Literal
• Each appearance of a variable, either uncomplemented
or complemented, is called a literal.
Implicant
• A product term that indicates the input valuation(s) for which a given function
is equal to 1 is called an implicant of the function.
• In the truth table given, there are 11 implicants.
• Of which 5 are minterms given below,

• Then there are the implicants that correspond to all possible pairs of minterms
that can be combined (5 nos).
• Finally, there is one implicant that covers a group of four minterms
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logic with Verilog Design”, Tata McGraw Hill Publishing
Contd..
Prime Implicant
• An implicant is called a prime implicant if it cannot be combined into another
implicant that has fewer literals
Cover
• A collection of implicants that account for all valuations for which a given
function is equal to 1 is called a cover of that function
• Eg : set of all minterms, set of prime implicants etc.
• A cover also defines a particular implementation of the function. For e.g.
• From the K-map a cover consisting of minterms leads to the expression

• Another valid cover is given by the expression

• The cover comprising the prime implicants is

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logic with Verilog Design”, Tata McGraw Hill Publishing
 Essential Prime Implicant
• The lowest-cost implementation is achieved when the cover of a given
function consists of prime implicants.
• The question then is how to determine the minimum-cost subset of
prime implicants that will cover the function.
• If a prime implicant includes a minterm for which f = 1 that is not
included in any other prime implicant, then it must be included in the
cover and is called an essential prime implicant

• Both of these prime implicants are essential

• Therefore, the minimum-cost realization is :
𝒇 = 𝒙𝟏 + 𝒙𝟐𝒙𝟑

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logic with Verilog Design”, Tata McGraw Hill Publishing
Steps in finding minimum cost circuit
• The process of finding a minimum-cost circuit involves the following
steps:
1. Generate all prime implicants for the given function f .
2. Find the set of essential prime implicants.
3. If the set of essential prime implicants covers all valuations for
which f = 1, then this set is the desired cover of f .
4. Otherwise, determine the nonessential prime implicants that
should be added to form a complete minimum-cost cover.

Stephen Brown, Zvonko Vranesic, “Fundamentals of Digital

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logic with Verilog Design”, Tata McGraw Hill Publishing
 Example 1

1 1

1 1 1

1 1 1 1

• The essential prime implicants are indicated in pink colour

• Now, the left minterm, m7 can be covered by either 𝑥ഥ1𝑥3 or 𝑥ഥ1𝑥2 𝑥4 , but the former is
less costly
• So, The minimum-cost realization is :
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logic with Verilog Design”, Tata McGraw Hill Publishing