Multiplexers

• In computer systems it is often necessary to choose data from exactly

one of a number of possible sources.
• Multiplexers do that job
• A multiplexer circuit has a number of data inputs, one or more select
inputs, and one output.
• It passes the signal value on one of the data inputs to the output.
• The data input is selected by the values of the select inputs.

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2-to-1 multiplexer
• The sum-of-products implementation of the 2-to-1 multiplexer is
shown below. 𝑓 = 𝑠𝑤
ҧ 0 + 𝑠𝑤1

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4-to-1 multiplexer.
• It realizes the multiplexer function

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Larger multiplexers using
smaller multiplexers

MorrisaMano, Using
“Digital Circuits and Logic Design”, PHI 4-to-1 multiplexers to build a 16-to-1
Using 2-to-1 multiplexers to build 4-to-1
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multiplexer
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Synthesis of Logic Functions Using
Multiplexers
• Multiplexers can also be used to synthesize logic functions.
• The truth table defines the function (XOR operation), f = w1 ⊕ w2.
• Circuit shows XOR using 4 to 1 Mux

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XOR using 2-to-1 MUX
• It allows f to be implemented by a single 2-to-1
multiplexer.
• This procedure can be applied to synthesize a circuit
that implements any logic function.

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3 input Majority function implementation
using 4-to-1 MUX

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3-input XOR implemented with 2-to-1MUX
• The function f = w1 ⊕ w2 ⊕ w3 can be implemented using 2-to-1 multiplexers.

w2 ⊕ w3

• In the corresponding circuit, the left multiplexer in the circuit produces w2 ⊕ w3

and the right multiplexer uses the value of w1 to select either w2 ⊕ w3 or its
complement. Morris Mano, “Digital Circuits and Logic Design”, PHI
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3-input XOR implemented with a 4-to-1 MUX

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Logic functions as combination of multiplexers
and other logic gates.
• It is also possible to connect more complex circuits as inputs to a
multiplexer.

• This allows functions to be synthesized using a combination of

multiplexers and other logic gates.

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3-input majority function implemented using
a 2-to-1 multiplexer and other gates.

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Contd.
• This implementation can be derived using
algebraic manipulation as well.
• The function is expressed in SOP as,

• It can be manipulated as,

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 Truth table

Decoders
• Consider the truth table:
• It has two inputs, w1 and w0, and four outputs, y0,
y1, y2 and y3
• only one of the outputs is asserted at a time.
• Setting the inputs w1w0 to 00, 01, 10, or 11
causes the output y0, y1, y2, or y3 to be set to A 2-to-4 decoder.
1, respectively.
• This type of circuit is called a binary
decoder.
• Also called one-hot encoding
• Means exactly one of the bits is set to 1 at a time.

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Contd.
• The circuit for the decoder is as below,
• Each output is driven by an AND gate that decodes the corresponding
valuation of w1w0.

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Decoder with Enable control
• It is useful to include an enable input,
En, in a decoder circuit.
• When enabled by setting En = 1 the outputs
are asserted as per the input valuations
• But, if it is disabled by setting En = 0, then Truth table
none of the outputs are asserted.
• Only five rows are shown in the truth
table, because if En = 0 then all outputs
are equal to 0 regardless of the values of
w1 and w0.
Graphical symbol
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Decoder with Enable control – Circuit diagram
• Connecting the Enable input directly with all the AND gates, we can
get the circuit
• Larger decoders like 3-to-8 or 4-to-16 etc.. can be built using similar
sum-of-products structure
n-to-2n binary decoder

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A 3-to-8 decoder using two 2-to-4 decoders
• Larger decoders can also be constructed from smaller decoders.
• Figure shows how a 3-to-8 decoder is built with two 2-to-4 decoders.
• The w2 input drives the enable inputs of the two decoders.

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A 4-to-16 decoder built
using a decoder tree
• Figure shows how five 2-to-4
decoders can be used to
construct a 4-to-16 decoder.
• Because of its treelike structure,
this type of circuit is often
referred to as a decoder tree.

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Decoder as Multiplexer
• Decoders are useful for many practical purposes.
• For example, decoder can be used to build a multiplexer.
• The enable input of the decoder is not needed in this case, and it is set to 1.
• The four outputs of the decoder represent the four valuations of the select
inputs.

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A 4-to-1 multiplexer built using a decoder
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Demultiplexers
• The purpose of the multiplexer circuit is to multiplex the n
data inputs onto the single data output under control of the
select inputs.
• A circuit that performs the opposite function, namely, placing
the value of a single data input onto multiple data outputs, is
called a demultiplexer.
• The demultiplexer can be implemented using a decoder
circuit.
• For example, the 2-to-4 decoder can be used as a 1-to-4
demultiplexer.
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 1-to-4 Demultiplexer using Decoder
• For example, the 2-to-4 decoder can be used as a 1-to-4 demultiplexer.
• In this case the En input serves as the data input for the demultiplexer, and the y0
to y3 outputs are the data outputs.
• The valuation of w1w0 determines which of the outputs is set to the value of En.
• In general, an n-to-2n decoder circuit can be used as a 1-to-2n demultiplexer.

I (Data In)

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Problem: Implement the function f (w1, w2, w3) = Σm(0,
1, 3, 4, 6, 7) by using a 3-to-8 binary decoder
• Solution : The decoder generates a separate output for each minterm of
the required function.
• These outputs are then combined in the OR gate, giving the circuit in
Figure

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Encoders - Binary Encoders
• An encoder performs the opposite function of a decoder. It encodes given
information into a more compact form.
• A binary encoder encodes information from 2n inputs into an n-bit code.
• Exactly one of the input signals should have a value of 1, and the outputs present
the binary number that identifies which input is equal to 1.
• Encoders are used to reduce the number of bits needed to represent given
information.

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A 2 -to-n binary encoder
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 4-to-2 binary encoder.
• The truth table for a 4-to-2 encoder is shown in
Figure.
• The output y0 is 1 when either input w1 or w3 is 1,
and output y1 is 1 when input w2 or w3 is 1.
• Hence these outputs can be generated by the circuit
in Figure.
• Note that we assume that the inputs are one-hot
encoded.
• All input patterns that have multiple inputs set to 1
are not shown in the truth table, and they are
treated as don’t-care conditions.
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Problem: Derive a circuit that implements an 8-to-3 binary
encoder.
• The truth table for the encoder is shown in Figure.

• From the truth table it is seen that the desired circuit is defined by the
equations,

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 Input Code Output
Code Converters code converter code

• The purpose of the decoder and encoder circuits is to convert

from one type of input encoding to a different output encoding.
• For example, a 3-to-8 binary decoder converts from a binary
number on the input to a one-hot encoding at the output. An 8-
to-3 binary encoder performs the opposite conversion.
• There are many other possible types of code converters. One
common example is a BCD-to-7-segment decoder.
• A similar decoder is often used to display hexadecimal
information on seven-segment displays.
• A hex-to-7-segment decoder can be implemented as shown in
figure.

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BCD-to-Excess-3 Code converter
• BCD is a code for the decimal
digits 0-9
• Excess-3 code is easily formed by
adding a binary 3 to the binary or
BCD for the digit.
• It can be assumed that only valid
BCD inputs will appear so the six
combinations not used can be
treated as don’t cares.

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Expressions for W X Y Z
• W(A,B,C,D) = Σm(5,6,7,8,9)
ABCD WXYZ
+d(10,11,12,13,14,15)
• X(A,B,C,D) = Σm(1,2,3,4,9)
+d(10,11,12,13,14,15)
• Y(A,B,C,D) = Σm(0,3,4,7,8)
+d(10,11,12,13,14,15)
• Z(A,B,C,D) = Σm(0,2,4,6,8)
+d(10,11,12,13,14,15)
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▪ Truth table: K-maps:
BCD Excess-3
C C
A B C D W X Y Z CD CD
AB 00 01 11 10 AB 00 01 11 10
0 0 0 0 0 0 0 1 1 00 00 1 1 1
1 0 0 0 1 0 1 0 0 01 01
1 1 1 1
2 0 0 1 0 0 1 0 1 11 B 11 B
X X X X X X X X
3 0 0 1 1 0 1 1 0 A 10 A 10
1 1 X X 1 X X
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0 D D
W X
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
C C
8 1 0 0 0 1 0 1 1 CD CD
AB 00 01 11 10 AB 00 01 11 10
9 1 0 0 1 1 1 0 0 00 1 1 00 1 1
10 1 0 1 0 X X X X 01 1 1 01 1 1
11 1 0 1 1 X X X X 11 B 11 B
X X X X X X X X
12 1 1 0 0 X X X X A 10 A 10
1 X X 1 X X
13 1 1 0 1 X X X X
14 1 1 1 0 X X X X D D
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Optimization – BCD-to-Excess-3
• Lay out K-maps for each output, W X Y Z

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Minimize for W
• W minimization

• Find W = A + BC + BD

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Minimize for X
• X minimization

• Find X = BC’D’+B’C+B’D

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Minimize for Y
• Y minimization

• Find Y = CD + C’D’

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Minimize for Z
• Z minimization

• Find Z = D’

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BCD-to-Excess-3 Code Converter
CD C CD C
AB 00 01 11 10 AB 00 01 11 10
00 00 1 1 1 W = A + BC + BD
01 1 1 1 01 1
B B
11 X X X X 11 X X X X
A A
10 1 1 X X 10 1 X X X = B'C + B'D + BC'D'
W D X D

Y = CD + C'D'
CD C CD C
AB 00 01 11 10 AB 00 01 11 10
00 1 1 00 1 1
Z = D'
01 1 1 01 1 1
B B
11 X X X X 11 X X X X
A A
10 1 X X 10 1 X X

Y D Z D

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A hex-to-7-segment display code converter
• Digits 0 to 9 are displayed the same as in
the case of the BCD-to-7-segment decoder.
• Digits 10 to 15 are displayed as A, b, C, d,
E, and F.
• This circuit can be implemented in the way
we have already studied.
• Although the word decoder is traditionally
used for such circuits, a more appropriate
term is code converter.
• The term decoder is more appropriate for
circuits that produce one-hot encoded
outputs

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