Counter with Unused States

• Inputs KB and KC have only

1’s and X’s in their columns,
so these inputs are always
equal to 1.
• The other flip‐flop input
equations can be simplified
by using minterms 3 and 7
as don’t‐care conditions.
• The simplified equations
are,

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 1
of Digital logic with Verilog Design”
Contd.
• Logic circuit diagram is shown in figure.
• If the unused states are treated as don’t‐care
conditions, then once the circuit is designed, it
must be investigated to determine the effect of
the unused states.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 2
of Digital logic with Verilog Design”
Lock-out condition in counter with unused
states
• Once the circuit is designed and constructed, outside interference
during its operation may cause the circuit to enter one of the unused
states.
• In that case, it is necessary to ensure that the circuit eventually goes
into one of the valid states so that it can resume normal operation.
• Otherwise, if the sequential circuit circulates among unused states,
there will be no way to bring it back to its intended sequence of state
transitions.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 3
of Digital logic with Verilog Design”
4

Programmable Logic Devices

Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to
achieve specific logic functions. PLDs provide specific functions, including device-to-device interfacing, data
communication, signal processing, data display, timing and control operations, and almost every other function a
system must perform.

Classification in PLD devices.

▪PROM ( programmable read only memory)
▪PLA (programmable logic array)
▪PAL (programmable array logic)
▪CPLD (complex programmable logic device)
▪FPGA (field programmable logic array)
Morris Mano, “Digital Circuits and Logic Design”, PHI
Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
 Programmable Logic Devices
➢ A PLD is a general-purpose chip for implementing logic circuits

➢ It can be viewed as a “black box” that contains logic gate arrays like
AND and OR and programmable switches

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 5
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 Programmable Logic Devices

The programmable switches allow the logic gates inside the PLD to be connected together to implement whatever logic circuit
is needed.
Morris Mano, “Digital Circuits and Logic Design”, PHI
Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 6
of Digital logic with Verilog Design”
PROM
• The PROM has a fixed AND array constructed as a
decoder and a programmable OR array.
• The programmable OR gates implement the Boolean
functions in sum‐of‐minterms form.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 7
of Digital logic with Verilog Design”
Programmable Logic Array (PLA)

✓ Using PLA, logic functions can be realized in sum-of-products

form

✓ a PLA comprises a collection of AND gates that feeds a set of

OR gates.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 8
of Digital logic with Verilog Design”
 Programmable Logic Array (PLA)
Gate-level diagram of a PLA.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 9
of Digital logic with Verilog Design”
 Programmable Logic Array (PLA)
Gate-level diagram of a PLA.
✓ Each AND gate in the AND plane has
six inputs, corresponding to the true
and complemented versions of the
three input signals.

✓ Each connection to an AND gate is

programmable

✓ AND gate plane produce:

Hence P1 = x1x2. Similarly, P2 = x1x3,
P3 = x1x2x3, and P4 = x1x3.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 10
of Digital logic with Verilog Design”
 Programmable Logic Array (PLA)
Gate-level diagram of a PLA.
Conclusion:
By programming the AND and OR planes
differently, each of the outputs f1 and f2
could implement various functions of x1,
x2, and x3.

Constraint :
Size of the AND Plane

Commercially:
PLAs come in larger sizes

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 11
of Digital logic with Verilog Design”
 Programmable Logic Array (PLA)
Customary schematic for the PLA
At any crossing of a vertical and horizontal line, a
programmable connection, indicated by an X.

Difficulties in PLA:

In a PLA both the AND and OR planes are

programmable. The programmable switches presented
two difficulties for manufacturers of these devices:
✓ They were hard to fabricate correctly
✓ Reduced the speed-performance of circuits
implemented in the PLAs.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 12
of Digital logic with Verilog Design”
1
3

Example
Implement the following Boolean function with a PLA?
F1(A,B,C) = ∑(0,1,2,4) ; F2(A,B,C) = ∑(0,5,6,7) ; F3(A,B,C) = ∑ (0,3,5,7)

F1 = B’C’+A’B’+A’C’

F2 = A’B’C’+AC+AB

F3 = A’B’C’+BC+AC Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
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1
4

F1 = B’C’+A’B’+A’C’
PLA Circuit Diagram
F2 = A’B’C’+AC+AB

F3 = A’B’C’+BC+AC

Each input goes through a buffer–inverter combination, shown

in the diagram with a composite graphic symbol, that has both
Morris Mano, “Digital Circuits and Logic Design”, PHI
the true and complement outputs. Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
1
5

Programmable Array Logic

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
 Programmable Array Logic (PAL)

The drawbacks in PLA led to the development

of a similar device

In which the AND plane is programmable, but

the OR plane is fixed. Such a chip is known as
a programmable array logic (PAL) device.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 16
of Digital logic with Verilog Design”
 Programmable Array Logic (PAL)
In which the AND plane is programmable, but
the OR plane is fixed. Such a chip is known as a
programmable array logic (PAL) device.

In Figure:

✓ The product terms P1 and P2 are

hardwired to one OR gate

✓ P3 and P4 are hardwired to the other OR

gate.
f1 = x1x2x3’ + x1’x2x3 and f2 = x1’x2’ +
Morris Mano, “Digital Circuits and Logic Design”, PHI
x1x2x3. Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
17
Contd.
• Unlike the situation with a PLA, a product term cannot be
shared among two or more OR gates.
• Therefore, each function can be simplified by itself, without
regard to common product terms.
• The number of product terms in each section is fixed

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 18
of Digital logic with Verilog Design”
1
9

Example: PAL

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2
0

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Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
2
1

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
2
2

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
 4. Complex Programmable Logic Devices (CPLDs)

For implementation of circuits that require more inputs and outputs, either multiple
PLAs or PALs can be employed or else a more sophisticated type of chip, called a
Complex Programmable Logic Device (CPLD), can be used.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 23
of Digital logic with Verilog Design”
4. Complex Programmable Logic Devices (CPLDs)

CPLDs Include :
✓ Multiple PAL or PLA Blocks
✓ Interconnections Wire
✓ Input and Output Blocks

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 24
of Digital logic with Verilog Design”
Complex Programmable Logic Devices (CPLDs)
Structure

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 25
of Digital logic with Verilog Design”
 Field-Programmable Gate Arrays
Why FPGA:
✓ PLDs can implement only max upto 10000 gates.
✓ By modern standards, a logic circuit with 10,000 gates is not large. To
implement larger circuits, it is convenient to use a different type of chip
that has a larger logic capacity.
✓ A field-programmable gate array (FPGA) is a programmable logic
device that supports implementation of relatively large logic circuits.
✓ FPGAs are quite different from PLDs and CPLDs because FPGAs do not
contain AND or OR planes.

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 26
of Digital logic with Verilog Design”
2
7

FPGA contd.
✓ Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around
a matrix of configurable logic blocks (CLBs) connected via programmable interconnects.

✓ FPGAs can be reprogrammed to desired application or functionality requirements after

manufacturing.

✓ This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs),
which are custom manufactured for specific design tasks.

✓ Although one-time programmable (OTP) FPGAs are available, the dominant types are
SRAM based which can be reprogrammed as the design evolves

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals
of Digital logic with Verilog Design”
 4. Field-Programmable Gate Arrays
General structure of an FPGA:
✓ The logic elements are arranged in a two-
dimensional array

✓ The interconnection wires are organized as

horizontal and vertical routing channels
between rows and columns of logic blocks.

✓ The routing channels contain wires and

programmable switches

Morris Mano, “Digital Circuits and Logic Design”, PHI

Publication, Stephen Brown, Zvonko Vranesic, “Fundamentals 28
of Digital logic with Verilog Design”
2
9
FPGA Block Diagram

✓ CLB contain lookup table. A lookup table is a truth table stored in an SRAM and
Morris Mano, “Digital Circuits and Logic Design”, PHI
provides the combinational circuit functions for the logic block
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