Department of Electrical Engineering

ELEC261 - Digital Systems Design

VHDL Modelling Styles

ELEC261
Lecture 7 Prof. F Bensaali
Content:
• Synthesis vs. Simulation
• Modelling styles
o Concurrent signal assignments
o Components and instantiation
o The process statement
o Sequential statements
o Behavioural style
o Dataflow style
o Structural style

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 Synthesis vs. Simulation
Modelling styles
 VHLD is both, a Synthesis language and a Simulation
language
o Small subset of the language is ‘synthesizable’, i.e., it can be
translated into logic gates, and other ‘hardware’ components
o Another subset of the language includes many features for
‘simulation’ or ‘verification’, features that have NO meaning in
hardware

Used to write code

to simulate the VHDL
behaviour of a design Used to implement
VHDL
the design into
Synthesizable hardware (e.g., FPGA)

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 Modelling styles
Modelling styles

Modeling styles

Circuit is described as an I/O relationship

Behavioural using sequential statements inside a
process

Structural Circuit is described as a network of

interconnected components

Circuit is described using concurrent

Dataflow
statements

Mixed This style of modelling uses any combination

of other styles

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 Concurrent signal
Concurrent signal assignments
assignments

 Within VHDL, signals are assigned values using “Signal

Assignment Statements”

 Multiple signal assignment statements are executed

concurrently (i.e., in parallel) and referred to us as
Concurrent Signal Assignment Statements:
o Simple Signal Assignments
o Conditional Signal Assignments
o Selected Signal Assignments

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 Simple signal
Simple signal assignments
assignments

 These have the form

target <= expression;

o Each time any signal on the right-hand side of the assignment

changes, the left-hand side is updated
o Operators can be included (and, or, +, etc.) in expression
Example
Write the VHDL code to implement a three input OR gate
using simple signal assignments. The three input signal
names are A, B and C and the output signal name is F
A Entity??
B My_OR3
C
F Architecture??
Signal Assignment ??
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 Simple signal
Simple signal assignments
assignments (Cont’d)
(Cont’d)

Solution

entity My_OR3 is
port( A: in std_logic;
B: in std_logic;
C: in std_logic;
F: out std_logic
A
);
B My_OR3 F End My_OR3;
C
architecture behavioral of My_OR3 is
begin
F <= A or B or C;

end behavioral

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 Simple signal
Simple signal assignments
assignments (Cont’d)
(Cont’d)

L M N F
Exercise
0 0 0 0
Write the VHDL code to 0 0 1 1
implement the function 0 1 0 0
expressed in the following 0 1 1 0
truth table using simple 1 0 0 0
signal assignments 1 0 1 0
1 1 0 1
1 1 1 1

L Entity??
M My_F F F = ?? Architecture??
N
Signal Assignment ??

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 Simple signal
Simple signal assignments
assignments (Cont’d)
(Cont’d)

Solution entity my_f is

port ( L, M, N : in std_logic;
F: out std_logic);
end my_f;

architecture f_1 of my_f is

L
M My_F F
signal A1, A2 : std_logic; -- intermediate
N -- signals
begin

A1 <= ((not L) and (not M) and N);

A2 <= L and M;
F <= A1 or A2;
F = L M N + LM end f_1;

Alternative architecture:
architecture f_2 of my_f is
begin
F <= ((not L) and (not M) and N) or (L and M);
end f_2;
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 Conditional signal
Conditional signal assignment
assignment

 These have the form

target <= expression_1 when condition_1 else
expression_2 when condition_2 else
...
expression_n when condition_n else
expression;
Exercise
Write the VHDL code to implement a 4:1 multiplexer
using conditional signal assignments.
D0
D1 Entity?
My_4to1_
D2 mux
mx_out Architecture?
D3
Conditional Signal Assignment ?

2
sel

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 Conditional signal
Conditional signal assignment
assignment (Cont’d)
(Cont’d)

Solution

entity my_4to1_mux is
port ( D3,D2,D1,D0 : in std_logic;
SEL : in std_logic_vector(1 downto 0);
D0 MX_OUT : out std_logic);
end my_4to1_mux;
D1
My_4to1_
mx_out
D2 mux architecture mux4to1 of my_4to1_mux is
D3
begin
MX_OUT <= D3 when (SEL = "11") else
2 D2 when (SEL = "10") else
sel D1 when (SEL = "01") else
D0 when (SEL = "00") else
'0' ;
end mux4to1;

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 Selectedsignal
Selected signalassignments
assignment
 These are of the form
with choose_expression select
target <= expression_1 when choices_1,
expression_2 when choices_2,
...
expression_n when choices_n[others];

 All possible choices must be entity My_4to1_mux is

included, unless the others port( D0, D1, D2, D3: in std_logic;
sel: in std_logic_vector(1 downto 0);
clause is used as the last choice mx_out: out std_logic );
end My_4to1_mux;
Example
D0 architecture mux_4to1 of My_4to1_mux is
begin
D1
My_4to1_ with sel select
mx_out
D2 mux mx_out <= D3 when "11",
D2 when "10",
D3
D1 when "01",
D0 when "00",
2 '0' when others;
sel end mux_4to1;
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 Components &
Components & instantiation
instantiation

 VHDL allows designs to be built hierarchically by building

subcomponents and interconnecting them to model the whole
system.
 Component instantiation instantiates (i.e., create instances of)
predefined components within a design architecture.
o Each component is first declared in the declaration section of
that architecture, and then "instantiated" one or more times in
the body of the architecture.
o The "component declaration" defines the component interface,
which corresponds to the component's entity declaration.

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 Components &
Components & instantiation
instantiation (Cont’d)
(Cont’d)
entity entity_name is
port( input signals: in type;
 Construct one component output signals: out type );
declaration for each unique end entity_name;
architecture arch_name of entity_name is
component that the model will
-- declare components used
use component component1_name is
port( input signals: in type;
o Can be easily constructed output signals: out type );
from the component entity end component;

description component component2_name is

port( input signals: in type;
output signals: out type );
 A component instantiation end component;

statement is written using the -- declare all signals used to connect the components

port map ()construct Begin

-- label each component and connect its ports to signals
o Will have as many entries as -- or entity ports

there are ports on the Label1: component1_name port map (port => signal, ...);
Label2: component2_name port map (port => signal, ...);
component end arch_name;

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Components &
Components & instantiation
instantiation (Cont’d)
(Cont’d)

B
a1 b1
b2 A b5
A a3
a2 b3 b6
b4
A

entity B_entity is
port( b1, b2, b3, b4: in std_logic;
b5, b6: out std_logic
entity A_entity is );
port( a1, a2: in std_logic; end B_entity;
a3: out std_logic architecture B_arch of B_entity is
);
end A_entity;
component
componentA_entity;
A_entity is
architecture A_arch of A_entity is port(
port( a1,
a1,a2:
a2:ininBit;
std_logic;
begin a3:
a3:out
outBit
std_logic
-- architecture description; ););
end A_arch; end
endcomponent;
component;
Begin
B_1: A_entityport
B1: A_entity portmap
map(b1,
(b1,b2,
b2,b5);
b5);
B_2:
B1: A_entity portmap
A_entityport map(b3,
(b3,b3,
b4,b6);
b6);
end B_arch;

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 Components &
Components & instantiation
instantiation (Cont’d)
(Cont’d)

Exercise

X
Y
a W
b c
Z

Entity?? Entity ??
Architecture?? Component ??
Architecture ??
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 Components &
Components & instantiation
instantiation (Cont’d)
(Cont’d)

X a
c
a Y b
b c a
c W
a b
c
Z b

entity my_Circuit is
port( X, Y, Z: in std_logic;
W: out std_logic
entity and_gate is );
port( a, b: in std_logic; end my_Circuit ;
c: out std_logic architecture my_Circuit _arch of my_Circuit is
);
end and_gate; signal g1, g2 : std_logic;
component and_gate is
architecture and_gate_arch of and_gate is port( a,b: in std_logic;
begin c: out std_logic
c <= a and b; );
end and_gate_arch; end component;
Begin
n1: and_gate port map (X, Y, g1);
n2: and_gate port map (Y, Z, g2);
n3: and_gate port map (g1, g2, W);
end my_Circuit _arch;
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 The process
The process statement
statement

 A Process is a sequence of instructions referred to as

sequential statements
o It has two states: execution and wait Execution
o It consists of sequential statements but as
a block behaves as a concurrent
statement
o It is executed in parallel with other
processes and concurrent statements Wait
o It must contain an explicit sensitivity list
or a wait statement Until a condition
is satisfied

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 The The
process statement
process (Cont’d)
statement
A process can be given a unique name using
an optional LABEL

[label:] PROCESS [(sensitivity list)] List of signals to which the process is

[declaration part] sensitive
BEGIN
statement part
ALL statements within the process are
END PROCESS [label]; executed SEQUENTIALLY. Hence the
order of statements is important
The process must end with the
keywords END PROCESS

 The sensitivity list:

o Contains all the signals that are able to trigger the process
o Any event on any of these signal will cause to execute the process
at least once
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 Process with
Process with aa sensitivity
sensitivity list
list

 Whenever there is an event on any

[label:] PROCESS (sensitivity list)
of the signals in the sensitivity list, [declaration part]
the process is executed BEGIN
statement part
 Every time the process is triggered, it END PROCESS [label];
will run entirely

Example
architecture Behavioural of XOR3 is
begin
XOR3_Proc: process (A, B, C)
begin
A if ((A xor B xor C) = '1') then
B D D <= '1';
C else
D <= '0';
end if;
end process XOR3_Proc;
Execution is controlled by end Behavioural;
changes to A, B and C signals

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 Sequential statements
Sequential statements

 IF statement
 CASE statement
 Loops
o FOR
o WHILE (not synthesisable)
o LOOP

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 IF statement
IF statement

 Syntax: Example

if <condition> then Write the VHDL code to implement

statements the following function using an IF
...
[ statement inside a process with a
elsif <condition> then sensitivity list:
statements
…
else
F = ABC + BC
statements
…
]
end if;

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 IF statement
IF statement (Cont’d)
(Cont’d)
Solution
entity my_if_ex is
port ( A,B,C : in std_logic;
F: out std_logic);
end my_if_ex;
architecture exercise2 of my_if_ex is
begin
proc: process (A, B, C)
begin
if (A = '0' and B = '0' and C = '1') then
F <= '1'; F ( A, B, C ) = ABC + BC
elsif (B = '1' and C = '1') then
F <= '1';
else
F <= '0';
end if;
end process proc1;
end exercise2;

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 IF statement
IF statement (Cont’d)
(Cont’d)

Exercise
Implement an 8:1 MUX using IF statement

Data_in mux_out
8
Architecture??
3

SEL

entity mux_8to1 is
port ( Data_in : in std_logic_vector (7 downto 0);
SEL : in std_logic_vector (2 downto 0);
mux_out : out std_logic);
end mux_8to1;

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 IF statement
IF statement (Cont’d)
(Cont’d)

Solution

Data_in mux_out
8

architecture my_8to1_mux of mux_8to1 is

3
begin
SEL
my_proc: process (Data_in, SEL)
begin
If (SEL="111") then mux_out <= Data_in(7);
elsif (SEL="110") then mux_out <= Data_in(6);
elsif (SEL="101") then mux_out <= Data_in(5);
elsif (SEL="100") then mux_out <= Data_in(4);
elsif (SEL="011") then mux_out <= Data_in(3);
elsif (SEL="010") then mux_out <= Data_in(2);
elsif (SEL="001") then mux_out <= Data_in(1);
elsif (SEL="000") then mux_out <= Data_in(0);
else mux_out <= '0';
end if;
end process my_proc;
end my_8to1_mux;

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 CASE statement
CASE statement

 Syntax: Example
Previous 8:1 MUX using CASE
case <expression> is statement
when <choice(s)> => statements;
architecture my_case_ex of mux_8to1 is
…
when … begin
my_proc: process (Data_in, SEL)
[ when others => statements;]
begin
case (SEL) is
end case; when "000" => mux_out <= Data_in(0);
when "001" => mux_out <= Data_in(1);
when "010" => mux_out <= Data_in(2);
when "011" => mux_out <= Data_in(3);
when "100" => mux_out <= Data_in(4);
when "101" => mux_out <= Data_in(5);
when "110" => mux_out <= Data_in(6);
when "111" => mux_out <= Data_in(7);
when others => mux_out <= '0';
end case;
end process my_proc;
end my_case_ex;

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 CASE
IF & statement
CASE statement
Exercise
Let’s add a chip enable CE signal to the previous 8:1 MUX:
o When CE is ‘1’, the MUX output is as in last example
o When CE is ‘0’ the MUX output is ‘0’

Data_in mux_out
8
Architecture using
3
IF & CASE
SEL CE statements ??

entity mux_8to1 is
port ( Data_in : in std_logic_vector (7 downto 0);
SEL : in std_logic_vector (2 downto 0);
CE: in std_logic;
mux_out : out std_logic);
end mux_8to1;
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 IF &
IF & CASE
CASE statement
statement (Cont’d)
(Cont’d)

Solution architecture my_case_ex of mux_8to1 is

begin
my_proc: process (Data_in, SEL, CE)
begin
if (CE = '1') then
case (SEL) is
Data_in mux_out
when "000" => mux_out <= Data_in(0);
8 when "001" => mux_out <= Data_in(1);
when "010" => mux_out <= Data_in(2);
3 when "011" => mux_out <= Data_in(3);
when "100" => mux_out <= Data_in(4);
SEL CE when "101" => mux_out <= Data_in(5);
when "110" => mux_out <= Data_in(6);
when "111" => mux_out <= Data_in(7);
when others => mux_out <= '0';
end case;
else
mux_out <= '0';
endif;
end process my_proc;
end my_case_ex;

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 Loops
Loops
 Sequences of statements can be repeated some number of times
under the control of WHILE, FOR or LOOP constructs
[label:] for loop_variable in starting_value to stopping_value loop
sequence of statements
end loop [label];

[label:] while condition loop [label:] loop

sequence of statements sequence of statements
end loop [label]; end loop [label];

Example

Initialise_A: while i < 10 loop Initialise_A: for i in 0 to 9 loop

-- or for i in 9 downto 0 loop
A(i) := 0;
i := i+1; A(i) := 0;
end loop Initialise_A; end loop Initialise_A;

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 Loop termination
Loop termination statement
statement

 EXIT statement may be used in a loop to immediately exit the

loop

[ label: ] exit [ label2 ] [ when condition ];

Example
variable sum, cnt: integer;
begin
sum := 0; cnt := 0;
first: loop
cnt := cnt + 1;
sum := sum + cnt;
exit when (sum > 100) ;
end loop first;
second: loop
cnt := cnt + 1;
sum := sum + cnt;
if (sum > 100) then exit;
end if
end loop second;
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 Dataflow modelling
Dataflow modelling style
style

 Describes how data moves through xor1

xor2
xor1_out
the system and the various A
B C
processing steps xor2_out

 Dataflow uses series of concurrent

statements to realise logic
architecture Dataflow_XOR3 of XOR3 is
o Concurrent statements are Signal xor1_out : std_logic;
evaluated at the same time begin

o Order of this statements doesn’t xor1_out <= A xor B;

xor2_out <= xor1_out xor C;
matter
end Dataflow_XOR3 ;
 Dataflow is most useful style when
series of Boolean equations can
represent a logic

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 Behavioural modelling
Behavioural modelling style
style

 It accurately models what xor1

xor2

happens on the inputs and A

B
xor1_out

C
outputs of the black box (no xor2_out

matter what is inside and how it

works)
architecture Behav_XOR3 of XOR3 is
 This style uses Process
begin
statement XOR3_Proc: process (A, B, C)
begin
o Executions is controlled by if ((A xor B xor C) = ’1’) then
xor2_out <= ’1’;
changes to signals which appear else
in the sensitivity list end if;
xor2_out <= ’0’;

end process XOR3_Proc;

end Behav_XOR3;

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 Structural modelling
Structural modelling style
style

 This design style utilises simple xor1

xor2
A xor1_out
building blocks to compose logic B C
functions xor2_out

 Components are interconnected in a

hierarchical manner
 Structural style is useful when
expressing a design that is naturally
composed of sub-blocks ?
 Design steps:
Entity, architecture, instantiation,
mapping

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 Structural modelling
Structural modelling style
style (Cont’d)
(Cont’d)
xor xor1
xor2
X A xor1_out
Z
Y B C
xor2_out

entity XOR3 is
port( A, B, C: in std_logic;
xor2_out: out std_logic
);
entity XOR2 is end XOR3;
port( x, y: in std_logic; architecture XOR3_arch of XOR3 is
z: out std_logic
); signal xor1_out : std_logic;
end XOR2; component XOR2 is
port( x,y: in std_logic;
architecture XOR2_arch of XOR2 is z: out std_logic
);
begin
end component;
z <= x xor y;
end XOR_arch; Begin
X1: XOR2 port map (A, B, xor1_out);
X2: XOR2 port map (xor1_out, C, xor2_out);
end XOR3_arch;

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