Body effect

- The body effect occurs when there is a voltage difference between the B and
S terminals of the MOSFET in the case that the B terminal is not connected to
the S terminal but is connected to a different voltage level.
For example: the B terminal is grounded while the S terminal is not grounded.
In other words, the voltage V SB is now non-zero.
- Consider the case the bulk voltage of an NFET drops below the source
voltage

+ Since the S and D junctions remain reverse-biased, we surmise that the

device continues to operate properly, but some of its characteristics may
change.
To understand the effect, suppose VS = VD = 0, and VG is somewhat less than
VTH, so that a depletion region is formed under the gate but no inversion layer
exists. As VB becomes more negative, more holes are attracted to the
substrate connection, leaving a larger negative charge behind; i.e., as depicted
in Fig. 2.23, the depletion region becomes wider.

+ From equation:

the threshold voltage is a function of the total charge in the depletion region
because the gate charge must mirror Qd before an inversion layer is formed.
Thus, as VB drops and Qd increases, VTH also increases.
 Body effect or back gate effect
-It can be proved that with body effect:

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- For body effect to manifest itself, the bulk potential, Vsub, need not change:
if the source voltage varies with respect to Vsub, the same phenomenon
occurs.

For example, consider the circuit in Fig. 2.25(a), first ignoring body effect. We
note that as Vin varies, Vout closely follows the input because the drain current
remains equal to I1. In fact, we can write:

concluding that Vin − Vout is constant if I1 is constant [Fig. 2.25(b)]

Now suppose that the substrate is tied to ground and body effect is significant.
Then, as Vin and hence Vout become more positive, the potential difference
between the source and the bulk increases, raising the value of VTH. Equation
(2.26) implies that Vin − Vout must increase so as to maintain ID constant [Fig.
2.25(c)].
- Body effect is usually undesirable.
+The change in the threshold voltage
+Often complicates the design of analog (and even digital) circuits.
Device technologists balance Nsub and Cox to obtain a reasonable value for γ .

Channel-Length Modulation
-The semiconductor manufacturing process still has certain errors that affect
the channel length L.
+ Limits of photolithography, corrosion, doping and heating technology cause
the actual channel length to often be shorter than the channel length drawn on
the layout or put on the design mask for production.
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+ Especially with the rapid development of semiconductor technology, the
reduction in component size to increase MOSFET performance makes the
influence of technology on the change in channel length even stronger.
 The change in L due to technology or channel constriction is called
Channel-Length Modulation, or short channel effect because short
channels are affected more clearly than long channels.
-From the flow equation of ID

L’ is in fact a function of VDS. It can be seen that, the smaller L is, the larger ID
is. Therefore, the channel change effect is modeled by a channel length
change coefficient λ and the equation ID is rewritten as shown in equation
below. With Delta L is the change in channel length caused by technology

Where L’ = L – deltaL , i.e., 1/L ≈ (1+ deltaL/L)/L

As shown in the figure below

As illustrated in figure this phenomenon leads to a nonzero slope in the ID/VDS

characteristic and hence a nonideal current source between D and S in
saturation. Parameter λ represents the relative change in length for a given
increase in VDS . Thus, the length of the channel is inversely proportional to
the value of λ and is determined by deltaL/L = λ VDS.
- With channel-length modulation, some of the expressions derived for gm
must be modified. Equations below are respectively rewritten as

Rewitten:

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While while Eq remains unchanged.
-The dependence of ID upon VDS in saturation may suggest that the bias
current of a MOSFET can be defined by the proper choice of the drain-source
voltage, allowing freedom in the choice of VGS − VTH. However, since the
dependence on VDS is much weaker, the drain-source voltage is not used to
set the current. That is, we always consider VGS − VTH as the current-defining
parameter. The effect of VDS on ID is usually considered an error

Short channel effect

Threshold Voltage Variation
As the MOSFET channel length decreases, the threshold voltage (Vth) is also
affected.
-As the channel length L decreases, the depletion regions at the Source and
Drain extend into the channel region, reducing the charge required to create
the inversion layer.
As a result, Vth decreases as L decreases
- Drain-Induced Barrier Lowering (DIBL): The strong electric field from the
Drain affects the potential barrier at the Source, reducing Vth, reduces the
output impedance of the MOSFET
Consequences: Easily causes logic errors in digital circuits, increasing leakage
current when the MOSFET is in the off state.

Mobility Degradation with Vertical Field

1. What is Mobility Degradation with Vertical Field?
 When VGS (Gate-Source voltage) increases, the vertical electric field
between the Gate and the channel also increases.
 This strong electric field confines charge carriers (electrons or
holes) closer to the Si-SiO₂ interface.
 As a result, carriers experience more scattering due to:
o Interface traps and defects.

o Interactions with atoms in the silicon lattice.

 This reduces carrier mobility (μ), degrading the performance of

MOSFETs.

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2. Mathematical Model of Mobility Degradation
Carrier mobility under high vertical fields is modeled by the empirical equation:

Where:
 μ0: Low-field mobility (mobility in the absence of this effect).
 Θ: Fitting parameter, dependent on oxide thickness tox:

Key observations from the equation:

 As VGS−Vth increases, mobility μ decreases.
 For thinner oxide tox, θ increases, making this effect more
pronounced.
Example: If tox=100 Å, then θ≈1 V−1. This means that when the overdrive
voltage
VGS−Vth exceeds 100 mV, mobility starts to degrade significantly.

3. Consequences of Mobility Degradation

1. Reduced Current Drive Capability
 Since ID (drain current) depends on carrier mobility, a reduction in
μ leads to lower ID.
 This degrades the switching speed in digital circuits and gain in
analog circuits.
2. Deviation from the Ideal Quadratic Model
 In an ideal MOSFET, drain current in saturation follows:

 With mobility degradation, ID no longer follows this simple quadratic

behavior.
3. Generation of Odd Harmonics in Drain Current
 In an ideal MOSFET, if VGS is a sinusoidal signal, the drain current
contains only even harmonics.
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  Due to mobility degradation, odd harmonics appear, causing signal
distortion in analog circuits.
4. Reduced Transconductance (gm)
 Transconductance gm is defined as:

 Since ID decreases due to lower mobility, gm also decreases.

 Lower gm reduces amplifier gain and degrades analog circuit
performance.

- Velocity Saturation
1. What is Velocity Saturation?
 Carrier mobility (μ) depends on the lateral electric field (Ex) in the
channel.
 Normally, carrier velocity follows the relationship: v=μEx
 However, when Ex becomes very high (≈1V/μm), carrier velocity stops
increasing and reaches a saturation velocity:
Vsat ≈ 10^7 cm/s
 This means that, as electrons enter the channel and accelerate toward
the Drain, they eventually reach a maximum speed and cannot move
any faster, even if Ex increases further.

2. How Velocity Saturation Affects Drain Current (IDI_DID)

 In extreme cases, carriers experience velocity saturation along the
entire channel.
 Instead of following the ideal quadratic relation:

ID∝(VGS−Vth)2
The current now follows a linear relationship with overdrive voltage:

ID∝(VGS−Vth)

 Key consequence: MOSFET behaves more linearly, rather than

following the traditional square-law model.
Experimental observation:

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 When L<1μm, devices exhibit velocity saturation because equal
increments in
VGS−Vth result in equal increments in ID (instead of squared
increments).

 This causes the ID−VDS curve to deviate from the expected

behavior in short-channel MOSFETs.

3. Effect on Transconductance (gm)

 In ideal MOSFETs: gm∝ID

 In velocity saturation: gm≈vsatWCox
 Key consequence:
o Transconductance (gm) becomes weakly dependent on ID and
channel length (L).
o This reduces the gain of analog circuits, making MOSFETs less
efficient as amplifiers.

4. Premature Saturation Before Pinch-Off

 In an ideal MOSFET, saturation occurs when: VDS>VGS−Vth

 But with velocity saturation, the drain current saturates earlier at:
VD0<VGS−Vth
 This means the MOSFET enters saturation earlier than expected,
reducing the available current for switching or amplification.

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Key observation:
 If VGS increases, the drain current saturates well before pinch-off
occurs, further deviating from traditional models.
 This limits current drive, impacting the performance of high-speed
and high-frequency circuits.

5. Mathematical Model of Velocity Saturation

The drain current in the velocity saturation regime is given by:

Where:
 W = MOSFET width
 Cox = Gate oxide capacitance per unit area
 vsat = Saturation velocity (~10710^7107 cm/s)
 μeff = Effective mobility
Key takeaways from the equation:
1. If L or vsat is large, the equation simplifies to the traditional square-
law model.
2. If VGS−Vth is small, the device still behaves closely to the square-
law model.
3. For small LLL, velocity saturation dominates, leading to a linear
current dependence on VGS−Vth.

Hot carrier effects

1. What are Hot Carrier Effects?

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 In short-channel MOSFETs, when VDS is high, the lateral electric
field between Source and Drain becomes very strong.
 While the average carrier velocity saturates, some carriers continue
to gain higher kinetic energy as they accelerate toward the Drain.
 These high-energy carriers are called hot carriers.
Result:
 Hot carriers can collide violently with silicon atoms near the Drain,
causing impact ionization.
 This process generates new electron-hole pairs, leading to
unwanted leakage currents.

2. Consequences of Hot Carrier Effects

1. Drain-to-Substrate Leakage Current
 Due to impact ionization, newly generated electrons move toward the
Drain, while holes move toward the Substrate.
 This creates a drain-to-substrate leakage current (I sub), which
affects MOSFET stability.
2. Hot Carriers Can Get Trapped in the Gate Oxide
 If some electrons have very high energy, they may:
o Become trapped in the oxide layer of the Gate.

o Even enter the Gate terminal, leading to a Gate leakage

current (IG).
 This process alters the threshold voltage (Vth) over time.
Effects:
 MOSFET performance degrades over time (long-term reliability
issue).
 CMOS circuits can fail due to unstable Vth.

3. How to Reduce Hot Carrier Effects?

 As semiconductor technology scales down (CMOS 7nm, 5nm, 3nm),
Hot Carrier Effects become less severe because:
o Lower supply voltage (VDD) reduces the maximum energy
carriers can attain.
o For example: The energy required to create an electron-hole pair
is 1.12 eV, but if VDD≈1V, most electrons cannot reach this
energy level.
 Techniques to mitigate Hot Carrier Effects:

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 o Reduce maximum VDS in circuit design.

o Increase doping concentration near Drain (Halo

Implantation) to reduce the electric field.
o Use FinFET / GAAFET structures, which improve current
control without requiring high VDS.

Output Impedance Variation with Drain-Source

Voltage
1. Overview of Output Impedance rO in MOSFET
 The output impedance rO of a MOSFET is defined as the inverse of the
channel-length modulation parameter (λ): rO=1 \ λID
 In an ideal MOSFET, rO is assumed to be constant in the saturation
region.
 However, in realityrO varies with VDS due to physical effects in the
channel.

2. Effect of Channel-Length Modulation

 When VDS increases, the pinch-off point moves closer to the
Source, effectively reducing the channel length.
 A shorter effective channel increases drain current ID, leading to a
decrease in rO.
Key observation:
 rO is no longer constant but decreases as VDS increases.
 This behavior is similar to the capacitance of a reverse-biased PN
junction:
o At low reverse bias, the depletion region width is highly
dependent on voltage.
o At high reverse bias, the depletion region width changes less
significantly.

3. Effect of Drain-Induced Barrier Lowering (DIBL)

 In short-channel MOSFETs, as VDS increases:
o DIBL reduces the threshold voltage (Vth), leading to an
increase in ID.
o This partially compensates for the effect of Channel-Length
Modulation, keeping rO relatively stable over a certain voltage
range.
 At very high VDS, impact ionization becomes significant:
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 o Carriers gain enough energy to ionize silicon atoms near the
Drain, generating additional electron-hole pairs.
o This creates a drain-to-substrate leakage current, further
reducing rO.

4. Consequences of Output Impedance Variation

1. Nonlinearity in Analog Circuits
o Since rO varies with VDS, the output voltage-dependent
impedance causes nonlinear distortion.
o Example: In an operational amplifier (op-amp), variations in
rO lead to fluctuations in gain, reducing circuit precision.
2. Limits the Gain of Cascode Amplifiers
o In a cascode structure, a high rO is desirable for achieving high
gain.
o However, impact ionization introduces additional leakage
paths, reducing rO and thus limiting gain.

Latch up
Explanation of "Latch-Up" in MOSFET (CMOS)

1. What is Latch-Up?
 Latch-up is a failure mechanism in CMOS circuits where an
unintended parasitic bipolar junction transistor (BJT) structure
turns on, creating a low-resistance path between VDD and GND.
 Once triggered, this can cause a large current to flow, potentially
damaging the circuit.
This issue occurs in CMOS but does not exist in NMOS-only circuits.
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2. What Causes Latch-Up?
The Parasitic BJT Structure in CMOS
 CMOS technology consists of both NMOS and PMOS transistors,
fabricated in different semiconductor regions (n-well, p-well, or
bulk silicon).
 Due to fabrication constraints, two unintended BJTs (parasitic
transistors) form naturally:
o Q1 (PNP) is associated with the PMOS in the n-well.

o Q2 (NPN) is associated with the NMOS in the p-substrate.

 These transistors form a positive feedback loop, meaning that once

triggered, they can sustain themselves in the ON state
indefinitely.
How it Happens:
 A small injected current can turn on Q1, which then feeds current to
Q2.
 Q2 then feeds back into Q1, amplifying the current continuously.
 This creates a short circuit between VDD and GND, drawing
excessive current that can permanently damage the device.

3. Common Causes of Latch-Up

1. Large Voltage Swings at the Drain
o Due to capacitive coupling in CMOS circuits, large voltage
swings at the drain of a MOSFET can induce displacement
currents into the n-well or substrate, triggering latch-up.
2. High Current Injection from Large Digital Buffers
o In high-speed digital circuits, rapid transitions can inject large
transient currents into the substrate, initiating latch-up.
3. Forward Biasing of Source-to-Bulk Junction Diodes
o In CMOS, the PN junction between Source and Bulk can
become forward biased, allowing current to flow into the
substrate and triggering latch-up.

4. How to Prevent Latch-Up

Design techniques to minimize latch-up risk:
 Reduce the resistance of the n-well and p-substrate to limit the
effect of parasitic currents.

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 Place n-well and p-substrate contacts closer to transistors to
provide a low-resistance discharge path.
 Minimize the gain of the parasitic BJT transistors by optimizing
doping profiles.
 Follow latch-up prevention layout guidelines to maintain proper
spacing between semiconductor regions.

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