ORCATOP Design Santhosh
ORCATOP Design Santhosh
PRESENTED BY
CH.SANTHOSH
Flow use commands and shortcuts
Go to the directory( cd ICC2_STUD/lab2_floorplan)
csh source /opt/source * icc2_exec | tee floorplan.log(invoke the tool)
open_lib ORCA_TOP.dlib list_blocks open_block ORCA_TOP/floorplan.design
start_gui link_block list_blocks save_block -as floorplanSRK list_blocks
If you want to close the block (close_block -force)
Control+D remove all
Control+M remove the flylines
M (movable)
Control+shift+F or control+shift+N flylines
Control+R properties
Control+A select all macros
Remove the blockages select the area “D” enter
Check_legality if any cells are illegally placed or overlap cells
Control+shift+E open the error browser
Control+shift+N select all macros
get_attribute [current_block] bbox it shows the block size
get_voltage_areas it shows the voltage area
remove_voltage_areas <name of the voltage >
get_voltage_area_shapes it shows the voltage shapes
set_attribute[get_voltage_area_shapes VOLTAGE_AREA_SHAPE_1] –name voltage_area.
physical_status -value unrestricted voltage area issues
Physical design inputs
Load all the inputs
1.gate level netlist (.v) (read_Verilog <filename>)
2.sdc (.sdc)
3.upf (.upf) (load_upf)
4.scandef
5.def (.def) (read_def <filename>)
6.mmmc (.mmmc)
7.IO file
8.library file (.lib)
9.lef (.lef)
10.tlu+ files (.tlu)
11.technology file (.tf)
12.guidelines/additional scripts
Sanity checks
1. netlist checks
2. Sdc checks
◦ Floating inputs and nets 3. Library checks
• Unconstrained path • Logical libraries
◦ Vdd and vss shorts
• Multiclock driven • Physical libraries
◦ Multi driven nets
register • Antenna effects
◦ Combinational loops • Unconstrained
◦ Unloaded output • Routing resources
endpoint • Blockages
◦ Unconstraints pins • Port IO delay • Site information0
◦ Pins mismatch missing • Unit dimension(H/W)
◦ Block boxes • Port skew/load check_timing
◦ Unique module missing check_timing–physicallibrary
• Clock definition is check_library
check_design –netlist missing
check_design -all check_constraints
check_timing
Floorplan (T shape)
initialize_floorplan -side_ratio { 2 1 1 1 1 1 } -core_utilization 0.45 -core_offset { 1 1 } -shape T
Floorplan (square shape)
initialize_floorplan -side_ratio { 2 2 2 2 } -core_utilization 0.45 -core_offset { 1 1 } -shape R
Rectangle shape
initialize_floorplan -side_ratio { 2 1 1 1 1 2} -core_utilization 0.45 -core_offset { 1 1 } -shape R
Floorplan
initialize_floorplan -side_ratio { 2 2 1 2 } -core_utilization 0.45 -core_offset { 1 1 } -shape L
Cont..,
initialize_floorplan -side_ratio { 2 2 1 2 } -core_utilization 0.45 -core_offset { 1 1 } -shape L
Cmd:
create_placement
Cmd:
Check_legality
cmd
legalize_placement
Congestion (high)
Cmds:
report_congestion
Congestion (met):
Check_legality:
report_utilization:
report_global_timing (violated):
Report_timing (setup slack violated by
1210ps)
report_qor:
report_power:
report_clocks:
CTS clock tree
INPUTS
1.clock spec file
2.Placeopt.v
3.Placeopt.ndm
4. LIB
Cmd:clock_opt
CTS Utilization:
report_global_timing:
report_qor:
report_congestion:
report_constraints –all
report_power:
check_legality:
Route
Cmd:
route_auto
route_opt
report_global_timing ( route_opt)
Utilization:
report_qor:
Check_lvs
report_power:
report_congestion:
report_constraints -all
report_timing: