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ORCATOP Design Santhosh

The document outlines commands and procedures for using the ORCA TOP design tool, including flow commands, physical design inputs, sanity checks, and floorplan initialization. It details various commands for checking legality, managing I/O ports, and performing placement and routing tasks. Additionally, it provides guidelines for macro placement and utilization checks throughout the design process.

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BALA KRISHNA
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111 views43 pages

ORCATOP Design Santhosh

The document outlines commands and procedures for using the ORCA TOP design tool, including flow commands, physical design inputs, sanity checks, and floorplan initialization. It details various commands for checking legality, managing I/O ports, and performing placement and routing tasks. Additionally, it provides guidelines for macro placement and utilization checks throughout the design process.

Uploaded by

BALA KRISHNA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ORCATOP_Design

PRESENTED BY
CH.SANTHOSH
Flow use commands and shortcuts
Go to the directory( cd ICC2_STUD/lab2_floorplan)
csh source /opt/source * icc2_exec | tee floorplan.log(invoke the tool)
open_lib ORCA_TOP.dlib list_blocks open_block ORCA_TOP/floorplan.design
start_gui link_block list_blocks save_block -as floorplanSRK list_blocks
If you want to close the block (close_block -force)
Control+D remove all
Control+M remove the flylines
M (movable)
Control+shift+F or control+shift+N flylines
Control+R properties
Control+A select all macros
Remove the blockages select the area “D” enter
Check_legality if any cells are illegally placed or overlap cells
Control+shift+E open the error browser
Control+shift+N select all macros
get_attribute [current_block] bbox it shows the block size
get_voltage_areas it shows the voltage area
remove_voltage_areas <name of the voltage >
get_voltage_area_shapes it shows the voltage shapes
set_attribute[get_voltage_area_shapes VOLTAGE_AREA_SHAPE_1] –name voltage_area.
physical_status -value unrestricted voltage area issues
Physical design inputs
Load all the inputs
1.gate level netlist (.v) (read_Verilog <filename>)
2.sdc (.sdc)
3.upf (.upf) (load_upf)
4.scandef
5.def (.def) (read_def <filename>)
6.mmmc (.mmmc)
7.IO file
8.library file (.lib)
9.lef (.lef)
10.tlu+ files (.tlu)
11.technology file (.tf)
12.guidelines/additional scripts
Sanity checks
1. netlist checks
2. Sdc checks
◦ Floating inputs and nets 3. Library checks
• Unconstrained path • Logical libraries
◦ Vdd and vss shorts
• Multiclock driven • Physical libraries
◦ Multi driven nets
register • Antenna effects
◦ Combinational loops • Unconstrained
◦ Unloaded output • Routing resources
endpoint • Blockages
◦ Unconstraints pins • Port IO delay • Site information0
◦ Pins mismatch missing • Unit dimension(H/W)
◦ Block boxes • Port skew/load check_timing
◦ Unique module missing check_timing–physicallibrary
• Clock definition is check_library
check_design –netlist missing
check_design -all check_constraints
check_timing
Floorplan (T shape)
initialize_floorplan -side_ratio { 2 1 1 1 1 1 } -core_utilization 0.45 -core_offset { 1 1 } -shape T
Floorplan (square shape)
initialize_floorplan -side_ratio { 2 2 2 2 } -core_utilization 0.45 -core_offset { 1 1 } -shape R
Rectangle shape
initialize_floorplan -side_ratio { 2 1 1 1 1 2} -core_utilization 0.45 -core_offset { 1 1 } -shape R
Floorplan
initialize_floorplan -side_ratio { 2 2 1 2 } -core_utilization 0.45 -core_offset { 1 1 } -shape L
Cont..,
initialize_floorplan -side_ratio { 2 2 1 2 } -core_utilization 0.45 -core_offset { 1 1 } -shape L

Follow the macro guidelines


▪ Macro to IO
▪ Macro to macro
▪ Macro to standard cells
▪ Macros placed around the
core boundary area.
▪ Right to left ….. MY
orientation.
▪ Left to right …. Ro
orientation
▪ All macro guidelines follow
get_cells -hierarchical -filter {is_hard_macro} macro names
sizeof_collection [get_cells –hierarchical -filter{is_hard_macro}] macro count
get_pins –filter “direction==in”
sizeof_collection [get_pins -filter “direction==in”]
get_ports -filter “direction==in”
sizeof_collection [get_ports -filter “direction==in”]
get_ports shows the all ports names
sizeof_collection [get_ports] it is shows the noof ports counts
sizeof_collection [get_ports -filter “direction==out”]
sizeof_collection [get_ports -filter “direction==inout”]
Sizeof_collection [get_pins –of_objects [get_selection]] select the macro, pins of macro, macro pins count
create_pin_guide -boundary{{x1 y1}{x2 y2}} –name inputs[all_inputs]
remove_pin_guide -inputs
remove_pin_guide -all
Select the pin remove_objects [get_selection]
FP Utilisation:
check_legality:
IO ports:
set_block_pin_constraints -self -allowed_layers {M3 M4 M5 M6} place_pins –self
change_selection [get_ports *clk]
create_pin_guide -exclusive -boundary {{483 538} {490 541}} [get_ports *clk] -name clk_ports -
pin_spacing 5
set_individual_pin_constraints -ports [get_ports *clk] -width 0.1 -length 0.4 place_pins -self
change_selection [get_ports *clk]
set_fixed_objects [get_flat_cells -filter "is_hard_macro"]
checks for Powerplan:
cmd:
check_pg_missing_vias
check_pg_connectivity:
Cmd: check_pg_connectivity
Placement
Source all the
inputs.(.v, .db, .
ndm, scandef,
mmmc) Cmd: place_opt

Cmd:
create_placement

Cmd:
Check_legality

cmd
legalize_placement
Congestion (high)
Cmds:
report_congestion
Congestion (met):
Check_legality:
report_utilization:
report_global_timing (violated):
Report_timing (setup slack violated by
1210ps)
report_qor:
report_power:
report_clocks:
CTS clock tree
INPUTS
1.clock spec file
2.Placeopt.v
3.Placeopt.ndm
4. LIB

Cmd:clock_opt
CTS Utilization:
report_global_timing:
report_qor:
report_congestion:
report_constraints –all
report_power:
check_legality:
Route
Cmd:
route_auto
route_opt
report_global_timing ( route_opt)
Utilization:
report_qor:
Check_lvs
report_power:
report_congestion:
report_constraints -all
report_timing:

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