1

AI System Semiconductor Design

Week1: Introduction – IC Designer,
Install Python
Lecturer: Taewook Kang

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 About Taewook Kang
▪ B.S. & M.S. Seoul National University, 2011, 2013
▪ Advisor: Jaeha Kim
▪ Circuit Designer in Silicon Mitus, Korea, 2013-2016
▪ Ph.D. University of Michigan, 2021
▪ Advisor: Michael Flynn
▪ pH sensor system IC with fabrication of sensing membrane
▪ Acoustic beamformer system IC for speech recognition
▪ Apple (Cupertino, CA, USA) Analog-Mixed Signal (AMS) Team, 2021~2024
▪ RF mixer design / EM transformer design
▪ Digital block design/verification
▪ Python-based RF system operation
▪ RF system MATLAB modeling
▪ Assistant Professor in SKKU since 2024
▪ https://sites.google.com/view/tkanggroup/home
▪ Research Interest: Mixed-signal system IC
▪ High-resolution ADC
▪ Acoustic beamformer
▪ Keyword spotting CNN
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 Overview
▪ Coarse Goal
▪ Understanding AI, especially Deep Neural Networks
▪ Implement MNIST DNN in Python
▪ Implement MNIST DNN in Verilog
▪ Prerequisites Classes – 논리회로/논리회로설계실험 (logic circuit design/lab)
▪ Python skill is required
▪ Good to have Verilog experiences
▪ Grading (may change) – Attendance (5%), Exams (45%), Labs (20%), Projects (30%)
▪ Absolute evaluation (절대평가).
▪ Flip Learning
▪ Wed night: Lecture Video Upload, please watch it before the next Wed in-person class
▪ Wed: Offline Lecture – QnA, Python/Verilog practice
▪ TA: 전찬홍

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 Syllabus – May Change
Weeks Date In-person Recording

1 3/5 Introduction, Python Setup Classification Vs. regression, linear regression

2 3/12 Linear regression Logistic regression
3 3/19 Logistic regression Shallow NN (SNN) model
4 3/26 Shallow NN implementation SNN gradient descent, DNN
5 4/2 PyTorch, SNN implementation DNN Youtube tutorial, Stochastic gradient descent (SGD)
6 4/9 MNIST implementation (Project) PyTorch, MNIST implementation

7 4/16 Midterm review X

8 4/23 Midterm Basics of Digital System

9 4/30 Install Vivado, simple Verilog example Verilog Basics – combinational logic
10 5/7 Combinational lab, multiplier synthesize in Vivado Verilog Basics – sequential logic
11 5/14 Sequential logic lab DNN Behavioral Model Implementation
Neuron.sv
12 5/21 DNN Behavioral Model Implementation
Project name: MNIST_part1
Get accuracy from simulation DNN Behavioral Model Implementation – multi-dim bus, Layer_1~4 parameter, weight learning,
13 5/28
Project name: zynet try different DNN sizes

Project announcement Vivienne Sze lectures

14 6/4
Project name: MNIST_part3 Research trend
Project
15 6/11 X
Final review
16 6/18 Final

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 Circuit Designer’s Job – Make Chips

All are IC (Integrated Circuit) chips

▪ Mac’s new M3 chip ▪ NVIDIA RTX 4090 board

https://www.apple.com/newsroom/2023/10//apple-unveils-m3-m3-pro-and-m3-max-the-most-advanced-chips-for-a-personal-computer
https://www.techspot.com/news/98689-apple-testing-m3-chip-12-cpu-cores-18.html
https://www.techpowerup.com/review/nvidia-geforce-rtx-4090-founders-edition/4.html

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 Circuit Designer’s Job – Make Chips
But circuit designers are not the only contributors in the chip-making industry!
▪ Algorithms – software engineer…
▪ Analog and digital circuits – circuit designer…
▪ Chip fabrication (Silicon Wafer) – device engineer, material engineer, chemist…
▪ Chip packaging – packaging engineer, thermal engineer…
▪ PCB module – PCB engineer, system engineer…
▪ Product verification – test engineer…

or

Circuit Design Chip fabrication Packaging PCB design Product

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 Chip Fabrication – Moore’s Law
Why Advanced Technology?
▪ Higher Density
▪ Lower Power
(low heat dissipation)
▪ Faster Operation

https://www.vyrian.com/what-nm-stands-for-in-a-processor-and-why-it-is-
https://en.wikipedia.org/wiki/Moore%27s_law#/media/File:Moore's_Law_Transistor_Count_1970 -2020.png important/#:~:text=Nm%20is%20an% 20acronym% 20for,or%20process%20node%20in%20technology.

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 IC Packaging
▪ Apple M1 Ultra Processor

Cross section
https://www.techinsights.com/blog/apple-m1-ultra-advanced-packaging

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 Analog Vs. Digital Circuits
Analog Cicuits Digital Circuits
▪ Voltage: 0, 0.1, … 0.22, ... ▪ Voltage: Only 0 and 1
▪ Verilog Coding
▪ People prefer digital circuits
▪ Scalable circuit / Robust (immune to
noise, PVT)

Sensors
Cameras
Audio systems
ADC: Analog-to-Digital Converter
DSP: Digital Signal Processor

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 Miniaturized pH Sensor

Taewook Kang, I. Lee, T. Jang, Y. Kim, H. Ahn, G. Kim, S. Shin, S. Jeong, D. Sylvester,
and D. Blaauw, “A 1.7×4.1×2 mm3 Fully Integrated pH Sensor for Implantable Applications
using Differential Sensing and Drift-Compensation,” in IEEE Symp. VLSI Circuits, 2019.

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 Scope of Work
1050μm Reference
REFET
Electrode
Parylene
Pt Passivation layer (Si3N4)
Al Al
pH sensor
Pt RE
CDAC

CDAC
Control
REFET Stirrer
ISFET

board
1380μm

OSC Silicon

CVCC LDO CVCC

1mm
REFET's M6

FSM Parylene edge

▪ Device Fabrication in Cleanroom

▪ Verilog FSM Implementation ▪ Start Chem. Lab and Testing
▪ Analog Blocks Design from scratch
▪ Analog + Digital Co-simulation ▪ Setup Python Testing Env.
▪ Stacking IC Sensor System
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 Solution 1 – Removing Reference Electrode
Conventional pH Sensing Kit Differential pH Sensor System w/o Kit
Solution
Reference ISFET REFET
Electrode
Silver wire mm3 Quasi-reference
Internal filling
solution (KCL)
cm3 electrode (platinum)

VOUT,ISFET Sensing only

ISFET
AgCl
Noise in VAQ pH change

Porous

Stable VAQ Canceling

VOUT,REFET noise
Solution

▪ Remove huge reference electrode

→ Differential sensing [Bergveld, Sens. and Act’03] by using a novel REFET

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 System Diagram
VBAT=4V
LDO Voltage Solution H+
Reference LDO
OH OH
X2 VDD=1.8V OH2+ OH2+ VAQ Parylene
CVCC REFET Si3N4 Pt Si3N4
M6 Al M6
CVCC ISFET M5 M5
Reference
Const M4 electrode M4
VB VGS
Gate Poly Gate Poly
Current source p+ p+ p+ p+
H+ n+ n+
A2 p-substrate ISFET REFET
ISFET
Cap DAC
VS,CAL
▪ SAR ADC with 10bit CDAC
A1 ▪ 1.25KHz oscillator
VADC_REF ▪ LDO (4V → 1.8 V)
Pt
1.25KHz
▪ 176nW
Reference
electrode FSM ▪ Need a post-fabrication
▪ REFET and Pt Deposition
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 Clean Room Fabrication

https://cores.research.umich.edu/core/lurie-nanofabrication-facility-lnf/

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 REFET and Pt Electrode Fabrication
Pt Deposition

Platinum
Photoresist pattern Photoresist pattern
Passivation layer (Si3N4) Passivation layer (Si3N4) Passivation layer (Si3N4) Pt Passivation layer (Si3N4)
Al Al Al Al Al Al Al Al

Silicon Silicon Silicon Silicon

Bare silicon without polymide Apply photoresist pattern Deposit 100nm platinum Remove the photoresist with
for platinum deposition using an E-beam evaporator acetone (lift-off process)

REFET O2 plasma etching

Quasi-
Reference
REFET
PR Electrode
Parylene Parylene Parylene REFET's M6
Pt Passivation layer (Si3N4) Pt Passivation layer (Si3N4) Pt Passivation layer (Si3N4)
Al Al Al Al Al Al

Parylene edge
Silicon Silicon Silicon

Coat the sample with 100nm Apply photoresist (PR) Fabrication is done
parylene using PDS 2035 patterning as a sacrificial
equipment layer, and etch parylene
with O2 plasma
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 Complete Sensor System
Solution

1mm
Solar Cell
Clear epoxy Spacer ISFET/REFET
Harvester
Proposed pH Sensor
Black epoxy
Radio
Decap
Processor
Power Management IC
Encapsulated pH sensor

30 20
Add acid
Differential ADC Code

25
(ΔpH=2) ▪ The system is mounted on
Differential ADC Code

20 15
15
PGA and verified through the
10
10 measurement
5
5 Slope = 7.86 LSB / pH
0
6
0
5.5 6.5 7.0 7.5 8.0 8.5 9.0 0 2 4 6 8 10
pH
Time [min]
*From stand-alone test **From complete system test
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 Acoustic Beamformer for Speech
Recognition Front-End
0.5mm
0.45mm

0.18mm
ADC 1

0.9mm
ADC 2
ADC 3
DSP
ADC 4
Outstanding Research
Award Winner
▪ S. Lee, Taewook Kang, J. Bell, M. R. Haghighat, A. J. Martinez, and M. P. Flynn, “An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency
Energy Features Enabling 95% Speech Recognition Accuracy,” in IEEE Symp. VLSI Circuits, 2020.
▪ S. Lee, Taewook Kang, J. Bell, M. R. Haghighat, A. J. Martinez, and M. P. Flynn, “An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor,” IEEE JSSC, Aug.
2021.
▪ Taewook Kang, S. Lee, M. R. Haghighat, D. Abramson, and M. P. Flynn, “A 650µW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction,” in
IEEE CICC, Apr. 2021.
▪ Taewook Kang, S. Lee, M. R. Haghighat, D. Abramson, and M. P. Flynn, “A 650µW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction,”
IEEE SSCL, Sep. 2021.
▪ Taewook Kang*, S. Lee*, S. Song, M. R. Haghighat, and M. P. Flynn, “A Multi-mode 157μW 4-channel 80dBA-SNDR Speech Recognition Frontend with Self-DOA Correction Adaptive Beamformer,”
in IEEE ISSCC, Feb. 2022.
▪ Taewook Kang, S. Lee, S. Song, M. R. Haghighat, and M. P. Flynn, “A Multimode 157 μ W 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive
Beamformer,” IEEE JSSC, 2024.

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 Scope of Work
0.5mm
0.45mm
0.18mm

ADC 1

0.9mm
ADC 2
ADC 3
DSP
ADC 4

▪ Verilog DSP Implementation ▪ Verilog FPGA Implementation

▪ Analog ADC Design ▪ Setup Python Testing Environment
▪ Mixed Simulation ▪ Software DNN Implementation
DSP: Digital Signal Processor ▪ Microphone Measurement
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 Speech Recognition System
Noise
Noisy Signal Suppression

Smart Speaker

ADC
Feature
Acoustic
Extractor
Beamformer
DSP Classifier

Noise ADC

Freq.
MIC

Time

DSP: Digital Signal Processor

Beamformer Improves a Recognition Accuracy
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 Prototype System – Idea1: New Beamforming Algorithm
4ch Multi-Mode ADC Multi-Mode Beamformer IC
DOA Tracking
DAS OUTDAS + OUTGABF IIR Bandpass
3 Variable SNR Beamformer Filter Array
-
ADC (DTDAS)
MATLAB
Software
x1 x2 x3 x4 Bandout DNN
DNN
ADC Turn on/off 1~40 Classifier
Mode
Classifier
y1
Features
y2 Multiple-input
Greedy Blocking Energy 1~40
BF y3 Canceller
Mode Matrix (GBM) Calculator
Mode y4 (MC)
Controller
Feature Extractor

Conventional Blocking Matrix Proposed Blocking Matrix

 High Power ☺ 80x Lower Power
 Slow Response ☺ Fast Response
 No DoA Tracking ☺ DoA Tracking
DoA: Direction of Arrival
SKKU Kang Research Group / SEE3007 Spring 2025 except ADC is implemented in digital
*All blocks 20
 Idea 2 & 3: Multi-mode ADC & Beamformer
4ch Multi-Mode ADC Multi-Mode Beamformer IC
DOA Tracking
DAS OUTDAS + OUTGABF IIR Bandpass
3 Variable SNR Beamformer Filter Array
-
ADC (DTDAS)
MATLAB
Software
x1 x2 x3 x4 Bandout DNN
DNN
ADC Turn on/off 1~40 Classifier
Mode
Classifier
y1
Features
y2 Multiple-input
Greedy Blocking Energy 1~40
BF y3 Canceller
Mode Matrix (GBM) Calculator
Mode y4 (MC)
Controller
Feature Extractor

Fixed ADC + DSP Novel Multi-mode ADC &

Performance Dual-mode Beamformer
 Full Power Regardless ☺ Up to 2x Less Power
of Input Condition Depending on Input Condition

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 Measurement Setup

LDO

Single
Input
AVDD (1V)
DVDD (0.7V) Single-Differential 4ch Single-Differential

4ch DAC Main Board

Single-Differential Board
SoC Board
Single-Differential

4ch Diff Data In DAC LDO

Single-Differential
Input
Extracted Level Shifter SoC
SPI Features TDM
FPGA
DAC
PC
FPGA
(MATLAB DNN)

FPGA 4ch S2D

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 Measured Beamformer Spectrogram

40 40 40

Freqeuncy Bin [No.]

30 30 30

20 20 20

10 10 10

0.2 0.6 1.0 0.2 0.6 1.0 0.2 0.6 1.0

Time [s] Time [s] Time [s]
Beamformer Mode No BF DTDAS Only GABF Full
Recognition
Accuracy [%] 54% 57% 83%

BF: Beamforming
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 High-performance ADC

▪ Seungheun Song, Taewook Kang, Seungjong Lee, and Michael P. Flynn, "A 150-
MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier
and Gain-Enhancing Miller Negative-C," IEEE Symposium on VLSI Circuits
(VLSI-Symp), Jun. 2023.
▪ Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, and Michael P.
Flynn, "An 81.6 dB SNDR 15.625 MHz BW 3rd Order CT SDM with a True Time-
Interleaving Noise-Shaping Quantizer," IEEE Journal of Solid-State Circuits
(JSSC), Dec. 2022.
▪ Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, and Michael
Flynn, “An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS
Quantizer,” IEEE Symposium on VLSI Circuits (VLSI-Symp), Jun. 2022.

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 Time-Interleaved Continuous SAR ADC

• Utilize time-interleaving for higher BW

• Add additional delay on the ADC structure to
enable time-interleaving
• Excessive delay compensation

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 Time-Interleaved Continuous SAR ADC

• BW = 15.6MHz
• SNDR = 81.6dB
• Power = 6.4mW
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 Kang Research Lab – Members since 2025.
▪ Ph.D. Students
▪ Chanhong Jeon

▪ M.S. Students
▪ Jeongmin Lee
▪ Dongwhan So
▪ Huijeong Woo
▪ Undergrad. Interns
▪ Seojin Kim / Seoyoon Chae / Sunwoo Lim / Jaehyun Kim / Yejin Hwang

▪ Collaborator
▪ Michael P. Flynn: Professor, University of Michigan, MI
▪ Seungjong Lee: ADC designer, AMD, San Jose, CA.
▪ Seungheun Song: ADC designer, Apple, Cupertino, CA.

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 Kang Research Lab – 2024 Dec. Tape-Out
▪ 2024/Dec, IDEC 28nm MPW, successfully taped out.
▪ Participants – as undergrad research interns
▪ Huijeong Woo, Chanhong Jeon, Jeongmin Lee

▪ 1st order 8bit quantizer NSSAR ▪ Speech Recognition DSCNN

▪ OSR = 32, SNDR = 61dB, ENOB = 9bit ▪ 8-bit integer calculation

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 Research Goal – Intelligent Audio Sensor System

How much?

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 Research Goal – Intelligent Audio Sensor System

Necessary Skills
▪ Analog Circuit
▪ Digital Circuit
▪ Python Coding
▪ FPGA
▪ Machine-Learning
+Fabrication (MEMS microphone)

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 Drone Audition System IC

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 PYTHON SETUP

Acknowledgments
Prof. Woowhan Jung, DSLAB, Hanyang Univ.

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33
Installation Order
▪ Anaconda
▪ Installation: https://www.anaconda.com/products/individual
▪ PyTorch
▪ Deep learning framework
▪ Download: https://pytorch.org/get-started/locally/
▪ PyCharm
▪ IDE
▪ Download: https://www.jetbrains.com/ko-kr/pycharm/download
▪ Jupyter
▪ A powerful tool for interactively developing and presenting data science projects
▪ Installation: https://jupyter.org/install

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 Why

Others

PyTorch

Tensorflow

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https://paperswithcode.com/
 INSTALL ANACONDA

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 Anaconda
▪ Virtual Environment (Not virtual machine)
▪ Optimized for data science
▪ Easy to install/maintain packages

▪ Access to terminal
▪ Windows
▪ 작업표시줄 검색 (start→search) → Anaconda Powershell Prompt

▪ Mac
▪ Use terminal

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 Anaconda Download

https://www.anaconda.com/download

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 Anaconda Install - Mac

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 Anaconda Install - Mac

▪ After installation, open the terminal and

type:

conda --version

conda update conda

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 Anaconda Install - Windows

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 Anaconda Install - Windows

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 Anaconda Install - Windows

▪ After installation, open the terminal and

type:

conda --version
conda update conda

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 Anaconda – Start Virtual env
▪ Create virtual env
▪ conda create –n eee3063 python=3.11

conda create –n <ENV_NAME>(python=3.11)

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 Anaconda – Virtual env
▪ Check virtual env

conda envlist

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 Anaconda – Activate Virtual Env.
▪ Activate virtual env
conda activate <ENV_NAME>

▪ Deactivate virtual env

conda deactivate

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 Anaconda – Delete Virtual Env.

conda env remove-n <ENV_NAME>

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 INSTALL PYTORCH WITHOUT GPU

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 PyTorch – Installation

• Windows command: conda install pytorch torchvision torchaudio -c pytorch

• This will install relative lib, too (e.g., numpy)

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 INSTALL PYTORCH WITH GPU

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 PyTorch GPU
1. Check graphic driver version installed by nvidia-smi: in command, “nvidia-smi”

If you don’t have nvidia-smi , then install the graphic driver

→ https://www.nvidia.com/Download/index.aspx?lang=kr

Check your version for CUDA installation

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51
Check your Graphic Card Version

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 PyTorch GPU – Install CUDA
2. Install CUDA
https://developer.nvidia.com/cuda-downloads
Choose proper options for your PC

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 PyTorch GPU – Install CUDA

4. After installation, restart (or may not need restart)

Open Anaconda Prompt and check if CUDA is

installed
nvcc --version

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54
PyTorch GPU – Check CUDA installation
▪ If you install things correctly, you can try the below command without error

>>> import torch

>>> device = torch.device("cuda:0")
>>> device

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55
PyTorch GPU – Install cuDNN by .exe
5. Install cuDNN (require Nvidia account) : https://developer.nvidia.com/cudnn

▪ Though my Windows is 11, Version=10 works, too

▪ Check C:\Program Files\NVIDIA\CUDNN\v9.0
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56
PyTorch GPU – Install PyTorch

▪ https://pytorch.org/get-started/locally/
▪ conda install pytorch torchvision torchaudio pytorch-cuda=12.1 -c pytorch -c nvidia

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57
PyTorch GPU – Check if you are using GPU

>>> import torch

>>> torch.cuda.is_available()
True
>>> torch.cuda.device_count()
1
>>> torch.cuda.current_device()
0
>>> torch.cuda.device(0)
<torch.cuda.device object at 0x000001CA0A0A0850>
>>> torch.cuda.get_device_name(0) https://stackoverflow.com/questions/48152674/
'NVIDIA GeForce RTX 3060' how-do-i-check-if-pytorch-is-using-the-gpu

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 INSTALL JUPYTER NOTEBOOK
(COMMON FOR WITH/WITHOUT GPU)

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 Jupyter notebook
▪ A powerful tool for interactively developing and presenting data science projects
▪ conda install jupyter notebook
▪ Launch
▪ jupyter notebook

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60
Launch Jupyter
▪ >>> Jupyter notebook
▪ Check Python Version
▪ Check “import torch”

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 INSTALL PYCHARM (COMMON FOR
WITH/WITHOUT GPU)

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62
PyCharm Download
▪ https://www.jetbrains.com/pycharm/download/?section=windows

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63
Setup PyCharm Interpreter
▪ How to bring conda env?
▪ https://www.youtube.com/watch?v=n1SFlh-pW_Q

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64
Use Vim in Pycharm
▪ Strongly recommended text editor for coding
▪ If you haven’t used it before, you need some time to get used to it. But it is worth it!

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 Libraries Installation
▪ You can install libraries on your need in the future as below:
▪ conda install scipy
▪ Scipy is an example library name

After installation, try “import scipy”

It should work as left

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